16-Bit, 100 kSPS, Single-Ended PulSAR ADC in MSOP/QFN Data Sheet AD7683 FEATURES APPLICATION DIAGRAM 16-bit resolution with no missing codes 0.5V TO VDD 2.7V TO 5.5V Throughput: 100 kSPS INL: ±1 LSB typical, ±3 LSB maximum REF VDD Pseudo differential analog input range 0V TO VREF +IN DCLOCK 0 V to VREF with VREF up to VDD –IN AD7683 DOUT 3IN-WTEIRREF ASCPEI Single-supply operation: 2.7 V to 5.5 V CS SPeorwiaelr i dnitsesrifpaactei oSnP:I /4Q mSPWI/ @M I5C VR,O 1W.5I RmEW/D @SP 2 c.7o mV, patible GND 04301-001 Figure 1. 150 μW @ 2.7 V/10 kSPS Standby current: 1 nA 8-lead packages: Table 1. MSOP, QFN (LFCSP)/SOT-23, 14-/16-/18-Bit MSOP PulSAR ADC 3 mm × 3 mm QFN (LFCSP) (SOT-23 size) 400 kSPS Improved second source to ADS8320 and ADS8325 100 250 to ≥1000 ADC Type kSPS kSPS 500 kSPS kSPS Driver APPLICATIONS 18-Bit True AD7691 AD7690 AD7982 ADA4941-1 Differential AD7984 ADA4841-1 Battery-powered equipment 16-Bit True AD7684 AD7687 AD7688 ADA4941-1 Data acquisition Differential AD7693 ADA4841-1 16-Bit AD7680 AD7685 AD7686 AD7980 ADA4841-1 Instrumentation Pseudo AD7683 AD7694 Medical instruments Differential Process control 14-Bit AD7940 AD7942 AD7946 ADA4841-1 Pseudo Differential GENERAL DESCRIPTION The AD7683 is a 16-bit, charge redistribution, successive analog input, +IN, between 0 V to REF with respect to a ground approximation, PulSAR® analog-to-digital converter (ADC) sense, –IN. The reference voltage, REF, is applied externally and that operates from a single power supply, VDD, between 2.7 V can be set up to the supply voltage. Its power scales linearly with and 5.5 V. It contains a low power, high speed, 16-bit sampling throughput. ADC with no missing codes (B grade), an internal conversion The AD7683 is housed in an 8-lead MSOP or an 8-lead QFN clock, and a serial, SPI-compatible interface port. The part also (LFCSP) package, with an operating temperature specified from contains a low noise, wide bandwidth, short aperture delay, −40°C to +85°C. track-and-hold circuit. On the CS falling edge, it samples an Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7683 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Circuit Information .................................................................... 12  Applications ....................................................................................... 1  Converter Operation .................................................................. 12  Application Diagram ........................................................................ 1  Transfer Functions ..................................................................... 12  General Description ......................................................................... 1  Typical Connection Diagram ................................................... 13  Revision History ............................................................................... 2  Analog Input ............................................................................... 13  Specifications ..................................................................................... 3  Driver Amplifier Choice ........................................................... 13  Timing Specifications .................................................................. 5  Voltage Reference Input ............................................................ 14  Absolute Maximum Ratings ............................................................ 6  Power Supply ............................................................................... 14  Thermal Resistance ...................................................................... 6  Digital Interface .......................................................................... 14  ESD Caution .................................................................................. 6  Layout .......................................................................................... 14  Pin Configurations and Function Descriptions ........................... 7  Evaluating the AD7683 Performance ...................................... 14  Terminology ...................................................................................... 8  Outline Dimensions ....................................................................... 15  Typical Performance Characteristics ............................................. 9  Ordering Guide .......................................................................... 16  Applications Information .............................................................. 12  REVISION HISTORY 2/16—Rev. A to Rev. B Changes to Table 1 ............................................................................ 1 Added Figure 7 and Table 9; Renumbered Sequentially ............. 7 Changes to Table 10 ........................................................................ 13 Changes to Digital Interface Section ............................................ 14 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 16 2/08—Rev. 0 to Rev. A Change to Title .................................................................................. 1 Moved Figure 3, Figure 4, and Figure 5 ......................................... 5 Changes to Figure 4 .......................................................................... 5 Moved Figure 17 and Figure 18 .................................................... 11 Changes to Figure 22 ...................................................................... 13 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 16 9/04—Initial Version: Revision 0 Rev. B | Page 2 of 16

Data Sheet AD7683 SPECIFICATIONS VDD = 2.7 V to 5.5 V; V = VDD; T = –40°C to +85°C, unless otherwise noted. REF A Table 2. AD7683 All Grades Parameter Conditions Min Typ Max Unit RESOLUTION 16 Bits ANALOG INPUT Voltage Range +IN − (–IN) 0 V V REF Absolute Input Voltage +IN −0.1 VDD + 0.1 V −IN −0.1 0.1 V Analog Input CMRR f = 100 kHz 65 dB IN Leakage Current at 25°C Acquisition phase 1 nA Input Impedance See the Analog Input section THROUGHPUT SPEED Complete Cycle 10 µs Throughput Rate 0 100 kSPS DCLOCK Frequency 0 2.9 MHz REFERENCE Voltage Range 0.5 VDD + 0.3 V Load Current 100 kSPS, V − V = V /2 = 2.5 V 50 µA +IN −IN REF DIGITAL INPUTS Logic Levels V −0.3 0.3 × VDD V IL V 0.7 × VDD VDD + 0.3 V IH I −1 +1 µA IL I −1 +1 µA IH Input Capacitance 5 pF DIGITAL OUTPUTS Data Format Serial, 16 bits straight binary V I = −500 µA VDD − 0.3 V OH SOURCE V I = +500 µA 0.4 V OL SINK POWER SUPPLIES VDD Specified performance 2.7 5.5 V VDD Range1 2.0 5.5 V Operating Current 100 kSPS throughput VDD VDD = 5 V 800 µA VDD = 2.7 V 560 µA Standby Current2, 3 VDD = 5 V, 25°C 1 50 nA Power Dissipation VDD = 5 V 4 6 mW VDD = 2.7 V 1.5 mW VDD = 2.7 V, 10 kSPS throughput2 150 µW TEMPERATURE RANGE Specified Performance T to T −40 +85 °C MIN MAX 1 See the Typical Performance Characteristics section for more information. 2 With all digital inputs forced to VDD or GND, as required. 3 During acquisition phase. Rev. B | Page 3 of 16

AD7683 Data Sheet VDD = 5 V; V = VDD; T = –40°C to +85°C, unless otherwise noted. REF A Table 3. A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit ACCURACY No Missing Codes 15 16 Bits Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB Transition Noise 0.5 0.5 LSB Gain Error1, T to T ±2 ±24 ±2 ±15 LSB MIN MAX Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C Offset Error1, T to T ±0.7 ±1.6 ±0.4 ±1.6 mV MIN MAX Offset Temperature Drift ±0.3 ±0.3 ppm/°C Power Supply Sensitivity VDD = 5 V ± 5% ±0.05 ±0.05 LSB AC ACCURACY Signal-to-Noise f = 1 kHz 90 88 91 dB2 IN Spurious-Free Dynamic Range f = 1 kHz −100 −108 dB IN Total Harmonic Distortion f = 1 kHz −100 −106 dB IN Signal-to-(Noise + Distortion) f = 1 kHz 90 88 91 dB IN Effective Number of Bits f = 1 kHz 14.7 14.8 Bits IN 1 See the Terminology section. These specifications include full temperature range variation but do not include the error contribution from the external reference. 2 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. VDD = 2.7 V; V = 2.5V; T = –40°C to +85°C, unless otherwise noted. REF A Table 4. A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit ACCURACY No Missing Codes 15 16 Bits Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB Transition Noise 0.85 0.85 LSB Gain Error1, T to T ±2 ±30 ±2 ±15 LSB MIN MAX Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C Offset Error1, T to T ±0.7 ±3.5 ±0.7 ±3.5 mV MIN MAX Offset Temperature Drift ±0.3 ±0.3 ppm/°C Power Supply Sensitivity VDD = 2.7 V ±5% ±0.05 ±0.05 LSB AC ACCURACY Signal-to-Noise f = 1 kHz 85 86 dB2 IN Spurious-Free Dynamic Range f = 1 kHz −96 −100 dB IN Total Harmonic Distortion f = 1 kHz −94 −98 dB IN Signal-to-(Noise + Distortion) f = 1 kHz 85 86 dB IN Effective Number of Bits f = 1 kHz 13.8 14 Bits IN 1 See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. 2 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. Rev. B | Page 4 of 16

Data Sheet AD7683 TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V; T = −40°C to +85°C, unless otherwise noted. A Table 5. Parameter Symbol Min Typ Max Unit Throughput Rate t 100 kHz CYC CS Falling to DCLOCK Low t 0 μs CSD CS Falling to DCLOCK Rising t 20 ns SUCS DCLOCK Falling to Data Remains Valid t 5 16 ns HDO CS Rising Edge to D High Impedance t 14 100 ns OUT DIS DCLOCK Falling to Data Valid t 16 50 ns EN Acquisition Time t 400 ns ACQ D Fall Time t 11 25 ns OUT F D Rise Time t 11 25 ns OUT R Timing and Circuit Diagrams t CYC COMPLETE CYCLE CS tSUCS tACQ POWER DOWN DCLOCK 1 4 5 tCSD tEN tHDO tDIS HIGH-Z HIGH-Z DOUT 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 (MSB) (LSB) N1 . O ADTO EMUSITNGIMOUEMS OLOF W22 OCNL OTCHKE DCCYCLOLECSK AFRAEL LRINEQGU EIRDEGDE FFOORLL 1O6-WBIINT GC OTHNEV ELRSSBI ORNE.A SDHINOGW.N ARE 24 CLOCK CYCLES. 04301-002 Figure 2. Serial Interface Timing 500µA IOL TO DOUT 1.4V CL 100pF 500µA IOH 04301-003 Figure 3. Load Circuit for Digital Interface Timing 2V 0.8V t t EN EN 20V.8V 20V.8V 04301-004 Figure 4. Voltage Reference Levels for Timing 90% DOUT tR tF 10% 04301-006 Figure 5. DOUT Rise and Fall Timing Rev. B | Page 5 of 16

AD7683 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 6. Stresses at or above those listed under Absolute Maximum Parameter Rating Ratings may cause permanent damage to the product. This is a Analog Inputs stress rating only; functional operation of the product at these +IN1, –IN1 GND − 0.3 V to VDD + 0.3 V or or any other conditions above those indicated in the operational ±130 mA section of this specification is not implied. Operation beyond REF GND − 0.3 V to VDD + 0.3 V the maximum operating conditions for extended periods may Supply Voltages affect product reliability. VDD to GND −0.3 V to +6 V Digital Inputs to GND −0.3 V to VDD + 0.3 V THERMAL RESISTANCE Digital Outputs to GND −0.3 V to VDD + 0.3 V Storage Temperature Range −65°C to +150°C Table 7. Thermal Resistance Junction Temperature 150°C Package Type θJA θJC Unit Lead Temperature Range JEDEC J-STD-20 8-Lead MSOP 200 44 °C/W Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD CAUTION 1 See the Analog Input section. Rev. B | Page 6 of 16

Data Sheet AD7683 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 8 VDD +IN 2 AD7683 7 DCLOCK G–NIDN 34 (NToOt Pto V SIEcWale) 65 DCSOUT 04301-005 Figure 6. 8-Lead MSOP Pin Configuration Table 8. 8-Lead MSOP Pin Function Descriptions Pin No. Mnemonic Type1 Function 1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple the REF pin closely to the GND pin with a ceramic capacitor of a few μF. 2 +IN AI Analog Input. It is referred to Pin –IN. The voltage range, that is, the difference between +IN and –IN, is 0 V to V . REF 3 –IN AI Analog Input Ground Sense. Connect this pin to either the analog ground plane or a remote sense ground. 4 GND P Power Supply Ground. 5 CS DI Chip Select Input. On its falling edge, it initiates the conversions. The part returns to shutdown mode as soon as the conversion is completed. It also enables D . When high, D is high impedance. OUT OUT 6 D DO Serial Data Output. The conversion result is output on this pin. It is synchronized to DCLOCK. OUT 7 DCLOCK DI Serial Data Clock Input. 8 VDD P Power Supply. 1 AI = analog input; DI = digital input; DO = digital output; and P = power. REF 1 8 VDD +IN 2 AD7683 7 DCLOCK –IN 3 (NToOt Pto V SIEcWale) 6 DOUT GND 4 5 CS N1 . O EISTXE NPSOOST ERDEQPAUDIR. ECDOTNON EMCETE TTH SEP EEXCPIFOIESDE DELPEACDTTROIC GANL DP.E TRHFIOS RCMOANNNCEEC.TION 04301-107 Figure 7. 8-Lead QFN (LFCSP) Pin Configuration Table 9. 8-Lead QFN (LFCSP) Pin Function Descriptions Pin No. Mnemonic Type1 Function 1 REF AI Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple the REF pin closely to the GND pin with a ceramic capacitor of a few μF. 2 +IN AI Analog Input. It is referred to Pin –IN. The voltage range, that is, the difference between +IN and –IN, is 0 V to V . REF 3 –IN AI Analog Input Ground Sense. Connect this pin to either the analog ground plane or a remote sense ground. 4 GND P Power Supply Ground. 5 CS DI Chip Select Input. On its falling edge, it initiates the conversions. The part returns to shutdown mode as soon as the conversion is completed. It also enables D . When high, D is high impedance. OUT OUT 6 D DO Serial Data Output. The conversion result is output on this pin. It is synchronized to DCLOCK. OUT 7 DCLOCK DI Serial Data Clock Input. 8 VDD P Power Supply. EPAD Exposed Pad. Connect the exposed pad to GND. This connection is not required to meet specified electrical performance. 1 AI = analog input; DI = digital input; DO = digital output; and P = power. Rev. B | Page 7 of 16

AD7683 Data Sheet TERMINOLOGY Signal-to-(Noise + Distortion) Ratio (SINAD) Integral Nonlinearity Error (INL) SINAD is the ratio of the rms value of the actual input signal to Linearity error refers to the deviation of each individual code the rms sum of all other spectral components below the Nyquist from a line drawn from negative full scale through positive frequency, including harmonics but excluding dc. The value for full scale. The point used as negative full scale occurs ½ LSB SINAD is expressed in dB. before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation Effective Number of Bits (ENOB) is measured from the middle of each code to the true straight ENOB is a measurement of the resolution with a sine wave line (see Figure 22). input. It is related to SINAD (as represented by S/(N+D)) by the following formula and is expressed in bits: Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the ENOB=(S/[N+D] −1.76)/6.02 dB maximum deviation from this ideal value. It is often specified in Total Harmonic Distortion (THD) terms of resolution for which no missing codes are guaranteed. THD is the ratio of the rms sum of the first five harmonic Offset Error components to the rms value of a full-scale input signal and is The first transition should occur at a level ½ LSB above analog expressed in dB. ground (38.1 µV for the 0 V to 5 V range). The offset error is Signal-to-Noise Ratio (SNR) the deviation of the actual transition from that point. SNR is the ratio of the rms value of the actual input signal to Gain Error the rms sum of all other spectral components below the Nyquist The last transition (from 111...10 to 111...11) should occur for frequency, excluding harmonics and dc. The value for SNR is an analog voltage 1½ LSB below the nominal full scale expressed in dB. (4.999886 V for the 0 V to 5 V range). The gain error is the Aperture Delay deviation of the actual level of the last transition from the ideal Aperture delay is a measure of the acquisition performance and level after the offset has been adjusted out. is the time between the falling edge of the CS input and when Spurious-Free Dynamic Range (SFDR) the input signal is held for a conversion. The difference, in decibels (dB), between the rms amplitude of Transient Response the input signal and the peak spurious signal. Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev. B | Page 8 of 16

Data Sheet AD7683 TYPICAL PERFORMANCE CHARACTERISTICS 3 3 POSITIVE INL = +0.43LSB POSITIVE DNL = +0.43LSB NEGATIVE INL = –0.97LSB NEGATIVE DNL = –0.41LSB 2 2 1 1 B) B) S S NL (L 0 NL (L 0 I D –1 –1 –2 –2 –3 04301-012 –3 04301-011 0 16384 32768 49152 65536 0 16384 32768 49152 65536 CODE CODE Figure 8. Integral Nonlinearity vs. Code Figure 11. Differential Nonlinearity vs. Code 7000 120000 62564 VDD = REF = 2.5V 102287 VDD = REF = 5V 6000 100000 5000 80000 S4000 S UNT 35528 UNT60000 O O C3000 C 25440 40000 2000 1000 20000 15152 13619 0 0 0 1 50 2755 4604 130 0 0 04301-009 0 0 0 6 8 0 0 04301-010 79FD 79FE 79FF 7A00 7A01 7A02 7A03 7A04 7A05 7A06 7A07 7A08 7A0E 7A0F 7A10 7A11 7A12 7A13 7A14 7A15 7A16 CODE IN HEX CODE IN HEX Figure 9. Histogram of a DC Input at the Code Center Figure 12. Histogram of a DC Input at the Code Center 0 0 16384 POINT FFT 16384 POINT FFT OF FULL SCALE) ––––86420000 VffSTSSIHNDNF =DDDR= R 1===20 0 =0–R9. k142–ES03.1F75kP0d .H6=S7B.z d45BdVB OF FULL SCALE) ––––86420000 STSVffSIHNDNF =DDDR= R 1===20 0 =0–R8. k148–ES03.1F72kP0d .H4=S6B.z d62Bd.5BV AMPLITUDE (dB –––111420000 AMPLITUDE (dB –––111420000 ––1186000 10 20 30 40 5004301-008 ––1186000 10 20 30 40 5004301-007 FREQUENCY (kHz) FREQUENCY (kHz) Figure 10. FFT Plot Figure 13. FFT Plot Rev. B | Page 9 of 16

AD7683 Data Sheet 100 17 –80 –85 95 16 VREF 2.5V = –1dB SNR –90 B) SNR, SINAD (d90 ENOB SINAD 15 ENOB (Bits) THD (dB)–1–0905 VREF 5V = –1dB 85 14 –105 80 13 04301-013 –110 04301-015 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 40 80 120 160 200 REFERENCE VOLTAGE (V) FREQUENCY (kHz) Figure 14. SNR, SINAD, and ENOB vs. Reference Voltage Figure 16. THD vs. Frequency 100 1200 fS = 100kSPS 95 1000 VREF = 5V, –10dB A) µ 90 T ( 800 B) VREF = 5V, –1dB REN d R D (85 CU 600 SINA VREF = 2.5V, –1dB TING 80 A 400 R E P O 75 200 70 04301-014 0 04301-017 0 50 100 150 200 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz) SUPPLY (V) Figure 15. SINAD vs. Frequency Figure 17. Operating Current vs. Supply Rev. B | Page 10 of 16

Data Sheet AD7683 900 6 VDD = 5V,fS = 100kSPS 5 800 4 RRENT (µA) 765000000 VDD = 2.7V,fS = 100kSPS RROR (LSB) 321 OFFSET ERROR CU N E 0 G 400 AI N G –1 OPERATI 320000 OFFSET, ––23 GAIN ERROR –4 1000 04301-018 ––56 04301-016 –55 –34 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. Operating Current vs. Temperature Figure 20. Offset and Gain Error vs. Temperature 1000 nA) 750 T ( N E R R U N C 500 W O D ER- W 250 O P 0–55 –35 –15 5 25 45 65 85 105 12504301-019 TEMPERATURE (°C) Figure 19. Power-Down Current vs. Temperature Rev. B | Page 11 of 16

AD7683 Data Sheet APPLICATIONS INFORMATION +IN SWITCHES CONTROL MSB LSB SW+ 32,768C 16,384C 4C 2C C C BUSY REF CONTROL COMP LOGIC GND OUTPUT CODE 32,768C 16,384C 4C 2C C C MSB LSB SW– CNV –IN 04301-020 Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION array between GND and REF, the comparator input varies by binary-weighted voltage steps (V /2, V /4...V /65,536). REF REF REF The AD7683 is a low power, single-supply, 16-bit ADC using a The control logic toggles these switches, starting with the MSB, successive approximation architecture. to bring the comparator back into a balanced condition. After The AD7683 is capable of converting 100,000 samples per the completion of this process, the part returns to the acquisition second (100 kSPS) and powers down between conversions. phase and the control logic generates the ADC output code. When operating at 10 kSPS, for example, it consumes typically TRANSFER FUNCTIONS 150 µW with a 2.7 V supply, ideal for battery-powered applications. The ideal transfer function for the AD7683 is shown in Figure 22 and Table 10. The AD7683 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple, multiplexed channel applications. Y) AR 111...111 The AD7683 is specified from 2.7 V to 5.5 V. It is housed in an BIN 111...110 8-lead MSOP or a tiny, 8-lead QFN (LFCSP) package. T 111...101 H G The AD7683 is an improved second source to the ADS8320 and AI R T ADS8325. For even better performance, consider the AD7685. S E ( D CONVERTER OPERATION O C C The AD7683 is a successive approximation ADC based on a AD 000...010 charge redistribution DAC. Figure 21 shows the simplified 000...001 schematic of the ADC. The capacitive DAC consists of two 000...000 identical arrays of 16 binary-weighted capacitors that connect –FS –FS + 1 LSB +FS – 1 LSB to the two comparator inputs. –FS + 0.5 LSB ANALOG IN+PFUST – 1.5 LSB 04301-021 During the acquisition phase, terminals of the array tied to the Figure 22. ADC Ideal Transfer Function comparator’s input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. Table 10. Output Codes and Ideal Input Voltages Thus, the capacitor arrays are used as sampling capacitors and Analog Input Digital Output Code Description V = 5 V Hexadecimal acquire the analog signal on the +IN and −IN inputs. When the REF FSR – 1 LSB 4.999924 V FFFF1 acquisition phase is complete and the CS input goes low, a con- Midscale + 1 LSB 2.500076 V 8001 version phase is initiated. When the conversion phase begins, Midscale 2.5 V 8000 SW+ and SW− are opened first. The two capacitor arrays are Midscale – 1 LSB 2.499924 V 7FFF then disconnected from the inputs and connected to the GND –FSR + 1 LSB 76.3 µV 0001 input. Therefore, the differential voltage between the inputs, –FSR 0 V 00002 +IN and −IN, captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to 1 This is also the code for an overranged analog input (V+IN – V–IN above become unbalanced. By switching each element of the capacitor VREF – VGND). 2 This is also the code for an underranged analog input (V+IN – V–IN below VGND). Rev. B | Page 12 of 16

Data Sheet AD7683 (NOTE 1) REF 2.7V TO 5.25V CREF 100nF 2.2µF TO 10µF (NOTE 2) REF VDD 33Ω +IN 0V TO VREF DCLOCK (NOTE 3) 2.7nF AD7683 DOUT 3-WIRE INTERFACE (NOTE 4) –IN CS GND NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 234... CSOERPEETF ID OISRN IAUVLSE URFA IALLMTLEPYRL A.I FS 1IEE0EµRF AC CNHEAORLICAOEMG IS CINE CPCAUTPITOA SNCE.ICTOTIRO N(X.5R). 04301-022 Figure 23. Typical Application Diagram TYPICAL CONNECTION DIAGRAM pass filter that reduces undesirable aliasing effects and limits the noise. Figure 23 shows an example of the recommended application diagram for the AD7683. When the source impedance of the driving circuit is low, the AD7683 can be driven directly. Large source impedances signi- ANALOG INPUT ficantly affect the ac performance, especially THD. The dc Figure 24 shows an equivalent circuit of the input structure of performances are less sensitive to the input impedance. the AD7683. The two diodes, D1 and D2, provide ESD protec- DRIVER AMPLIFIER CHOICE tion for the analog inputs, +IN and −IN. Care must be taken to ensure that the analog input signal never exceeds the supply rails Although the AD7683 is easy to drive, the driver amplifier by more than 0.3 V because this causes these diodes to become needs to meet the following requirements: forward-biased and start conducting current. However, these  The noise generated by the driver amplifier needs to be diodes can handle a forward-biased current of 130 mA maximum. kept as low as possible to preserve the SNR and transition For instance, these conditions can eventually occur when the noise performance of the AD7683. Note that the AD7683 input buffer (U1) supplies are different from VDD. In such a has a noise figure much lower than most other 16-bit case, use an input buffer with a short-circuit current limitation ADCs and, therefore, can be driven by a noisier op amp to protect the part. while preserving the same or better system performance. VDD The noise coming from the driver is filtered by the AD7683 analog input circuit, 1-pole, low-pass filter made by R +IN D1 RIN CIN and C or by the external filter, if one is used. IN OR–IN IN CPIN D2  For ac applications, the driver needs to have a THD GND 04301-023 ptheer fTorHmDa nvcse. fsrueiqtaubelnec tyo tthhaatt tohf et hder iAveDr 7s6h8o3u. lFdi gexucreee 1d6. shows Figure 24. Equivalent Analog Input Circuit  For multichannel multiplexed applications, the driver This analog input structure allows the sampling of the differen- amplifier and the AD7683 analog input circuit must be tial signal between +IN and −IN. By using this differential input, able to settle for a full-scale step of the capacitor array at a small signals common to both inputs are rejected. For instance, 16-bit level (0.0015%). In the amplifier data sheet, settling by using −IN to sense a remote signal ground, ground potential at 0.1% to 0.01% is more commonly specified. This could differences between the sensor and the local ADC ground are differ significantly from the settling time at a 16-bit level eliminated. During the acquisition phase, the impedance of the and should be verified prior to driver selection. analog input, +IN, can be modeled as a parallel combination of Capacitor CPIN and the network formed by the series connection Table 11. Recommended Driver Amplifiers of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically Amplifier Typical Application 600 Ω and is a lumped component consisting of some serial ADA4841-1 Very low noise and low power resistors and the on resistance of the switches. C is typically IN OP184 Low power, low noise, and low frequency 30 pF and is mainly the ADC sampling capacitor. During the AD8605, AD8615 5 V single-supply, low power conversion phase, when the switches are opened, the input AD8519 Low power and low frequency impedance is limited to C . R and C make a 1-pole, low- PIN IN IN AD8031 High frequency and low power Rev. B | Page 13 of 16

AD7683 Data Sheet VOLTAGE REFERENCE INPUT DCLOCK falling edges. The data is valid on both DCLOCK edges. Although the rising edge can be used to capture the data, The AD7683 voltage reference input, REF, has a dynamic input a digital host also using the DCLOCK falling edge allows a impedance. Therefore, it should be driven by a low impedance faster reading rate, provided it has an acceptable hold time. source with efficient decoupling between the REF and GND pins, as explained in the Layout section. CONVERT When REF is driven by a very low impedance source (such as an unbuffered reference voltage like the low temperature drift CS DIGITAL HOST AD7683 ADR435 reference or a reference buffer using the AD8031 or DOUT DATA IN DCLOCK the AD8605), a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. CLK 04301-025 If desired, smaller reference decoupling capacitors with values Figure 26. Connection Diagram as low as 2.2 μF can be used with a minimal impact on perfor- LAYOUT mance, especially DNL. Design the PCB that houses the AD7683 so that the analog and POWER SUPPLY digital sections are separated and confined to certain areas of The AD7683 powers down automatically at the end of each the board. The pin configuration of the AD7683, with all its conversion phase and, therefore, the power scales linearly with analog signals on the left side and all its digital signals on the the sampling rate, as shown in Figure 25. This makes the part right side, eases this task. ideal for low sampling rates (even of a few Hz) and low battery- Avoid running digital lines under the device because these powered applications. couple noise onto the die, unless a ground plane under the 1000 AD7683 is used as a shield. Fast switching signals, such as CS or clocks, should never run near analog signal paths. Avoid VDD = 5V crossover of digital and analog signals. 100 A) µ Use at least one ground plane. It can be common or split between T ( N VDD = 2.7V the digital and analog sections. In such a case, it should be joined E 10 R R underneath the AD7683. U C G The AD7683 voltage reference input (REF) has a dynamic input N 1 ATI impedance and should be decoupled with minimal parasitic R E P inductances. Accomplish this by placing the reference decoupling O 0.1 ceramic capacitor close to, and ideally right up against, the REF 0.01 04301-024 aimndp eGdNanDc ep tirnasc aens.d by connecting these pins with wide, low 10 100 1k 10k 100k SAMPLING RATE (SPS) Finally, decouple the power supply, VDD, of the AD7683 with a Figure 25. Operating Current vs. Sampling Rate ceramic capacitor, typically 100 nF, placed close to the AD7683. DIGITAL INTERFACE Connect it using short and large traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. The AD7683 is compatible with SPI®, QSPI™, digital hosts, MICROWIRE™, and DSPs (for example, Blackfin® ADSP-BF531, EVALUATING THE AD7683 PERFORMANCE ADSP-BF532, ADSP-BF533, or the ADSP-2191M). The connection Other recommended layouts for the AD7683 are outlined in the diagram is shown in Figure 26 and the corresponding timing is evaluation board for the AD7683 (EVAL-AD7683CBZ). The given in Figure 2. evaluation board package includes a fully assembled and tested A falling edge on CS initiates a conversion and the data transfer. evaluation board, documentation, and software for controlling After the fifth DCLOCK falling edge, D is enabled and forced the board from a PC via the EVAL-CONTROL BRD3Z. OUT low. The data bits are then clocked, MSB first, by subsequent Rev. B | Page 14 of 16

Data Sheet AD7683 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L50A.1N0ARICTOYMPLIANT0. 2T5O JEDEC STA0°NDARDS 0M.0O9-187-AA 0.40 10-07-2009-B Figure 27. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions Shown in millimeters 3.10 0.35 3.00 SQ 0.30 0.65 BSC 2.90 0.25 5 8 PIN 1 INDEX EXPOSED 1.74 AREA PAD 1.64 0.50 1.49 0.40 0.30 4 1 0.20 MIN TOP VIEW BOTTOM VIEW PIN 1 INDICATOR 0.80 MAX 2.48 (R 0.2) 0.80 0.55 NOM 2.38 0.75 0.05 MAX 2.23 0.70 0.02 NOM FOR PROPER CONNECTION OF SEPALTAINNGE 0.20 REF TTFSHHUEENEC CTPEITIOXNIPON CON OOS DFNEE DFTSIH GPCISAUR DRIDP,AA TRTTIOEIAOFN NSES HRAE NTEODT. 02-05-2013-C Figure 28. 8-Terminal Quad Flat No Lead Package (QFN) [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-3) Dimensions Shown in millimeters Rev. B | Page 15 of 16

AD7683 Data Sheet ORDERING GUIDE Integral Package Ordering Model1 Nonlinearity Temperature Range Package Description2 Option Branding Quantity AD7683ACPZRL7 ±6 LSB max –40°C to +85°C 8-Lead QFN [LFCSP_WD] CP-8-3 C4G Reel, 1,500 AD7683ARMZ ±6 LSB max –40°C to +85°C 8-Lead MSOP RM-8 C4G Tube, 50 AD7683ARMZRL7 ±6 LSB max –40°C to +85°C 8-Lead MSOP RM-8 C4G Reel, 1,000 AD7683BCPZRL7 ±3 LSB max –40°C to +85°C 8-Lead QFN [LFCSP_WD] CP-8-3 C38 Reel, 1,500 AD7683BRMZ ±3 LSB max –40°C to +85°C 8-Lead MSOP RM-8 C38 Tube, 50 AD7683BRMZRL7 ±3 LSB max –40°C to +85°C 8-Lead MSOP RM-8 C38 Reel, 1,000 EVAL-AD7683SDZ Evaluation Board EVAL-CONTROL BRD3Z Controller Board 1 Z = RoHS Compliant Part. 2 The EVAL CONTROL BRD3Z board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04301-0-2/16(B) Rev. B | Page 16 of 16

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7683BCPZRL7 AD7683ARMZ AD7683BRMZ AD7683BRMZRL7 EVAL-AD7683SDZ AD7683ARMZRL7 AD7683ACPZRL7