a CMOS Dual 8-Bit Buffered Multiplying DAC AD7628 FEATURES FUNCTIONAL BLOCK DIAGRAM On-Chip Latches for Both DACs +12 V to +15 V Operation DACs Matched to 1% Four Quadrant Multiplication TTL/CMOS Compatible from +12 V to +15 V Latch Free (Protection Schottkys not Required) APPLICATIONS Disk Drives Programmable Filters X-Y Graphics Gain/Attenuation GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7628 is a monolithic dual 8-bit digital/analog converter 1. DAC to DAC matching: since both of the AD7628 DACs featuring excellent DAC-to-DAC matching. It is available in are fabricated at the same time on the same chip, precise small 0.3" wide 20-pin DIPs and in 20-terminal surface mount matching and tracking between DAC A and DAC B is inher- packages. ent. The AD7628’s matched CMOS DACs make a whole new range of applications circuits possible, particularly in the Separate on-chip latches are provided for each DAC to allow audio, graphics and process control areas. easy microprocessor interface. 2. Small package size: combining the inputs to the on-chip Data is transferred into either of the two DAC data latches via a DAC latches into a common data bus and adding a DAC A/ common 8-bit TTL/CMOS compatible input port. Control in- DAC B select line has allowed the AD7628 to be packaged in put DAC A/DAC B determines which DAC is to be loaded. a small 20-pin 0.3" wide DIP, 20-pin SOIC, 20-terminal The AD7628’s load cycle is similar to the write cycle of a ran- PLCC and 20-terminal LCC. dom access memory, and the device is bus compatible with most 8-bit microprocessors, including 6502, 6809, 8085, Z80. 3. TTL-Compatibility: All digital inputs are TTL-compatible over a +12 V to +15 V power supply range. The device operates from a +12 V to +15 V power supply and is TTL-compatible over this range. Power dissipation is a low 20 mW. Both DACs offer excellent four quadrant multiplication charac- teristics with a separate reference input and feedback resistor for each DAC. REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 617/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 617/326-8703 © Analog Devices, Inc., 1996

AD7628–SPECIFICATIONS (V = +10.8 V to +15.75 V, V A = V B = +10 V; OUT A = OUT B = 0 V unless DD REF REF otherwise noted) T = –40(cid:56)C T = –55(cid:56)C A A Parameter T = +25(cid:56)C1 to +85(cid:56)C to +125(cid:56)C1 Units Test Conditions/Comments A STATIC PERFORMANCE2 Resolution 8 8 8 Bits Relative Accuracy – 1/2 – 1/2 – 1/2 LSB max This is an Endpoint Linearity Specification Differential Nonlinearity – 1 – 1 – l LSB max All Grades Guaranteed Monotonic Over Full Operating Temperature Range Gain Error – 2 – 3 – 3 LSB max Measured Using Internal RFB A and RFB B. Both DAC Latches Loaded with 11111111. Gain Error is Adjustable Using Circuits of Figures 4 and 5. Gain Temperature Coefficient3 D Gain/D Temperature – 0.0035 – 0.0035 %/(cid:176)C max Output Leakage Current OUT A (Pin 2) – 50 – 200 – 200 nA max DAC Latches Loaded with 00000000 OUT B (Pin 20) – 50 – 200 – 200 nA max Input Resistance (V A, V B) 8 8 8 kW min Input Resistance TC = –300 ppm/(cid:176)C, Typical REF REF 15 15 15 kW max Input Resistance is 11 kW V A/V B Input Resistance REF REF Match – 1 – 1 – 1 % max DIGITAL INPUTS4 Input High Voltage (V ) 2.4 2.4 2.4 V min IH Input Low Voltage (V ) 0.8 0.8 0.8 V max IL Input Current (I ) – 1 – 10 – 10 m A max V = 0 or V IN IN DD Input Capacitance DB0–DB7 10 10 10 pF max WR, CS, DACA/DACB 15 15 15 pF max SWITCHING CHARACTERISTICS3 See Timing Diagram Chip Select to Write Set Up Time (t ) 160 160 210 ns min CS Chip Select to Write Hold Time (t ) 10 10 10 ns min CH DAC Select to Write Set Up Time (t ) 160 160 210 ns min AS DAC Select to Write Hold Time (t ) 10 10 10 ns min AH Data Valid to Write Set Up Time (t ) 160 160 210 ns min DS Data Valid to Write Hold Time (t ) 10 10 10 ns min DH Write Pulse Width (t ) 150 170 210 ns min WR POWER SUPPLY See Figure 3 I , K Grade 2 2 mA All Digital Inputs V or V DD IL IH B, T Grades 2 2.5 2.5 mA All Digital Inputs V or V IL IH All Grades 100 500 500 m A All Digital Inputs 0 V or V DD Specifications subject to change without notice. AC PERFORMANCE CHARACTERISTICS These characteristics are included for Design Guidance only and are not subject to test. V = +10.8 V to +15.75 V. (Measured Using Recommended PC Board Layout (Figure 7) and AD644 as Output Amplifiers) DD T = –40(cid:56)C T = –55(cid:56)C A A Parameter T = +25(cid:56)C1 to +85(cid:56)C1 to +125(cid:56)pC1 Units Test Conditions/Comments A DC SUPPLY REJECTION (D GAIN/D V ) 0.01 0.02 0.02 % per % max D V = – 5% DD DD CURRENT SETTLING TIME 350 400 400 ns max To 1/2 LSB OutA/OutB Load = 100 W . WR = CS = 0 V. DB0–DB7 = 0 V to V or V to 0 V DD DD DIGITAL-TO-ANALOG GLITCH IMPULSE 330 nV sec typ For Code Transition 00000000 to 11111111 OUTPUT CAPACITANCE C A 25 25 25 pF max DAC Latches Loaded with 00000000 OUT C B 25 25 25 pF max OUT C A 60 60 60 pF max DAC Latches Loaded with 11111111 OUT C B 60 60 60 pF max OUT AC FEEDTHROUGH V A to OUT A –70 –65 –65 dB max V A, V B = 20 V p-p Sine Wave REF REF REF V B to OUT B –70 –65 –65 dB max @ 10 kHz REF CHANNEL-TO-CHANNEL ISOLATION Both DAC Latches Loaded with 11111111. V A to OUT B –80 dB typ V A = 20 V p-p Sine Wave @ 10 kHz REF REF V B = 0 V See Figure 6. REF V B to OUTA –80 dB typ V B = 20 V p-p Sine Wave @ 10 kHz REF REF V A = 0 V See Figure 6. REF DIGITAL CROSSTALK 60 nV sec typ Measured for Code Transition 00000000 to 11111111 HARMONIC DISTORTION –85 dB typ V = 6 V rms @ 1 kHz IN NOTES 1Temperature Ranges are K Version; –40(cid:176)C to +85(cid:176)C; B Version; –40(cid:176)C to +85(cid:176)C; T Version; –55(cid:176)C to +125(cid:176)C. 2Specification applies to both DACs in AD7628. 3Guaranteed by design but not production tested. 4Logic inputs are MOS Gates. Typical input current (+25(cid:176)C) is less than 1 nA. Specifications subject to change without notice. –2– REV. A

AD7628 ABSOLUTE MAXIMUM RATINGS TERMINOLOGY (T = +25(cid:176)C unless otherwise noted) A Relative Accuracy: VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V Relative accuracy or endpoint nonlinearity is a measure of the VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V maximum deviation from a straight line passing through the AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V endpoints of the DAC transfer function. It is measured after ad- DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V justing for zero and full-scale, and is normally expressed in Digital Input Voltage to DGND . . . . . . –0.3 V, VDD + 0.3 V LSBs or as a percentage of full-scale reading. V , V to AGND . . . . . . . . . . . . . .–0.3 V, V + 0.3 V PIN2 PIN20 DD Differential Nonlinearity: V A, V B to AGND . . . . . . . . . . . . . . . . . . . . . . .– 25 V REF REF Differential nonlinearity is the difference between the measured V A, V B to AGND . . . . . . . . . . . . . . . . . . . . . . .– 25 V RFB RFB change and the ideal 1 LSB change between any two adjacent Power Dissipation (Any Package) to +75(cid:176) C . . . . . . . . 450 mW codes. A specified differential nonlinearity of – 1 LSB max over Derates above +75(cid:176) C by . . . . . . . . . . . . . . . . . . . 6 mW/(cid:176) C the operating temperature range ensures monotonicity. Operating Temperature Range Commercial (K) Grades . . . . . . . . . . . . . . . –40(cid:176) C to +85(cid:176) C Gain Error: Industrial (B) Grades . . . . . . . . . . . . . . . . . –40(cid:176) C to +85(cid:176) C Gain error is a measure of the output error between an ideal Extended (T) Grades . . . . . . . . . . . . . . . . –55(cid:176) C to +125(cid:176) C DAC and the actual device output. It is measured with all 1s in Storage Temperature . . . . . . . . . . . . . . . . . –65(cid:176) C to +150(cid:176) C the DAC latches after offset error has been adjusted out. Gain Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300(cid:176) C error of both DACs is adjustable to zero with external resistance. Output Capacitance: ORDERING GUIDE Capacitance from OUT A or OUT B to AGND. Temperature Relative Gain Package Digital-to-Analog Glitch Impulse: Model1 Range Accuracy Error Option2 The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally AD7628KN –40(cid:176) C to +85(cid:176) C – 1/2 LSB – 2 LSB N-20 specified as the area of the glitch in either pA-secs or nV-secs, AD7628KP –40(cid:176) C to +85(cid:176) C – 1/2 LSB – 2 LSB P-20A depending upon whether the glitch is measured as a current or AD7628KR –40(cid:176) C to +85(cid:176) C – 1/2 LSB – 2 LSB R-20 voltage signal. Glitch impulse is measured with V A, V B AD7628BQ –40(cid:176) C to +85(cid:176) C – 1/2 LSB – 2 LSB Q-20 REF REF = AGND. AD7628TQ –55(cid:176) C to +125(cid:176) C – 1/2 LSB – 2 LSB Q-20 AD7628TE –55(cid:176) C to +125(cid:176) C – 1/2 LSB – 2 LSB E-20A Channel-to-Channel Isolation: The proportion of input signal from one DAC’s reference input NOTES that appears at the output of the other DAC, expressed as a 1To order MIL-STD-883, Class B process parts, add /883B to part number. ratio in dB. Contact your local sales office for military data sheet. 2E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Digital Crosstalk: Carrier; Q = Cerdip; R = SOIC. The glitch energy transferred to the output of one converter due to a change in digital input code to the other converter. Speci- fied in nV secs. PIN CONFIGURATIONS DIP, SOIC LCCC PLCC A A D B B A A D B B AGND 1 20 OUT B RFB OUT AGN OUT RFB RFB OUT AGN OUT RFB OUT A 2 19 RFB B 3 2 1 20 19 3 2 1 20 19 VRRFEBF AA 43 AD7628 1178 VVRDEDF B VDRGEFN AD45 AD7628 1187 VVRDEDF B VDRGEFN AD 45 AD7628 1187 VVRDEDF B DGND 5 TOP VIEW 16 WR DAC A /DAC B 6 TOP VIEW 16 WR DAC A/DAC B 6 TOP VIEW 16 WR DAC A/DAC B 6 (Not to Scale) 15 CS DB7 (MSB) 7 (Not to Scale) 15 CS (Not to Scale) DB7 (MSB) 7 15 CS (MSB) DB7 7 14 DB0 (LSB) DB6 8 14 DB0 (LSB) DB6 8 14 DB0 (LSB) DB6 8 13 DB1 9 10 11 12 13 DB5 9 12 DB2 5 4 3 2 1 9 10 11 12 13 B B B B B DB4 10 11 DB3 D D D D D B5 B4 B3 B2 B1 D D D D D CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7628 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE REV. A –3–

AD7628 INTERFACE LOGIC INFORMATION weighted currents are switched between the DAC output and DAC Selection AGND, thus maintaining fixed currents in each ladder leg inde- Both DAC latches share a common 8-bit input port. The con- pendent of switch state. trol input DAC A/DAC B selects which DAC can accept data from the input port. EQUIVALENT CIRCUIT ANALYSIS Mode Selection Figure 2 shows an approximate equivalent circuit for one of Inputs CS and WR control the operating mode of the selected the AD7628’s D/A converters, in this case DAC A. A similar DAC. See Mode Selection Table below. equivalent circuit can be drawn for DAC B. Note that AGND (Pin 1) is common for both DAC A and DAC B. Write Mode When CS and WR are both low, the selected DAC is in the write The current source I is composed of surface and junc- LEAKAGE mode. The input data latches of the selected DAC are transpar- tion leakages and, as with most semiconductor devices, approxi- ent and its analog output responds to activity on DB0–DB7. mately doubles every 10(cid:176) C. The resistor Ro, as shown in Fig- ure 2, is the equivalent output resistance of the device, which Hold Mode varies with input code (excluding all 0s code) from 0.8R to 2R. The selected DAC latch retains the data that was present on R is typically 11 kW . C is the capacitance due to the N-channel DB0–DB7 just prior to CS or WR assuming a high state. Both OUT switches and varies from about 50 pF to 120 pF, depending on analog outputs remain at the values corresponding to the data in the digital input. g(V A, N) is the Thevenin equivalent volt- their respective latches. REF age generator due to the reference input voltage V A and the REF Mode Selection Table transfer function of the R-2R ladder. For further information on CMOS multiplying D/A converters, DAC A/ DAC B CS WR DAC A DAC B refer to “CMOS DAC Application Guide, 2ND Edition” avail- able from Analog Devices, Publication Number G872a–15–4/86. L L L WRITE HOLD H L L HOLD WRITE X H X HOLD HOLD X X H HOLD HOLD L = Low State, H = High State, X = Don’t Care WRITE CYCLE TIMING DIAGRAM Figure 2.Equivalent Analog Output Circuit of DAC A CIRCUIT INFORMATION–DIGITAL SECTION The input buffers are simple CMOS level-shifters designed so that when the AD7628 is operated with V from 10.8 V to DD 15.75 V, the buffer converts TTL input levels (2.4 V and 0.8 V) into CMOS logic levels. When V is in the region of 1.0 volt to IN 2.0 volts, the input buffers operate in their linear region and pass a quiescent current (see Figure 3). To minimize power sup- ply currents, it is recommended that the digital input voltages be as close to the supply rails (V and DGND) as practicably possible. DD The AD7628 may be operated with any supply voltage in the range 10.8 £ V £ 15.75 volts. DD CIRCUIT INFORMATION—D/A SECTION The AD7628 contains two identical 8-bit multiplying D/A con- verters, DAC A and DAC B. Each DAC consists of a highly stable thin film R-2R ladder and eight N-channel current steering switches. A simplified D/A circuit for DAC A is shown in Figure 1. An inverted R-2R ladder structure is used; that is, binary Figure 3.Typical Plot of Supply Current, I vs. Logic DD Input Voltage V to V = +15 V Figure 1.Simplified Functional Circuit for DAC A IN DD –4– REV. A

AD7628 Figure 4.Dual DAC Unipolar Binary Operation (2 Quadrant Multiplication). See Table I. Figure 5.Dual DAC Bipolar Operation (4 Quadrant Multiplication). See Table II. Table I. Unipolar Binary Code Table Table II. Bipolar (Offset Binary) Code Table DAC Latch Contents Analog Output DAC Latch Contents Analog Output MSB LSB (DAC A or DAC B) MSB LSB (DAC A or DAC B) 1 1 1 1 1 1 1 1 –VIN(cid:230)Ł(cid:231) 225565(cid:246)ł(cid:247) 1 1 1 1 1 1 1 1 +VIN(cid:230)Ł(cid:231) 112287(cid:246)ł(cid:247) 1 0 0 0 0 0 0 1 –VIN(cid:230)Ł(cid:231) 122596(cid:246)ł(cid:247) 1 0 0 0 0 0 0 1 +VIN(cid:230)Ł(cid:231) 1218(cid:246)ł(cid:247) (cid:230) 128(cid:246) V 1 0 0 0 0 0 0 0 –VINŁ(cid:231) 256ł(cid:247) =– 2IN 1 0 0 0 0 0 0 0 0 (cid:230) 127(cid:246) (cid:230) 1 (cid:246) 0 1 1 1 1 1 1 1 –VINŁ(cid:231) 256ł(cid:247) 0 1 1 1 1 1 1 1 –VINŁ(cid:231) 128ł(cid:247) (cid:230) 1 (cid:246) (cid:230) 127(cid:246) 0 0 0 0 0 0 0 1 –VINŁ(cid:231) 256ł(cid:247) 0 0 0 0 0 0 0 1 –VINŁ(cid:231) 128ł(cid:247) 0 0 0 0 0 0 0 0 –VIN(cid:230)Ł(cid:231) 2506(cid:246)ł(cid:247) =0 0 0 0 0 0 0 0 0 –VIN(cid:230)Ł(cid:231) 112288(cid:246)ł(cid:247) NOTE: 1 LSB = (2–8)(VIN) = 2516(VIN) NOTE: 1 LSB = (2–7)(VIN) = 1218(VIN) Table III. Recommended Trim Resistor Values Trim Resistor K/B/T R1; R3 500 R2; R4 150 REV. A –5–

AD7628 APPLICATIONS INFORMATION Figure 7 shows a printed circuit layout for the AD7628 and the Application Hints AD644 dual op amp, which minimizes feedthrough and crosstalk. To ensure system performance consistent with AD7628 specifi- SINGLE SUPPLY APPLICATIONS cations, careful attention must be given to the following points: The AD7628 DAC R-2R ladder termination resistors are con- 1.GENERAL GROUND MANAGEMENT: AC or transient nected to AGND within the device. This arrangement is par- voltages between the AD7628 AGND and DGND can cause ticularly convenient for single supply operation because AGND noise injection into the analog output. The simplest method may be biased at any voltage between DGND and VDD. Figure of ensuring that voltages at AGND and DGND are equal is 8 shows a circuit that provides two +5 V to +8 V analog outputs to tie AGND and DGND together at the AD7628. In more by biasing AGND +5 V up from DGND. The two DAC refer- omplex systems where the AGND–DGND intertie is on the ence inputs are tied together and a reference input voltage is ob- backplane, it is recommended that diodes be connected in tained without a buffer amplifier by making use of the constant inverse parallel between the AD7628 AGND and DGND and matched impedances of the DAC A and DAC B reference pins (1N914 or equivalent). inputs. Current flows through the two DAC R-2R ladders into R1, and R1 is adjusted until the V A and V B inputs are 2.OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a REF REF at +2 V. The two analog output voltages range from +5 V to code-dependent output resistance which, in turn, causes a +8 V for DAC codes 00000000 to l l l l l l l l . code-dependent amplifier noise gain. The effect is a code- dependent differential nonlinearity term at the amplifier output that depends on V (V is amplifier input offset OS OS voltage). This differential nonlinearity term adds to the R/2R differential nonlinearity. To maintain monotonic operation, it is recommended that amplifier V be no greater than 10% of OS 1 LSB over the temperature range of interest. 3.HIGH FREQUENCY CONSIDERATIONS: The output capacitance of a CMOS DAC works in conjunction with the amplifier feedback resistance to add a pole to the open loop response. This can cause ringing or oscillation. Stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor. DYNAMIC PERFORMANCE Figure 8.AD7628 Single Supply Operation The dynamic performance of the two DACs in the AD7628 will Figure 9 shows DAC A of the AD7628 connected in a positive depend on the gain and phase characteristics of the output am- reference, voltage switching mode. This configuration is useful plifiers, together with the optimum choice of the PC board lay- because V is the same polarity as V , allowing single supply out and decoupling components. Figure 6 shows the relationship OUT IN operation. However, to retain specified linearity, V must be in between input frequency and channel-to-channel isolation. IN the range 0 V to +2.5 V and the output buffered or loaded with a high impedance (see Figure 10). Note that the input voltage is connected to the DAC OUT A, and the output voltage is taken from the DAC V A pin. REF Figure 6.Channel-to-Channel Isolation Figure 9.AD7628 Single Supply, Voltage Switching Mode Figure 7.Suggested PC Board Layout for AD7628 with Figure 10.Typical AD7628 Performance in Single Supply AD644 Dual Op Amp Voltage Switching Mode –6– REV. A

AD7628 MICROPROCESSOR INTERFACE Figure 11.AD7628 Dual DAC to 6800 CPU Interface PROGRAMMABLE WINDOW COMPARATOR Figure 12.AD7628 Dual DAC to 8085 CPU Interface In the circuit of Figure 13, the AD7628 is used to implement a programmable window comparator. DACs A and B are loaded with the required upper and lower voltage limits for the test, respectively. If the test input is not within the programmed lim- its, the pass/fail output will indicate a fail (logic zero). Figure 13.Digitally Programmable Window Comparator CIRCUIT EQUATIONS (Upper and Lower Limit Detector) PROGRAMMABLE STATE VARIABLE FILTER C1 = C2, R1 = R2, R4 = R5 1 f = C 2p R C 1 1 R R Q = 3. F R R 4 FBB1 R A = – F O R S NOTE DAC equivalent resistance equals ( ) 256· DACLadderresistance DAC Digital Code Figure 14.Digitally Controlled State Variable Filter In this state, variable or universal filter configuration (Figure The filter provides low pass, high pass and band pass outputs 14) for DACs A1 and B1 control the gain and Q of the filter and is ideally suited for applications where microprocessor con- characteristic, while DACs A2 and B2 control the cutoff fre- trol of filter parameters is required, e.g., equalizer, tone con- quency, f . DACs A2 and B2 must track accurately for the simple trols, etc. C expression for f to hold. This is readily accomplished by the C Programmable range for component values shown is f = 0 kHz AD7628. Op amps are 2 · AD644. C3 compensates for the C to 15 kHz and Q = 0.3 to 4.5. effects of op amp gain-bandwidth limitations. REV. A –7–

AD7628 DIGITALLY CONTROLLED DUAL MECHANICAL INFORMATION TELEPHONE ATTENUATOR OUTLINE DIMENSIONS In this configuration, the AD7628 functions as a 2-channel Dimensions shown in inches and (mm). digitally controlled attenuator; ideal for stereo audio and tele- phone signal level control applications. Table IV gives input 20-Pin Cerdip (Q Suffix) codes vs. attenuation for a 0 dB to 15.5 dB range. 8 8 (cid:230) Attenuation, dB(cid:246) –3/ Input Code = 256 · 10 exp (cid:231) - (cid:247) –8 Ł 20 ł a 9 2 0 1 C 20-Pin Plastic DIP (N Suffix) Figure 15.Digitally Controlled Dual Telephone Attenuator Table IV. Attenuation vs. DAC A, DAC B Code for the Circuit of Figure 15 20-Terminal Leadless Chip DAC Input Code in DAC Input Code in Carrier (E Suffix) Attn. dB Code Decimal Attn. dB Code Decimal 0.0 1 1 1 1 1 1 1 1 255 8.0 0 1 1 0 0 1 1 0 102 0.5 1 1 1 1 0 0 1 0 242 8.5 0 1 1 0 0 0 0 0 96 1.0 1 1 1 0 0 1 0 0 228 9.0 0 1 0 1 1 0 1 1 91 1.5 1 1 0 1 0 1 1 1 215 9.5 0 1 0 1 0 1 1 0 86 2.0 1 1 0 0 1 0 1 1 203 10.0 0 1 0 1 0 0 0 1 81 2.5 1 1 0 0 0 0 0 0 192 10.5 0 1 0 0 1 1 0 0 76 3.0 1 0 1 1 0 1 0 1 181 11.0 0 1 0 0 1 0 0 0 72 3.5 1 0 1 0 1 0 1 1 171 11.5 0 1 0 0 0 1 0 0 68 4.0 1 0 1 0 0 0 1 0 162 12.0 0 1 0 0 0 0 0 0 64 4.5 1 0 0 1 1 0 0 0 152 12.5 0 0 1 1 1 1 0 1 61 5.0 1 0 0 1 0 0 0 0 144 13.0 0 0 1 1 1 0 0 1 57 5.5 1 0 0 0 1 0 0 0 136 13.5 0 0 1 1 0 1 1 0 54 20-Terminal 6.0 1 0 0 0 0 0 0 0 128 14.0 0 0 1 1 0 0 1 51 6.5 0 1 1 1 0 0 1 121 14.5 0 0 1 1 0 0 0 0 48 Plastic Leaded 7.0 0 1 1 1 0 0 1 0 114 15.0 0 0 1 0 1 1 1 0 46 Chip Carrier (P Suffix) A. 7.5 0 1 1 0 1 1 0 0 108 15.5 0 0 1 0 1 0 1 1 43 U.S. N D I E T N RI P –8– REV. A

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7628KN AD7628KRZ AD7628KPZ AD7628KNZ AD7628KPZ-REEL AD7628KRZ-REEL AD7628KP-REEL