8-/6-/4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC Data Sheet AD7606/AD7606-6/AD7606-4 FEATURES APPLICATIONS 8/6/4 simultaneously sampled inputs Power-line monitoring and protection systems True bipolar analog input ranges: ±10 V, ±5 V Multiphase motor control Single 5 V analog supply and 2.3 V to 5 V V Instrumentation and control systems DRIVE Fully integrated data acquisition solution Multiaxis positioning systems Analog input clamp protection Data acquisition systems (DAS) Input buffer with 1 MΩ analog input impedance Table 1. High Resolution, Bipolar Input, Simultaneous Second-order antialiasing analog filter Sampling DAS Solutions On-chip accurate reference and reference buffer Single- True Number of 16-bit ADC with 200 kSPS on all channels Ended Differential Simultaneous Oversampling capability with digital filter Resolution Inputs Inputs Sampling Channels Flexible parallel/serial interface 18 Bits AD7608 AD7609 8 SPI/QSPI™/MICROWIRE™/DSP compatible 16 Bits AD7606 8 Performance AD7606-6 6 7 kV ESD rating on analog input channels AD7606-4 4 95.5 dB SNR, −107 dB THD 14 Bits AD7607 8 ±0.5 LSB INL, ±0.5 LSB DNL Low power: 100 mW Standby mode: 25 mW Temperature range: −40°C to +85°C 64-lead LQFP package FUNCTIONAL BLOCK DIAGRAM AVCC AVCC REGCAP REGCAP REFCAPBREFCAPA V1 CLAMP1MΩ RFB V1GND CLAMP1MΩ RFB OSREDCEORN LDP-F T/H L2.D5OV L2.D5OV V2 CLAMP1MΩ RFB REFIN/REFOUT V2GND CLAMP1MΩ RFB OSREDCEORN LDP-F T/H 2.5V REF SELECT V3 CLAMP1MΩ RFB REF AGND V3GND CLAMP1MΩ RFB OSREDCEORN LDP-F T/H OOSS 21 OS 0 V4 CLAMP1MΩ RFB V4GND CLAMP1MΩ RFB OSREDCEORN LDP-F T/H 8:1 SERIAL DDOOUUTTAB V5GNVD5 CCLLAAMMPP11MMΩΩ RRFFBB OSREDCEORN LDP-F T/H MUX 1S6-ABRIT DFIIGLTITEARL IPNATSREEARRLFIALAELCLE/ RCPADSR/S/CSELKR/BYTE SEL V6 CLAMP1MΩ RFB VDRIVE V6GND CLAMP1MΩ RFB OSREDCEORN LDP-F T/H PARALLEL DB[15:0] V7 CLAMP1MΩ RFB AD7606 V7GND CLAMP1MΩ RFB OSREDCEORN LDP-F T/H CLK OSC V8 CLAMP1MΩ RFB CONTROL BUSY V8GND CLAMP1MΩ RFB OSRAEDGCENORND LDP-F T/H CONVST ACONIVNSPTU TBSRESETRANGE FRSTDATA 08479-001 Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7606/AD7606-6/AD7606-4 Data Sheet TABLE OF CONTENTS Features........................................................................................... 1 Analog Input ............................................................................ 22 Applications ................................................................................... 1 ADC Transfer Function .......................................................... 23 Functional Block Diagram ............................................................ 1 Internal/External Reference .................................................... 24 Revision History ............................................................................ 2 Typical Connection Diagram.................................................. 25 General Description ...................................................................... 3 Power-Down Modes ................................................................ 25 Specifications ................................................................................. 4 Conversion Control ................................................................. 26 Timing Specifications ................................................................ 7 Digital Interface ........................................................................... 27 Absolute Maximum Ratings ....................................................... 11 Parallel Interface (PAR/SER/BYTE SEL = 0)......................... 27 Thermal Resistance ................................................................. 11 Parallel Byte (PAR/SER/BYTE SEL = 1, DB15 = 1) .............. 27 ESD Caution............................................................................. 11 Serial Interface (PAR/SER/BYTE SEL = 1)............................ 27 Pin Configurations and Function Descriptions ........................ 12 Reading During Conversion ................................................... 28 Typical Performance Characteristics.......................................... 17 Digital Filter ............................................................................. 29 Terminology ................................................................................. 21 Layout Guidelines .................................................................... 32 Theory of Operation.................................................................... 22 Outline Dimensions .................................................................... 34 Converter Details..................................................................... 22 Ordering Guide........................................................................ 34 REVISION HISTORY 5/2018—Rev. D to Rev. E 10/2011—Rev. A to Rev. B Changes to Patent Note, Note 1 .....................................................3 Changes to Input High Voltage (V ) and Input Low Voltage INH Changes to t Parameter, Table 3..............................................7 (V ) Parameters and Endnote 6, Table 2 ....................................4 CONV INL Changes to Table 3 ..........................................................................7 11/2017—Rev. C to Rev. D Changes to Table 4 ........................................................................11 Changes to Features Section ..........................................................1 Changes to Pin 32 Description, Table 6 ......................................13 Changes to Specifications Table Summary ...................................3 Changes to Analog Input Clamp Protection Section .................22 Deleted Endnote 1, Table 1; Renumbered Sequentially ...............6 Changes to Typical Connection Diagram Section .....................25 Change to Table 6 .........................................................................14 Changes to Typical Performance Characteristics Section .........17 8/2010—Rev. 0 to Rev. A Changes to Terminology Section.................................................21 Changes to Note 1, Table 2.............................................................6 Changes to Ordering Guide .........................................................34 5/2010—Revision 0: Initial Version 1/2012—Rev. B to Rev. C Changes to Analog Input Ranges Section ...................................22 Rev. E | Page 2 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 GENERAL DESCRIPTION The AD76061/AD7606-6/AD7606-4 are 16-bit, simultaneous all channels. The input clamp protection circuitry can tolerate sampling, analog-to-digital data acquisition systems (DAS) with voltages up to ±16.5 V. The AD7606 has 1 MΩ analog input eight, six, and four channels, respectively. Each part contains impedance regardless of sampling frequency. The single supply analog input clamp protection, a second-order antialiasing filter, operation, on-chip filtering, and high input impedance eliminate a track-and-hold amplifier, a 16-bit charge redistribution successive the need for driver op amps and external bipolar supplies. The approximation analog-to-digital converter (ADC), a flexible AD7606/AD7606-6/AD7606-4 antialiasing filter has a 3 dB cutoff digital filter, a 2.5 V reference and reference buffer, and high frequency of 22 kHz and provides 40 dB antialias rejection when speed serial and parallel interfaces. sampling at 200 kSPS. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the 3 dB bandwidth. The AD7606/AD7606-6/AD7606-4 operate from a single 5 V supply and can accommodate ±10 V and ±5 V true bipolar input 1 Protected by US Patent Number 8,072,360. signals while sampling at throughput rates up to 200 kSPS for Rev. E | Page 3 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet SPECIFICATIONS V = 2.5 V external/internal, AV = 4.75 V to 5.25 V, V = 2.3 V to 5.25 V, f = 200 kSPS, T = −40°C to +85°C, unless otherwise noted. REF CC DRIVE SAMPLE A Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE f = 1 kHz sine wave unless otherwise noted IN Signal-to-Noise Ratio (SNR)1, 2 Oversampling by 16; ±10 V range; f = 130 Hz 94 95.5 dB IN Oversampling by 16; ±5 V range; f = 130 Hz 93 94.5 dB IN No oversampling; ±10 V Range 88.5 90 dB No oversampling; ±5 V range 87.5 89 dB Signal-to-(Noise + Distortion) (SINAD)1 No oversampling; ±10 V range 88 90 dB No oversampling; ±5 V range 87 89 dB Dynamic Range No oversampling; ±10 V range 90.5 dB No oversampling; ±5 V range 90 dB Total Harmonic Distortion (THD)1 −107 −95 dB Peak Harmonic or Spurious Noise (SFDR)1 −108 dB Intermodulation Distortion (IMD)1 fa = 1 kHz, fb = 1.1 kHz Second-Order Terms −110 dB Third-Order Terms −106 dB Channel-to-Channel Isolation1 f on unselected channels up to 160 kHz −95 dB IN ANALOG INPUT FILTER Full Power Bandwidth −3 dB, ±10 V range 23 kHz −3 dB, ±5 V range 15 kHz −0.1 dB, ±10 V range 10 kHz −0.1 dB, ±5 V range 5 kHz t ±10 V Range 11 µs GROUP DELAY ±5 V Range 15 µs DC ACCURACY Resolution No missing codes 16 Bits Differential Nonlinearity1 ±0.5 ±0.99 LSB3 Integral Nonlinearity1 ±0.5 ±2 LSB Total Unadjusted Error (TUE) ±10 V range ±6 LSB ±5 V range ±12 LSB Positive Full-Scale Error1, 4 External reference ±8 ±32 LSB Internal reference ±8 LSB Positive Full-Scale Error Drift External reference ±2 ppm/°C Internal reference ±7 ppm/°C Positive Full-Scale Error Matching1 ±10 V range 5 32 LSB ±5 V range 16 40 LSB Bipolar Zero Code Error1, 5 ±10 V range ±1 ±6 LSB ± 5 V range ±3 ±12 LSB Bipolar Zero Code Error Drift ±10 V range 10 µV/°C ± 5 V range 5 µV/°C Bipolar Zero Code Error Matching1 ±10 V range 1 8 LSB ±5 V range 6 22 LSB Negative Full-Scale Error1, 4 External reference ±8 ±32 LSB Internal reference ±8 LSB Negative Full-Scale Error Drift External reference ±4 ppm/°C Internal reference ±8 ppm/°C Negative Full-Scale Error Matching1 ±10 V range 5 32 LSB ±5 V range 16 40 LSB Rev. E | Page 4 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 Parameter Test Conditions/Comments Min Typ Max Unit ANALOG INPUT Input Voltage Ranges RANGE = 1 ±10 V RANGE = 0 ±5 V Analog Input Current 10 V; see Figure 31 5.4 µA 5 V; see Figure 31 2.5 µA Input Capacitance6 5 pF Input Impedance See the Analog Input section 1 MΩ REFERENCE INPUT/OUTPUT Reference Input Voltage Range See the ADC Transfer Function section 2.475 2.5 2.525 V DC Leakage Current ±1 µA Input Capacitance6 REF SELECT = 1 7.5 pF Reference Output Voltage REFIN/REFOUT 2.49/ V 2.505 Reference Temperature Coefficient ±10 ppm/°C LOGIC INPUTS Input High Voltage (V ) 0.7 × V V INH DRIVE Input Low Voltage (V ) 0.3 × V V INL DRIVE Input Current (I ) ±2 µA IN Input Capacitance (C )6 5 pF IN LOGIC OUTPUTS Output High Voltage (V ) I = 100 µA V − 0.2 V OH SOURCE DRIVE Output Low Voltage (V ) I = 100 µA 0.2 V OL SINK Floating-State Leakage Current ±1 ±20 µA Floating-State Output Capacitance6 5 pF Output Coding Twos complement CONVERSION RATE Conversion Time All eight channels included; see Table 3 4 µs Track-and-Hold Acquisition Time 1 µs Throughput Rate Per channel, all eight channels included 200 kSPS POWER REQUIREMENTS AV 4.75 5.25 V CC V 2.3 5.25 V DRIVE I Digital inputs = 0 V or V TOTAL DRIVE Normal Mode (Static) AD7606 16 22 mA AD7606-6 14 20 mA AD7606-4 12 17 mA Normal Mode (Operational)7 f = 200 kSPS SAMPLE AD7606 20 27 mA AD7606-6 18 24 mA AD7606-4 15 21 mA Standby Mode 5 8 mA Shutdown Mode 2 6 µA Rev. E | Page 5 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit Power Dissipation Normal Mode (Static) AD7606 80 115.5 mW Normal Mode (Operational)7 f = 200 kSPS SAMPLE AD7606 100 142 mW AD7606-6 90 126 mW AD7606-4 75 111 mW Standby Mode 25 42 mW Shutdown Mode 10 31.5 µW 1See the Terminology section. 2 This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with VDRIVE = 5 V, SNR typically reduces by 1.5 dB and THD by 3 dB. 3 LSB means least significant bit. With ±5 V input range, 1 LSB = 152.58 µV. With ±10 V input range, 1 LSB = 305.175 µV. 4 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from the external reference. 5 Bipolar zero code error is calculated with respect to the analog input voltage. See the Analog Input Clamp Protection section. 6 Sample tested during initial release to ensure compliance. 7 Operational power/current figure includes contribution when running in oversampling mode. Rev. E | Page 6 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 TIMING SPECIFICATIONS AV = 4.75 V to 5.25 V, V = 2.3 V to 5.25 V, V = 2.5 V external reference/internal reference, T = T to T , unless otherwise noted.1 CC DRIVE REF A MIN MAX Table 3. Limit at TMIN, TMAX Limit at TMIN, TMAX (0.1 × VDRIVE and (0.3 × VDRIVE and 0.9 × VDRIVE 0.7 × VDRIVE Logic Input Levels) Logic Input Levels) Parameter Min Typ Max Min Typ Max Unit Description PARALLEL/SERIAL/BYTE MODE tCYCLE 1/throughput rate 5 5 µs Parallel mode, reading during or after conversion; or serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines 9.4 µs Serial mode reading after a conversion; VDRIVE = 2.7 V 9.7 10.7 µs Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines tCONV2 Conversion time 3.45 4 4.2 3.45 4 4.2 µs Oversampling off; AD7606 3 3 µs Oversampling off; AD7606-6 2 2 µs Oversampling off; AD7606-4 7.87 9.1 7.87 9.1 µs Oversampling by 2; AD7606 16.05 18.8 16.05 18.8 µs Oversampling by 4; AD7606 33 39 33 39 µs Oversampling by 8; AD7606 66 78 66 78 µs Oversampling by 16; AD7606 133 158 133 158 µs Oversampling by 32; AD7606 257 315 257 315 µs Oversampling by 64; AD7606 tWAKE-UP STANDBY 100 100 µs STBY rising edge to CONVST x rising edge; power-up time from standby mode tWAKE-UP SHUTDOWN Internal Reference 30 30 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode External Reference 13 13 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode tRESET 50 50 ns RESET high pulse width tOS_SETUP 20 20 ns BUSY to OS x pin setup time tOS_HOLD 20 20 ns BUSY to OS x pin hold time t1 40 45 ns CONVST x high to BUSY high t2 25 25 ns Minimum CONVST x low pulse t3 25 25 ns Minimum CONVST x high pulse t4 0 0 ns BUSY falling edge to CS falling edge setup time t53 0.5 0.5 ms Maximum delay allowed between CONVST A, CONVST B rising edges t6 25 25 ns Maximum time between last CS rising edge and BUSY falling edge t7 25 25 ns Minimum delay between RESET low to CONVST x high PARALLEL/BYTE READ OPERATION t8 0 0 ns CS to RD setup time t9 0 0 ns CS to RD hold time t10 RD low pulse width 16 19 ns VDRIVE above 4.75 V 21 24 ns VDRIVE above 3.3 V 25 30 ns VDRIVE above 2.7 V 32 37 ns VDRIVE above 2.3 V t11 15 15 ns RD high pulse width t12 22 22 ns CS high pulse width (see Figure 5); CS and RD linked Rev. E | Page 7 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet Limit at T , T Limit at T , T MIN MAX MIN MAX (0.1 × V and (0.3 × V and DRIVE DRIVE 0.9 × V 0.7 × V DRIVE DRIVE Logic Input Levels) Logic Input Levels) Parameter Min Typ Max Min Typ Max Unit Description t Delay from CS until DB[15:0] three-state disabled 13 16 19 ns V above 4.75 V DRIVE 20 24 ns V above 3.3 V DRIVE 25 30 ns V above 2.7 V DRIVE 30 37 ns V above 2.3 V DRIVE t 4 Data access time after RD falling edge 14 16 19 ns V above 4.75 V DRIVE 21 24 ns V above 3.3 V DRIVE 25 30 ns V above 2.7 V DRIVE 32 37 ns V above 2.3 V DRIVE t 6 6 ns Data hold time after RD falling edge 15 t 6 6 ns CS to DB[15:0] hold time 16 t 22 22 ns Delay from CS rising edge to DB[15:0] three-state 17 enabled SERIAL READ OPERATION f Frequency of serial read clock SCLK 23.5 20 MHz V above 4.75 V DRIVE 17 15 MHz V above 3.3 V DRIVE 14.5 12.5 MHz V above 2.7 V DRIVE 11.5 10 MHz V above 2.3 V DRIVE t Delay from CS until D A/D B three-state 18 OUT OUT disabled/delay from CS until MSB valid 15 18 ns V above 4.75 V DRIVE 20 23 ns V above 3.3 V DRIVE 30 35 ns V = 2.3 V to 2.7 V DRIVE t 4 Data access time after SCLK rising edge 19 17 20 ns V above 4.75 V DRIVE 23 26 ns V above 3.3 V DRIVE 27 32 ns V above 2.7 V DRIVE 34 39 ns V above 2.3 V DRIVE t 0.4 t 0.4 t ns SCLK low pulse width 20 SCLK SCLK t 0.4 t 0.4 t ns SCLK high pulse width 21 SCLK SCLK t 7 7 SCLK rising edge to D A/D B valid hold time 22 OUT OUT t 22 22 ns CS rising edge to D A/D B three-state enabled 23 OUT OUT FRSTDATA OPERATION t Delay from CS falling edge until FRSTDATA three- 24 state disabled 15 18 ns V above 4.75 V DRIVE 20 23 ns V above 3.3 V DRIVE 25 30 ns V above 2.7 V DRIVE 30 35 ns V above 2.3 V DRIVE t25 ns Delay from CS falling edge until FRSTDATA high, serial mode 15 18 ns V above 4.75 V DRIVE 20 23 ns V above 3.3 V DRIVE 25 30 ns V above 2.7 V DRIVE 30 35 ns V above 2.3 V DRIVE t Delay from RD falling edge to FRSTDATA high 26 16 19 ns V above 4.75 V DRIVE 20 23 ns V above 3.3 V DRIVE 25 30 ns V above 2.7 V DRIVE 30 35 ns V above 2.3 V DRIVE Rev. E | Page 8 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 Limit at TMIN, TMAX Limit at TMIN, TMAX (0.1 × VDRIVE and (0.3 × VDRIVE and 0.9 × VDRIVE 0.7 × VDRIVE Logic Input Levels) Logic Input Levels) Parameter Min Typ Max Min Typ Max Unit Description t27 Delay from RD falling edge to FRSTDATA low 19 22 ns VDRIVE = 3.3 V to 5.25V 24 29 ns VDRIVE = 2.3 V to 2.7V t28 Delay from 16th SCLK falling edge to FRSTDATA low 17 20 ns VDRIVE = 3.3 V to 5.25V 22 27 ns VDRIVE = 2.3 V to 2.7V t29 24 29 ns Delay from CS rising edge until FRSTDATA three- state enabled 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2 In oversampling mode, typical tCONV for the AD7606-6 and AD7606-4 can be calculated using ((N × tCONV) + ((N − 1) × 1 µs)). N is the oversampling ratio. For the AD7606-6, tCONV = 3 µs; and for the AD7606-4, tCONV = 2 µs. 3 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets. 4 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins. Timing Diagrams t5 CONVST A, CONVST B tCYCLE t2 CONVST A, CONVST B t3 tCONV t1 BUSY t4 CS t7 RESET tRESET 08479-002 Figure 2. CONVST Timing—Reading After a Conversion t5 CONVST A, CONVST B tCYCLE t2 CONVST A, CONVST B t3 tCONV t1 BUSY t6 CS t7 RESET tRESET 08479-003 Figure 3. CONVST Timing—Reading During a Conversion Rev. E | Page 9 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet CS t9 t8 t10 t11 RD t16 t13 t14 t15 t17 DATA: DB[15:0] INVALID V1 V2 V3 V4 V7 V8 FRSTDATA t24 t26 t27 t29 08479-004 Figure 4. Parallel Mode, Separate CS and RD Pulses t12 CS AND RD t13 t16 t17 DATA: V1 V2 V3 V4 V5 V6 V7 V8 DB[15:0] FRSTDATA 08479-005 Figure 5. CS and RD, Linked Parallel Mode CS SCLK t21 t20 t18 t19 t22 t23 DOUTA, DB15 DB14 DB13 DB1 DB0 DOUTB FRSTDATA t25 t28 t29 08479-006 Figure 6. Serial Read Operation (Channel 1) CS t8 t9 t10 t11 RD t16 t13 t14 t15 t17 DATA: DB[7:0] INVALID BYHTIGEH V1 BYLTOEW V1 BYHTIGEH V8 BYLTOEW V8 t26 t27 t29 FRSTDATAt24 08479-007 Figure 7. BYTE Mode Read Operation Rev. E | Page 10 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. THERMAL RESISTANCE A θ is specified for the worst-case conditions, that is, a device Table 4. JA soldered in a circuit board for surface-mount packages. These Parameter Rating specifications apply to a 4-layer board. AV to AGND −0.3 V to +7 V CC V to AGND −0.3 V to AV + 0.3 V DRIVE CC Table 5. Thermal Resistance Analog Input Voltage to AGND1 ±16.5 V Package Type θ θ Unit JA JC Digital Input Voltage to AGND −0.3 V to V + 0.3 V DRIVE 64-Lead LQFP 45 11 °C/W Digital Output Voltage to AGND −0.3 V to V + 0.3 V DRIVE REFIN to AGND −0.3 V to AV + 0.3 V CC Input Current to Any Pin Except Supplies1 ±10 mA ESD CAUTION Operating Temperature Range B Version −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Pb/SN Temperature, Soldering Reflow (10 sec to 30 sec) 240 (+0)°C Pb-Free Temperature, Soldering Reflow 260 (+0)°C ESD (All Pins Except Analog Inputs) 2 kV ESD (Analog Input Pins Only) 7 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. E | Page 11 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS D D D D D D D D N N N N N N N N G G G G G G G G 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 V V V V V V V V V V V V V V V V 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVCC 1 48 AVCC ANALOG INPUT AGND 2 PIN 1 47 AGND DECOUPLING CAP PIN OS 0 3 46 REFGND POWER SUPPLY OS 1 4 45 REFCAPB GROUND PIN OS 2 5 44 REFCAPA DATA OUTPUT PAR/SER/BYTE SEL 6 AD7606 43 REFGND DIGITAL OUTPUT STBY 7 TOP VIEW 42 REFIN/REFOUT DIGITAL INPUT RANGE 8 (Not to Scale) 41 AGND CONVST A 9 40 AGND REFERENCE INPUT/OUTPUT CONVST B 10 39 REGCAP RESET 11 38 AVCC RD/SCLK 12 37 AVCC CS 13 36 REGCAP BUSY 14 35 AGND FRSTDATA 15 34 REF SELECT DB0 16 33 DB15/BYTE SEL 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DB1 DB2 DB3 DB4 DB5 DB6 VDRIVEDB7/DAOUTDB8/DBOUT AGND DB9 DB10 DB11 DB12 DB13 DB14/HBEN 08479-008 Figure 8. AD7606 Pin Configuration AGND AGND V6GND V6 V5GND V5 V4GND V4 AGND AGND V3GND V3 V2GND V2 V1GND V1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVCC 1 48 AVCC ANALOG INPUT AGND 2 PIN 1 47 AGND DECOUPLING CAP PIN OS 0 3 46 REFGND POWER SUPPLY OS 1 4 45 REFCAPB GROUND PIN OS 2 5 44 REFCAPA DATA OUTPUT PAR/SER/BYTE SEL 6 AD7606-6 43 REFGND DIGITAL OUTPUT STBY 7 TOP VIEW 42 REFIN/REFOUT DIGITAL INPUT RANGE 8 (Not to Scale) 41 AGND CONVST A 9 40 AGND REFERENCE INPUT/OUTPUT CONVST B 10 39 REGCAP RESET 11 38 AVCC RD/SCLK 12 37 AVCC CS 13 36 REGCAP BUSY 14 35 AGND FRSTDATA 15 34 REF SELECT DB0 16 33 DB15/BYTE SEL 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DB1 DB2 DB3 DB4 DB5 DB6 VDRIVEDB7/DAOUTDB8/DBOUT AGND DB9 DB10 DB11 DB12 DB13 DB14/HBEN 08479-009 Figure 9. AD7606-6 Pin Configuration Rev. E | Page 12 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 AGND AGND AGND AGND V4GND V4 V3GND V3 AGND AGND AGND AGND V2GND V2 V1GND V1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVCC 1 48 AVCC ANALOG INPUT AGND 2 PIN 1 47 AGND DECOUPLING CAP PIN OS 0 3 46 REFGND POWER SUPPLY OS 1 4 45 REFCAPB GROUND PIN OS 2 5 44 REFCAPA DATA OUTPUT PAR/SER/BYTE SEL 6 AD7606-4 43 REFGND DIGITAL OUTPUT STBY 7 TOP VIEW 42 REFIN/REFOUT DIGITAL INPUT RANGE 8 (Not to Scale) 41 AGND CONVST A 9 40 AGND REFERENCE INPUT/OUTPUT CONVST B 10 39 REGCAP RESET 11 38 AVCC RD/SCLK 12 37 AVCC CS 13 36 REGCAP BUSY 14 35 AGND FRSTDATA 15 34 REF SELECT DB0 16 33 DB15/BYTE SEL 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DB1 DB2 DB3 DB4 DB5 DB6 VDRIVEDB7/DAOUTDB8/DBOUT AGND DB9 DB10 DB11 DB12 DB13 DB14/HBEN 08479-010 Figure 10. AD7606-4 Pin Configuration Table 6. Pin Function Descriptions Mnemonic Pin No. Type1 AD7606 AD7606-6 AD7606-4 Description 1, 37, 38, P AV AV AV Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to CC CC CC 48 the internal front-end amplifiers and to the ADC core. These supply pins should be decoupled to AGND. 2, 26, 35, P AGND AGND AGND Analog Ground. These pins are the ground reference points for all analog 40, 41, 47 circuitry on the AD7606. All analog input signals and external reference signals should be referred to these pins. All six of these AGND pins should connect to the AGND plane of a system. 5, 4, 3 DI OS [2:0] OS [2:0] OS [2:0] Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling ratio. OS 2 is the MSB control bit, and OS 0 is the LSB control bit. See the Digital Filter section for more details about the oversampling mode of operation and Table 9 for oversampling bit decoding. 6 DI PAR/SER/ PAR/SER/ PAR/SER/ Parallel/Serial/Byte Interface Selection Input. Logic input. If this pin is tied to BYTE SEL BYTE SEL BYTE SEL a logic low, the parallel interface is selected. If this pin is tied to a logic high, the serial interface is selected. Parallel byte interface mode is selected when this pin is logic high and DB15/BYTE SEL is logic high (see Table 8). In serial mode, the RD/SCLK pin functions as the serial clock input. The DB7/D A pin and the DB8/D B pin function as serial data outputs. When OUT OUT the serial interface is selected, the DB[15:9] and DB[6:0] pins should be tied to ground. In byte mode, DB15, in conjunction with PAR/SER/BYTE SEL, is used to select the parallel byte mode of operation (see Table 8). DB14 is used as the HBEN pin. DB[7:0] transfer the 16-bit conversion results in two RD operations, with DB0 as the LSB of the data transfers. 7 DI STBY STBY STBY Standby Mode Input. This pin is used to place the AD7606/AD7606-6/ AD7606-4 into one of two power-down modes: standby mode or shutdown mode. The power-down mode entered depends on the state of the RANGE pin, as shown in Table 7. When in standby mode, all circuitry, except the on- chip reference, regulators, and regulator buffers, is powered down. When in shutdown mode, all circuitry is powered down. Rev. E | Page 13 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet Mnemonic Pin No. Type1 AD7606 AD7606-6 AD7606-4 Description 8 DI RANGE RANGE RANGE Analog Input Range Selection. Logic input. The polarity on this pin deter- mines the input range of the analog input channels. If this pin is tied to a logic high, the analog input range is ±10 V for all channels. If this pin is tied to a logic low, the analog input range is ±5 V for all channels. A logic change on this pin has an immediate effect on the analog input range. Changing this pin during a conversion is not recommended for fast throughput rate applications. See the Analog Input section for more information. 9, 10 DI CONVST A, CONVST A, CONVST A, Conversion Start Input A, Conversion Start Input B. Logic inputs. These CONVST B CONVST B CONVST B logic inputs are used to initiate conversions on the analog input channels. For simultaneous sampling of all input channels, CONVST A and CONVST B can be shorted together, and a single convert start signal can be applied. Alternatively, CONVST A can be used to initiate simultaneous sampling: V1, V2, V3, and V4 for the AD7606; V1, V2, and V3 for the AD7606-6; and V1 and V2 for the AD7606-4. CONVST B can be used to initiate simultaneous sampling on the other analog inputs: V5, V6, V7, and V8 for the AD7606; V4, V5, and V6 for the AD7606-6; and V3 and V4 for the AD7606-4. This is possible only when oversampling is not switched on. When the CONVST A or CONVST B pin transitions from low to high, the front-end track-and-hold circuitry for the respective analog inputs is set to hold. 11 DI RESET RESET RESET Reset Input. When set to logic high, the rising edge of RESET resets the AD7606/AD7606-6/AD7606-4. The device should receive a RESET pulse directly after power-up. The RESET high pulse should typically be 50 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied during a read, the contents of the output registers reset to all zeros. 12 DI RD/SCLK RD/SCLK RD/SCLK Parallel Data Read Control Input When the Parallel Interface Is Selected (RD)/ Serial Clock Input When the Serial Interface Is Selected (SCLK). When both CS and RD are logic low in parallel mode, the output bus is enabled. In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge takes the DOUTA and DOUTB data output lines out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the D A and D B OUT OUT serial data outputs. For more information, see the Conversion Control section. 13 DI CS CS CS Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in parallel mode, the DB[15:0] output bus is enabled and the conversion result is output on the parallel data bus lines. In serial mode, CS is used to frame the serial read transfer and clock out the MSB of the serial output data. 14 DO BUSY BUSY BUSY Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges and indicates that the conversion process has started. The BUSY output remains high until the conversion process for all channels is complete. The falling edge of BUSY signals that the conversion data is being latched into the output data registers and is available to read after a Time t . Any data read while BUSY is high must be completed before the 4 falling edge of BUSY occurs. Rising edges on CONVST A or CONVST B have no effect while the BUSY signal is high. 15 DO FRSTDATA FRSTDATA FRSTDATA Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back on the parallel, byte, or serial interface. When the CS input is high, the FRSTDATA output pin is in three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel mode, the falling edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high, indicating that the result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low following the next falling edge of RD. In serial mode, FRSTDATA goes high on the falling edge of CS because this clocks out the MSB of V1 on D A. It returns low on the 16th SCLK OUT falling edge after the CS falling edge. See the Conversion Control section for more details. Rev. E | Page 14 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 Mnemonic Pin No. Type1 AD7606 AD7606-6 AD7606-4 Description 22 to 16 DO DB[6:0] DB[6:0] DB[6:0] Parallel Output Data Bits, DB6 to DB0. When PAR/SER/BYTE SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB6 to DB0 of the conversion result. When PAR/SER/BYTE SEL = 1, these pins should be tied to AGND. When operating in parallel byte interface mode, DB[7:0] outputs the 16-bit con- version result in two RD operations. DB7 (Pin 24) is the MSB; DB0 is the LSB. 23 P V V V Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin DRIVE DRIVE DRIVE determines the operating voltage of the interface. This pin is nominally at the same supply as the supply of the host interface (that is, DSP and FPGA). 24 DO DB7/DOUTA DB7/DOUTA DB7/DOUTA Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (DOUTA). When PAR/SER/BYTE SEL = 0, this pins acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is used to output DB7 of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions as D A and outputs serial conversion data (see the Conversion Control OUT section for more details). When operating in parallel byte mode, DB7 is the MSB of the byte. 25 DO DB8/D B DB8/D B DB8/D B Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (D B). OUT OUT OUT OUT When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is used to output DB8 of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions as D B and outputs serial conversion data (see the Conversion Control OUT section for more details). 31 to 27 DO DB[13:9] DB[13:9] DB[13:9] Parallel Output Data Bits, DB13 to DB9. When PAR/SER/BYTE SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB13 to DB9 of the conversion result. When PAR/SER/BYTE SEL = 1, these pins should be tied to AGND. 32 DO/DI DB14/ DB14/ DB14/ Parallel Output Data Bit 14 (DB14)/High Byte Enable (HBEN). When PAR/ HBEN HBEN HBEN SER/BYTE SEL = 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB14 of the conversion result. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7606/ AD7606-6/AD7606-4 operate in parallel byte interface mode. In parallel byte mode, the HBEN pin is used to select whether the most significant byte (MSB) or the least significant byte (LSB) of the conversion result is output first. When HBEN = 1, the MSB is output first, followed by the LSB. When HBEN = 0, the LSB is output first, followed by the MSB. In serial mode, this pin should be tied to GND. 33 DO/DI DB15/ DB15/ DB15/ Parallel Output Data Bit 15 (DB15)/Parallel Byte Mode Select (BYTE SEL). BYTE SEL BYTE SEL BYTE SEL When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB15 of the conversion result. When PAR/SER/BYTE SEL = 1, the BYTE SEL pin is used to select between serial interface mode and parallel byte interface mode (see Table 8). When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0, the AD7606 operates in serial interface mode. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7606 operates in parallel byte interface mode. 34 DI REF SELECT REF SELECT REF SELECT Internal/External Reference Selection Input. Logic input. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. 36, 39 P REGCAP REGCAP REGCAP Decoupling Capacitor Pin for Voltage Output from Internal Regulator. These output pins should be decoupled separately to AGND using a 1 μF capacitor. The voltage on these pins is in the range of 2.5 V to 2.7 V. Rev. E | Page 15 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet Mnemonic Pin No. Type1 AD7606 AD7606-6 AD7606-4 Description 42 REF REFIN/ REFIN/ REFIN/ Reference Input (REFIN)/Reference Output (REFOUT). The on-chip reference REFOUT REFOUT REFOUT of 2.5 V is available on this pin for external use if the REF SELECT pin is set to logic high. Alternatively, the internal reference can be disabled by setting the REF SELECT pin to logic low, and an external reference of 2.5 V can be applied to this input (see the Internal/External Reference section). Decoupling is required on this pin for both the internal and external reference options. A 10 μF capacitor should be applied from this pin to ground close to the REFGND pins. 43, 46 REF REFGND REFGND REFGND Reference Ground Pins. These pins should be connected to AGND. 44, 45 REF REFCAPA, REFCAPA, REFCAPA, Reference Buffer Output Force/Sense Pins. These pins must be connected REFCAPB REFCAPB REFCAPB together and decoupled to AGND using a low ESR, 10 μF ceramic capacitor. The voltage on these pins is typically 4.5 V. 49 AI V1 V1 V1 Analog Input. This pin is a single-ended analog input. The analog input range of this channel is determined by the RANGE pin. 50, 52 AI GND V1GND, V1GND, V1GND, Analog Input Ground Pins. These pins correspond to Analog Input Pin V1 V2GND V2GND V2GND and Analog Input Pin V2. All analog input AGND pins should connect to the AGND plane of a system. 51 AI V2 V2 V2 Analog Input. This pin is a single-ended analog input. The analog input range of this channel is determined by the RANGE pin. 53 AI/GND V3 V3 AGND Analog Input 3. For the AD7606-4, this is an AGND pin. 54 AI GND/ V3GND V3GND AGND Analog Input Ground Pin. For the AD7606-4, this is an AGND pin. GND 55 AI/GND V4 AGND AGND Analog Input 4. For the AD7606-6 and the AD7606-4, this is an AGND pin. 56 AI GND/ V4GND AGND AGND Analog Input Ground Pin. For the AD7606-6 and AD7606-4, this is an GND AGND pin. 57 AI V5 V4 V3 Analog Inputs. These pins are single-ended analog inputs. The analog input range of these channels is determined by the RANGE pin. 58 AI GND V5GND V4GND V3GND Analog Input Ground Pins. All analog input AGND pins should connect to the AGND plane of a system. 59 AI V6 V5 V4 Analog Inputs. These pins are single-ended analog inputs. 60 AI GND V6GND V5GND V4GND Analog Input Ground Pins. All analog input AGND pins should connect to the AGND plane of a system. 61 AI/GND V7 V6 AGND Analog Input Pins. For the AD7606-4, this is an AGND pin. 62 AI GND/ V7GND V6GND AGND Analog Input Ground Pins. For the AD7606-4, this is an AGND pin. GND 63 AI/GND V8 AGND AGND Analog Input Pin. For the AD7606-4 and AD7606-6, this is an AGND pin. 64 AI GND/ V8GND AGND AGND Analog Input Ground Pin. For the AD7606-4 and AD7606-6, this is an GND AGND pin. 1 P is power supply, DI is digital input, DO is digital output, REF is reference input/output, AI is analog input, GND is ground. Rev. E | Page 16 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 TYPICAL PERFORMANCE CHARACTERISTICS Temperature range is from −40°C to +85°C. The AD7606 is functional up to 105°C with throughput rates < 160 kSPS. Specifications are guaranteed for the operating temperature range of −40°C to +85°C only. 0 2.0 AVCC, VDRIVE = 5V AVCC, VDRIVE = 5V –20 I±N1T0EVR RNAANLG REEFERENCE 1.5 FTSAA =M 2P5L°EC = 200kSPS FSAMPLE = 200kSPS INTERNAL REFERENCE –40 FIN = 1kHz 1.0 ±10V RANGE 16,384 POINT FFT dB) –60 STHNDR == –9100.167.2d5BdB 0.5 DE ( –80 SB) LITU –100 NL (L 0 P I M –0.5 A –120 –1.0 –140 –160 –1.5 –1800 10k 20k 30IkNPU4T0 kFRE5Q0kUEN6C0Yk (Hz7)0k 80k 90k 100k 08479-011 –2.00 10k 20k 30CkODE 40k 50k 60k 08479-013 Figure 11. AD7606 FFT, ±10 V Range Figure 14. AD7606 Typical INL, ±10 V Range 0 1.0 AVCC, VDRIVE = 5V AVCC, VDRIVE = 5V –20 I±N5TVE RRANNAGLE REFERENCE 0.8 TFSAA =M 2P5L°EC = 200kSPS –40 FFSINA M= P1LkEH =z 200kSPS 0.6 I±N1T0EVR RNAANLG REEFERENCE 16,384 POINT FFT LITUDE (dB) –1––086000 STHNDR == –8190.488.6d5BdB NL (LSB) 00..420 MP D –0.2 A –120 –0.4 –140 –0.6 –160 –0.8 –1800 10k 20k 30IkNPU4T0 kFRE5Q0kUEN6C0Yk (Hz7)0k 80k 90k 100k 08479-012 –1.00 10k 20k 30CkODE 40k 50k 60k 08479-014 Figure 12. AD7606 FFT Plot, ±5 V Range Figure 15. AD7606 Typical DNL, ±10 V Range 0 2.0 –10 AVCC, VDRIVE = 5V AVCC, VDRIVE = 5V INTERNAL REFERENCE INTERNAL REFERENCE –20 ±10V RANGE 1.5 ±5V RANGE –30 FSAMPLE = 11.5kSPS FSAMPLE = 200kSPS –40 TA = 25°C 1.0 TA = 25°C –50 FIN = 133Hz dB) ––6700 8O1S9 2B YP O1I6NT FFT 0.5 LITUDE ( –1––089000 STHNDR == –9160.081.0d5BdB NL (LSB) 0 MP –110 I –0.5 A –120 –130 –1.0 –140 –150 –160 –1.5 –170 –1800 0.5 1.0 1.5 2.F0RE2Q.5UEN3C.0Y (k3H.5z) 4.0 4.5 5.0 5.5 08479-031 –2.00 8192 16,384 24,576 3C2O,7D6E8 40,960 49,152 57,344 65,536 08479-015 Figure 13. FFT Plot Oversampling By 16, ±10 V Range Figure 16. AD7606 Typical INL, ±5 V Range Rev. E | Page 17 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet 1.00 10 AVCC, VDRIVE = 5V INTERNAL REFERENCE 8 00..5705 ±FT5SAVA =M R 2PA5LN°EC G=E 200kSPS G (LSB) 6 PFS ERROR N 4 HI B) 0.25 ATC 2 NFS ERROR S M NL (L 0 NEL 0 D–0.25 HAN –2 C S –4 –0.50 PF S/ –6 F –0.75 N 10V RANGE –9 AVCC, VDRIVE = 5V EXTERNAL REFERENCE –1.000 8192 16,384 24,576 3C2O,7D6E8 40,960 49,152 57,344 65,536 08479-016 –10–40 –25 –10 T5EMPER20ATURE3 5(°C) 50 65 80 08479-018 Figure 17. AD7606 Typical DNL, ±5 V Range Figure 20. NFS and PFS Error Matching 20 10 15 8 10 B) ±10V RANGE %FS) 6 ERROR (LS 50 ±5V RANGE S ERROR ( 4 NFS –5 FS/NF 2 AVCC, VDRIVE = 5V –10 P FSAMPLE = 200 kSPS TA = 25°C 0 EXTERNAL REFERENCE –15 200kSPS SOURCE RESISTANCE IS MATCHED ON AVCC, VDRIVE = 5V THE VxGND INPUT EXTERNAL REFERENCE ±10V AND ±5V RANGE –20–40 –25 –10 T5EMPER20ATURE3 5(°C) 50 65 80 08479-017 –20 20k S4O0UkRCE RE6S0kISTANCE8 0(kΩ) 100k 120k 08479-019 Figure 18. NFS Error vs. Temperature Figure 21. PFS and NFS Error vs. Source Resistance 20 1.0 0.8 15 B) LS 0.6 10 R ( O 0.4 R (LSB) 5 DE ERR 0.2 RO 0 CO 0 PFS ER –5 ±10V RA±N5GVE RANGE AR ZERO ––00..42 5V RANGE –10 L 10V RANGE O P –0.6 –15 200kSPS BI 200kSPS AVCC, VDRIVE = 5V –0.8 AVCC, VDRIVE = 5V EXTERNAL REFERENCE EXTERNAL REFERENCE –20–40 –25 –10 T5EMPER20ATURE3 5(°C) 50 65 80 08479-118 –1.0–40 –25 –10 T5EMPER20ATURE3 5(°C) 50 65 80 08479-023 Figure 19. PFS Error vs. Temperature Figure 22. Bipolar Zero Code Error vs. Temperature Rev. E | Page 18 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 4 98 B) S G (L 3 96 HIN 5V RANGE 94 C 2 T A M 92 R 1 DE ERRO 0 10V RANGE SNR (dB) 9808 CO –1 O 86 R OS BY 64 E –2 OS BY 32 AR Z 84 OOSS BBYY 186 AFSVACMCP, LVED CRIHVEA N=G 5EVS WITH OS RATE POL –3 2A0V0CkCS,P VSDRIVE = 5V 82 OOSS BBYY 24 TINAT =E R25N°ACL REFERENCE BI EXTERNAL REFERENCE NO OS ±5V RANGE –4–40 –25 –10 T5EMPER20ATURE3 5(°C) 50 65 80 08479-024 8010 100 INPUT FRE1QkUENCY (Hz) 10k 100k 08479-020 Figure 23. Bipolar Zero Code Error Matching Between Channels Figure 26. SNR vs. Input Frequency for Different Oversampling Rates, ±5 V Range –40 100 ±10V RANGE AVCC, VDRIVE = +5V 98 –50 FSAMPLE = 200kSPS RSOURCE MATCHED ON Vx AND VxGND INPUTS 96 –60 94 –70 B) B) 92 d d D ( –80 R ( 90 H N T 105kΩ S 88 –90 48.7kΩ 23.7kΩ 86 OS BY 64 –100 10kΩ OS BY 32 51k.2ΩkΩ 84 OOSS BBYY 186 AFSVACMCP, LVED CRIHVEA N=G 5EVS WITH OS RATE –110 15010ΩΩ 82 OOSS BBYY 24 ITNAT =E R25N°ACL REFERENCE 0Ω NO OS ±10V RANGE –1201k INPUT FRE1Q0kUENCY (Hz) 100k 08479-021 8010 100 INPUT FRE1QkUENCY (Hz) 10k 100k 08479-121 Figure 24. THD vs. Input Frequency for Various Source Impedances, Figure 27. SNR vs. Input Frequency for Different Oversampling Rates, ±10 V Range ±10 V Range –40 –50 ±5V RANGE AVCC, VDRIVE = 5V –50 AFRSVSAOCMUCPR, LCVEED =RM IV2AE0T0 =Ck SH+P5EVSD ON Vx AND VxGND INPUTS N (dB) –60 IAFNSDTA7EM6RP0LN6E AR =LE C1R5OE0FMkESMRPEESNNDCEED DECOUPLING USED –60 ATIO –70 TINAT =E R25F°ECRER ON ALL UNSELECTED CHANNELS OL –80 –70 S dB) EL I –90 D ( –80 NN ±10V RANGE H A –100 T –90 1420835..77kkkΩΩΩ TO-CH –110 ±5V RANGE –100 10kΩ EL- 5kΩ N –120 1.2kΩ AN –110 100Ω CH –130 51Ω 0Ω –1201k INPUT FRE1Q0kUENCY (Hz) 100k 08479-122 –1400 20 40 NOIS60E FREQ80UENCY10 (0kHz)120 140 160 08479-025 Figure 25. THD vs. Input Frequency for Various Source Impedances, Figure 28. Channel-to-Channel Isolation ±5 V Range Rev. E | Page 19 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet 100 22 98 ±10V RANGE 20 96 A) m DYNAMIC RANGE (dB) 9998842086 ±5V RANGE SUPPLY CURRENT (CC 11118642 V 84 AVCC, VDRIVE = 5V A AVCC, VDRIVE = 5V TA = 25°C 10 TA = 25°C 82 INTERNAL REFERENCE INTERNAL REFERENCE FSAMPLE SCALES WITH OS RATIO FSAMPLE VARIES WITH OS RATE 80 OFF OS2 OOVSE4RSAMOPSL8ING ROAST1IO6 OS32 OS64 08479-026 N8O OS OS2 OOSV4ERSAMOPSL8ING RAOTSIO16 OS32 OS6408479-027 Figure 29. Dynamic Range vs. Oversampling Rate Figure 32. Supply Current vs. Oversampling Rate 2.5010 140 dB) 130 2.5005 AVCC = 5.25V O ( V) AVCC = 5V RATI 120 ±10V RANGE AGE (2.5000 TION 110 LT EC ±5V RANGE UT VO2.4995 AVCC = 4.75V Y REJ 100 REFO2.4990 SUPPL 90 R 80 AVCC, VDRIVE = 5V E INTERNAL REFERENCE 2.4985 OW 70 AD7606 RECOMMENDED DECOUPLING USED P FSAMPLE = 200kSPS TA = 25°C 2.4980–40 –25 –10 T5EMPER20ATURE3 5(°C) 50 65 80 08479-029 600 100 200 3A0V0CC 4N0O0ISE50 F0RE6Q0U0EN7C00Y (k8H0z0) 900 1000 1100 08479-030 Figure 30. Reference Output Voltage vs. Temperature for Figure 33. PSRR Different Supply Voltages 8 AVCC, VDRIVE = 5V 6 FSAMPLE = 200kSPS 4 A) µ 2 T ( N E 0 R R U C –2 T U NP –4 I –6 +85°C –8 +25°C –40°C –10–10 –8 –6 –4 INP–U2T VO0LTAG2E (V) 4 6 8 10 08479-028 Figure 31. Analog Input Current vs. Temperature for Various Supply Voltages Rev. E | Page 20 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 TERMINOLOGY Integral Nonlinearity Total Harmonic Distortion (THD) The maximum deviation from a straight line passing through The ratio of the rms sum of the harmonics to the fundamental. the endpoints of the ADC transfer function. The endpoints of For the AD7606/AD7606-6/AD7606-4, it is defined as the transfer function are zero scale, at ½ LSB below the first THD (dB) = code transition; and full scale, at ½ LSB above the last code V 2+V 2+V 2+V 2+V 2+V 2+V2+V2 transition. 20log 2 3 4 5 6 7 8 9 V Differential Nonlinearity 1 where: The difference between the measured and the ideal 1 LSB V is the rms amplitude of the fundamental. change between any two adjacent codes in the ADC. 1 V to V are the rms amplitudes of the second through ninth 2 9 Bipolar Zero Code Error harmonics. The deviation of the midscale transition (all 1s to all 0s) from Peak Harmonic or Spurious Noise the ideal, which is 0 V − ½ LSB. The ratio of the rms value of the next largest component in the Bipolar Zero Code Error Match ADC output spectrum (up to f/2, excluding dc) to the rms value S The absolute difference in bipolar zero code error between any of the fundamental. Normally, the value of this specification is two input channels. determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is Positive Full-Scale Error determined by a noise peak. The deviation of the actual last code transition from the ideal Intermodulation Distortion last code transition (10 V − 1½ LSB (9.99954) and 5 V − 1½ LSB (4.99977)) after bipolar zero code error is adjusted out. The With inputs consisting of sine waves at two frequencies, fa and fb, positive full-scale error includes the contribution from the any active device with nonlinearities creates distortion products internal reference buffer. at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which Positive Full-Scale Error Match neither m nor n is equal to 0. For example, the second-order The absolute difference in positive full-scale error between any terms include (fa + fb) and (fa − fb), and the third-order terms two input channels. include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). Negative Full-Scale Error The calculation of the intermodulation distortion is per the The deviation of the first code transition from the ideal first THD specification, where it is the ratio of the rms sum of the code transition (−10 V + ½ LSB (−9.99984) and −5 V + ½ LSB individual distortion products to the rms amplitude of the sum (−4.99992)) after the bipolar zero code error is adjusted out. of the fundamentals expressed in decibels (dB). The negative full-scale error includes the contribution from the Power Supply Rejection Ratio (PSRR) internal reference buffer. Variations in power supply affect the full-scale transition but not Negative Full-Scale Error Match the converter’s linearity. PSR is the maximum change in full- The absolute difference in negative full-scale error between any scale transition point due to a change in power supply voltage two input channels. from the nominal value. The PSR ratio (PSRR) is defined as the Total Unadjusted Error (TUE) ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC’s TUE is a comprehensive specification that includes the gain V and V supplies of Frequency f. DD SS S linearity and offset errors. PSRR (dB) = 10 log (Pf/Pf) Signal-to-(Noise + Distortion) Ratio S where: The measured ratio of signal-to-(noise + distortion) at the Pf is equal to the power at Frequency f in the ADC output. output of the ADC. The signal is the rms amplitude of the Pf is equal to the power at Frequency f coupled onto the AV fundamental. Noise is the sum of all nonfundamental signals S S CC supply. up to half the sampling frequency (f/2, excluding dc). S Channel-to-Channel Isolation The ratio depends on the number of quantization levels in Channel-to-channel isolation is a measure of the level of crosstalk the digitization process: the more levels, the smaller the between all input channels. It is measured by applying a full-scale quantization noise. sine wave signal, up to 160 kHz, to all unselected input channels The theoretical signal-to-(noise + distortion) ratio for an ideal and then determining the degree to which the signal attenuates N-bit converter with a sine wave input is given by in the selected channel with a 1 kHz sine wave signal applied (see Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Figure 28). Thus, for a 16-bit converter, the signal-to-(noise + distortion) is 98 dB. Rev. E | Page 21 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet THEORY OF OPERATION CONVERTER DETAILS Analog Input Clamp Protection The AD7606/AD7606-6/AD7606-4 are data acquisition systems Figure 34 shows the analog input structure of the AD7606/ that employ a high speed, low power, charge redistribution, AD7606-6/AD7606-4. Each analog input of the AD7606/ successive approximation analog-to-digital converter (ADC) AD7606-6/AD7606-4 contains clamp protection circuitry. and allow the simultaneous sampling of eight/six/four analog input Despite single 5 V supply operation, this analog input clamp channels. The analog inputs on the AD7606/AD7606-6/AD7606-4 protection allows for an input over voltage of up to ±16.5 V. can accept true bipolar input signals. The RANGE pin is used to RFB select either ±10 V or ±5 V as the input range. The AD7606/ 1MΩ AD7606-6/AD7606-4 operate from a single 5 V supply. Vx CLAMP 1MΩ The AD7606/AD7606-6/AD7606-4 contain input clamp VxGND CLAMP palrioatseinctgi ofinlt, eirn, ptruatc skig-annadl -shcaollidn gam amplpifliiefiresr, sa,n a osnec-ochnidp- orerfdeerre nanceti,- RFB SOERCLPDOFENRD- 08479-032 Figure 34. Analog Input Circuitry reference buffers, a high speed ADC, a digital filter, and high Figure 35 shows the voltage vs. current characteristic of the speed parallel and serial interfaces. Sampling on the AD7606/ clamp circuit. For input voltages of up to ±16.5 V, no current AD7606-6/AD7606-4 is controlled using the CONVST signals. flows in the clamp circuit. For input voltages that are above ±16.5 V, ANALOG INPUT the AD7606/AD7606-6/AD7606-4 clamp circuitry turns on. Analog Input Ranges The AD7606/AD7606-6/AD7606-4 can handle true bipolar, 30 ATAV C=C 2, 5V°DCRIVE = 5V single-ended input voltages. The logic level on the RANGE pin 20 determines the analog input range of all analog input channels. mA) If this pin is tied to a logic high, the analog input range is ±10 V NT ( 10 E for all channels. If this pin is tied to a logic low, the analog input RR 0 U range is ±5 V for all channels. A logic change on this pin has an C P –10 immediate effect on the analog input range; however, there is AM typically a settling time of approximately 80 μs, in addition to T CL –20 U the normal acquisition time requirement. The recommended NP –30 I practice is to hardwire the RANGE pin according to the desired –40 input range for the system signals. –50 Dshuoruinldg rneomramina lw oiptherinat tiohne ,a tnhael oagp pinlipeudt a rnaanlgoeg sienlpeuctte vdo vltiaag teh e –20 –15 –10 SO–U5RCE VO0LTAGE5 (V) 10 15 20 08479-033 RANGE pin. A RESET pulse must be applied after power up to Figure 35. Input Protection Clamp Profile ensure the analog input channels are configured for the range A series resistor should be placed on the analog input channels selected. to limit the current to ±10 mA for input voltages above ±16.5 V. When in a power-down mode, it is recommended to tie the In an application where there is a series resistance on an analog analog inputs to GND. Per the Analog Input Clamp Protection input channel, Vx, a corresponding resistance is required on the section, the overvoltage clamp protection is recommended for analog input GND channel, VxGND (see Figure 36). If there is use in transient overvoltage conditions and should not remain no corresponding resistor on the VxGND channel, an offset active for extended periods. Stressing the analog inputs outside error occurs on that channel. It is recommended that the input of the conditions mentioned here may degrade the bipolar zero overvoltage clamp protection circuitry be used to protect the code error and THD performance of the AD7606/AD7606-6/ AD7606/AD7606-6/AD7606-4 against transient overvoltage AD7606-4. events. It is not recommended to leave the AD7606/AD7606-6/ AD7606-4 in a condition where the clamp protection circuitry Analog Input Impedance is active in normal or power-down conditions for extended The analog input impedance of the AD7606/AD7606-6/ periods because this may degrade the bipolar zero code error AD7606-4 is 1 MΩ. This is a fixed input impedance that does performance of the AD7606/AD7606-6/AD7606-4. not vary with the AD7606 sampling frequency. This high analog input impedance eliminates the need for a driver amplifier in front of the AD7606/AD7606-6/AD7606-4, allowing for direct connection to the source or sensor. With the need for a driver amplifier eliminated, bipolar supplies (which are often a source of noise in a system) can be removed from the signal chain. Rev. E | Page 22 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 hold (that is, the delay time between the external CONVST x AD7606 RFB signal and the track-and-hold actually going into hold) is well ANALOG R Vx 1MΩ INPUT CLAMP matched, by design, across all eight track-and-holds on one SIGNAL R C VxGND 1MΩ device and from device to device. This matching allows more CLAMP RFB 08479-034 tshimanu lotannee AouDs7ly6 0in6 /aA sDys7t6e0m6.- 6/AD7606-4 device to be sampled Figure 36. Input Resistance Matching on the Analog Input of the The end of the conversion process across all eight channels is AD7606/AD7606-6/AD7606-4 indicated by the falling edge of BUSY; and it is at this point that the Analog Input Antialiasing Filter track-and-holds return to track mode, and the acquisition time An analog antialiasing filter (a second-order Butterworth) is also for the next set of conversions begins. provided on the AD7606/AD7606-6/AD7606-4. Figure 37 and The conversion clock for the part is internally generated, and Figure 38 show the frequency and phase response, respectively, the conversion time for all channels is 4 μs on the AD7606, of the analog antialiasing filter. In the ±5 V range, the −3 dB 3 μs on the AD7606-6, and 2 μs on the AD7606-4. On the AD7606, frequency is typically 15 kHz. In the ±10 V range, the −3 dB the BUSY signal returns low after all eight conversions to indicate frequency is typically 23 kHz. the end of the conversion process. On the falling edge of BUSY, 5 the track-and-hold amplifiers return to track mode. New data can be read from the output register via the parallel, parallel 0 ±10V RANGE byte, or serial interface after BUSY goes low; or, alternatively, B) –1–05 AFTSAVA C=MC 2P, 5LV°EDC =R IV2E00 =k S5VPS ±5V RANGE dhaigtah .f rRoemad tihneg pdraetvai foruosm c othnev eArDsio7n60 c6a/nA bDe7 r6e0a6d- 6w/AhiDle7 B60U6S-Y4 is d N ( while a conversion is in progress has little effect on performance O –15 TI and allows a faster throughput to be achieved. In parallel mode A NU –20 ±10V RANGE 0.1dB 3dB at V > 3.3 V, the SNR is reduced by ~1.5 dB when reading TE –40 10,303 24,365Hz DRIVE AT –25 +25 9619 23,389Hz during a conversion. +85 9326 22,607Hz –30 ADC TRANSFER FUNCTION ±5V RANGE 0.1dB 3dB –40 5225 16,162Hz –35 +25 5225 15,478Hz The output coding of the AD7606/AD7606-6/AD7606-4 is +85 4932 14,990Hz twos complement. The designed code transitions occur midway –40 100 IN1kPUT FREQUENCY (1H0zk) 100k 08479-035 bTehtew LeeSnB s suiczcee isss iFvSeR in/6te5g,e5r3 L6 SfBo rv tahluee As, Dth7a6t 0is6,. 1 T/2h eL SidBe aanl dtr 3a/n2s fLeSrB . Figure 37. Analog Antialiasing Filter Frequency Response characteristic for the AD7606/AD7606-6/AD7606-4 is shown in Figure 39. 18 VIN REF ±10V CODE = × 32,768 × 16 10V 2.5V ±5V RANGE VIN REF 14 ±5V CODE = × 32,768 × 5V 2.5V 12 011...111 011...110 LAY (µs) 1086 ±10V RANGE C CODE000000......000010 LSB =+FS 2–1 (6–FS) E DE 4 AD111...111 HAS 2 100...010 P 0 100...001 100...000 –2 –FS + 1/2LSB 0V – 1/2LSB+FS – 3/2LSB –4 AVCC, VDRIVE = 5V ANALOG INPUT ––6810FTSAA =M 2P5L°EC = 200kSPIS1NkPUT FREQUENCY (1H0zk) 100k 08479-036 Figu±±15reV0V 3R 9RA.AN ANGDGE7E60+++651F/V0SAVD76000M6VVID-6S/CAADL7E606–––51F-4V0S VTransfe13Lr50S C25BµµhVVaracterist08479-037ic s Figure 38. Analog Antialias Filter Phase Response The LSB size is dependent on the analog input range selected. Track-and-Hold Amplifiers The track-and-hold amplifiers on the AD7606/AD7606-6/ AD7606-4 allow the ADC to accurately acquire an input sine wave of full-scale amplitude to 16-bit resolution. The track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of CONVST x. The aperture time for the track-and- Rev. E | Page 23 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet INTERNAL/EXTERNAL REFERENCE Internal Reference Mode The AD7606/AD7606-6/AD7606-4 contain an on-chip 2.5 V One AD7606/AD7606-6/AD7606-4 device, configured to operate band gap reference. The REFIN/REFOUT pin allows access to in the internal reference mode, can be used to drive the remaining the 2.5 V reference that generates the on-chip 4.5 V reference AD7606/AD7606-6/AD7606-4 devices, which are configured to internally, or it allows an external reference of 2.5 V to be applied operate in external reference mode (see Figure 42). The REFIN/ to the AD7606/AD7606-6/AD7606-4. An externally applied REFOUT pin of the AD7606/AD7606-6/AD7606-4, configured reference of 2.5 V is also gained up to 4.5 V, using the internal in internal reference mode, should be decoupled using a 10 μF buffer. This 4.5 V buffered reference is the reference used by the ceramic decoupling capacitor. The other AD7606/AD7606-6/ SAR ADC. AD7606-4 devices, configured in external reference mode, should use at least a 100 nF decoupling capacitor on their The REF SELECT pin is a logic input pin that allows the user to REFIN/REFOUT pins. select between the internal reference and an external reference. If this pin is set to logic high, the internal reference is selected REFIN/REFOUT and enabled. If this pin is set to logic low, the internal reference SAR is disabled and an external reference voltage must be applied REFCAPA BUF to the REFIN/REFOUT pin. The internal reference buffer is 10µF always enabled. After a reset, the AD7606/AD7606-6/AD7606-4 REFCAPB operate in the reference mode selected by the REF SELECT pin. 2.5V Dtheec ionuteprlinnagl aisn rde qexutierernda ol nre tfheere RnEceF IoNp/tiRoEnFs.O AU 1T0 pμiFn cfoerra bmoitch REF 08479-038 capacitor is required on the REFIN/REFOUT pin. Figure 40. Reference Circuitry The AD7606/AD7606-6/AD7606-4 contain a reference buffer configured to gain the REF voltage up to ~4.5 V, as shown in AD7606 AD7606 AD7606 Figure 40. The REFCAPA and REFCAPB pins must be shorted REF SELECT REF SELECT REF SELECT together externally, and a ceramic capacitor of 10 μF applied to REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT REFGND, to ensure that the reference buffer is in closed-loop operation. The reference voltage available at the REFIN/REFOUT 100nF 100nF 100nF pin is 2.5 V. ADR421 Wextheernn atlh ree AfeDre7n6c0e6 m/AoDde7,6 t0h6e- 6R/EAFDIN76/R06E-F4O aUreT c opninfi gisu ar ehdi ginh 0.1µF 08479-040 Figure 41. Single External Reference Driving Multiple AD7606/AD7606-6/ input impedance pin. For applications using multiple AD7606 AD7606-4 REFIN Pins devices, the following configurations are recommended, depending on the application requirements. VDRIVE External Reference Mode AD7606 AD7606 AD7606 One ADR421 external reference can be used to drive the REF SELECT REF SELECT REF SELECT REFIN/REFOUT pins of all AD7606 devices (see Figure 41). REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT In this configuration, each REFIN/REFOUT pin of the AD7606/AD7606-6/AD7606-4 should be decoupled with at + 10µF 100nF 100nF least a 100 nF decoupling capacitor. 08479-039 Figure 42. Internal Reference Driving Multiple AD7606/AD7606-6/AD7606-4 REFIN Pins Rev. E | Page 24 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 TYPICAL CONNECTION DIAGRAM The power-down mode is selected through the state of the RANGE pin when the STBY pin is low. Table 7 shows the Figure 43 shows the typical connection diagram for the AD7606/ configurations required to choose the desired power-down mode. AD7606-6/AD7606-4. There are four AV supply pins on the CC When the AD7606/AD7606-6/AD7606-4 are placed in standby part, and each of the four pins should be decoupled using a 100 nF mode, the current consumption is 8 mA maximum and power- capacitor at each supply pin and a 10 µF capacitor at the supply up time is approximately 100 µs because the capacitor on the source. The AD7606/AD7606-6/AD7606-4 can operate with the internal reference or an externally applied reference. In this REFCAPA and REFCAPB pins must charge up. In standby mode, configuration, the AD7606 is configured to operate with the the on-chip reference and regulators remain powered up, and the amplifiers and ADC core are powered down. internal reference. When using a single AD7606/AD7606-6/ AD7606-4 device on the board, the REFIN/REFOUT pin When the AD7606/AD7606-6/AD7606-4 are placed in shutdown should be decoupled with a 10 µF capacitor. Refer to the mode, the current consumption is 6 µA maximum and power-up Internal/External Reference section when using an application time is approximately 13 ms (external reference mode). In shut- with multiple AD7606/AD7606-6/AD7606-4 devices. The down mode, all circuitry is powered down. When the AD7606/ REFCAPA and REFCAPB pins are shorted together and AD7606-6/AD7606-4 are powered up from shutdown mode, decoupled with a 10 µF ceramic capacitor. a RESET signal must be applied to the AD7606/AD7606-6/ The V supply is connected to the same supply as the AD7606-4 after the required power-up time has elapsed. DRIVE processor. The V voltage controls the voltage value of the DRIVE Table 7. Power-Down Mode Selection output logic signals. For layout, decoupling, and grounding Power-Down Mode STBY RANGE hints, see the Layout Guidelines section. Standby 0 1 After supplies are applied to the AD7606/AD7606-6/AD7606-4, Shutdown 0 0 a reset should be applied to the AD7606/AD7606-6/AD7606-4 to ensure that it is configured for the correct mode of operation. POWER-DOWN MODES Two power-down modes are available on the AD7606/AD7606-6/ AD7606-4: standby mode and shutdown mode. The STBY pin controls whether the AD7606/AD7606-6/AD7606-4 are in normal mode or in one of the two power-down modes. ANALOG SUPPLY DIGITAL SUPPLY VOLTAGE 5V1 VOLTAGE +2.3V TO +5.25V + 10µF 1µF 100nF 100nF REFIN/REFOUT REGCAP2 AVCC VDRIVE R/R/ OE REFCAPA ST 10µF+ REFCAPB DB0 TO DB15 IPNATREARLFLAECLE ROCESONVERDSP REFGND CONVST A, CONVST B PC OO CS RR V1 CC V1GND RD MIMI V2 AD7606 BUSY V2GND RESET V3 V3GND OS 2 OS 1 OVERSAMPLING EIGHT ANALOG V4 OS 0 INPUTS V1 TO V8 V4GND VV55GND REF SELECT VDRIVE V6 PAR/SER SEL V6GND V7 RANGE V7GND STBY VDRIVE V8 V8GND AGND 12DDDEEECCCOOOUUUPPPLLLIIINNNGGG CSSHHAOOPAWWCNNIT OOONNR TTCHHAEEN AR BVEECG CSC HPAAIPNR PAEIPNDP ABLPEIEPTSWL ITEEOSE NET OAAC VEHCAC AC PVHIC NRC E 3PG7I NCA AN(PPDI NPP II1NN, P(3P8INI.N 3 376, ,P PININ 3 389, )P.IN 48). 08479-041 Figure 43. AD7606 Typical Connection Diagram Rev. E | Page 25 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet CONVERSION CONTROL transformers. In a 50 Hz system, this allows for up to 9° of phase compensation; and in a 60 Hz system, it allows for up to 10° of Simultaneous Sampling on All Analog Input Channels phase compensation. The AD7606/AD7606-6/AD7606-4 allow simultaneous sampling of all analog input channels. All channels are sampled simul- This is accomplished by pulsing the two CONVST pins taneously when both CONVST pins (CONVST A, CONVST B) independently and is possible only if oversampling is not in use. are tied together. A single CONVST signal is used to control both CONVST A is used to initiate simultaneous sampling of the CONVST x inputs. The rising edge of this common CONVST first set of channels (V1 to V4 for the AD7606, V1 to V3 for the signal initiates simultaneous sampling on all analog input channels AD7606-6, and V1 and V2 for the AD7606-4); and CONVST B (V1 to V8 for the AD7606, V1 to V6 for the AD7606-6, and V1 is used to initiate simultaneous sampling on the second set of to V4 for the AD7606-4). analog input channels (V5 to V8 for the AD7606, V4 to V6 for the AD7606-6, and V3 and V4 for the AD7606-4), as illustrated The AD7606 contains an on-chip oscillator that is used to in Figure 44. On the rising edge of CONVST A, the track-and- perform the conversions. The conversion time for all ADC hold amplifiers for the first set of channels are placed into hold channels is t . The BUSY signal indicates to the user when CONV mode. On the rising edge of CONVST B, the track-and-hold conversions are in progress, so when the rising edge of CONVST amplifiers for the second set of channels are placed into hold is applied, BUSY goes logic high and transitions low at the end mode. The conversion process begins once both rising edges of the entire conversion process. The falling edge of the BUSY of CONVST x have occurred; therefore BUSY goes high on the signal is used to place all eight track-and-hold amplifiers back rising edge of the later CONVST x signal. In Table 3, Time t 5 into track mode. The falling edge of BUSY also indicates that indicates the maximum allowable time between CONVST x the new data can now be read from the parallel bus (DB[15:0]), sampling points. the D A and D B serial data lines, or the parallel byte bus, OUT OUT There is no change to the data read process when using two DB[7:0]. separate CONVST x signals. Simultaneously Sampling Two Sets of Channels Connect all unused analog input channels to AGND. The results The AD7606/AD7606-6/AD7606-4 also allow the analog input for any unused channels are still included in the data read because channels to be sampled simultaneously in two sets. This can be all channels are always converted. used in power-line protection and measurement systems to compensate for phase differences introduced by PT and CT V1 TO V4 TRACK-AND-HOLD ENTER HOLD V5 TO V8 TRACK-AND-HOLD ENTER HOLD CONVST A t5 CONVST B AD7606 CONVERTS ON ALL 8 CHANNELS BUSY tCONV CS/RD DATA: DB[15:0] V1 V2 V3 V7 V8 FRSTDATA 08479-042 Figure 44. AD7606 Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B Signals—Parallel Mode Rev. E | Page 26 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 DIGITAL INTERFACE The AD7606/AD7606-6/AD7606-4 provide three interface When the RD signal is logic low, it enables the data conversion options: a parallel interface, a high speed serial interface, and result from each channel to be transferred to the digital host a parallel byte interface. The required interface mode is selected (DSP, FPGA). via the PAR/SER/BYTE SEL and DB15/BYTE SEL pins. When there is only one AD7606/AD7606-6/AD7606-4 in a system/board and it does not share the parallel bus, data can Table 8. Interface Mode Selection be read using just one control signal from the digital host. The PAR/SER/BYTE SEL DB15 Interface Mode CS and RD signals can be tied together, as shown in Figure 5. 0 0 Parallel interface mode In this case, the data bus comes out of three-state on the falling 1 0 Serial interface mode edge of CS/RD. The combined CS and RD signal allows the data 1 1 Parallel byte interface mode to be clocked out of the AD7606/AD7606-6/AD7606-4 and to Operation of the interface modes is discussed in the following be read by the digital host. In this case, CS is used to frame the sections. data transfer of each data channel. PARALLEL INTERFACE (PAR/SER/BYTE SEL = 0) PARALLEL BYTE (PAR/SER/BYTE SEL = 1, DB15 = 1) Data can be read from the AD7606/AD7606-6/AD7606-4 via Parallel byte interface mode operates much like the parallel the parallel data bus with standard CS and RD signals. To read the interface mode, except that each channel conversion result is read data over the parallel bus, the PAR/SER/BYTE SEL pin should out in two 8-bit transfers. Therefore, 16 RD pulses are required be tied low. The CS and RD input signals are internally gated to to read all eight conversion results from the AD7606. For the enable the conversion result onto the data bus. The data lines, AD7606-6, 12 RD pulses are required; and on the AD7606-4, DB15 to DB0, leave their high impedance state when both CS eight RD pulses are required to read all the channel results. and RD are logic low. To configure the AD7606/AD76706-6/AD7606-4 to operate in parallel byte mode, the PAR/SER/BYTE SEL and BYTE SEL/ AD7606 INTERRUPT BUSY 14 DB15 pins should be tied to logic high (see Table 8). In parallel CS 13 byte mode, DB[7:0] are used to transfer the data to the digital RD/SCLK 12 DIGITAL host. DB0 is the LSB of the data transfer, and DB7 is the MSB of DB[15:0] [[3232::2146]] HOST 08479-043 tphine .d Watha etnra DnsBfe1r4. /IHn BpEarNa lilse lt ibeydt et om loogdiec, hDiBgh1,4 t ahcet sm aoss at n HBEN Figure 45. AD7606 Interface Diagram—One AD7606 Using the Parallel Bus, significant byte (MSB) of the conversion result is output first, with CS and RD Shorted Together followed by the LSB of the conversion result. When DB14 is tied The rising edge of the CS input signal three-states the bus, and to logic low, the LSB of the conversion result is output first, the falling edge of the CS input signal takes the bus out of the followed by the MSB of the conversion result. The FRSTDATA high impedance state. CS is the control signal that enables the pin remains high until the entire 16 bits of the conversion result data lines; it is the function that allows multiple AD7606/ from V1 are read from the AD7606/AD7606-6/AD7606-4. AD7606-6/ AD7606-4 devices to share the same parallel SERIAL INTERFACE (PAR/SER/BYTE SEL = 1) data bus. To read data back from the AD7606 over the serial interface, the The CS signal can be permanently tied low, and the RD signal PAR/SER/BYTE SEL pin must be tied high. The CS and SCLK can be used to access the conversion results as shown in Figure 4. signals are used to transfer data from the AD7606. The AD7606/ A read operation of new data can take place after the BUSY AD7606-6/AD7606-4 have two serial data output pins, D A OUT signal goes low (see Figure 2); or, alternatively, a read operation and D B. Data can be read back from the AD7606/AD76706- OUT of data from the previous conversion process can take place 6/AD7606-4 using one or both of these D lines. For the OUT while BUSY is high (see Figure 3). AD7606, conversion results from Channel V1 to Channel V4 The RD pin is used to read data from the output conversion first appear on DOUTA, and conversion results from Channel V5 results register. Applying a sequence of RD pulses to the RD pin to Channel V8 first appear on DOUTB. For the AD7606-6, conversion results from Channel V1 to Channel V3 first appear of the AD7606/AD7606-6/AD7606-4 clocks the conversion on D A, and conversion results from Channel V4 to Channel results out from each channel onto the Parallel Bus DB[15:0] in OUT V6 first appear on D B. For the AD7606-4, conversion results ascending order. The first RD falling edge after BUSY goes low OUT from Channel V1 and Channel V2 first appear on D A, and clocks out the conversion result from Channel V1. The next RD OUT conversion results from Channels V3 and Channel V4 first falling edge updates the bus with the V2 conversion result, and so appear on D B. on. On the AD7606, the eighth falling edge of RD clocks out the OUT conversion result for Channel V8. Rev. E | Page 27 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet The CS falling edge takes the data output lines, D A and D B, The falling edge of CS takes the bus out of three-state and clocks OUT OUT out of three-state and clocks out the MSB of the conversion out the MSB of the 16-bit conversion result. This MSB is valid result. The rising edge of SCLK clocks all subsequent data bits on the first falling edge of the SCLK after the CS falling edge. onto the serial data outputs, DOUTA and DOUTB. The CS input The subsequent 15 data bits are clocked out of the AD7606/ can be held low for the entire serial read operation, or it can be AD7606-6/AD7606-4 on the SCLK rising edge. Data is valid on pulsed to frame each channel read of 16 SCLK cycles. Figure 46 the SCLK falling edge. To access each conversion result, 16 clock shows a read of eight simultaneous conversion results using two cycles must be provided to the AD7606/AD7606-6/AD7606-4. D lines on the AD7606. In this case, a 64 SCLK transfer is used OUT The FRSTDATA output signal indicates when the first channel, to access data from the AD7606, and CS is held low to frame the V1, is being read back. When the CS input is high, the FRSTDATA entire 64 SCLK cycles. Data can also be clocked out using just output pin is in three-state. In serial mode, the falling edge of one D line, in which case it is recommended that D A be OUT OUT CS takes FRSTDATA out of three-state and sets the FRSTDATA used to access all conversion data because the channel data is pin high, indicating that the result from V1 is available on the output in ascending order. For the AD7606 to access all eight D A output data line. The FRSTDATA output returns to OUT conversion results on one D line, a total of 128 SCLK cycles OUT a logic low following the 16th SCLK falling edge. If all channels is required. These 128 SCLK cycles can be framed by one CS are read on D B, the FRSTDATA output does not go high when OUT signal, or each group of 16 SCLK cycles can be individually V1 is being output on this serial data output pin. It goes high framed by the CS signal. The disadvantage of using just one only when V1 is available on D A (and this is when V5 is OUT DOUT line is that the throughput rate is reduced if reading occurs available on DOUTB for the AD7606). after conversion. The unused D line should be left unconnected OUT READING DURING CONVERSION in serial mode. For the AD7606, if D B is to be used as a single OUT D line, the channel results are output in the following order: Data can be read from the AD7606/AD7606-6/AD7606-4 while OUT V5, V6, V7, V8, V1, V2, V3, and V4; however, the FRSTDATA BUSY is high and the conversions are in progress. This has little indicator returns low after V5 is read on D B. For the AD7606-6 effect on the performance of the converter, and it allows a faster OUT and the AD7606-4, if D B is to be used as a single D line, throughput rate to be achieved. A parallel, parallel byte, or serial OUT OUT the channel results are output in the following order: V4, V5, V6, read can be performed during conversions and when oversampling V1, V2, and V3 for the AD7606-6; and V3, V4, V1, and V2 for may or may not be in use. Figure 3 shows the timing diagram for the AD7606-4. reading while BUSY is high in parallel or serial mode. Reading during conversions allows the full throughput rate to be achieved Figure 6 shows the timing diagram for reading one channel of when using the serial interface with V above 4.75 V. data, framed by the CS signal, from the AD7606/AD7606-6/ DRIVE AD7606-4 in serial mode. The SCLK input signal provides the Data can be read from the AD7606 at any time other than on clock source for the serial read operation. The CS goes low to the falling edge of BUSY because this is when the output data access the data from the AD7606/AD7606-6/AD7606-4. registers are updated with the new conversion data. Time t6, as outlined in Table 3, should be observed in this condition. CS 64 SCLK DOUTA V1 V2 V3 V4 DOUTB V5 V6 V7 V8 08479-044 Figure 46. AD7606 Serial Interface with Two DOUT Lines Rev. E | Page 28 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 DIGITAL FILTER tCYCLE The AD7606/AD7606-6/AD7606-4 contain an optional digital CONVST A AND tCONV first-order sinc filter that should be used in applications where CONVST B 19µs slower throughput rates are used or where higher signal-to-noise 9µs ratio or dynamic range is desirable. The oversampling ratio of the 4µs digital filter is controlled using the oversampling pins, OS [2:0] (see BUSY OS = 0 OS = 2 OS = 4 Table 9). OS 2 is the MSB control bit, and OS 0 is the LSB control bit. Table 9 provides the oversampling bit decoding to select the t4 t4 t4 different oversample rates. The OS pins are latched on the falling edge of BUSY. This sets the oversampling rate for the next CS conversion (see Figure 48). In addition to the oversampling function, the output result is decimated to 16-bit resolution. RD ICf OthNe VOSST p xin rsis ainreg seedt gteo tsaekleecst t ahne fOirSs tr asatimo polfe e fiogrh te,a tchhe cnheaxntn el, DBD[A15T:A0]: 08479-046 Figure 47. AD7606—No Oversampling, Oversampling × 2, and and the remaining seven samples for all channels are taken with Oversampling × 4 While Using Read After Conversion an internally generated sampling signal. These samples are then Figure 47 shows that the conversion time extends as the over- averaged to yield an improvement in SNR performance. Table 9 sampling rate is increased, and the BUSY signal lengthens for the shows typical SNR performance for both the ±10 V and the ±5 V different oversampling rates. For example, a sampling frequency range. As Table 9 shows, there is an improvement in SNR as the of 10 kSPS yields a cycle time of 100 μs. Figure 47 shows OS × 2 OS ratio increases. As the OS ratio increases, the 3 dB frequency and OS × 4; for a 10 kSPS example, there is adequate cycle time to is reduced, and the allowed sampling frequency is also reduced. further increase the oversampling rate and yield greater improve- In an application where the required sampling frequency is ments in SNR performance. In an application where the initial 10 kSPS, an OS ratio of up to 16 can be used. In this case, the sampling or throughput rate is at 200 kSPS, for example, and application sees an improvement in SNR, but the input 3 dB oversampling is turned on, the throughput rate must be reduced bandwidth is limited to ~6 kHz. to accommodate the longer conversion time and to allow for the The CONVST A and CONVST B pins must be tied/driven read. To achieve the fastest throughput rate possible when over- together when oversampling is turned on. When the over- sampling is turned on, the read can be performed during the sampling function is turned on, the BUSY high time for the BUSY high time. The falling edge of BUSY is used to update the conversion process extends. The actual BUSY high time output data registers with the new conversion data; therefore, the depends on the oversampling rate that is selected: the higher the reading of conversion data should not occur on this edge. oversampling rate, the longer the BUSY high, or total conversion time (see Table 3). CONVST A AND CONVST B OVERSAMPLE RATE LATCHED FOR CONVERSION N + 1 CONVERSION N CONVERSION N + 1 BUSY tOS_HOLD OS x tOS_SETUP 08479-045 Figure 48. OS x Pin Timing Table 9. Oversample Bit Decoding OS SNR 5 V Range SNR 10 V Range 3 dB BW 5 V Range 3 dB BW 10 V Range Maximum Throughput OS[2:0] Ratio (dB) (dB) (kHz) (kHz) CONVST Frequency (kHz) 000 No OS 89 90 15 22 200 001 2 91.2 92 15 22 100 010 4 92.6 93.6 13.7 18.5 50 011 8 94.2 95 10.3 11.9 25 100 16 95.5 96 6 6 12.5 101 32 96.4 96.7 3 3 6.25 110 64 96.9 97 1.5 1.5 3.125 111 Invalid Rev. E | Page 29 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet Figure 49 to Figure 55 illustrate the effect of oversampling on 1400 OVERSAMPLING BY 8 the code spread in a dc histogram plot. As the oversample rate FSAMPLE = 25kSPS 1263 1200 AVCC = 5V is increased, the spread of the codes is reduced. VDRIVE = 2.5V S E C1000 1000 N 900 NFASOVAC MOCPV =LE E5R V=S 2A0M0PkSLPINSG 928 887 CCURE 800 783 ES 800 VDRIVE = 2.5V OF O 600 CCURENC 670000 NUMBER 400 O 500 F 200 O R 400 NUMBE 230000 131 0 –03 –02 –21 CODE0 (LSB) 1 20 30 08479-050 97 Figure 52. Histogram of Codes—OS × 8 (Three Codes) 100 0 3 2 0 –3 –2 –1 CODE0 (LSB) 1 2 3 08479-047 11420000 OFASVVACEMCRP S=L EA5 MV= P1L2I.N5kGS PBSY 16 1453 Figure 49. Histogram of Codes—No OS (Six Codes) VDRIVE = 2.5V S E C1000 N 1400 OFSVAEMRPSLEA M= P1L0I0NkGSP BSY 2 CCURE 800 1200 VADVRCICV E= =5 V2.5V 1148 OF O 600 CURENCES1080000 804 NUMBER 400 595 C O 200 F O 600 R 0 0 0 0 0 NUMBE 400 0 –3 –2 –1 CODE0 (LSB) 1 2 3 08479-151 Figure 53. Histogram of Codes—OS × 16 (Two Codes) 200 80 0 –03 –02 –1 CODE0 (LSB) 1 126 30 08479-048 11640000 OFAVSDVVARCEMICVRP ES=L EA=5 MV=2. P56LV.1IN25Gk SBPYS 32 1417 Figure 50. Histogram of Codes—OS × 2 (Four Codes) ES1200 C N E R1000 1400 U S1200 VOFASDVVARCEMICVRP ES=L EA=5 MV=2. P55LV0IkNSGP SBY 4 1262 ER OF OCC 680000 631 E B C1000 M CUREN 800 764 NU 400 C 200 O UMBER OF 460000 0 –03 –02 –01 CODE0 (LSB) 1 20 30 08479-152 N Figure 54. Histogram of Codes—OS × 32 (Two Codes) 200 1600 Fig0ure– 0531. His–t02ogram1– 91ofC COoDdE0e (Ls—SBO) S1 × 4 (Fo23ur Cod30es) 08479-049 CES11420000 OFAVSDVVARCEMICVRP ES=L EA=5 MV=2. P53LVkISNPGS BY 64 1679 N E R1000 CU C O 800 F O ER 600 B M NU 400 369 200 0 0 0 0 0 0 –3 –2 –1 CODE0 (LSB) 1 2 3 08479-153 Figure 55. Histogram of Codes—OS × 64 (Two Codes) Rev. E | Page 30 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 When the oversampling mode is selected for the AD7606/ 0 AVCC = 5V AD7606-6/AD7606-4, it has the effect of adding a digital filter –10 VDRIVE = 5V TA = 25°C function after the ADC. The different oversampling rates and –20 10V RANGE OS BY 16 the CONVST sampling frequency produce different digital filter B) –30 frequency profiles. N (d –40 O Figure 56 to Figure 61 show the digital filter frequency profiles for ATI –50 U the different oversampling rates. The combination of the analog N E –60 T antialiasing filter and the oversampling digital filter can be used AT –70 to eliminate and reduce the complexity of the design of any filter –80 before the AD7606/AD7606-6/AD7606-4. The digital filtering –90 combines steep roll-off and linear phase response. –100 VTAADV RC=ICV 2 E=5 ° =5C V5V –100100 Figure 15k9. DigitaF1lR 0FEkiQltUeEr NRCeYs1 p(0Ho0zkn)se for O1SM 16 10M 08479-154 10V RANGE –20 OS BY 2 0 dB) –30 –10 AVDVRCICV E= =5 V5V N ( TA = 25°C O –40 –20 10V RANGE TI OS BY 32 A NU –50 B) –30 ATTE –60 ON (d –40 –70 UATI –50 N E –60 –80 TT A –70 –90100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 08479-051 ––8900 Figure 56. Digital Filter Response for OS 2 –100 VADVRCICV E= =5 V5V –100100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 08479-155 TA = 25°C Figure 60. Digital Filter Response for OS 32 –20 10V RANGE OS BY 4 0 dB) –30 –10 AVDVRCICV E= =5 V5V N ( –40 TA = 25°C ATIO –50 –20 1O0SV B RYA 6N4GE ATTENU ––6700 ON (dB) ––3400 ATI –50 –80 U N E –60 –90 TT A –70 –100100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 08479-052 ––9800 Figure 57. Digital Filter Response for OS 4 –100 VADVRCICV E= =5 V5V –100100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 08479-156 TA = 25°C Figure 61. Digital Filter Response for OS 64 –20 10V RANGE OS BY 8 B) –30 d N ( –40 O ATI –50 U N E –60 T T A –70 –80 –90 –100100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 08479-053 Figure 58. Digital Filter Response for OS 8 Rev. E | Page 31 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet LAYOUT GUIDELINES Figure 62 shows the recommended decoupling on the top layer of the AD7606 board. Figure 63 shows bottom layer decoupling, The printed circuit board that houses the AD7606/AD7606-6/ which is used for the four AV pins and the V pin decoupling. AD7606-4 should be designed so that the analog and digital CC DRIVE Where the ceramic 100 nF caps for the AV pins are placed sections are separated and confined to different areas of the board. CC close to their respective device pins, a single 100 nF capacitor At least one ground plane should be used. It can be common or can be shared between Pin 37 and Pin 38. split between the digital and analog sections. In the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably as close as possible to the AD7606/AD7606-6/AD7606-4. If the AD7606/AD7606-6/AD7606-4 are in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only one point: a star ground point that should be established as close as possible to the AD7606/AD7606-6/AD7606-4. Good connections should be made to the ground plane. Avoid sharing one connection for multiple ground pins. Use individual vias or multiple vias to the ground plane for each ground pin. Avoid running digital lines under the devices because doing so caolluopwleeds ntoo irsuen o unntod ethr eth deie A. TDh7e6 0a6n/aAloDg7 g6r0o6u-n6d/A pDla7n6e0 s6h-o4u tlod be 08479-054 avoid noise coupling. Fast switching signals like CONVST A, Figure 62. Top Layer Decoupling REFIN/REFOUT, REFCAPA, REFCAPB, and REGCAP Pins CONVST B, or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. Avoid crossover of digital and analog signals. Traces on layers in close proximity on the board should run at right angles to each other to reduce the effect of feedthrough through the board. The power supply lines to the AV and V pins on the CC DRIVE AD7606/AD7606-6/AD7606-4 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Where possible, use supply planes and make good connections between the AD7606 supply pins and the power tracks on the board. Use a single via or multiple vias for each supply pin. Good decoupling is also important to lower the supply impedance presented to the AD7606/AD7606-6/AD7606-4 and to reduce tshheo umldag bnei tpuldacee odf ctlhoes esu top p(ildye saplilky,e rsi.g Thht eu pd eacgoauinpslitn) gth ceaspea pciitnosr s 08479-055 Figure 63. Bottom Layer Decoupling and their corresponding ground pins. Place the decoupling capacitors for the REFIN/REFOUT pin and the REFCAPA and REFCAPB pins as close as possible to their respective AD7606/ AD7606-6/AD7606-4 pins; and, where possible, they should be placed on the same side of the board as the AD7606 device. Rev. E | Page 32 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 To ensure good device-to-device performance matching in AAVVCCCC a system that contains multiple AD7606/AD7606-6/AD7606-4 devices, a symmetrical layout between the AD7606/AD7606-6/ AD7606-4 devices is important. Figure 64 shows a layout with two AD7606/AD7606-6/AD7606-4 devices. The AV supply plane runs to the right of both devices, UU22 CC and the V supply track runs to the left of the two devices. DRIVE The reference chip is positioned between the two devices, and the reference voltage track runs north to Pin 42 of U1 and south to Pin 42 of U2. A solid ground plane is used. These symmetrical layout principles can also be applied to a system that contains more than two AD7606/AD7606-6/AD7606-4 devices. The AD7606/AD7606-6/AD7606-4 devices can be placed in a north-south direction, with the reference voltage located midway between the devices and the reference track running in the north-south direction, similar to Figure 64. UU11 08479-056 Figure 64. Layout for Multiple AD7606 Devices—Top Layer and Supply Plane Layer Rev. E | Page 33 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet OUTLINE DIMENSIONS 12.20 0.75 12.00 SQ 0.60 1.60 11.80 0.45 MAX 64 49 1 48 PIN 1 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 1.45 0.20 1.40 0.09 1.35 7° 3.5° 0.15 0° 16 33 0.05 SPELAANTEING 0.08 17 32 COPLANARITY VIEW A 0.27 0.50 BSC 0.22 VIEW A LEAD PITCH 0.17 ROTATED 90° CCW COMPLIANTTO JEDEC STANDARDS MS-026-BCD 051706-A Figure 65. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimetres ORDERING GUIDE Model1, 2, 3 Temperature Range Package Description Package Option AD7606BSTZ −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7606BSTZ-RL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7606BSTZ-6 −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7606BSTZ-6RL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7606BSTZ-4 −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD7606BSTZ-4RL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 EVAL-AD7606SDZ Evaluation Board for the AD7606 EVAL-AD7606-6SDZ Evaluation Board for the AD7606-6 EVAL-AD7606-4SDZ Evaluation Board for the AD7606-4 EVAL-SDP-CB1Z Evaluation Controller Board 1 Z = RoHS Compliant Part. 2 The EVAL-AD7606SDZ, EVAL-AD7606-6SDZ, and EVAL-AD7606-4SDZ can be used as standalone evaluation boards or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes. 3 The EVAL-SDP-CB1Z allows the PC to control and communicate with all Analog Devices, Inc., evaluation boards ending in the SDZ designator. Rev. E | Page 34 of 36

Data Sheet AD7606/AD7606-6/AD7606-4 NOTES Rev. E | Page 35 of 36

AD7606/AD7606-6/AD7606-4 Data Sheet NOTES ©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08479-0-5/18(E) Rev. E | Page 36 of 36

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7606BSTZ-6 AD7606BSTZ AD7606BSTZ-RL AD7606BSTZ-4 AD7606BSTZ-6RL AD7606BSTZ-4RL EVAL- AD7606-4SDZ AD7606TSTZ-EP AD7606TSTZ-EP-RL