Isolated Sigma-Delta Modulator Data Sheet AD7401 FEATURES GENERAL DESCRIPTION 20 MHz maximum external clock rate The AD74011 is a second-order, sigma-delta (Σ-Δ) modulator Second-order modulator that converts an analog input signal into a high speed, 1-bit data 16 bits no missing codes stream with on-chip digital isolation based on Analog Devices, ±2 LSB INL typical at 16 bits Inc., iCoupler® technology. The AD7401 operates from a 5 V 3.5 μV/°C maximum offset drift power supply and accepts a differential input signal of ±200 mV On-board digital isolator (±320 mV full-scale). The analog input is continuously sampled On-board reference by the analog modulator, eliminating the need for external sample- Low power operation: 20 mA maximum at 5.25 V and-hold circuitry. The input information is contained in the −40°C to +105°C operating range output stream as a density of ones with a data rate up to 20 MHz. 16-lead SOIC package The original information can be reconstructed with an appropriate Safety and regulatory approvals digital filter. The serial input/output can use a 5 V or a 3 V UL recognition supply (V ). DD2 5000 V rms for 1 minute per UL 1577 The serial interface is digitally isolated. High speed CMOS, CSA Component Acceptance Notice #5A combined with monolithic air core transformer technology, VDE Certificate of Conformity means the on-chip isolation provides outstanding performance DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 characteristics, superior to alternatives such as optocoupler devices. V = 891 V peak IORM The device contains an on-chip reference. The AD7401 is offered APPLICATIONS in a 16-lead SOIC and has an operating temperature range of −40°C to +105°C. AC motor controls Data acquisition systems An internal clock version, AD7400, is also available. A/D + opto-isolator replacements 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 AD7401 VIN+ T/H VIN– Σ-∆ADC UPDATE WATCHDOG BUF ENCODE DECODE MDAT REF CONTROLLOGIC WATCHDOG UPDATE DECODE ENCODE MCLKIN GND1 GND2 05851-001 Figure 1. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7401 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................9 Applications ....................................................................................... 1 Terminology .................................................................................... 12 General Description ......................................................................... 1 Theory of Operation ...................................................................... 13 Functional Block Diagram .............................................................. 1 Circuit Information .................................................................... 13 Revision History ............................................................................... 2 Analog Input ............................................................................... 13 Specifications ..................................................................................... 3 Differential Inputs ...................................................................... 14 Timing Specifications .................................................................. 4 Digital Filter ................................................................................ 15 Insulation and Safety Related Specifications ............................ 5 Applications Information .............................................................. 17 Regulatory Information ............................................................... 5 Grounding and Layout .............................................................. 17 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Evaluating the AD7401 Performance ...................................... 17 Characteristics .............................................................................. 6 Insulation Lifetime ..................................................................... 17 Absolute Maximum Ratings ............................................................ 7 Outline Dimensions ....................................................................... 18 ESD Caution .................................................................................. 7 Ordering Guide .......................................................................... 18 Pin Configuration and Function Descriptions ............................. 8 REVISION HISTORY 4/2018—Rev. E to Rev. F 9/2007—Rev. A to Rev. B Changes to Table 3 and Table 4 ....................................................... 5 Updated VDE Certification Throughout ...................................... 1 Changes to Table 6 ............................................................................. 7 12/2015—Rev. D to Rev. E Changes to Ordering Guide .......................................................... 18 12/2006—Rev. 0 to Rev. A Changes to Features and General Description .............................. 1 7/2011—Rev. C to Rev. D Changes to Table 1 ............................................................................. 3 Changes to Minimum External Air Gap (Clearance) Parameter, Changes to Table 2 ............................................................................. 4 Table 3 and Minimum External Tracking (Creepage) Parameter, Changes to Table 6 ............................................................................. 7 Table 3 ................................................................................................ 5 Changes to Table 8 ............................................................................. 8 Changes to Figure 5; Pin 1 Description, Table 8; and Pin 7 Changes to Circuit Information Section ..................................... 13 Description, Table 8 .......................................................................... 8 Changes to Figure 27 ...................................................................... 15 1/2011—Rev. B to Rev. C 1/2006—Revision 0: Initial Version Changes to Features Section............................................................ 1 Changes to Input-to-Output Momentary Withstand Voltage Parameter, Table 3, UL Column, Table 4, and Note 1, Table 4 ........ 5 Changes to Ordering Guide ............................................................ 18 Rev. F | Page 2 of 18

Data Sheet AD7401 SPECIFICATIONS V = 4.5 V to 5.25 V, V = 3 V to 5.5 V, V + = −200 mV to +200 mV, and V − = 0 V (single-ended); T = T to T , DD1 DD2 IN IN A MIN MAX f = 16 MHz maximum, tested with Sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. MCLK Table 1. Parameter Y Version1, 2 Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 16 Bits min Filter output truncated to 16 bits Integral Nonlinearity3 ±15 LSB max −40°C to +85°C; ±2 LSB typical; f = 20 MHz maximum4 MCLK ±25 LSB max >85°C to 105°C ±55 LSB max f = 20 MHz maximum4; V + = −250 mV to +250 mV MCLK IN Differential Nonlinearity3 ±0.9 LSB max Guaranteed no missed codes to 16 bits; f = 20 MHz maximum4; V + = −250 mV to +250 mV MCLK IN Offset Error3 ±0.6 mV max f = 20 MHz maximum4; V + = −250 mV to +250 mV MCLK IN ±50 µV typ T = 25°C A Offset Drift vs. Temperature 3.5 µV/°C max −40°C to +105°C 1 µV/°C typ Offset Drift vs. V 120 µV/V typ DD1 Gain Error3 ±1.6 mV max −40°C to +85°C ±2 mV max >85°C to 105°C ±1 mV typ f = 20 MHz maximum4; V + = −250 mV to +250 mV MCLK IN Gain Error Drift vs. Temperature 23 µV/°C typ −40°C to +105°C Gain Error Drift vs. V 110 µV/V typ DD1 ANALOG INPUT Input Voltage Range ±200 mV min/mV max For specified performance; full range ±320 mV Dynamic Input Current ±9 µA max V + = 400 mV, V − = 0 V IN IN DC Leakage Current ±0.5 µA max Input Capacitance 10 pF typ DYNAMIC SPECIFICATIONS V + = 5 kHz, 400 mV p-p sine IN Signal-to-(Noise + Distortion) Ratio (SINAD)3 70 dB min −40°C to +85°C; f = 9 MHz to 20 MHz4 MCLK 68 dB min −40°C to +85°C; f = 5 MHz to <9 MHz MCLK 65 dB min >85°C to 105°C 65 dB min f = 20 MHz maximum4; V + = −250 mV to +250 mV MCLK IN 81 dB typ Signal-to-Noise Ratio (SNR) 80 dB min −40°C to +105°C; 82 dB typ 80 dB min f = 20 MHz maximum4; V + = −250 mV to +250 mV MCLK IN Total Harmonic Distortion (THD)3 −92 dB typ f = 20 MHz maximum4; V + = −250 mV to +250 mV MCLK IN Peak Harmonic or Spurious Noise (SFDR)3 −92 dB typ Effective Number of Bits (ENOB)3 11.5 Bits Isolation Transient Immunity3 25 kV/µs min 30 kV/µs typ LOGIC INPUTS Input High Voltage, V 0.8 × V V min IH DD2 Input Low Voltage, V 0.2 × V V max IL DD2 Input Current, I ±0.5 µA max IN Input Capacitance, C 5 10 pF max IN Rev. F | Page 3 of 18

AD7401 Data Sheet Parameter Y Version1, 2 Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, V V − 0.1 V min I = −200 μA OH DD2 O Output Low Voltage, V 0.4 V max I = +200 μA OL O POWER REQUIREMENTS V 4.5/5.25 V min/V max DD1 V 3/5.5 V min/V max DD2 I 6 12 mA max V = 5.25 V DD1 DD1 I 7 8 mA max V = 5.5 V DD2 DD2 4 mA max V = 3.3 V DD2 1 Temperature range is −40°C to +85°C. 2 All voltages are relative to their respective ground. 3 See the Terminology section. 4 For fMCLK > 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, VDD1 = VDD2 = 5 V ± 5%, and TA = −40°C to +85°C. 5 Sample tested during initial release to ensure compliance. 6 See Figure 15. 7 See Figure 17. TIMING SPECIFICATIONS V = 4.5 V to 5.25 V, V = 3 V to 5.5 V, T = T to T , unless otherwise noted.1 DD1 DD2 A MAX MIN Table 2. Parameter Limit at T , T Unit Description MIN MAX f 2, 3 20 MHz max Master clock input frequency MCLKIN 5 MHz min Master clock input frequency t4 25 ns max Data access time after MCLK rising edge 1 t4 15 ns min Data hold time after MCLK rising edge 2 t 0.4 × t ns min Master clock low time 3 MCLKIN t 0.4 × t ns min Master clock high time 4 MCLKIN 1 Sample tested during initial release to ensure compliance 2 Mark space ratio for clock input is 40/60 to 60/40 for fMCLKIN to 16 MHz and 48/52 to 52/48 for fMCLKIN > 16 MHz to 20 MHz. 3 VDD1 = VDD2 = 5 V ± 5% for fMCLKIN > 16 MHz to 20 MHz. 4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 200µA IOL TO OUTPUT 1.6V PIN CL 25pF 200µA IOH 05851-002 Figure 2. Load Circuit for Digital Output Timing Specifications t 4 MCLKIN MDAT t1 t2 t3 05851-003 Figure 3. Data Timing Rev. F | Page 4 of 18

Data Sheet AD7401 INSULATION AND SAFETY RELATED SPECIFICATIONS Table 3. Parameter Symbol Value Unit Conditions Input-to-Output Momentary Withstand Voltage V 5000 min V rms 1-minute duration ISO Minimum External Air Gap (Clearance) L(I01) 7.81,2 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 7.81,2 min mm Measured from input terminals to output terminals, shortest distance path along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1 Isolation Group II Material Group (DIN VDE 0110, 1/89, Table I) 1 In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 m. 2 Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained. REGULATORY INFORMATION Table 4. UL1 CSA VDE2 Recognized under 1577 Approved under CSA Component Certified according to DIN V VDE V 0884-10 Component Recognition Program1 Acceptance Notice #5A (VDE V 0884-10):2006-122 5000 V rms Isolation Voltage Basic insulation per CSA 60950-1-07 Reinforced insulation per DIN V VDE V 0884-10 and IEC 60950-1, 780 V rms (VDE V 0884-10):2006-12, 891V peak maximum working voltage. Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 390 V rms maximum working voltage. File E214100 File 205078 File 2471900-4880-0001 1 In accordance with UL 1577, each AD7401 is proof tested by applying an insulation test voltage ≥6000 V rms for 1 second (current leakage detection limit = 15 µA). 2 In accordance with DIN V VDE V 0884-10, each AD7401 is proof tested by applying an insulation test voltage ≥1671 V peak for 1 second (partial discharge detection limit = 5 pC). Rev. F | Page 5 of 18

AD7401 Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Table 5. Description Symbol Characteristic Unit INSTALLATION CLASSIFICATION PER DIN VDE 0110 For Rated Mains Voltage ≤ 300 V rms I–IV For Rated Mains Voltage ≤ 450 V rms I–II For Rated Mains Voltage ≤ 600 V rms I–II CLIMATIC CLASSIFICATION 40/105/21 POLLUTION DEGREE (DIN VDE 0110, TABLE I) 2 MAXIMUM WORKING INSULATION VOLTAGE V 891 V peak IORM INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1 V × 1.875 = V , 100% Production Test, t = 1 sec, Partial Discharge < 5 pC V 1671 V peak IORM PR m PR INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A V PR After Environmental Test Subgroup 1 1426 V peak V × 1.6 = V , t = 60 sec, Partial Discharge < 5 pC IORM PR m After Input and/or Safety Test Subgroup 2/3 1069 V peak V × 1.2 = V , t = 60 sec, Partial Discharge < 5 pC IORM PR m HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, t = 10 sec) V 6000 V peak TR TR SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, ALSO SEE Figure 4) Case Temperature T 150 °C S Side 1 Current I 265 mA S1 Side 2 Current I 335 mA S2 INSULATION RESISTANCE AT T, V = 500 V R >109 Ω S IO S 350 300 A) m T ( 250 N E SIDE#2 R UR 200 C G N TI 150 MI SIDE#1 LI Y- 100 T E F A S 50 00 50 CASETEMP1E0R0ATURE(°C)150 200 05851-004 Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. F | Page 6 of 18

Data Sheet AD7401 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. All voltages are relative to A Stresses at or above those listed under Absolute Maximum their respective ground. Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these Table 6. or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Operation beyond V to GND −0.3 V to +6.5 V DD1 1 the maximum operating conditions for extended periods may V to GND −0.3 V to +6.5 V DD2 2 affect product reliability. Analog Input Voltage to GND −0.3 V to V + 0.3 V 1 DD1 Digital Input Voltage to GND2 −0.3 V to VDD1 + 0.5 V Table 7. Maximum Continuous Working Voltage1 Output Voltage to GND −0.3 V to V + 0.3 V 2 DD2 Parameter Max Unit Constraint Input Current to Any Pin Except Supplies1 ±10 mA AC Voltage, 565 V 50-year minimum lifetime PK Operating Temperature Range −40°C to +105°C Bipolar Waveform Storage Temperature Range −65°C to +150°C AC Voltage, 891 V Maximum CSA/VDE PK Junction Temperature 150°C Unipolar Waveform approved working voltage SOIC Package DC Voltage 891 V Maximum CSA/VDE θ Thermal Impedance 89.2°C/W approved working voltage JA θJC Thermal Impedance 55.6°C/W 1 Refers to continuous voltage magnitude imposed across the isolation Resistance (Input to Output), R 1012 Ω barrier. See the Insulation Lifetime section for more details. I-O Capacitance (Input to Output), C 2 1.7 pF typ ESD CAUTION I-O Lead-Free Temperature, Soldering Reflow 260 (+0)°C ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause SCR to latch-up. 2 f = 1 MHz. Rev. F | Page 7 of 18

AD7401 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 1 16 GND2 VIN+ 2 15 NC VIN– 3 AD7401 14 VDD2 NC 4 TOP VIEW 13 MCLKIN NC 5 (Not to Scale) 12 NC NC 6 11 MDAT VDD1/NC 7 10 NC GND1 8NC = NO CONNECT9 GND2 05851-005 Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1 V Supply Voltage. 4.5 V to 5.25 V. This is the supply voltage for the isolated side of the AD7401 and is relative to GND. DD1 1 2 V + Positive Analog Input. Specified range of ±200 mV. IN 3 V − Negative Analog Input. Normally connected to GND. IN 1 4 to 6, 10, NC No Connect. 12, 15 7 V /NC Supply Voltage. 4.5 V to 5.25 V. This is the supply voltage for the isolated side of the AD7401 and is relative to GND. DD1 1 No Connect (NC). If desired, Pin 7 may be allowed to float. It should not be tied to ground. The AD7401 will operate normally provided that the supply voltage is applied to Pin 1. 8 GND Ground 1. This is the ground reference point for all circuitry on the isolated side. 1 9, 16 GND Ground 2. This is the ground reference point for all circuitry on the nonisolated side. 2 11 MDAT Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are clocked out on the rising edge of the MCLKIN input and valid on the following MCLKIN rising edge. 13 MCLKIN Master Clock Logic Input. 20 MHz maximum. The bit stream from the modulator is valid on the rising edge of MCLKIN. 14 V Supply Voltage. 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND. DD2 2 Rev. F | Page 8 of 18

Data Sheet AD7401 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, using a 25 kHz brick wall filter, unless otherwise noted. A 100 –90 VDD1=VDD2=5V 90 –85 80 MCLKIN=16MHz MCLKIN=10MHz –80 70 MCLKIN=16MHz –75 B) 60 B) R (d 50 D (d –70 SR MCLKIN=5MHz MCLKIN=10MHz NA P 40 SI –65 30 –60 20 200mVp-pSINEWAVE ONVDD1 NODECOUPLING –55 10 VDD1=VDD2=5V 1MHzCUTOFFFILTER 0 –50 0 100 200SUP3P0L0YR4IP00PLE5F00REQ6U0E0NC7Y0(0kHz8)00 900 1000 05851-006 0.170.180.190.200.210.±22 IN0.P23U0T.2A4M0.2P5L0IT.2U6D0.E27(V0.)280.290.300.310.320.33 05851-028 Figure 6. PSRR vs. Supply Ripple Frequency Without Supply Decoupling Figure 9. SINAD vs. VIN –90 0.4 VDD1V=DD1V=VDDD2D=25V=5V –85 0.3 MCLKIN=16MHz 0.2 –80 B) 0.1 –75 S SINAD (dB) ––7605 MCLKIN=10MHz MCLKIN=5MHz NL ERROR (L –0.10 D –0.2 –60 –0.3 –55 –0.4 VIN+ = –200mV TO +200mV VIN– = 0V –50 –0.5 0 1k 2k 3kINPU4TkFREQ5kUENC6kY(Hz7)k 8k 9k 10k 05851-027 0 10k 20k C3O0DkE 40k 50k 60k 05851-043 Figure 7. SINAD vs. Analog Input Frequency Figure 10. Typical DNL (±200 mV Range) 20 0.8 4096 POINT FFT VIN+=–200mVTO+200mV 0 fIN = 5kHz VIN–=0V SINAD = 81.984dB 0.6 –20 THD = –96.311dB DECIMATION BY 256 –40 B) 0.4 –60 LS (dB) –80 RROR ( 0.2 –100 L E –120 IN 0 –140 –0.2 –160 –180 –0.4 0 5 10FREQUE1N5CY (kHz)20 25 30 05851-042 0 10k 20k C3O0DkE 40k 50k 60k 05851-044 Figure 8. Typical FFT (±200 mV Range) Figure 11. Typical INL (±200 mV Range) Rev. F | Page 9 of 18

AD7401 Data Sheet 250 0.0105 200 VMDCDL1K=INVD=D126=MH4.z5V VMDCDL1K=INVD=D120=MH4.z5V 0.0100 VDDM1=CLVKDIDN2==156VMHz MCTLAKI=N+=851°6CMHz MCLKIN=16MHz 150 VDD1=VDD2=4.5V VDD1=VDD2=5V TA=–40°C TA=+105°C MCLKIN=5MHz MCLKIN=5MHz 0.0095 100 VDD1=VDD2=5V MCLKIN=16MHz 0.0090 V) 50 MCLKIN=10MHz MCLKIN=10MHz SET (µ 0 (A)D10.0085 TA=–40°C TA=+105°C F D0.0080 OF –50 I MCLKIN=10MHz 0.0075 TA=+85°C –100 VDD1=VDD2=5.25V VDD1=VDD2=5.25V MCLKIN=16MHz MCLKIN=10MHz ––125000 VMDCDL1K=INVD=D120=MH5Vz VMDCDL1K=INVD=D52M=H5z.25V 00..00006750 MCTLAK=IN+8=55°CMHz MCTLAK=IN–4=05°CMHz MTCALK=IN+1=055°MCHz –250 0.0060 –45–35–25–15 –5 5TE1M5PE25RA3T5UR4E5(°C55) 65 75 85 95 105 05851-029 –0.33–0.28–0.23–0.18–V0I.N13D–C0. 0I8N–P0U.0T3V0.O03LT0A.0G8E0(.1V3) 0.18 0.23 0.28 0.33 05851-034 Figure 12. Offset Drift vs. Temperature for Various Supply Voltages Figure 15. IDD1 vs. VIN at Various Temperatures 200.5 0.0070 VDD1=VDD2=4.5V VDD1=VDD2=4.5V VDD1=VDD2=5V 200.4 MCLKIN=16MHz MCLKIN=10MHz 0.0065 MCLKIN=16MHz TA=25°C VDD1=VDD2=4.5V VDD1=VDD2=5V 200.3 MCLKIN=5MHz MCLKIN=5MHz 0.0060 200.2 VMDCDL1K=INVD=D126=MH5Vz VMDCDL1K=INVD=D120=MH5.z25V 0.0055 mV) 200.1 VMDCDL1K=INVD=D126=MH5.z25V VMDCDL1K=INVD=D52M=H5z.25V A) 0.0050 MCLKIN=10MHz GAIN ( 210909..09 VMDCDL1K=INVD=D120=MH5Vz I (DD200..00004450 199.8 0.0035 MCLKIN=5MHz 199.7 0.0030 199.6 0.0025 199.5 0.0020 –45–35–25–15 –5 5TE1M5PE25RA3T5UR4E5(°C55) 65 75 85 95 105 05851-036 –0.325–0.275–0.225–0.175–V0.I1N25D–0C.0 7IN5–P0.U02T50V.0O2L5T0A.07G5E0.(1V2)50.1750.2250.2750.325 05851-037 Figure 13. Gain Error Drift vs. Temperature for Various Supply Voltages Figure 16. IDD2 vs. VIN DC Input Voltage 0.0105 0.0070 VDD1=VDD2=5V VDD1=VDD2=5V 0.0100 TA=25°C 0.0065 0.0060 MCLKIN=16MHz 0.0095 MCLKIN=16MHz MCLKIN=16MHz TA=+105°C MCLKIN=16MHz 0.0055 TA=–40°C TA=+85°C 0.0090 0.0050 MCLKIN=10MHz MCLKIN=10MHz A) A) TA=–40°C TA=+105°C (D10.0085 MCLKIN=10MHz (D20.0045 D D I I 0.0040 MCLKIN=10MHz 0.0080 TA=+85°C 0.0035 MCLKIN=5MHz 0.0075 MCLKIN=5MHz TA=–40°C 0.0030 0.0070 0.0025 MCLKIN=5MHz MCLKIN=5MHz TA=+85°C TA=+105°C 0.0065 0.0020 –0.33–0.28–0.23–0.18–V0I.N13D–C0. 0I8N–P0U.0T3V0.O03LT0A.0G8E0(.1V3) 0.18 0.23 0.28 0.33 05851-033 –0.325–0.275–0.225–0.175–V0.I1N25D–0C.0 7IN5–P0.U02T50V.0O2L5T0A.07G5E0.(1V2)50.1750.2250.2750.325 05851-038 Figure 14. IDD1 vs. VIN DC Input Voltage Figure 17. IDD2 vs. VIN at Various Temperatures Rev. F | Page 10 of 18

Data Sheet AD7401 8 1.0 VDD1 = VDD2 = 4.5V TO 5.25V VDD1 = VDD2 = 5V 50kHz BRICK WALL FILTER 6 MCLKIN = 16MHz 0.8 4 MCLKIN = 10MHz 2 V) 0.6 I (µA)IN 0 MCLKIN = 5MHz OISE (m –2 N 0.4 MCLKIN = 5MHz –4 0.2 –6 MCLKIN = 16MHz MCLKIN = 10MHz –8 0 –0.35 –0.30 –0.25 –0.20 –0.15 –0.10VIN––0.05 DC 0INPU0.05T (V0.10) 0.15 0.20 0.25 0.30 0.35 05851-030 –0.30 –0.25 –0.20 –0.15 –0.10VIN–0.05 DC I0NPUT0.05 (V) 0.10 0.15 0.20 0.25 0.30 05851-032 Figure 18. IIN vs. VIN− DC Input Figure 20. RMS Noise Voltage vs. VIN DC Input 0 VDD1=VVDDD1D=V2DD2==5V5V –20 –40 dB) MCLKIN=5MHz R ( –60 R M C MCLKIN=10MHz –80 –100 MCLKIN=16MHz –120 0.1 1 RIPPLEFRE1Q0UENCY(kHz)100 1000 05851-031 Figure 19. CMRR vs. Common-Mode Ripple Frequency Rev. F | Page 11 of 18

AD7401 Data Sheet TERMINOLOGY Differential Nonlinearity Total Harmonic Distortion (THD) Differential nonlinearity is the difference between the measured THD is the ratio of the rms sum of harmonics to the and the ideal 1 LSB change between any two adjacent codes in fundamental. For the AD7401, it is defined as the ADC. V 2 +V 2 +V 2 +V 2 +V 2 Integral Nonlinearity THD(dB)=20log 2 3 4 5 6 V Integral nonlinearity is the maximum deviation from a straight 1 line passing through the endpoints of the ADC transfer function. where: The endpoints of the transfer function are specified negative V1 is the rms amplitude of the fundamental. full-scale, −200 mV (VIN+ − VIN−), Code 12,288 for the 16-bit V2, V3, V4, V5, and V6 are the rms amplitudes of the second level, and specified positive full-scale, +200 mV (V + − V −), through the sixth harmonics. IN IN Code 53,248 for the 16-bit level. Peak Harmonic or Spurious Noise Offset Error Peak harmonic or spurious noise is defined as the ratio of the Offset error is the deviation of the midscale code (Code 32,768 rms value of the next largest component in the ADC output for the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V). spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is Gain Error determined by the largest harmonic in the spectrum, but for Gain error includes both positive full-scale gain error and ADCs where the harmonics are buried in the noise floor, it is a negative full-scale gain error. Positive full-scale gain error is the noise peak. deviation of the specified positive full-scale code (53,248 for the 16-bit level) from the ideal V + − V − (+200 mV) after the Common-Mode Rejection Ratio (CMRR) IN IN offset error is adjusted out. Negative full-scale gain error is the CMRR is defined as the ratio of the power in the ADC output at deviation of the specified negative full-scale code (12,288 for ±200 mV frequency, f, to the power of a 200 mV p-p sine wave the 16-bit level) from the ideal VIN+ − VIN− (−200 mV) after the applied to the common-mode voltage of VIN+ and VIN− of offset error is adjusted out. Gain error includes reference error. frequency fS, expressed as Signal-to-(Noise + Distortion) Ratio CMRR (dB) = 10 log(Pf/PfS) This ratio is the measured ratio of signal-to-(noise + distortion) where: at the output of the ADC. The signal is the rms amplitude of the Pf is the power at frequency f in the ADC output. fundamental. Noise is the sum of all nonfundamental signals up Pf is the power at frequency f in the ADC output. S S to half the sampling frequency (f/2), excluding dc. The ratio is S Power Supply Rejection Ratio (PSRR) dependent on the number of quantization levels in the digitization Variations in power supply affect the full-scale transition but process; the more levels, the smaller the quantization noise. The not converter linearity. PSRR is the maximum change in the theoretical signal-to-(noise + distortion) ratio for an ideal N-bit specified full-scale (±200 mV) transition point due to a change converter with a sine wave input is given by in power supply voltage from the nominal value (see Figure 6). Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Isolation Transient Immunity Therefore, for a 12-bit converter, this is 74 dB. The isolation transient immunity specifies the rate of rise/fall of Effective Number of Bits (ENOB) a transient pulse applied across the isolation boundary beyond The ENOB is defined by which clock or data is corrupted. (It was tested using a transient pulse frequency of 100 kHz.) ENOB = (SINAD − 1.76)/6.02 Rev. F | Page 12 of 18

Data Sheet AD7401 THEORY OF OPERATION CIRCUIT INFORMATION A differential input of 320 mV results in a stream of, ideally, all 1s. This is the absolute full-scale range of the AD7401, while The AD7401 isolated Σ-Δ modulator converts an analog input 200 mV is the specified full-scale range, as shown in Table 9. signal into a high speed (20 MHz maximum), single-bit data stream; the time average of the modulator single-bit data is Table 9. Analog Input Range directly proportional to the input signal. Figure 23 shows a typical Analog Input Voltage Input application circuit where the AD7401 is used to provide isolation Full-Scale Range +640 mV between the analog input, a current sensing resistor, and the digital Positive Full-Scale +320 mV output, which is then processed by a digital filter to provide an Positive Specified Input Range +200 mV N-bit word. Zero 0 mV ANALOG INPUT Negative Specified Input Range −200 mV Negative Full-Scale −320 mV The differential analog input of the AD7401 is implemented with a switched capacitor circuit. This circuit implements a second-order modulator stage that digitizes the input signal into a 1-bit output To reconstruct the original information, this output needs to be stream. The sample clock (MCLKIN) provides the clock signal digitally filtered and decimated. A Sinc3 filter is recommended for the conversion process as well as the output data-framing because this is one order higher than that of the AD7401 modu- clock. This clock source is external on the AD7401. The analog lator. If a 256 decimation rate is used, the resulting 16-bit word input signal is continuously sampled by the modulator and rate is 62.5 kHz, assuming a 16 MHz external clock frequency. compared to an internal voltage reference. A digital stream that Figure 22 shows the transfer function of the AD7401 relative to accurately represents the analog input over time appears at the the 16-bit output. output of the converter (see Figure 21). MODULATOR OUTPUT 65535 +FSANALOG INPUT 53248 ANALOG INPUFTigure 21. Analog Input vs. Modulator Outpu–tF S ANALOG INPUT 05851-020 DC CODE SPECIFIEDRANGE A A differential signal of 0 V results (ideally) in a stream of 1s and 12288 0s at the MDAT output pin. This output is high 50% of the time and low 50% of the time. A differential input of 200 mV produces a stream of 1s and 0s that are high 81.25% of the time. A differential input of −200 mV produces a stream of 1s and 0s that are high 0 18.75% of the time. –320mV –200mAVNALOG INPUT+200mV +320mV 05851-021 Figure 22. Filtered and Decimated 16-Bit Transfer Characteristic ISOLATED NONISOLATED 5V 5V/3V VDD1 AD7401 VDD2 VDD SINC3FILTER Σ-∆ CS + VIN+ ENMCOODD/ER DECODER MDAT MDAT INPUT SCLK CURRENT VIN– MCLKIN MCLK RSHUNT SDAT DECODER ENCODER GND1 GND2 GND 05851-019 Figure 23. Typical Application Circuit Rev. F | Page 13 of 18

AD7401 Data Sheet DIFFERENTIAL INPUTS When a capacitive load is switched onto the output of an operational amplifier, the amplitude momentarily drops. The The analog input to the modulator is a switched capacitor operational amplifier tries to correct the situation and, in the design. The analog signal is converted into charge by highly linear process, hits its slew rate limit. This nonlinear response, which sampling capacitors. A simplified equivalent circuit diagram of can cause excessive ringing, can lead to distortion. To remedy the analog input is shown in Figure 24. A signal source driving the situation, a low-pass RC filter can be connected between the the analog input must be able to provide the charge onto the amplifier and the input to the AD7401. The external capacitor at sampling capacitors every half MCLKIN cycle and settle to the each input aids in supplying the current spikes created during the required accuracy within the next half cycle. sampling process, and the resistor isolates the operational amplifier φA from the transient nature of the load. 1kΩ VIN+ φB 2pF The recommended circuit configuration for driving the differential inputs to achieve best performance is shown in Figure 25. A φA 2pF capacitor between the two input pins sources or sinks charge 1kΩ to allow most of the charge that is needed by one input to be VIN– φB effectively supplied by the other input. The series resistor again MCLKIN φA φB φA φB 05851-022 idsuorliantegs t hane ysa ompperliantigo pnraol caemssp. lRifeiecro fmromme ntdheed c uvarlrueenst fsopri tkhees rcerseisattoerds Figure 24. Analog Input Equivalent Circuit and capacitor are 22 Ω and 47 pF, respectively. Because the AD7401 samples the differential voltage across its R VIN+ analog inputs, low noise performance is attained with an input C AD7401 caimrcpuliitf itehrast upsreodvi tdoe sd lroiwve c tohme manoanlo-mg oindpeu ntos ipsela ayt ae accrhit iincaplu rto. Tleh ien VIN– R 05851-023 attaining the high performance available from the AD7401. Figure 25. Differential Input RC Network Rev. F | Page 14 of 18

Data Sheet AD7401 DIGITAL FILTER MCLKIN ACC1+ ACC2+ A Sinc3 filter is recommended for use with the AD7401. This filter ACC3+ can be implemented on an FPGA or possibly a DSP. The following IP_DATA1 + Z + Z + Z 05851-024 Verilog code provides an example of a Sinc3 filter implementation Figure 26. Accumulator on a Xylinx® Spartan-II 2.5 V FPGA. This code can possibly be Z = one sample delay compiled for another FPGA, such as an Altera® device. Note that MCLKIN = modulators conversion bit rate the data is read on the negative clock edge in this case, although */ it can be read on the positive edge if preferred. Figure 29 shows the always @ (posedge mclk1 or posedge reset) effect of using different decimation rates with various filter types. if (reset) begin /*`Data is read on negative clk edge*/ /*initialize acc registers on reset*/ module DEC256SINC24B(mdata1, mclk1, reset, acc1 <= 0; DATA); acc2 <= 0; input mclk1; /*used to clk filter*/ acc3 <= 0; input reset; /*used to reset filter*/ end input mdata1; /*ip data to be else filtered*/ begin output [15:0] DATA; /*filtered op*/ /*perform accumulation process*/ acc1 <= acc1 + ip_data1; integer location; acc2 <= acc2 + acc1; integer info_file; acc3 <= acc3 + acc2; reg [23:0] ip_data1; end reg [23:0] acc1; /*DECIMATION STAGE (MCLKIN/ WORD_CLK) */ reg [23:0] acc2; always @ (negedge mclk1 or posedge reset) reg [23:0] acc3; if (reset) reg [23:0] acc3_d1; word_count <= 0; reg [23:0] acc3_d2; else word_count <= word_count + 1; reg [23:0] diff1; always @ (word_count) reg [23:0] diff2; word_clk <= word_count[7]; reg [23:0] diff3; /*DIFFERENTIATOR (including decimation stage) reg [23:0] diff1_d; Perform the differentiation stage (FIR) at a reg [23:0] diff2_d; lower speed. reg [15:0] DATA; + DIFF1 + DIFF2 + DIFF3 ACC3 – –– – reg [7:0] word_count; Z–1 Z–1 Z–1 rreegg wionridt_;c l k; WORD_CLK 05851-025 Figure 27. Differentiator /*Perform the Sinc ACTION*/ Z = one sample delay always @ (mdata1) WORD_CLK = output word rate if(mdata1==0) */ ip_data1 <= 0; /* change from a 0 to a -1 for 2's comp */ else ip_data1 <= 1; /*ACCUMULATOR (INTEGRATOR) Perform the accumulation (IIR) at the speed of the modulator. Rev. F | Page 15 of 18

AD7401 Data Sheet always @ (posedge word_clk or posedge reset) DATA[9] <= diff3[17]; if(reset) DATA[8] <= diff3[16]; begin DATA[7] <= diff3[15]; acc3_d2 <= 0; DATA[6] <= diff3[14]; diff1_d <= 0; DATA[5] <= diff3[13]; diff2_d <= 0; DATA[4] <= diff3[12]; diff1 <= 0; DATA[3] <= diff3[11]; diff2 <= 0; DATA[2] <= diff3[10]; DATA[1] <= diff3[9]; DATA[0] <= diff3[8]; diff3 <= 0; end end endmodule else 90 SINC3 begin 80 diff1 <= acc3 - acc3_d2; diff2 <= diff1 - diff1_d; 70 SINC2 diff3 <= diff2 - diff2_d; 60 acc3_d2 <= acc3; diff1_d <= diff1; B) 50 d diff2_d <= diff2; R ( end SN 40 SINC1 /* Clock the Sinc output into an output 30 register 20 WORD_CLK DIFF3 DATA 05851-026 100 Figure 28. Clocking Sinc Output into an Output Register 1 10 DECIMATIONRAT1E00 1k 05851-035 WORD_CLK = output word rate Figure 29. SNR vs. Decimation Rate for Different Filter Types */ Figure 29 shows a plot of SNR performance vs. decimation rate always @ (posedge word_clk) with different filter types. Note that, for a given bandwidth begin requirement, a higher MCLKIN frequency can allow higher DATA[15] <= diff3[23]; decimation rates to be used, resulting in higher SNR performance. DATA[14] <= diff3[22]; DATA[13] <= diff3[21]; DATA[12] <= diff3[20]; DATA[11] <= diff3[19]; DATA[10] <= diff3[18]; Rev. F | Page 16 of 18

Data Sheet AD7401 APPLICATIONS INFORMATION GROUNDING AND LAYOUT These tests subject populations of devices to continuous cross isolation voltages. To accelerate the occurrence of failures, the Supply decoupling with a value of 100 nF is strongly recom- selected test voltages are values exceeding those of normal use. mended on both V and V . Decoupling on one or both DD1 DD2 The time to failure values of these units are recorded and used V pins does not affect performance significantly. In applications DD1 to calculate acceleration factors. These factors are then used to involving high common-mode transients, care must be taken to calculate the time to failure under normal operating conditions. ensure that board coupling across the isolation barrier is mini- The values shown in Table 7 are the lesser of the following mized. Furthermore, the board layout must be designed so any two values: coupling that occurs equally affects all pins on a given component side. Failure to ensure this may cause voltage differentials between • The value that ensures at least a 50-year lifetime of pins to exceed the absolute maximum ratings of the device, thereby continuous use leading to latch-up or permanent damage. Any decoupling used • The maximum CSA/VDE approved working voltage must be placed as close to the supply pins as possible. Note that the lifetime of the AD7401 varies according to the Series resistance in the analog inputs must be minimized to waveform type imposed across the isolation barrier. The avoid any distortion effects, especially at high temperatures. If iCoupler insulation structure is stressed differently depending possible, equalize the source impedance on each analog input to on whether the waveform is bipolar ac, unipolar ac, or dc. minimize offset. Beware of mismatch and thermocouple effects Figure 30, Figure 31, and Figure 32 illustrate the different on the analog input PCB tracks to reduce offset drift. isolation voltage waveforms. EVALUATING THE AD7401 PERFORMANCE RATEDPEAKVOLTAGE A simple standalone AD7401 evaluation board is available with split ground planes and a board split beneath the AD7401 package 0V 05851-039 to ensure isolation. This board allows access to each pin on the Figure 30. Bipolar AC Waveform device for evaluation purposes. External supplies and all other RATEDPEAKVOLTAGE circuitry (such as a digital filter) must be provided by the user. IANllS inUsLuAlatTioIOn sNtr LucIFtuEreTsI,M suEb jected to sufficient time and/or 0V 05851-040 voltage, are vulnerable to breakdown. In addition to the testing Figure 31. Unipolar AC Waveform performed by the regulatory agencies, Analog Devices has carried RATEDPEAKVOLTAGE out an extensive set of evaluations to determine the lifetime of the insulation structure within the AD7401. 0V 05851-041 Figure 32. DC Waveform Rev. F | Page 17 of 18

AD7401 Data Sheet OUTLINE DIMENSIONS 10.50(0.4134) 10.10(0.3976) 16 9 7.60(0.2992) 7.40(0.2913) 1 10.65(0.4193) 8 10.00(0.3937) 1.27(0.0500) 0.75(0.0295) BSC 2.65(0.1043) 0.25(0.0098) 45° 0.30(0.0118) 2.35(0.0925) 8° 0.10(0.0039) 0° COPLANARITY 0.10 0.51(0.0201) SPELAATNIENG 0.33(0.0130) 1.27(0.0500) 0.31(0.0122) 0.20(0.0079) 0.40(0.0157) C(RINOEFNPEATRRREOENNLCLTEIHNCEOGOSNDMELISPYM)LAEAIANNRNDSETIAORTRNOOESUJNANEORDDETEEDAICN-POSMPFTRIFALONLMPIDMIRLAELIRATIMTDEEESRTFSMEO;SRIRN-0ECU1QHS3U-EADIVAIINMAELDENENSSTIIOGSNNFS.OR 03-27-2007-B Figure 33. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD7401YRWZ −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 AD7401YRWZ-REEL −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 AD7401YRWZ-REEL7 −40°C to +105°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 EVAL-AD7401EDZ Evaluation Board EVAL-CED1Z Development Board 1 Z = RoHS Compliant Part. ©2006–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05851-0-4/18(F) Rev. F | Page 18 of 18