500 kSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC Data Sheet AD7327 FEATURES FUNCTIONAL BLOCK DIAGRAM 12-bit plus sign SAR ADC VDD REFIN/OUT VCC True bipolar input ranges AD7327 Software-selectable input ranges ±10 V, ±5 V, ±2.5 V, 0 V to +10 V VIN0 2.5V VIN1 VREF 13-BIT 580 a0n kalSoPgS i tnhpruotu cghhapnunte rlast we ith channel sequencer VVIINN23 MI/UPX T/H APSPURCOCAXEDISMCSAITVIEON VIN4 Single-ended, true differential, and pseudo differential VIN5 VIN6 TEMPERATURE analog input capability VIN7 INDICATOR High analog input impedance DOUT Low power: 18 mW CONTROLLOGIC SCLK Temperature indicator CHANNEL ANDREGISTERS CS SEQUENCER DIN Full power signal bandwidth: 22 MHz Internal 2.5 V reference VDRIVE HPoigwhe srp-deoewd ns emrioadl ienst erface AGND VSS DGND 05401-001 Figure 1. 20-lead TSSOP package iCMOS™ process technology GENERAL DESCRIPTION serial interface that can operate at throughput rates up to 500 kSPS. The AD73271 is an 8-channel, 12-bit plus sign successive PRODUCT HIGHLIGHTS approximation ADC designed on the iCMOS (industrial 1. The AD7327 can accept true bipolar analog input signals, CMOS) process. iCMOS is a process combining high voltage ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals. silicon with submicron CMOS and complementary bipolar 2. The eight analog inputs can be configured as eight single- technologies. It enables the development of a wide range of high ended inputs, four true differential inputs, four pseudo performance analog ICs capable of 33 V operation in a footprint differential inputs, or seven pseudo differential inputs. that no previous generation of high voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS 3. 500 kSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™- components can accept bipolar input signals while providing compatible interface. increased performance, dramatically reduced power 4. Low power, 18 mW, at a maximum throughput rate of consumption, and reduced package size. 500 kSPS. The AD7327 can accept true bipolar analog input signals. The 5. Channel sequencer. AD7327 has four software-selectable input ranges: ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V. Each analog input channel can be Table 1. Similar Devices independently programmed to one of the four input ranges. Device Throughput Number of The analog input channels on the AD7327 can be programmed Number Rate Number of bits Channels to be single-ended, true differential, or pseudo differential. AD7329 1000 kSPS 12-bit plus sign 8 AD7328 1000 kSPS 12-bit plus sign 8 The ADC contains a 2.5 V internal reference. The AD7327 also AD7324 1000 kSPS 12-bit plus sign 4 allows external reference operation. If a 3 V reference is applied AD7323 500 kSPS 12-bit plus sign 4 to the REFIN/OUT pin, the AD7327 can accept a true bipolar AD7322 1000 kSPS 12-bit plus sign 2 ±12 V analog input. Minimum ±12 V V and V supplies are DD SS AD7321 500 kSPS 12-bit plus sign 2 required for the ±12 V input range. The ADC has a high speed 1Protected by U.S. Patent No. 6,731,232. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7327 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Sequence Register ....................................................................... 23 Functional Block Diagram .............................................................. 1 Range Registers ........................................................................... 24 General Description ......................................................................... 1 Sequencer Operation ..................................................................... 25 Product Highlights ........................................................................... 1 Reference ..................................................................................... 27 Revision History ............................................................................... 2 V ............................................................................................ 27 DRIVE Specifications ..................................................................................... 3 Temperature Indicator ............................................................... 27 Timing Specifications .................................................................. 7 Modes of Operation ....................................................................... 28 Absolute Maximum Ratings ............................................................ 8 Normal Mode .............................................................................. 28 ESD Caution .................................................................................. 8 Full Shutdown Mode .................................................................. 28 Pin Configuration and Function Descriptions ............................. 9 Autoshutdown Mode ................................................................. 29 Typical Performance Characteristics ........................................... 10 Autostandby Mode ..................................................................... 29 Terminology .................................................................................... 14 Power vs. Throughput Rate ....................................................... 30 Theory of Operation ...................................................................... 16 Serial Interface ................................................................................ 31 Circuit Information .................................................................... 16 Microprocessor Interfacing ........................................................... 32 Converter Operation .................................................................. 16 AD7327 to ADSP-21xx .............................................................. 32 Analog Input Structure .............................................................. 17 AD7327 to ADSP-BF53x ........................................................... 32 Typical Connection Diagram ................................................... 19 Application Hints ........................................................................... 33 Analog Input ............................................................................... 19 Layout and Grounding .............................................................. 33 Driver Amplifier Choice ............................................................ 21 Power Supply Configuration .................................................... 33 Registers ........................................................................................... 22 Outline Dimensions ....................................................................... 34 Addressing Registers .................................................................. 22 Ordering Guide .......................................................................... 34 Control Register .......................................................................... 22 REVISION HISTORY 12/13—Rev. A to Rev. B Changes to Circuit Information Section and Table 6 ................ 16 Changes to Addressing Registers Section .................................... 22 Changes to Power Supply Configuration Section ...................... 33 Changes to Ordering Guide .......................................................... 34 1/10—Rev. 0 to Rev. A Change to Features and Product Highlights Sections ................. 1 Changes to Table 2 ............................................................................ 5 Change to Endnote 1 in Table 4 ...................................................... 8 Added Power Supply Configuration Section, Figure 56, and Table 16 ............................................................................................ 33 1/06—Revision 0: Initial Version Rev. B | Page 2 of 36

Data Sheet AD7327 SPECIFICATIONS V = 12 V to 16.5 V, V = −12 V to −16.5 V, V = 2.7 V to 5.25 V, V = 2.7 V to 5.25 V, V = 2.5 V to 3.0 V internal/external, DD SS CC DRIVE REF f = 10 MHz, f = 500 kSPS, T = T to T , unless otherwise noted. SCLK S A MAX MIN Table 2. B Version Parameter1 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE F = 50 kHz sine wave IN Signal-to-Noise Ratio (SNR)2 76 dB Differential mode, V = 4.75 V to 5.25 V CC 75.5 dB Differential mode, V < 4.75 V CC 72.5 dB Single-ended/pseudo differential mode; ±10 V, ±2.5 V and ±5 V ranges, V = 4.75 V to 5.25 V CC 72 dB Single-ended/pseudo differential mode; 0 V to 10 V V = 4.75 V to 5.25 V and all ranges at V < 4.75 V CC CC Signal-to-Noise + Distortion 75 dB Differential mode; ±2.5 V and ±5 V ranges (SINAD)2 74 Differential mode; 0 V to 10 V 76 dB Differential mode; ±10 V range 72 dB Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges 72.5 dB Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges Total Harmonic Distortion −80 dB Differential mode; ±2.5 V and ±5 V ranges (THD)2 −79 dB Differential mode; 0 V to 10 V ranges −82 dB Differential mode; ±10 V range −77 dB Single-ended/pseudo differential mode; ±5 V range −79 dB Single-ended/pseudo differential mode; ±2.5 V range −80 dB Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges Peak Harmonic or Spurious −81 dB Differential mode; ±2.5 V and ±5 V ranges Noise (SFDR)2 −80 dB Differential mode; 0 V to 10 V ranges −82 dB Differential mode; ±10 V ranges −78 dB Single-ended/pseudo differential mode; ±5 V range −80 Single-ended/pseudo differential mode; ±2.5 V range −79 dB Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges Intermodulation Distortion fa = 50 kHz, fb = 30 kHz (IMD)2 Second-Order Terms −88 dB Third-Order Terms −90 dB Aperture Delay3 7 ns Aperture Jitter3 50 ps Common-Mode Rejection −79 dB Up to 100 kHz ripple frequency; see Figure 17 (CMRR)2 Channel-to-Channel Isolation2 −72 dB F on unselected channels up to 100 kHz; see Figure 14 IN Full Power Bandwidth 22 MHz At 3 dB 5 MHz At 0.1 dB Rev. B | Page 3 of 36

AD7327 Data Sheet B Version Parameter1 Min Typ Max Unit Test Conditions/Comments DC ACCURACY4 Single-ended/pseudo differential mode 1 LSB = FSR/4096, unless otherwise noted. Differential mode 1 LSB = FSR/8192, unless otherwise noted. Resolution 13 Bits No Missing Codes 12-bit Bits Differential mode plus sign (13 bits) 11-bit Bits Single-ended/pseudo differential mode plus sign (12 bits) Integral Nonlinearity2 ±1.1 LSB Differential mode; V = 3 V to 5.25 V, typ for V = 2.7 V CC CC ±1 LSB Single-ended/pseudo differential mode, V = 3 V to CC 5.25 V, typ for V = 2.7 V CC −0.7/+1.2 LSB Single-ended/pseudo differential mode (LSB = FSR/8192) Differential Nonlinearity2 −0.9/+1.2 LSB Differential mode; guaranteed no missing codes to 13 bits ±0.9 LSB Single-ended mode; guaranteed no missing codes to 12 bits −0.7/+1 LSB Single-ended/pseudo differential mode (LSB = FSR/8192) Offset Error2, 5 −4/+9 LSB Single-ended/pseudo differential mode −7/+10 LSB Differential mode Offset Error Match2, 5 ±0.6 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Gain Error2, 5 ±8 LSB Single-ended/pseudo differential mode ±14 LSB Differential mode Gain Error Match2, 5 ±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Positive Full-Scale Error2, 6 ±4 LSB Single-ended/pseudo differential mode ±7 LSB Differential mode Positive Full-Scale Error Match2, 6 ±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Bipolar Zero Error2, 6 ±8.5 LSB Single-ended/pseudo differential mode ±7.5 LSB Differential mode Bipolar Zero Error Match2, 6 ±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Negative Full-Scale Error2, 6 ±4 LSB Single-ended/pseudo differential mode ±6 LSB Differential mode Negative Full-Scale Error Match2, 6 ±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode ANALOG INPUT Input Voltage Ranges Reference = 2.5 V; see Table 6 (Programmed via Range ±10 V V = +10 V min, V = −10 V min, V = +2.7 V to +5.25 V DD SS CC Registers) ±5 V V = +5 V min, V = −5 V min, V = +2.7 V to +5.25 V DD SS CC ±2.5 V V = +5 V min, V = −5 V min, V = +2.7 V to +5.25 V DD SS CC 0 to 10 V V = +10 V min, V = AGND min, V = +2.7 V to +5.25 V DD SS CC Pseudo Differential V (−) V = +16.5 V, V = −16.5 V, V = +5 V; see Figure 40 IN DD SS CC Input Range and Figure 41 ±3.5 V Reference = 2.5 V; range = ±10 V ±6 V Reference = 2.5 V; range = ±5 V ±5 V Reference = 2.5 V; range = ±2.5 V +3/−5 V Reference = 2.5 V; range = 0 V to +10 V Rev. B | Page 4 of 36

Data Sheet AD7327 B Version Parameter1 Min Typ Max Unit Test Conditions/Comments DC Leakage Current ±80 nA V = V or V IN DD SS 3 nA Per input channel, V = V or V IN DD SS Input Capacitance3 13.5 pF When in track, ±10 V range 16.5 pF When in track, ±5 V and 0 V to +10 V ranges 21.5 pF When in track, ±2.5 V range 3 pF When in hold, all ranges REFERENCE INPUT/OUTPUT Input Voltage Range 2.5 3 V Input DC Leakage Current ±1 µA Input Capacitance 10 pF Reference Output Voltage 2.5 V Reference Output Voltage Error ±5 mV at 25°C Reference Output Voltage ±10 mV T to T MIN MAX Reference Temperature 25 ppm/°C Coefficient 3 ppm/°C Reference Output Impedance 7 Ω LOGIC INPUTS Input High Voltage, V 2.4 V INH Input Low Voltage, V 0.8 V V = 4.75 V to 5.25 V INL CC 0.4 V V = 2.7 to 3.6 V CC Input Current, I ±1 µA V = 0 V or V IN IN DRIVE Input Capacitance, C 3 10 pF IN LOGIC OUTPUTS Output High Voltage, V V − V I = 200 µA OH DRIVE SOURCE 0.2 V Output Low Voltage, V 0.4 V I = 200 µA OL SINK Floating-State Leakage Current ±1 µA Floating-State Output 5 pF Capacitance3 Output Coding Straight natural binary Coding bit set to 1 in control register Twos complement Coding bit set to 0 in control register CONVERSION RATE Conversion Time 1.6 µs 16 SCLK cycles with SCLK = 10 MHz Track-and-Hold Acquisition 305 ns Full-scale step input; see the Terminology section Time2, 3 Throughput Rate 500 kSPS See the Serial Interface section POWER REQUIREMENTS Digital inputs = 0 V or V DRIVE V 12 16.5 V See Table 6 DD V −12 −16.5 V See Table 6 SS V 2.7 5.25 V See Table 6 CC V 2.7 5.25 V DRIVE Normal Mode (Static) 0.9 mA V /V = ±16.5 V, V /V = 5.25 V DD SS CC DRIVE Normal Mode (Operational) f = 500 kSPS SAMPLE I 180 µA V = 16.5 V DD DD I 205 µA V = −16.5 V SS SS I and I 2.2 mA V /V = 5.25 V CC DRIVE CC DRIVE Autostandby Mode (Dynamic) f = 250 kSPS SAMPLE I 100 µA V = 16.5 V DD DD I 110 µA V = −16.5 V SS SS I and I 0.75 mA V /V = 5.25 V CC DRIVE CC DRIVE Rev. B | Page 5 of 36

AD7327 Data Sheet B Version Parameter1 Min Typ Max Unit Test Conditions/Comments Autoshutdown Mode (Static) SCLK on or off I 1 µA V = 16.5 V DD DD I 1 µA V = −16.5 V SS SS I and I 1 µA V /V = 5.25 V CC DRIVE CC DRIVE Full Shutdown Mode SCLK on or off I 1 µA V = 16.5 V DD DD I 1 µA V = −16.5 V SS SS I and I 1 µA V /V = 5.25 V CC DRIVE CC DRIVE POWER DISSIPATION Normal Mode (Operational) 18 mW V = +16.5 V, V = −16.5 V, V = +5.25 V DD SS CC Full Shutdown Mode 38.25 µW V = +16.5 V, V = −16.5 V, V = +5.25 V DD SS CC 1 Temperature range is −40°C to +85°C. 2 See the Terminology section. 3 Sample tested during initial release to ensure compliance. 4 For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless otherwise noted. 5 Unipolar 0 V to 10 V range with straight binary output coding. 6 Bipolar range with twos complement output coding. Rev. B | Page 6 of 36

Data Sheet AD7327 TIMING SPECIFICATIONS V = 12 V to 16.5 V, V = −12 V to −16.5 V, V = 2.7 V to 5.25 V, V = 2.7 V to 5.25 V, V = 2.5 V to 3.0 V internal/external, DD SS CC DRIVE REF T = T to T . Timing specifications apply with a 32 pF load, unless otherwise noted.1 A MAX MIN Table 3. Limit at T , T Description MIN MAX Parameter V < 4.75 V V = 4.75 V to 5.25 V Unit V ≤ V CC CC DRIVE CC f 50 50 kHz min SCLK 10 10 MHz max t 16 × t 16 × t ns max t = 1/f CONVERT SCLK SCLK SCLK SCLK t 75 60 ns min Minimum time between end of serial read and next falling edge of CS QUIET t 12 5 ns min Minimum CS pulse width 1 t 2 25 20 ns min CS to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V) 2 45 35 ns min Unipolar input range (0 V to 10 V) t 26 14 ns max Delay from CS until DOUT three-state disabled 3 t 57 43 ns max Data access time after SCLK falling edge 4 t 0.4 × t 0.4 × t ns min SCLK low pulse width 5 SCLK SCLK t 0.4 × t 0.4 × t ns min SCLK high pulse width 6 SCLK SCLK t 13 8 ns min SCLK to data valid hold time 7 t 40 22 ns max SCLK falling edge to DOUT high impedance 8 10 9 ns min SCLK falling edge to DOUT high impedance t 4 4 ns min DIN set-up time prior to SCLK falling edge 9 t 2 2 ns min DIN hold time after SCLK falling edge 10 t 750 750 ns max Power-up from autostandby POWER-UP 500 500 µs max Power-up from full shutdown/autoshutdown mode, internal reference 25 25 µs typ Power-up from full shutdown/autoshutdown mode, external reference 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2 When using the 0 V to 10 V unipolar range, running at 500 kSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to 50:50. t1 CS tCONVERT t2 t6 SCLK 1 2 3 4 5 13 14 15 16 3t 3IDENTIFICATIONBITS t4 t7 t5 t8 tQUIET DOUT ADD1 ADD0 SIGN DB11 DB10 DB2 DB1 DB0 TSHTRAETEE- ADD2 t9 t10 THREE-STATE DIN WRITE SREELG1 SREELG2 MSB LSB DCOANR’ET 05401-002 Figure 2. Serial Interface Timing Diagram Rev. B | Page 7 of 36

AD7327 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to AGND, DGND −0.3 V to +16.5 V DD section of this specification is not implied. Exposure to absolute V to AGND, DGND +0.3 V to −16.5 V SS maximum rating conditions for extended periods may affect V to V V − 0.3 V to 16.5 V DD CC CC device reliability. V to AGND, DGND −0.3 V to +7 V CC V to AGND, DGND −0.3 V to +7 V DRIVE AGND to DGND −0.3 V to +0.3 V ESD CAUTION Analog Input Voltage to AGND1 V − 0.3 V to V + 0.3 V SS DD Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to V + 0.3 V DRIVE REFIN to AGND −0.3 V to V + 0.3 V CC Input Current to Any Pin ±10 mA Except Supplies2 Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package θ Thermal Impedance 143°C/W JA θ Thermal Impedance 45°C/W JC Pb-Free Temperature, Soldering Reflow 260(0)°C ESD 2.5 kV 1 If the analog inputs are driven from alternative VDD and VSS supply circuitry, Schottky diodes should be placed in series with the AD7327 VDD and VSS supplies. See Power Supply Configuration section. 2 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. B | Page 8 of 36

Data Sheet AD7327 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CS 1 20 SCLK DIN 2 19 DGND DGND 3 18 DOUT AD7327 AGND 4 TOPVIEW 17 VDRIVE (NottoScale) REFIN/OUT 5 16 VCC VSS 6 15 VDD VIN0 7 14 VIN2 VIN1 8 13 VIN3 VVIINN54 190 1112 VVIINN76 05401-003 Figure 3. TSSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7327 and frames the serial data transfer. 2 DIN Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the AD7327 on the falling edge of SCLK (see the Registers section). 3, 19 DGND Digital Ground. Ground reference point for all digital circuitry on the AD7327. The DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 4 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7327. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 5 REFIN/OUT Reference Input/Reference Output. The on-chip reference is available on this pin for external use to the AD7327. The nominal internal reference voltage is 2.5 V, which appears at this pin. A 680 nF capacitor should be placed on the reference pin (see the Reference section). Alternatively, the internal reference can be disabled and an external reference applied to this input. On power-up, the external reference mode is the default condition. 6 V Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. SS 7, 8, 14, 13, 9, V 0 to V 7 Analog Input 0 to Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold. IN IN 10, 12, 11 The analog input channel for conversion is selected by programming the channel address Bit ADD2 through Bit ADD0 in the control register. The inputs can be configured as eight single-ended inputs, four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs. The configuration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and Bit Mode 0, in the control register. The input range on each input channel is controlled by program- ming the range registers. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected on each analog input channel when a +2.5 V reference voltage is used (see the Registers section). 15 V Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. DD 16 V Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7327. CC This supply should be decoupled to AGND. 17 V Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface DRIVE operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at V , CC but it should not exceed V by more than 0.3 V. CC 18 DOUT Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The data stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data. The data is provided MSB first (see the Serial Interface section). 20 SCLK Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the AD7327. This clock is also used as the clock source for the conversion process. Rev. B | Page 9 of 36

AD7327 TYPICAL PERFORMANCE CHARACTERISTICS 0 1.0 4096POINTFFT VCC=VDRIVE=5V INT/EXT2.5VREFERENCE VCC=VDRIVE=5V 0.8 TA=25°C ±10VRANGE –20 VDD,VSS=±15V VDD,VSS=±15V +INL=+0.55LSB TA=25°C 0.6 –INL=–0.68LSB INT/EXT2.5VREFERENCE –40 ±10VRANGE 0.4 SFINNR==507k7H.3z0dB LSB) 0.2 SNR (dB) ––6800 STSHFINDDAR=D=–=8–7686.89..8625d2dBdBB L ERROR ( –0.20 N I –0.4 –100 –0.6 –120 –0.8 –1400 50 FR10E0QUENCY(1k5H0z) 200 250 05401-004 –1.00 51210241536204825603072358C44O09D64E6085120563261446656716876808192 05401-007 Figure 4. FFT True Differential Mode Figure 7. Typical INL True Differential Mode 1.0 0 4096POINTFFT 0.8 VCC=VDRIVE=5V –20 VDD,VSS=±15V 0.6 TA=25°C INT/EXT2.5VREFERENCE 0.4 –40 ±10VRANGE B) S FSINNR==507k4H.6z7dB R (L 0.2 SNR (dB) ––6800 STSHIFNDDAR=D=–=8–7284.56..0843d0dBdBB NL ERRO –0.20 D –0.4 –100 –0.6 VCC=VDRIVE=5V ±10VRANGE TA=25°C +DNL=+0.79LSB –120 –0.8 VDD,VSS=±15V –DNL=–0.38LSB INT/EXT2.5VREFERENCE –1.0 –1400 50 FR10E0QUENCY(1k5H0z) 200 250 05401-005 0 51210241536204825603072358C44O09D64E6085120563261446656716876808192 05401-043 Figure 5. FFT Single-Ended Mode Figure 8. Typical DNL Single-Ended Mode 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 B) B) LS 0.2 LS 0.2 R ( R ( RO 0 DNL ERRO –0.20 VCC=VDRIVE=5V INL ER ––00..24 TVACC==25V°DCRIVE=5V –0.4 TVADD=,2V5S°SC=±15V –0.6 IVNDTD/,EVXSTS2=.5±V15RVEFERENCE –0.6 INT/EXT2.5VREFERENCE ±10VRANGE ±10VRANGE –0.8 +INL=+0.87LSB –0.8 +DNL=+0.72LSB –INL=–0.49LSB –1.00 51210241536204825603072358C44O09D64E6–0D85N1L20=56–302.62124L4S66B56716876808192 05401-006 –1.00 51210241536204825603072358C44O09D64E6085120563261446656716876808192 05401-044 Figure 6. Typical DNL True Differential Mode Figure 9. Typical INL Single-Ended Mode Rev. B | Page 10 of 36

Data Sheet AD7327 –50 80 VCC=VDRIVE=3V ±5VDIFF –55 VDD/VSS=±12V ±2.5VDIFF TA=25°C 75 –60 fS=500kSPS ±5VSE INTERNALREFERENCE 0VTO+10VSE –65 ±2.5VSE ±10VSE 70 ±10VDIFF THD (dB) –––778050 0VT±O10+V1D0VIFDFIFF SINAD (dB) 65 ±10VSE 0VTO+100VVTSOE+10VDIFF ±5VSE ±5VDIFF 60 –85 ±2.5VDIFF VCC=VDRIVE=5V –90 55 VDD/VSS=±12V ±2.5VSE TA=25°C –95 fS=500kSPS INTERNALREFERENCE –100 50 10 ANALOG INPUT1F0R0EQUENCY(kHz) 1000 05401-060 10 ANALOG INPUT1F0R0EQUENCY(kHz) 1000 05401-063 Figure 10. THD vs. Analog Input Frequency Figure 13. SINAD vs. Analog Input Frequency for Single-Ended (SE) and True Differential Mode (Diff) at 3 V VCC for Single-Ended (SE) and True Differential Mode (Diff) at 5 V VCC –50 –50 VCC=VDRIVE=5V –55 VDD/VSS=±12V B) –55 –60 TfSA==52050°kCSPS 0VTO+10VSE ON (d –60 VCC=3V –65 INTERNALREFERENCE ±10VSE OLATI –65 VCC=5V D (dB) ––7705 ±10VDIFF NNEL IS –70 H 0VTO+10VDIFF A –75 T –80 CH –85 ±5V±S5EVDIFF NEL-TO- ––8805 SVIDNDG/VLSES-E=N±D1E2VDMODE –90 AN fS=500kSPS –95 ±2.5VSE CH –90 T50Ak=Hz2 5O°CNSELECTEDCHANNEL ±2.5VDIFF –100 –95 10 ANALOG INPUT1F0R0EQUENCY(kHz) 1000 05401-061 0 100 FREQU20E0NCY OF3 I0N0PUTNO4IS00E(kHz)500 600 05401-012 Figure 11. THD vs. Analog Input Frequency Figure 14. Channel-to-Channel Isolation for Single-Ended (SE) and True Differential Mode (Diff) at 5 V VCC 80 10k 9469 ±5VDIFF VCC=5V ±2.5VDIFF 9k VDD/VSS=±12V 75 ±5VSE 8k R10AkNSGAEM=P±L1E0SV 0V ±T2O.5+V10SVEDIFF NCES 7k TA=25°C 70 ±10VDIFF RE B) UR 6k SINAD (d 65 0VTO±+1100VVSSEE R OF OCC 54kk 60 E MB 3k 55 VTVACDCD=/=V2S5VS°DC=RIV±E12=V3V NU 2k fS=500kSPS 1k INTERNALREFERENCE 0 228 303 0 50 0 10 ANALOG INPUT1F0R0EQUENCY(kHz) 1000 05401-062 –2 –1 CO0DE 1 2 05401-013 Figure 12. SINAD vs. Analog Input Frequency Figure 15. Histogram of Codes, True Differential Mode for Single-Ended (SE) and True Differential Mode (Diff) at 3 V VCC Rev. B | Page 11 of 36

AD7327 8k 2.0 7600 VCC=5V 7k VDD/VSS=±12V 1.5 RANGE=±10V 10kSAMPLES ES 6k TA=25°C 1.0 C REN 5k SB) 0.5 F OCCU 4k RROR (L 0 INL=500kSPS O E ER 3k NL –0.5 B I M NU 2k –1.0 1201 1165 ±5VRANGE 1k –1.5 VINCTCE=RNVDARLIVREE=FE5VRENCE 0 23 11 0 SINGLE-ENDEDMODE 0 –2.0 –3 –2 –1 CO0DE 1 2 3 05401-014 5 7 ±V9DD/VSSS1U1PPLYV1O3LTAGE1(5V) 17 19 05401-050 Figure 16. Histogram of Codes, Single-Ended Mode Figure 19. INL Error vs. Supply Voltage at 500 kSPS –50 –50 100mVp-pSINEWAVE ONEACHSUPPLY –55 –55 NODECOUPLING SINGLE-ENDEDMODE –60 –60 fS=500kSPS VCC=5V –65 –65 B) –70 VCC=5V B) –70 VCC=3V d d R ( –75 R ( –75 R R CM –80 VCC=3V PS –80 VDD=12V –85 DIFFERENTIALMODE –85 FIN=50kHz VSS=–12V –90 VDD/VSS=±12V –90 fS=500kSPS –95 TA=25°C –95 –100 –100 0 200 R4IP0P0LEFRE6Q00UENCY(8k0H0z) 1000 1200 05401-055 0 200 SUPP4L0Y0RIPPLE6F0R0EQUEN8C0Y0(kHz)1000 1200 05401-054 Figure 17. CMRR vs. Common-Mode Ripple Frequency Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling 2.0 –50 VCC=VDRIVE=5V 1.5 –55 VDD/VSS=±12V TA=25°C ±10VRANGE 1.0 –60 IRNATNEGRENA=L±1R0EVFAND±2.5V RRIINN==43000000ΩΩ SB) 0.5 –65 DfSIF=F5E0R0EkSNPTSIALMODE RRIINN==21000000ΩΩ RROR (L 0 DNL=500kSPS D (dB) ––7705 RRIINN==11020ΩΩ NL E –0.5 TH –80 ±R2IN.5=V9R0A0N0ΩGE D –85 RRIINN==52500000ΩΩ –1.0 RIN=100Ω ±5VRANGE –90 RIN=12Ω –1.5 VCC=VDRIVE=5V INTERNALREFERENCE –95 SINGLE-ENDEDMODE –2.0 –100 5 7 ±V9DD/VSSS1U1PPLYV1O3LTAGE1(5V) 17 19 05401-049 10 INPUTFREQ10U0ENCY(kHz) 1000 05401-064 Figure 18. DNL Error vs. Supply Voltage at 500 kSPS Figure 21. THD vs. Analog Input Frequency for Various Source Impedances, True Differential Mode Rev. B | Page 12 of 36

Data Sheet AD7327 –50 VCC=VDRIVE=5V –55 VDD/VSS=±12V TA=25°C ±10VRANGE –60 IRNATNEGRENA=L±1R0EVFAND±2.5V RRIINN==42000000ΩΩ –65 fS=500kSPS RIN=1000Ω SINGLE-ENDEDMODE RIN=100Ω –70 RIN=50Ω B) d D ( –75 ±2.5VRANGE TH –80 RRIINN==43700000ΩΩ –85 RRIINN==1100000ΩΩ RIN=50Ω –90 –95 –10010 INPUTFREQ10U0ENCY(kHz) 1000 05401-065 Figure 22. THD vs. Analog Input Frequency for Various Source Impedances, Single-Ended Mode Rev. B | Page 13 of 36

AD7327 TERMINOLOGY Differential Nonlinearity Negative Full-Scale Error This is the difference between the measured and the ideal 1 LSB This applies when using twos complement output coding and change between any two adjacent codes in the ADC. any of the bipolar analog input ranges. This is the deviation of the first code transition (10 ... 000) to (10 ... 001) from the ideal Integral Nonlinearity (that is, −4 × V + 1 LSB, −2 × V + 1 LSB, −V + 1 LSB) This is the maximum deviation from a straight line passing REF REF REF after adjusting for the bipolar zero code error. through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (a point 1 LSB Negative Full-Scale Error Match below the first code transition) and full scale (a point 1 LSB This is the difference in negative full-scale error between any above the last code transition). two input channels. Offset Code Error Track-and-Hold Acquisition Time This applies to straight binary output coding. It is the deviation The track-and-hold amplifier returns into track mode after the of the first code transition (00 ... 000) to (00 ... 001) from the 14th SCLK rising edge. Track-and-hold acquisition time is the ideal, that is, AGND + 1 LSB. time required for the output of the track-and-hold amplifier to reach its final value, within ±½ LSB, after the end of a conversion. Offset Error Match For the ±2.5 V range, the specified acquisition time is the time This is the difference in offset error between any two input required for the track-and-hold amplifier to settle to within ±1 LSB. channels. Signal to (Noise + Distortion) Ratio Gain Error This is the measured ratio of signal to (noise + distortion) at the This applies to straight binary output coding. It is the deviation output of the ADC. The signal is the rms amplitude of the of the last code transition (111 ... 110) to (111 ... 111) from the fundamental. Noise is the sum of all non-fundamental signals up ideal (that is, 4 × V − 1 LSB, 2 × V − 1 LSB, V −1 LSB) REF REF REF to half the sampling frequency (f/2), excluding dc. The ratio is after adjusting for the offset error. S dependent on the number of quantization levels in the digi- Gain Error Match tization process. The more levels, the smaller the quantization This is the difference in gain error between any two input noise. Theoretically, the signal to (noise + distortion) ratio for channels. an ideal N-bit converter with a sine wave input is given by Bipolar Zero Code Error Signal to (Noise + Distortion) = (6.02 N + 1.76) dB This applies when using twos complement output coding and For a 13-bit converter, this is 80.02 dB. a bipolar analog input. It is the deviation of the midscale transition (all 1s to all 0s) from the ideal input voltage, that is, Total Harmonic Distortion AGND − 1 LSB. Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7327, it is defined as Bipolar Zero Code Error Match This refers to the difference in bipolar zero code error between V 2 +V 2 +V 2 +V 2 +V 2 any two input channels. THD(dB)=20log 2 3 4 5 6 V 1 Positive Full-Scale Error where V is the rms amplitude of the fundamental, and V, V, This applies when using twos complement output coding and 1 2 3 V, V, and V are the rms amplitudes of the second through the any of the bipolar analog input ranges. It is the deviation of the 4 5 6 sixth harmonics. last code transition (011…110) to (011…111) from the ideal (4 × V − 1 LSB, 2 × V − 1 LSB, V − 1 LSB) after adjusting Peak Harmonic or Spurious Noise REF REF REF for the bipolar zero code error. Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output Positive Full-Scale Error Match spectrum (up to f/2, excluding dc) to the rms value of the This is the difference in positive full-scale error between any S fundamental. Normally, the value of this specification is two input channels. determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, the largest harmonic could be a noise peak. Rev. B | Page 14 of 36

Data Sheet AD7327 Channel-to-Channel Isolation terms are usually at a frequency close to the input frequencies. Channel-to-channel isolation is a measure of the level of crosstalk As a result, the second- and third-order terms are specified between any two channels. It is measured by applying a full-scale, separately. The calculation of the intermodulation distortion is 100 kHz sine wave signal to all unselected input channels and per the THD specification, where it is the ratio of the rms sum determining the degree to which the signal attenuates in the of the individual distortion products to the rms amplitude of selected channel with a 50 kHz signal. Figure 14 shows the worst- the sum of the fundamentals expressed in decibels. case across all eight channels for the AD7327. The analog input PSR (Power Supply Rejection) range is programmed to be the same on all channels. Variations in power supply affect the full-scale transition but Intermodulation Distortion not the linearity of the converter. Power supply rejection is the With inputs consisting of sine waves at two frequencies, fa and maximum change in the full-scale transition point due to a fb, any active device with nonlinearities creates distortion products change in power supply voltage from the nominal value (see the at sum and difference frequencies of mfa ± nfb, where m, n = 0, Typical Performance Characteristics section). 1, 2, 3, and so on. Intermodulation distortion terms are those CMRR (Common-Mode Rejection Ratio) for which neither m nor n are equal to 0. For example, the CMRR is defined as the ratio of the power in the ADC output at second-order terms include (fa + fb) and (fa − fb), whereas the full-scale frequency, f, to the power of a 100 mV sine wave third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and applied to the common-mode voltage of the V + and V − IN IN (fa − 2fb). frequency, f, as S The AD7327 is tested using the CCIF standard where two input CMRR (dB) = 10 log (Pf/Pf) S frequencies near the top end of the input bandwidth are used. where Pf is the power at frequency f in the ADC output, and Pf In this case, the second-order terms are usually distanced in S is the power at frequency f in the ADC output (see Figure 17). frequency from the original sine waves, whereas the third-order S Rev. B | Page 15 of 36

AD7327 THEORY OF OPERATION CIRCUIT INFORMATION The analog inputs can be configured as eight single-ended inputs, four true differential inputs, four pseudo differential The AD7327 is a fast, 8-channel, 12-bit plus sign, bipolar input, inputs, or seven pseudo differential inputs. Selection can be serial ADC. The AD7327 can accept bipolar input ranges that made by programming the mode bits, Mode 0 and Mode 1, in include ±10 V, ±5 V, and ±2.5 V; it can also accept a 0 V to +10 V the control register. unipolar input range. A different analog input range can be The serial clock input accesses data from the part and provides programmed on each analog input channel via the on-chip the clock source for the successive approximation ADC. The registers. The AD7327 has a high speed serial interface that can AD7327 has an on-chip 2.5 V reference; however, the AD7327 operate at throughput rates up to 500 kSPS. can also work with an external reference. On power-up, the The AD7327 requires V and V dualsupplies for the high DD SS external reference operation is the default option. If the internal voltage analog input structures. These supplies must be equal reference is the preferred option, the user must write to the to or greater than the analog input range. See Table 6 for the reference bit in the control register to select the internal reference requirements of these supplies for each analog input range. The operation. AD7327 requires a low voltage 2.7 V to 5.25 V V supply to CC The AD7327 also features power-down options to allow power power the ADC core. savings between conversions. The power-down modes are selected Table 6. Reference and Supply Requirements for Each by programming the on-chip control register, as described in Analog Input Range the Modes of Operation section. Selected Full-Scale CONVERTER OPERATION Analog Input Reference Input Minimum Range (V) Voltage (V) Range (V) AVCC (V) VDD/VSS (V)1 The AD7327 is a successive approximation ADC built around ±10 2.5 ±10 3/5 ±10 two capacitive DACs. Figure 23 and Figure 24 show simplified 3.0 ±12 3/5 ±12 schematics of the ADC in single-ended mode during the ± 5 2.5 ±5 3/5 ±5 acquisition and conversion phases, respectively. Figure 25 and 3.0 ±6 3/5 ±6 Figure 26 show simplified schematics of the ADC in differential ±2.5 2.5 ±2.5 3/5 ±5 mode during acquisition and conversion phases, respectively. 3.0 ±3 3/5 ±5 The ADC is composed of control logic, a SAR, and capacitive 0 to +10 2.5 0 to +10 3/5 +10/AGND DACs. In Figure 23 (the acquisition phase), SW2 is closed and 3.0 0 to +12 3/5 +12/AGND 1 Guaranteed performance for VDD = 12 V to 16.5 V and VSS = −12 V to −16.5 V. SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor array acquires the signal The performance specifications are guaranteed for VDD = 12 V on the input. to 16.5 V and V = −12 V to −16.5 V. With V and V supplies SS DD SS CAPACITIVE outside this range, the AD7327 is fully functional but performance DAC is not guaranteed. It may be necessary to decrease the throughput B CS COMPARATOR rate when the AD7327 is configured with the minimum VDD VIN0 ASW1 SW2 CONTROL Tanydp iVcaSlS Psuerpfpolrimes atnoc me Ceeht atrhaec tpeerrifsotircms saenccteio snp)e.c Fifiigcuarteio 3n1s s(hseoew tsh e AGND LOGIC 05401-017 the change in THD as the VDD and VSS supplies are reduced. For Figure 23. ADC Acquisition Phase (Single-Ended) ac performance at the maximum throughput rate, the THD When the ADC starts a conversion (Figure 24), SW2 opens and degrades slightly as V and V are reduced. It might, therefore, DD SS SW1 moves to Position B, causing the comparator to become be necessary to reduce the throughput rate when using minimum unbalanced. The control logic and the charge redistribution V and V supplies so that there is less degradation of THD DD SS DAC are used to add and subtract fixed amounts of charge from and the specified performance can be maintained. The the capacitive DAC to bring the comparator back into a balanced degradation is due to an increase in the on resistance of the condition. When the comparator is rebalanced, the conversion input multiplexer when the V and V supplies are reduced. DD SS is complete. The control logic generates the ADC output code. Figure 18 and Figure 19 show the change in INL and DNL as the VDD and VSS voltages are varied. For dc performance when CAPACITIVE DAC operating at the maximum throughput rate, as the V and V DD SS supply voltages are reduced, the typical INL and DNL error B CS COMPARATOR remains constant. VIN0 ASW1 SW2 CONTROL AGND LOGIC 05401-018 Figure 24. ADC Conversion Phase (Single-Ended) Rev. B | Page 16 of 36

Data Sheet AD7327 Figure 25 shows the differential configuration during the The ideal transfer characteristic for the AD7327 when twos acquisition phase. For the conversion phase, SW3 opens and complement coding is selected is shown in Figure 27. The ideal SW1 and SW2 move to Position B (see Figure 26). The output transfer characteristic for the AD7327 when straight binary impedances of the source driving the V + and V − pins must coding is selected is shown in Figure 28. IN IN match; otherwise, the two inputs have different settling times, resulting in errors. 011...111 011...110 CAPACITIVE DAC DE O000...001 COMPARATOR C B CS C 000...000 VIN+ ASW1 SW3 CONTROL AD111...111 ASW2 LOGIC VIN– B CS 100...010 100...001 Figure 25. ADCV RDEiFfferential Configuration DurinCgA APDAcAqCCuITiIsVitEion 05401-019P hase 10–A0F.GS..R0N0/D20++11LLSSBB AGNDA–N1ALLSOBG I++NFFPSSURRT/2––1L1SLBSB BUINPIOPOLALRARRARNAGNGESE 05401-021 Figure 27. Twos Complement Transfer Characteristic CAPACITIVE DAC COMPARATOR 111...111 B CS 111...110 VVIINN+– AASSWW12 SW3 COLNOTGRICOL ODE111...000 B CS C C VREF CAPDAACCITIVE 05401-020 AD011...111 Figure 26. ADC Differential Configuration During Conversion Phase 000...010 000...001 Output Coding 000...000 The AD7327 default output coding is set to twos complement. –AFGSRN/D2++11LLSSBBANALOG I++NFFPSSURRT/–21–L1SLBSB BUINPIOPOLALRARRARNAGNGESE 05401-022 The output coding is controlled by the coding bit in the control Figure 28. Straight Binary Transfer Characteristic register. To change the output coding to straight binary coding, ANALOG INPUT STRUCTURE the coding bit in the control register must be set. When operating in sequence mode, the output coding for each channel in the The analog inputs of the AD7327 can be configured as single- sequence is the value written to the coding bit during the last ended, true differential, or pseudo differential via the control write to the control register. register mode bits (see Table 9). The AD7327 can accept true Transfer Functions bipolar input signals. On power-up, the analog inputs operate as eight single-ended analog input channels. If true differential or The designed code transitions occur at successive integer pseudo differential is required, a write to the control register is LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size necessary after power-up to change this configuration. is dependent on the analog input range selected. Figure 29 shows the equivalent analog input circuit of the Table 7. LSB Sizes for Each Analog Input Range AD7327 in single-ended mode. Figure 30 shows the equivalent Input Range Full-Scale Range/8192 Codes LSB Size analog input structure in differential mode. The two diodes ±10 V 20 V 2.441 mV provide ESD protection for the analog inputs. ±5 V 10 V 1.22 mV VDD ±2.5 V 5 V 0.61 mV 0 V to +10 V 10 V 1.22 mV D R1 C2 VIN0 C1 D VSS 05401-023 Figure 29. Equivalent Analog Input Circuit (Single-Ended) Rev. B | Page 17 of 36

AD7327 VDD The AD7327 enters track on the 14th SCLK rising edge. When running the AD7327 at a throughput rate of 500 kSPS with a VIN+ D R1 C2 10 MHz SCLK signal, the ADC has approximately C1 D 1.5 SCLK + t + t 8 QUIET VSS to acquire the analog input signal. The ADC goes back into hold mode on the CS falling edge. VDD As the V /V supply voltage is reduced, the on resistance of DD SS D R1 C2 the input multiplexer increases. Therefore, based on the equation VIN– C1 D for tACQ, it is necessary to increase the amount of acquisition time VSS 05401-024 pthrroovuidghedpu tto r tahtee. AFiDgu7r3e2 371, a snhdo,w tsh tehraetf oarse t,h dee VcrDeDa asne dt hVeS So svueprpallli es Figure 30. Equivalent Analog Input Circuit (Differential) are reduced, the specified THD performance degrades slightly. Care should be taken to ensure that the analog input does not If the throughput rate is reduced when operating with the exceed the VDD and VSS supply rails by more than 300 mV. minimum VDD and VSS supplies, the specified THD performance Exceeding this value causes the diodes to become forward is maintained. biased and to start conducting into either the V supply rail or DD –75 V supply rail. These diodes can conduct up to 10 mA without VCC=VDRIVE=5V SS INTERNALREFERENCE causing irreversible damage to the part. TA=25°C FIN=10kHz In Figure 29 and Figure 30, Capacitor C1 is typically 4 pF and –80 ±5VRANGE SEMODE can primarily be attributed to pin capacitance. Resistor R1 is a lumped component made up of the on resistance of the input B) d multiplexer and the track-and-hold switch. Capacitor C2 is the D ( –85 H T sampling capacitor; its capacitance varies depending on the analog input range selected (see the Specifications section). –90 Track-and-Hold Section 500kSPS The track-and-hold on the analog input of the AD7327 allows the ADC to accurately convert an input sine wave of full-scale –95 aanmdp-lhitouldde i st og r1e3a-tbeirt tahcacnu rtahcey N. Tyhqeu iisntp ruatt eb oafn tdhwei AdtDh Cof. Tthhee t rack- 5 7 9±VDD/V1S1SSUPP1L3IES(V)15 17 19 05401-051 Figure 31. THD vs. ±VDD/VSS Supply Voltage at 500 kSPS AD7327 can handle frequencies up to 22 MHz. Unlike other bipolar ADCs, the AD7327 does not have a The track-and-hold enters its tracking mode on the 14th SCLK resistive analog input structure. On the AD7327, the bipolar rising edge after the CS falling edge. The time required to analog signal is sampled directly onto the sampling capacitor. acquire an input signal depends on how quickly the sampling This gives the AD7327 high analog input impedance. An capacitor is charged. With 0 source impedance, 305 ns is sufficient approximation for the analog input impedance can be to acquire the signal to the 13-bit level. The acquisition time calculated from the following formula: required is calculated using the following formula: Z = 1/(f × C) S S t = 10 × ((R + R) × C) ACQ SOURCE where f is the sampling frequency, and C is the sampling S S where C is the sampling capacitance, and R is the resistance capacitor value. seen by the track-and-hold amplifier looking back on the input. C depends on the analog input range chosen (see the S For the AD7327, the value of R includes the on resistance of the Specifications section). When operating at 500 kSPS, the analog input multiplexer and is typically 300 Ω. RSOURCE should include input impedance is typically 145 kΩ for the ±10 V range. As the any extra source impedance on the analog input. sampling frequency is reduced, the analog input impedance further increases. As the analog input impedance increases, the current required to drive the analog input, therefore, decreases. Rev. B | Page 18 of 36

Data Sheet AD7327 TYPICAL CONNECTION DIAGRAM V+ 5V Figure 32 shows a typical connection diagram for the AD7327. AGND In this configuration, the AGND pin is connected to the analog VIN+ VDD VCC ground plane of the system, and the DGND pin is connected to AD73271 the digital ground plane of the system. The analog inputs on the AD7327 can be configured to operate in single-ended, true VSS differential, or pseudo differential mode. The AD7327 can operate with either an internal or external reference. In Figure 32, the AAD 68703 2n7F i sd ceocnofuipgulirnegd ctoap oapceitroatre i ws ritehq uthiree idn twerhneanl 2o.p5 eVra rteifnegre wnciteh. 1ADDIVT–IONALPINS OMITTEDFORCLARITY. 05401-026 the internal reference. Figure 33. Single-Ended Mode Typical Connection Diagram The V pin can be connected to either a 3 V supply voltage or a True Differential Mode CC 5 V supply voltage. The V and V are the dual supplies for the DD SS The AD7327 can have a total of four true differential analog high voltage analog input structures. The voltage on these pins input pairs. Differential signals have some benefits over single- must be equal to or greater than the highest analog input range ended signals, including better noise immunity based on the selected on the analog input channels (see Table 6). The V DRIVE common-mode rejection of the device and improvements in pin is connected to the supply voltage of the microprocessor. distortion performance. Figure 34 defines the configuration of The voltage applied to the V input controls the voltage of DRIVE the true differential analog inputs of the AD7327. the serial interface. V can be set to 3 V or 5 V. DRIVE +15V VCC+2.7VTO5.25V VIN+ + + 0.1µF 10µF 10µF 0.1µF AD73271 VDDA1D7327VCVCDRIVE 10µF + 0.1µF+3VSUPPLY 1ADDITIONALPINS OMVIINT–TEDFORCLARITY. 05401-027 VIN0 Figure 34. True Differential Inputs VIN1 CS A±1N0AVL,O±5GV ,IN±P2.U5TVS VVIINN23 DSOCLUKT µC/µP The amplitude of the differential signal is the difference 0VTO+10V VIN4 DIN between the signals applied to the VIN+ and VIN− pins in VVIINN56 each differential pair (VIN+ − VIN−). VIN+ and VIN− should VIN7 DGND SERIAL be simultaneously driven by two signals each of amplitude REFIN/OUT INTERFACE ±4 × V (depending on the input range selected) that are 680nF REF VSS1 AGND 180° out of phase. Assuming the ±4 × V mode, the amplitude REF –15V of the differential signal is −20 V to +20 V p-p (2 × 4 × V ), REF 0.1µF +10µF 1MDREAINPNIEMGNUEDMS OEVLNDEDTCHATENEDDH.IVGSHSESSUTPAPNLYALVOOGLT IANGPUETS 05401-025 rTehgea rcdolmesms oofn t hmeo cdoem ism tohne amvoerdaeg. e of the two signals Figure 32. Typical Connection Diagram (V + + V −)/2 ANALOG INPUT IN IN Single-Ended Inputs and is, therefore, the voltage on which the two input signals are centered. The AD7327 has a total of eight analog inputs when operating the AD7327 in single-ended mode. Each analog input can be This voltage is set up externally, and its range varies with reference independently programmed to one of the four analog input voltage. As the reference voltage increases, the common-mode ranges. In applications where the signal source is high impedance, range decreases. When driving the differential inputs with an it is recommended to buffer the signal before applying it to the amplifier, the actual common-mode range is determined by the ADC analog inputs. Figure 33 shows the configuration of the output swing of the amplifier. If the differential inputs are not AD7327 in single-ended mode. driven from an amplifier, the common-mode range is determined by the supply voltage on the V and the V supply pins. DD SS When a conversion takes place, the common mode is rejected, resulting in a noise-free signal of amplitude −2 × (4 × V ) to +2 × REF (4 × V ) corresponding to digital Code −4096 to Code +4095. REF Rev. B | Page 19 of 36

AD7327 5 8 ±5VRANGE 4 ±5VRANGE 6 R±A1N0GVE R±A2N.5GVE ±5VRANGE 3 ±2.5V RANGE 2 4 ±10V V RANGE (V)COM ––1210 ±10V R±A1N0GVE R±A2N.5GVE V RANGE (V)COM –220 RANGE –3 RANGE –4 –4 ±5VRANGE Figur––e65 35VV. CCRCEoFm==3m3VVon-M±1o6d.5eV RVaDnDg/VeS fSor VCC =± 132 VV VaDnDd/ VRSESFIN/OUT = 3 V05401-045 Figure––86 38. VVCCRoCEmF==m52Vo.5nV-M±o1d6e.5 RVaVnDgDe/V fSoSr VCC =± 51 2VV aVnDdD /RVESFSIN/OR±UA2NT.5 G=VE 2.5 05401-048V 8 Pseudo Differential Inputs ±5VRANGE ±5VRANGE The AD7327 can have four pseudo differential pairs or seven 6 pseudo differential inputs referenced to a common V − pin. ±2.5V ±2.5V IN RANGE RANGE The V + inputs are coupled to the signal source and must have V) 4 ±10V IN E ( RANGE an amplitude within the selected range for that channel as G AN 2 programmed in the range registers. A dc input is applied to the R OM R±A1N0GVE VIN− pin. The voltage applied to this input provides an offset for C V 0 the VIN+ input from ground or a pseudo ground. Pseudo differential inputs separate the analog input signal ground from –2 the ADC ground, allowing cancellation of dc common mode VCC=5V voltages. VREF=3V –4 ±16.5VVDD/VSS ±12VVDD/VSS 05401-046 Wto hCeond ae c−o4n0v9e6r sainodn tthaek ems apxlaimceu, mth ea mpspeluitduod ge rcoournreds pcoornrdess ptoo nds Figure 36. Common-Mode Range for VCC = 5 V and REFIN/OUT = 3 V Code +4095. 6 V+ 5V 4 ±5VRANGE ±5VRANGE 2 VIN+ VDD VCC V) GE ( 0 AD73271 N RA VIN– VSS M –2 CO ±2.5V ±10V V ±10V RANGE RANGE ±2.5V –4 RANGE RANGE ––86 VVCRCEF==32V.5V ±16.5VVDD/VSS ±12VVDD/VSS 05401-047 Figure 40 and F1AigDFuDigIVrTu–eIOr e4N 13A9 Ls. hPPIosNewSu dOtohM DeIT iTtffyEeDpreiFcnOatRila vCl IoLnAlptRuaItTgsYe . ra05401-028n ge on the Figure 37. Common-Mode Range for VCC = 3 V and REFIN/OUT = 2.5 V V − pin for the different analog input ranges when configured IN in the pseudo differential mode. For example, when the AD7327 is configured to operate in pseudo differential mode and the ±5 V range is selected, with ±16.5 V V /V supplies and 5 V V , the voltage on the V − DD SS CC IN pin can vary from −6.5 V to +6.5 V. Rev. B | Page 20 of 36

Data Sheet AD7327 8 The driver amplifier must be able to settle for a full-scale step to ±5V RANGE ±5V RANGE NGE (V) 64 R±A1N0GVE R±A2N.5GVE R±A2N.5GVE atrie m1q3ue-i broeiftm tlheeevn etA lw,D 0h7.0e3n12 2o72p. %Aer,n ait noin pleg sa ismn t phsi ansnug cltehh- eea nssd pteehdcei fmAieDodd8 ae0c.2 qT1uh mies ieAtieoDtsn8 t0h2is1 A R GE 2 needs an external compensating NPO type of capacitor. The TA AD8022 can also be used in high frequency applications where L O 0 V a dual version is required. For lower frequency applications, op T PU –2 amps such as the AD797, AD845, and AD8610 can be used with N ±10V O I RANGE the AD7327 in single-ended mode configuration. D –4 U E Differential operation requires that V + and V − be simulta- S IN IN P –6 VCC = 5V 0VRTAON G+1E0V 0VRTAON G+1E0V neously driven with two signals of equal amplitude that are 180° –8 VREF = 2.5V ±16.5V VDD/VSS ±12V VDD/VSS 05401-039 oAuDt 7o3f 2p7h.a Tseh.e T choem cmomonm-omno mdeo rdaen mgeu isst dbeet esremt uinpe edx tbeyr nthaell yR tEoF tIhNe/ Figure 40. Pseudo Input Range with VCC = 5 V OUT voltage, the VCC supply voltage, and the particular amplifier 4 used to drive the analog inputs. Differential mode with either an ±5V RANGE ac input or a dc input provides the best THD performance over a E (V) 2 ±5V RANGE R±A2N.5GVE wide frequency range. Because not all applications have a signal G preconditioned for differential operation, there is often a need to N A R 0 perform the single-ended-to-differential conversion. E G TA This single-ended-to-differential conversion can be performed L VO –2 ±10V using an op amp pair. Typical connection diagrams for an op PUT ±2.5V RANGE amp pair are shown in Figure 42 and Figure 43. In Figure 42, O IN –4 R±A1N0GVE RANGE the common-mode signal is applied to the noninverting input D EU 0VTO +10V 0VTO +10V of the second amplifier. PS –6 RANGE RANGE 1.5kΩ VCC = 3V –8 VREF = 2.5V ±16.5V VDD/VSS ±12V VDD/VSS 05401-040 VIN 3kΩ AD845 V+ Figure 41. Pseudo Input Range with VCC = 3 V DRIVER AMPLIFIER CHOICE 1.5kΩ 1.5kΩ In applications where the harmonic distortion and signal-to- 1.5kΩ noise ratio are critical specifications, the analog input of the AD7327 should be driven from a low impedance source. Large V– 10kΩ source impedances significantly affect the ac performance of the VCOM AD845 ADC and can necessitate the use of an input buffer amplifier. 20kΩ 05401-029 When no amplifier is used to drive the analog input, the source Figure 42. Single-Ended-to-Differential Configuration with the AD845 impedance should be limited to low values. The maximum source 442Ω impedance depends on the amount of THD that can be tolerated in the application. The THD increases as the source impedance VIN 442Ω AD8021 increases and performance degrades. Figure 21 and Figure 22 V+ show graphs of the THD vs. the analog input frequency for various source impedances. Depending on the input range and analog 442Ω input configuration selected, the AD7327 can handle source 442Ω impedances of up to 5.5 kΩ before the THD starts to degrade. 442Ω Due to the programmable nature of the analog inputs on the 442Ω AD7327, the choice of op amp used to drive the inputs is a function of the particular application and depends on the input V– configuration and the analog input voltage ranges selected. AD8021 100Ω 05401-030 Figure 43. Single-Ended-to-Differential Configuration with the AD8021 Rev. B | Page 21 of 36

AD7327 REGISTERS The AD7327 has four programmable registers: the control register, sequence register, Range Register 1, and Range Register 2. These registers are write-only registers. ADDRESSING REGISTERS A serial transfer on the AD7327 consists of 16 SCLK cycles. The three MSBs on the DIN line during the 16 SCLK transfer are decoded to determine which register is addressed. The three MSBs consist of the write bit, the Register Select 1 bit, and the Register Select 2 bit. The register select bits are used to determine which of the four on-board registers is selected. The write bit determines if the data on the DIN line following the register select bits loads into the addressed register. If the write bit is 1, the bits load into the register addressed by the register select bits. If the write bit is 0, the data on the DIN line does not load into any register. Combinations of the write bit, the Register Select 1 bit, and the Register Select 2 bit other than those specified in Table 8 access registers for Analog Devices internal use only. Do not access these registers, as doing so may lead to unspecified operation of the device. Table 8. Decoding Register Select Bits and Write Bit Write Register Select 1 Register Select 2 Description 0 0 0 Data on the DIN line during this serial transfer is ignored. 1 0 0 This combination selects the control register. The subsequent 12 bits are loaded into the control register. 1 0 1 This combination selects Range Register 1. The subsequent 8 bits are loaded into Range Register 1. 1 1 0 This combination selects Range Register 2. The subsequent 8 bits are loaded into Range Register 2. 1 1 1 This combination selects the sequence register. The subsequent 8 bits are loaded into the sequence register. CONTROL REGISTER The control register is used to select the analog input channel, analog input configuration, reference, coding, and power mode. The control register is a write-only, 12-bit register. Data loaded on the DIN line corresponds to the AD7327 configuration for the next conversion. If the sequence register is being used, data should be loaded into the control register after the range registers and the sequence register have been initialized. The bit functions of the control register are shown in Table 9 (the power-up status of all bits is 0). MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Register Register ADD2 ADD1 ADD0 Mode 1 Mode 0 PM1 PM0 Coding Ref Seq1 Seq2 ZERO 0 Select 1 Select 2 Table 9. Control Register Details Bit Mnemonic Description 12, 11, 10 ADD2, ADD1, These three channel address bits are used to select the analog input channel for the next conversion if the ADD0 sequencer is not being used. If the sequencer is being used, the three channel address bits are used to select the final channel in a consecutive sequence. 9, 8 Mode 1, Mode 0 These two mode bits are used to select the configuration of the eight analog input pins, V 0 to V 7. These IN IN pins are used in conjunction with the channel address bits. On the AD7327, the analog inputs can be configured as eight single-ended inputs, four fully differential inputs, four pseudo differential inputs, or seven pseudo differential inputs (see Table 10). 7, 6 PM1, PM0 The power management bits are used to select different power mode options on the AD7327 (see Table 11). 5 Coding This bit is used to select the type of output coding the AD7327 uses for the next conversion result. If coding = 0, the output coding is twos complement. If coding = 1, the output coding is straight binary. When operating in sequence mode, the output coding for each channel is the value written to the coding bit during the last write to the control register. 4 Ref The reference bit is used to enable or disable the internal reference. If Ref = 0, the external reference is enabled and used for the next conversion and the internal reference is disabled. If Ref = 1, the internal reference is used for the next conversion. When operating in sequence mode, the reference used for each channel is the value written to the Ref bit during the last write to the control register. 3, 2 Seq1, Seq2 The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Table 12). 1 ZERO A 0 should be written to this bit at all times. Rev. B | Page 22 of 36

Data Sheet AD7327 The eight analog input channels can be configured as seven pseudo differential analog inputs, four pseudo differential inputs, four true differential inputs, or eight single-ended analog inputs. Table 10. Analog Input Configuration Selection Mode 1 = 1, Mode 0 = 1 Mode 1 = 1, Mode 0 = 0 Mode 1 = 0, Mode 0 =1 Mode 1 = 0, Mode 0 = 0 Channel Address Bits 7 Pseudo Differential Inputs 4 Fully Differential Inputs 4 Pseudo Differential Inputs 8 Single-Ended Inputs ADD2 ADD1 ADD0 V + V − V + V − V + V − V + V − IN IN IN IN IN IN IN IN 0 0 0 V 0 V 7 V 0 V 1 V 0 V 1 V 0 AGND IN IN IN IN IN IN IN 0 0 1 V 1 V 7 V 0 V 1 V 0 V 1 V 1 AGND IN IN IN IN IN IN IN 0 1 0 V 2 V 7 V 2 V 3 V 2 V 3 V 2 AGND IN IN IN IN IN IN IN 0 1 1 V 3 V 7 V 2 V 3 V 2 V 3 V 3 AGND IN IN IN IN IN IN IN 1 0 0 V 4 V 7 V 4 V 5 V 4 V 5 V 4 AGND IN IN IN IN IN IN IN 1 0 1 V 5 V 7 V 4 V 5 V 4 V 5 V 5 AGND IN IN IN IN IN IN IN 1 1 0 V 6 V 7 V 6 V 7 V 6 V 7 V 6 AGND IN IN IN IN IN IN IN 1 1 1 Temperature indicator V 6 V 7 V 6 V 7 V 7 AGND IN IN IN IN IN Table 11. Power Mode Selection PM1 PM0 Description 1 1 Full Shutdown Mode. In this mode, all internal circuitry on the AD7327 is powered down. Information in the control register is retained when the AD7327 is in full shutdown mode. 1 0 Autoshutdown Mode. The AD7327 enters autoshutdown on the 15th SCLK rising edge when the control register is updated. All internal circuitry is powered down in autoshutdown. 0 1 Autostandby Mode. In this mode, all internal circuitry is powered down, excluding the internal reference. The AD7327 enters autostandby mode on the 15th SCLK rising edge after the control register is updated. 0 0 Normal Mode. All internal circuitry is powered up at all times. Table 12. Sequencer Selection Seq1 Seq2 Description 0 0 The channel sequencer is not used. The analog input channel, selected by programming the ADD2 bit to ADD0 bit in the control register, selects the next channel for conversion. 0 1 Uses the sequence of channels previously programmed into the sequence register for conversion. The AD7327 starts converting on the lowest channel in the sequence. The channels are converted in ascending order. If uninterrupted, the AD7327 keeps converting the sequence. The range for each channel defaults to the range previously written into the corresponding range register. 1 0 Used in conjunction with the channel address bits in the control register. This allows continuous conversions on a consecutive sequence of channels, from Channel 0 up to and including a final channel selected by the channel address bits in the control register. The range for each channel defaults to the range previously written into the corresponding range register. 1 1 The channel sequencer is not used. The analog channel, selected by programming the ADD2 bit to ADD0 bit in the control register, selects the next channel for conversion. SEQUENCE REGISTER The sequence register on the AD7327 is an 8-bit, write-only register. Each of the eight analog input channels has one corresponding bit in the sequence register. To select an analog input channel for inclusion in the sequence, set the corresponding channel bit to 1 in the sequence register. MSB LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Write Register Select 1 Register Select 2 V 0 V 1 V 2 V 3 V 4 V 5 V 6 V 7 0 0 0 0 0 IN IN IN IN IN IN IN IN Rev. B | Page 23 of 36

AD7327 RANGE REGISTERS The range registers are used to select one analog input range per analog input channel. Range Register 1 is used to set the ranges for Channel 0 to Channel 3. It is an 8-bit, write-only register with two dedicated range bits for each of the analog input channels from Channel 0 to Channel 3. There are four analog input ranges, ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V. A write to Range Register 1 is selected by setting the write bit to 1 and the register select bits to 0 and 1. After the initial write to Range Register 1 occurs, each time an analog input is selected, the AD7327 automatically configures the analog input to the appropriate range, as indicated by Range Register 1. The ±10 V input range is selected by default on each analog input channel (see Table 13). MSB LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Write Register Register V 0A V 0B V 1A V 1B V 2A V 2B V 3A V 3B 0 0 0 0 0 IN IN IN IN IN IN IN IN Select 1 Select 2 Range Register 2 is used to set the ranges for Channel 4 to Channel 7. It is an 8-bit, write-only register with two dedicated range bits for each of the analog input channels from Channel 4 to Channel 7. There are four analog input ranges, ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V. After the initial write to Range Register 2 occurs, each time an analog input is selected, the AD7327 automatically configures the analog input to the appropriate range, as indicated by Range Register 2. The ±10 V input range is selected by default on each analog input channel (see Table 13). MSB LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Write Register Register V 4A V 4B V 5A V 5B V 6A V 6B V 7A V 7B 0 0 0 0 0 IN IN IN IN IN IN IN IN Select 1 Select 2 Table 13. Range Selection V xA V xB Description IN IN 0 0 This combination selects the ±10 V input range on V x. IN 0 1 This combination selects the ±5 V input range on V x. IN 1 0 This combination selects the ±2.5 V input range on V x. IN 1 1 This combination selects the 0 V to +10 V input range on V x. IN Rev. B | Page 24 of 36

Data Sheet AD7327 SEQUENCER OPERATION POWER ON. CS DIN:WRITETORANGEREGISTER1TOSELECTTHERANGE FOREACHANALOG INPUTCHANNEL. DOUT:CONVERSIONRESULTFROMCHANNEL0,±10V RANGE,SINGLE-ENDEDMODE. CS DIN:WRITETORANGEREGISTER2TOSELECTTHERANGE FOREACHANALOG INPUTCHANNEL. DOUT:CONVERSIONRESULTFROMCHANNEL0, SINGLE-ENDEDMODE,RANGESELECTED IN RANGEREGISTER1. CS DIN:WRITETOSEQUENCEREGISTERTOSELECTTHE ANALOG INPUTCHANNELSTOBE INCLUDED IN THESEQUENCE. DOUT:CONVERSIONRESULTFROMCHANNEL0, SINGLE-ENDEDMODE,RANGESELECTED IN RANGEREGISTER1. CS DIN:WRITETOCONTROLREGISTERTOSTARTTHE SEQUENCE,Seq1=0,Seq2=1. DOUT:CONVERSIONRESULTFROMCHANNEL0, SINGLE-ENDEDMODE,RANGESELECTED IN RANGEREGISTER1. CS DIN:TIEDINLOW/WRITEBIT=0TOCONTINUETOCONVERT THROUGHTHESEQUENCE OFCHANNELS. CS DOUT:CONVERSIONTHREESSUEQLTUEFNRCOEM.FIRSTCHANNEL IN DINTIEDLOW/WRITEBIT=0. DIN:WRITETOCONTROL REGISTERTOSTOPTHE SEQUENCE,Seq1=0,Seq2=0. STOPPING CONTINUOUSLYCONVERT ASEQUENCE. ONTHESELECTEDSEQUENCE DOUT:CONVERSIONRESULT OFCHANNELS. FROMCHANNEL INSEQUENCE. SELECTINGANEWSEQUENCE. CS DIN:WRITETOSEQUENCEREGISTERTOSELECTTHE NEWSEQUENCE. DOUT:CONVERSIONRESULTFROMCHANNELX IN THEFIRSTSEQUENCE. 05401-031 Figure 44. Programmable Sequence Flowchart The AD7327 can be configured to automatically cycle through a These two initial serial transfers are only necessary if input number of selected channels using the on-chip sequence register ranges other than the default ranges are required. After the with the Seq1 bit and the Seq2 bit in the control register. Figure 44 analog input ranges are configured, a write to the sequence shows how to program the AD7327 register to operate in register is necessary to select the channels to be included in the sequence mode. sequence. Once the channels for the sequence have been selected, the sequence can be initiated by writing to the control register After power-up, all of the four on-chip registers contain default and setting Seq1 to 0 and Seq2 to 1. The AD7327 continues to values. Each analog input has a default input range of ±10 V. If convert through the selected sequence without interruption, different analog input ranges are required, a write to the range provided the sequence register remains unchanged and Seq1 = registers is required. This is shown in the first two serial transfers 0 and Seq2 = 1 in the control register. of Figure 44. Rev. B | Page 25 of 36

AD7327 If a change to one of the range registers is required during a Once the control register is configured to operate the AD7327 sequence, it is necessary to first stop the sequence by writing to in this mode, the DIN line can be held low or the write bit can the control register and setting Seq1 to 0 and Seq2 to 0. Next, be set to 0. To return to traditional multichannel operation, a the write to the range register should be completed to change write to the control register to set Seq1 to 0 and Seq2 to 0 is the required range. The previously selected sequence should necessary. then be initiated again by writing to the control register and When Seq1 and Seq2 are both set to 0, or when both are set setting Seq1 to 0 and Seq2 to 1. The ADC converts the first to 1, the AD7327 is configured to operate in traditional multi- channel in the sequence. channel mode, where a write to the Channel Address Bit ADD2 The AD7327 can be configured to convert a sequence of to Bit ADD0 in the control register selects the next channel for consecutive channels (see Figure 45). This sequence begins by conversion. converting on Channel 0 and ends with a final channel as selected by Bit ADD2 to Bit ADD0 in the control register. In this configuration, there is no need for a write to the sequence register. To operate the AD7327 in this mode, set Seq1 to 1 and Seq2 to 0, and then select the final channel in the sequence by programming Bit ADD2 to Bit ADD0 in the control register. POWER ON. CS DIN:WRITETORANGEREGISTER1TOSELECTTHERANGE FORANALOG INPUTCHANNELS. DOUT:CONVERSIONRESULTFROMCHANNEL0,±10V RANGE,SINGLE-ENDEDMODE. CS DIN:WRITETORANGEREGISTER2TOSELECTTHERANGE FORANALOG INPUTCHANNELS. DOUT:CONVERSIONRESULTFROMCHANNEL0, RANGESELECTED INRANGEREGISTER1, SINGLE-ENDEDMODE. CS DIN:WRITETOCONTROLREGISTERTOSELECTTHEFINAL CHANNEL INTHECONSECUTIVESEQUENCE,SETSeq1=1 ANDSeq2=0.SELECT OUTPUTCODINGFORSEQUENCE. DOUT:CONVERSIONRESULTFROMCHANNEL0, RANGESELECTED INRANGEREGISTER1, SINGLE-ENDEDMODE. CS DIN:WRITEBIT=0 ORDINLINEHELDLOWTOCONTINUE TOCONVERTTHROUGHTHESEQUENCE OF CONSECUTIVECHANNELS. DOUT:CONVERSIONRESULTFROMCHANNEL0, RANGESELECTED INRANGEREGISTER1. CS DIN:WRITEBIT=0 ORDINLINEHELDLOWTOCONTINUE THROUGHSEQUENCE OFCONSECUTIVECHANNELS. DOURTA:NCGOENSVEELRESCIOTENDR IENSRUALNTGFERORMEGCISHTAENRNE1.L1, DINTIEDLOW/WRITEBIT=0. CONTINUOUSLYCONVERT STOPPING ONCONSECUTIVESEQUENCE ASEQUENCE. OFCHANNELS. CS DIN:WRITETOCONTROL REGISTERTOSTOPTHE SEQUENCE,Seq1=0,Seq2=0. FDROOUMTC:HCAONNNVEELR SINIOSNEQREUSEUNLCTE. 05401-032 Figure 45. Flowchart for Consecutive Sequence of Channels Rev. B | Page 26 of 36

Data Sheet AD7327 REFERENCE TEMPERATURE INDICATOR The AD7327 can operate with either the internal 2.5 V on- The AD7327 has an on-chip temperature indicator. The chip reference or an externally applied reference. The internal temperature indicator can be used to give local temperature reference is selected by setting the Ref bit in the control register measurements on the AD7327. To access the temperature to 1. On power-up, the Ref bit is 0, which selects the external indicator, the ADC should be configured in pseudo differential reference for the AD7327 conversion. Suitable reference sources mode, Mode 1 = Mode 0 = 1, and channel Bit ADD2, Bit ADD1, for the AD7327 include AD780, AD1582, ADR431, REF193, and Bit ADD0 should be set to 1. V 7 must be tied to AGND or IN and ADR391. to a small dc voltage within the specified pseudo input range for the selected analog input range. When a conversion is initiated The internal reference circuitry consists of a 2.5 V band gap in this configuration, the output code represents the temperature reference and a reference buffer. When operating the AD7327 (see Figure 46 and Figure 47). When using the temperature in internal reference mode, the 2.5 V internal reference is available indicator on the AD7327, the part should be operated at low at the REFIN/OUT pin, which should be decoupled to AGND throughput rates, such as approximately 50 kSPS for the ±10 V using a 680 nF capacitor. It is recommended that the internal range and 30 kSPS for the ±2.5 V range. The throughput rate is reference be buffered before applying it elsewhere in the system. reduced for the temperature indicator mode because the AD7327 The internal reference is capable of sourcing up to 90 μA. requires more acquisition time for this mode. On power-up, if the internal reference operation is required for 4420 the ADC conversion, a write to the control register is necessary VCC=VDRIVE=5V to set the Ref bit to 1. During the control register write, the 4410 VDD/VSS=±12V 50kSPS conversion result from the first initial conversion is invalid. The 4400 reference buffer requires 500 μs to power up and charge the DE ±10VRANGE, INTREF 680 nF decoupling capacitor during the power-up time. O4390 C T U The AD7327 is specified for a 2.5 V to 3 V reference range. P4380 T U When a 3 V reference is selected, the ranges are ±12 V, ±6 V, O C4370 ±3 V, and 0 V to +12 V. For these ranges, the V and V supply D DD SS A must be equal to or greater than the maximum analog input 4360 range selected (see Table 6). 4350 V DRIVE 4340 tThhee s AerDia7l 3in2t7e hrfaasc ea oVpDeRrIVaEt efse.a Vture to a clolonwtrso tlh teh eA vDoClt atgoe e aats iwlyh ich –40 –20 0 TEM2P0ERATUR4E0(°C) 60 80 100 05401-033 DRIVE Figure 46. Temperature vs. ADC Output Code for ±10 V Range interface to both 3 V and 5 V processors. For example, if the 5450 AD7327 is operated with a V of 5 V, the V pin can be CC DRIVE VCC=VDRIVE=5V powered from a 3 V supply. This allows the AD7327 to accept VDD/VSS=±12V 5400 ±2.5VRANGE large bipolar input signals with low voltage digital processing. INTREFERENCE 30kSPS 5350 E D O C T5300 U P T U O5250 C D A 5200 5150 5100 –40 –20 0TEMPERA20TURE(°C4)0 60 80 05401-034 Figure 47. Temperature vs. ADC Output Code for ±2.5 V Range Rev. B | Page 27 of 36

AD7327 MODES OF OPERATION The AD7327 has several modes of operation that are designed The AD7327 remains fully powered up at the end of the to provide flexible power management options. These options conversion if both PM1 and PM0 contain 0 in the control can be chosen to optimize the power dissipation/throughput register. rate ratio for different application requirements. The mode of To complete the conversion and access the conversion result, operation of the AD7327 is controlled by the power management 16 serial clock cycles are required. At the end of the conversion, bits, Bit PM1 and Bit PM0, in the control register as shown in CS can idle either high or low until the next conversion. Table 11. The default mode is normal mode, where all internal Once the data transfer is complete, another conversion can be circuitry is fully powered up. initiated after the quiet time, t , has elapsed. QUIET NORMAL MODE FULL SHUTDOWN MODE (PM1 = PM0 = 0) (PM1 = PM0 = 1) This mode is intended for the fastest throughput rate performance In this mode, all internal circuitry on the AD7327 is powered with the AD7327 being fully powered up at all times. Figure 48 down. The part retains information in the registers during full shows the general operation of the AD7327 in normal mode. shutdown. The AD7327 remains in full shutdown mode until The conversion is initiated on the falling edge of CS, and the the power management bits, Bit PM1 and Bit PM0, in the track-and-hold section enters hold mode, as described in the control register are changed. Serial Interface section. Data on the DIN line during the 16 SCLK A write to the control register with PM1 = 1 and PM0 = 1 places transfer is loaded into one of the on-chip registers if the write bit the part into full shutdown mode. The AD7327 enters full shut- is set. The register is selected by programming the register select down mode on the 15th SCLK rising edge once the control register bits (see Table 8). is updated. CS If a write to the control register occurs while the part is in full 1 16 shutdown mode with the power management bits, Bit PM1 and SCLK Bit PM0, set to 0 (normal mode), the part begins to power up on the 15th SCLK rising edge once the control register is updated. DOUT 3CHANNEL I.D.BITS,SIGNBIT+CONVERSIONRESULT Figure 49 shows how the AD7327 is configured to exit full DIN DATA INTOCONTROLR/ESGEQISUTEENRCE/RANGE1/RANGE2 05401-035 stPhOuWtEdRo-UwP nsh mouoldde e. lTaop seen bsuefroer teh teh Ae Dne7x3t2 C7 Sis f afulllilnyg p eodwgeer. ed up, Figure 48. Normal Mode THEPARTISFULLYPOWEREDUP PART IS INFULL ONCEtPOWER-UPHASELAPSED SHUTDOWN PARTBEGINSTOPOWERUP ONTHE15TH SCLKRISINGEDGEASPM1=PM0=0 tPOWER-UP CS 1 16 1 16 SCLK SDATA INVALIDDATA CHANNEL IDENTIFIERBITS+CONVERSIONRESULT DIN DATA INTOCONTROLREGISTER DATA INTOCONTROLREGISTER CONTROLREGISTER IPSML1O=A0D,EPDM O0N=T0HEFIRST15CLOCKS, TOKEEPTHEPARITN INCONNOTRRMOALLRMEOGDISET,ELROADPM1=PM0=0 05401-041 Figure 49. Exiting Full Shutdown Mode Rev. B | Page 28 of 36

Data Sheet AD7327 AUTOSHUTDOWN MODE As is the case with autoshutdown mode, the AD7327 enters standby on the 15th SCLK rising edge once the control register is (PM1 = 1, PM0 = 0) updated (see Figure 50). The part retains information in the Once the autoshutdown mode is selected, the AD7327 auto- registers during standby. The AD7327 remains in standby until matically enters shutdown on the 15th SCLK rising edge. In it receives a CS rising edge. The ADC begins to power up on the autoshutdown mode, all internal circuitry is powered down. CS rising edge. On the CS rising edge, the track-and-hold, which The AD7327 retains information in the registers during was in hold mode while the part was in standby, returns to track. autoshutdown. The track-and-hold is in hold mode during autoshutdown. On the rising CS edge, the track-and-hold, which The power-up time from standby is 700 ns. The user should was in hold during autoshutdown, returns to track as the AD7327 ensure that 700 ns have elapsed before bringing CS low to begins to power up. The power-up from autoshutdown is 500 µs. attempt a valid conversion. Once this valid conversion is complete, the AD7327 again returns to standby on the 15th When the control register is programmed to transition to SCLK rising edge. The CS signal must remain low to keep the autoshutdown mode, it does so on the 15th SCLK rising edge. part in standby mode. Figure 50 shows the part entering autoshutdown mode. The AD7327 automatically begins to power up on the CS rising Figure 50 shows the part entering autoshutdown mode. The edge. The t is required before a valid conversion, initiated sequence of events is the same when entering autostandby POWER-UP by bringing the CS signal low, can take place. Once this valid mode. In Figure 50, the power management bits are configured for autoshutdown. For autostandby mode, the power management conversion is complete, the AD7327 powers down again on the bits, PM1 and PM0, should be set to 0 and 1, respectively. 15th SCLK rising edge. The CS signal must remain low again to keep the part in autoshutdown mode. AUTOSTANDBY MODE (PM1 = 0, PM0 =1) In autostandby mode, portions of the AD7327 are powered down, but the on-chip reference remains powered up. The reference bit in the control register should be 1 to ensure that the on-chip reference is enabled. This mode is similar to auto- shutdown but allows the AD7327 to power up much faster, which allows faster throughput rates. PARTBEGINSTOPOWER THEPART ISFULLYPOWEREDUP UP ONCSRISINGEDGE ONCEtPOWER-UPHASELAPSED PARTENTERSSHUTDOWNMODE tPOWER-UP ONTHE15THRISINGSCLKEDGE CS ASPM1=1,PM0=0 1 15 16 1 15 16 SCLK SDATA VALIDDATA VALIDDATA DIN DATA INTOCONTROLREGISTER DATA INTOCONTROLREGISTER CONTROLREGISTER IPSML1O=A1D,EPDM O0N=T0HEFIRST15CLOCKS, 05401-042 Figure 50. Entering Autoshutdown/Autostandby Mode Rev. B | Page 29 of 36

AD7327 POWER VS. THROUGHPUT RATE The power consumption of the AD7327 varies with throughput 20 VCC=5V rate. The static power consumed by the AD7327 is very low, and 18 VDD/VSS=±12V TA=25°C significant power savings can be achieved as the throughput rate is 16 INTERNALREFERENCE reduced. Figure 51 and Figure 52 shows the power vs. throughput mW) 14 rate for the AD7327 at a VCC of 3 V and 5 V, respectively. Both ER ( 12 plots clearly show that the average power consumed by the W AD7327 is greatly reduced as the sample frequency is reduced. E PO 10 This is true whether a fixed SCLK value is used or if it is scaled AG 8 R E with the sampling frequency. Figure 51 and Figure 52 show the AV 6 VARIABLESCLK power consumption when operating in normal mode for a 4 variable SCLK that scales with the sampling frequency. 2 12 10 TIVVNACDTCD=E/=VR2S5N3S°VAC=L±R1E2FVERENCE 00 100 THROU20G0HPUTRAT3E00(kSPS) 400 500 05401-053 Figure 52. Power vs. Throughput Rate with 5 V VCC W) m 8 ER ( W PO 6 E G A ER 4 VARIABLESCLK V A 2 0 0 100 THROU20G0HPUTRAT3E00(kSPS) 400 500 05401-052 Figure 51. Power vs. Throughput Rate with 3 V VCC Rev. B | Page 30 of 36

Data Sheet AD7327 SERIAL INTERFACE Figure 53 shows the timing diagram for the serial interface of Data is clocked into the AD7327 on the SCLK falling edge. The the AD7327. The serial clock applied to the SCLK pin provides three MSBs on the DIN line are decoded to select which register the conversion clock and controls the transfer of information to is addressed. The control register is a 12-bit register. If the control and from the AD7327 during a conversion. register is addressed by the three MSBs, the data on the DIN line is loaded into the control on the 15th SCLK falling edge. If The CS signal initiates the data transfer and the conversion the sequence register or either of the range registers is addressed, process. The falling edge of CS puts the track-and-hold into the data on the DIN line is loaded into the addressed register hold mode and takes the bus out of three-state. Then the analog on the 11th SCLK falling edge. input signal is sampled. Once the conversion is initiated, it requires 16 SCLK cycles to complete. Conversion data is clocked out of the AD7327 on each SCLK falling edge. Data on the DOUT line consists of three channel The track-and-hold goes back into track mode on the 14th SCLK identifier bits, a sign bit, and a 12-bit conversion result. The rising edge. On the 16th SCLK falling edge, the DOUT line returns channel identifier bits are used to indicate which channel to three-state. If the rising edge of CS occurs before 16 SCLK corresponds to the conversion result. The ADD2 bit is clocked cycles have elapsed, the conversion is terminated, and the DOUT out on the CS falling edge, and the ADD1 bit is clocked out on line returns to three-state. Depending on where the CS signal is the first SCLK falling edge. brought high, the addressed register may be updated. t1 CS tCONVERT t2 t6 SCLK 1 2 3 4 5 13 14 15 16 3t 3IDENTIFICATIONBITS t4 t7 t5 t8 tQUIET DOUT ADD1 ADD0 SIGN DB11 DB10 DB2 DB1 DB0 TSHTRAETEE- ADD2 t9 t10 THREE-STATE DIN WRITE SREELG1 SREELG2 MSB LSB DCOANR’ET 05401-036 Figure 53. Serial Interface Timing Diagram (Control Register Write) Rev. B | Page 31 of 36

AD7327 MICROPROCESSOR INTERFACING The serial interface on the AD7327 allows the part to be directly The frequency of the serial clock is set in the SCLKDIV register. connected to a range of different microprocessors. This section When the instruction to transmit with TFS is given (AX0 = explains how to interface the AD7327 with some common TX0), the state of the serial clock is checked. The DSP waits microcontroller and DSP serial interface protocols. until the SCLK has gone high, low, and high again before AD7327 TO ADSP-21xx starting the transmission. If the timer and SCLK are chosen so that the instruction to transmit occurs on or near the rising The ADSP-21xx family of DSPs interface directly to the AD7327 edge of SCLK, data can be transmitted immediately or at the without requiring glue logic. The V pin of the AD7327 takes DRIVE next clock edge. the same supply voltage as that of the ADSP-21xx. This allows For example, the ADSP-2111 has a master clock frequency of the ADC to operate at a higher supply voltage than its serial 16 MHz. If the SCLKDIV register is loaded with the value 3, an interface. The SPORT0 on the ADSP-21xx should be configured SCLK of 2 MHz is obtained, and eight master clock periods elapse as shown in Table 14. for every one SCLK period. If the timer registers are loaded with Table 14. SPORT0 Control Register Setup the value 803, 100.5 SCLKs occur between interrupts and, sub- Setting Description sequently, between transmit instructions. This situation leads to TFSW = RFSW = 1 Alternative framing nonequidistant sampling because the transmit instruction occurs INVRFS = INVTFS = 1 Active low frame signal on an SCLK edge. If the number of SCLKs between interrupts is DTYPE = 00 Right justify data an integer of N, equidistant sampling is implemented by the DSP. SLEN = 1111 16-bit data-word AD7327 TO ADSP-BF53x ISCLK = 1 Internal serial clock The ADSP-BF53x family of DSPs interfaces directly to the TFSR = RFSR = 1 Frame every word AD7327 without requiring glue logic, as shown in Figure 55. IRFS = 0 The SPORT0 Receive Configuration 1 register should be set up ITFS = 1 as outlined in Table 15. The connection diagram is shown in Figure 54. The ADSP-21xx has TFS0 and RFS0 tied together. TFS0 is set as an output, and AD73271 ADSP-BF53x1 RFS0 is set as an input. The DSP operates in alternative framing SCLK RSCLK0 mode, and the SPORT0 control register is set up as described in Table 14. The frame synchronization signal generated on the TFS CS RFS0 is tied to CS, and, as with all signal processing applications, requires DIN DT0 equidistant sampling. However, as in this example, the timer DOUT DR0 interrupt is used to control the sampling rate of the ADC, and VDRIVE under certain conditions, equidistant sampling cannot be achieved. AD7327S1CLK SCALKD0SP-21xx1 1ADDITIONALPINS OMITTEDFORCLARITY. VDD 05401-038 Figure 55. Interfacing the AD7327 to the ADSP-BF53x CS TFS0 RFS0 Table 15. SPORT0 Receive Configuration 1 Register DIN DT0 Setting Description DOUT DR0 RCKFE = 1 Sample data with falling edge of RSCLK VDRIVE LRFS = 1 Active low frame signal RFSR = 1 Frame every word IRFS = 1 Internal RFS used 1ADDITIONALPINS OMITTEDFORCLARITY. VDD 05401-037 RLSBIT = 0 Receive MSB first RDTYPE = 00 Zero fill Figure 54. Interfacing the AD7327 to the ADSP-21xx IRCLK = 1 Internal receive clock The timer registers are loaded with a value that provides an RSPEN = 1 Receive enable interrupt at the required sampling interval. When an interrupt SLEN = 1111 16-bit data-word is received, a value is transmitted with TFS/DT (ADC control TFSR = RFSR = 1 word). The TFS is used to control the RFS, and hence the reading of data. Rev. B | Page 32 of 36

Data Sheet AD7327 APPLICATION HINTS LAYOUT AND GROUNDING POWER SUPPLY CONFIGURATION The printed circuit board that houses the AD7327 should be It is recommended that Schottky diodes be placed in series with designed so that the analog and digital sections are confined to the AD7327 V and V supply signals. Figure 56 shows this DD SS certain areas of the board. This design facilitates the use of Schottky diode configuration. BAT43 Schottky diodes are used. ground planes that can easily be separated. V+ 3V/5V To provide optimum shielding for ground planes, a minimum etch technique is generally best. All AGND pins on the AD7327 VDD VCC should be connected to the AGND plane. Digital and analog AD73271 ground pins should be joined in only one place. If the AD7327 VIN0 CS is in a system where multiple devices require an AGND and VIN1 DGND connection, the connection should still be made at only VIN2 SCLK one point. A star point should be established as close as possible VIN3 to the ground pins on the AD7327. VIN4 DOUT VIN5 Good connections should be made to the power and ground VIN6 DIN planes. This can be done with a single via or multiple vias for VIN7 VSS each supply and ground pin. Avoid running digital lines under the AD7327 device because tphlaisn ceo suhpoluelsd n boeis ael loonwtoed t htoe druien. Hunodweerv tehre, tAheD a7n3a2l7o gto g arvoouindd 1ADDITIONAL PINS OVM–ITTED FOR CLARITY.05401-056 Figure 56. Schottky Diode Connection noise coupling. The power supply lines to the AD7327 device should use as large a trace as possible to provide low impedance In an application where non-symmetrical VDD and VSS supplies paths and reduce the effects of glitches on the power supply line. are being used, adhere to the following guidelines. Table 16 outlines the V supply range that can be used for particular To avoid radiating noise to other sections of the board, com- SS V voltages when non-symmetrical supplies are required. ponents, such as clocks, with fast switching signals should be DD When operating the AD7327 with low V and V voltages, it shielded with digital ground and never run near the analog inputs. DD SS is recommended that these supplies be symmetrical. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough within the board, traces should be run at right Table 16. Non-Symmetrical V and V Requirements DD SS angles to each other. A microstrip technique is the best method, V Typical V Range DD SS but its use may not be possible with a double-sided board. In 5 V −5 V to −5.5 V this technique, the component side of the board is dedicated to 6 V −5 V to −8.5 V ground planes, and signals are placed on the other side. 7 V −5 V to −11.5 V Good decoupling is also important. All analog supplies should 8 V −5 V to −15 V be decoupled with 10 µF tantalum capacitors in parallel with 9 V −5 V to −16.5 V 0.1 µF capacitors to AGND. To achieve the best results from 10 V to 16.5 V −5 V to −16.5 V these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The For the 0 to 4 × V range, V can be tied to AGND as per REF SS 0.1 µF capacitors should have a low effective series resistance minimum supply recommendations outlined in Table 6. (ESR) and low effective series inductance (ESI), such as is typical of common ceramic and surface mount types of capacitors. These low ESR, low ESI capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Rev. B | Page 33 of 36

AD7327 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 0.15 1.20 MAX 0.20 0.05 0.09 0.75 0.30 8° 0.60 COPLANARITY 0.19 SEATING 0° 0.45 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 57. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions show in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD7327BRUZ −40°C to +85°C 20-Lead TSSOP RU-20 AD7327BRUZ-REEL −40°C to +85°C 20-Lead TSSOP RU-20 AD7327BRUZ-REEL7 −40°C to +85°C 20-Lead TSSOP RU-20 EVAL-AD7327SDZ Evaluation Board EVAL-SDP-CB1Z Controller Board 1 Z = RoHS Compliant Part. Rev. B | Page 34 of 36

Data Sheet AD7327 NOTES Rev. B | Page 35 of 36

AD7327 Data Sheet NOTES ©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05401-0-12/13(B) Rev. B | Page 36 of 36

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7327BRUZ-REEL AD7327BRUZ-REEL7 AD7327BRUZ