500 kSPS, 4-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC Data Sheet AD7323 FEATURES FUNCTIONAL BLOCK DIAGRAM 12-bit plus sign SAR ADC VDD REFIN/OUT VCC True bipolar input ranges AD7323 Software-selectable input ranges ±10 V, ±5 V, ±2.5 V, 0 V to +10 V 2.5V VIN0 VREF 500 kSPS throughput rate VIN1 I/P SUC1C3-EBSITSIVE Four analog input channels with channel sequencer VIN2 MUX T/H APPROXIMATION VIN3 ADC Single-ended, true differential, and pseudo differential analog input capability High analog input impedance DOUT Low power: 18 mW CHANNEL CONTROLLOGIC SCLK Full power signal bandwidth: 22 MHz SEQUENCER ANDREGISTERS CS Internal 2.5 V reference DIN High speed serial interface VDRIVE P1o6-wleeard-d ToSwSnO mP poadceksa ge AGND VSS DGND 05400-001 iCMOS process technology Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD73231 is a 4-channel, 12-bit plus sign successive 1. The AD7323 can accept true bipolar analog input signals, approximation analog-to-digital converter (ADC) designed on ±10 V, ±5 V, and ±2.5 V, and 0 V to +10 V unipolar signals. the iCMOS™ (industrial CMOS) process. iCMOS is a process 2. The four analog inputs can be configured as four single- combining high voltage silicon with submicron CMOS and ended inputs, two true differential input pairs, two pseudo complementary bipolar technologies. It enables the development differential inputs, or three pseudo differential inputs. of a wide range of high performance analog ICs capable of 33 V 3. 500 kSPS serial interface. SPI-/QSPI™-/DSP-/MICROWIRE™- operation in a footprint that no previous generation of high compatible interface. voltage parts could achieve. Unlike analog ICs using conven- 4. Low power, 18 mW, at a maximum throughput rate of tional CMOS processes, iCMOS components can accept bipolar 500 kSPS. input signals while providing increased performance, dramati- 5. Channel sequencer. cally reduced power consumption, and reduced package size. Table 1. Similar Devices The AD7323 can accept true bipolar analog input signals. The Device Throughput Number of AD7323 has four software selectable input ranges, ±10 V, ±5 V, Number Rate Number of bits Channels ±2.5 V, and 0 V to +10 V. Each analog input channel can be AD7329 1000 kSPS 12-bit plus sign 8 independently programmed to one of the four input ranges. AD7328 1000 kSPS 12-bit plus sign 8 The analog input channels on the AD7323 can be programmed AD7327 500 kSPS 12-bit plus sign 8 to be single-ended, true differential, or pseudo differential. AD7324 1000 kSPS 12-bit plus sign 4 The ADC contains a 2.5 V internal reference. The AD7323 also AD7322 1000 kSPS 12-bit plus sign 2 allows for external reference operation. If a 3 V reference is AD7321 500 kSPS 12-bit plus sign 2 applied to the REFIN/OUT pin, the AD7323 can accept a true bipolar ±12 V analog input. Minimum ±12 V V and V DD SS supplies are required for the ±12 V input range. The ADC has a high speed serial interface that can operate at throughput rates up to 500 kSPS. 1 Protected by U.S. Patent No. 6,731,232. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7323 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Control Register ......................................................................... 23 Functional Block Diagram .............................................................. 1 Sequence Register ....................................................................... 25 General Description ......................................................................... 1 Range Register ............................................................................ 25 Product Highlights ........................................................................... 1 Sequencer Operation ..................................................................... 26 Revision History ............................................................................... 2 Reference ..................................................................................... 28 Specifications ..................................................................................... 3 V ............................................................................................ 28 DRIVE Timing Specifications .................................................................. 7 Modes of Operation ....................................................................... 29 Absolute Maximum Ratings ............................................................ 8 Normal Mode (PM1 = PM0 = 0) ............................................. 29 ESD Caution .................................................................................. 8 Full Shutdown Mode (PM1 = PM0 = 1) ................................. 29 Pin Configuration and Function Descriptions ............................. 9 Autoshutdown Mode (PM1 = 1, PM0 = 0) ............................. 30 Typical Performance Characteristics ........................................... 10 Autostandby Mode (PM1 = 0, PM0 = 1) ................................ 30 Terminology .................................................................................... 14 Power vs. Throughput Rate ....................................................... 31 Theory of Operation ...................................................................... 16 Serial Interface ................................................................................ 32 Circuit Information .................................................................... 16 Microprocessor Interfacing ........................................................... 33 Converter Operation .................................................................. 16 AD7323 to ADSP-21xx .............................................................. 33 Analog Input Structure .............................................................. 17 AD7323 to ADSP-BF53x ........................................................... 33 Typical Connection Diagram ................................................... 19 Application Hints ........................................................................... 34 Analog Input ............................................................................... 19 Layout and Grounding .............................................................. 34 Driver Amplifier Choice ............................................................ 21 Power Supply Configuration .................................................... 34 Registers ........................................................................................... 22 Outline Dimensions ....................................................................... 35 Addressing Registers .................................................................. 22 Ordering Guide .......................................................................... 35 REVISION HISTORY 12/13—Rev. A to Rev. B Changes to Figure 30 ...................................................................... 18 Changes to Circuit Information Section and Table 6 ................ 16 Changes to Figure 33 and Figure 34............................................. 19 Changes to Addressing Registers Section .................................... 22 Changes to Figure 39 ...................................................................... 20 Changes to Power Supply Configuration Section ...................... 34 Changes to Figure 40 and Figure 41............................................. 21 Changes to Autostandby Mode (PM1 = 0, PM0 = 1) Section .. 30 1/10—Rev. 0 to Rev. A Changes to Table 14 and Table 15 ................................................ 33 Changes to Features and General Description Sections .............. 1 Added Power Supply Configuration Section .............................. 34 Changes to Power Requirements, Normal Mode (Operational), Added Figure 54; Renumbered Sequentially .............................. 34 I and I Parameter; and Power Dissipation, Normal Mode Added Table 16; Renumbered Sequentially ................................ 34 CC DRIVE (Operational) Parameter, Table 2 ................................................... 5 Changes to Ordering Guide .......................................................... 35 Changes to Endnote 1, Table 4 ........................................................ 8 Changes to Table 6, Figure 23, and Figure 24 ............................. 16 1/06—Revision 0: Initial Version Changes to Figure 25, Figure 26, and Figure 29 ......................... 17 Rev. B | Page 2 of 36

Data Sheet AD7323 SPECIFICATIONS V = 12 V to 16.5 V, V = −12 V to −16.5 V, V = 2.7 V to 5.25 V, V = 2.7 V to 5.25 V, V = 2.5 V to 3.0 V internal/external, DD SS CC DRIVE REF f = 10 MHz, f = 500 kSPS, T = T to T , unless otherwise noted. SCLK S A MAX MIN Table 2. B Version Parameter1 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave IN Signal-to-Noise Ratio (SNR)2 76 dB Differential mode, V = 4.75 V to 5.25 V CC 75.5 dB Differential mode, V < 4.75 V CC 72.5 dB Single-ended/pseudo differential mode; ±10 V, ±2.5 V and ±5 V ranges, V = 4.75 V to 5.25 V CC 72 dB Single-ended/pseudo differential mode; 0 V to 10 V, V = 4.75 V to 5.25 V and all ranges at V < 4.75 V CC CC Signal-to-Noise + Distortion 75 dB Differential mode; ±2.5 V and ±5 V ranges (SINAD)2 74 dB Differential mode; 0 V to 10 V 76 dB Differential mode; ±10 V range 72 dB Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges 72.5 dB Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges Total Harmonic Distortion −80 dB Differential mode; ±2.5 V and ±5 V ranges (THD)2 −79 dB Differential mode; 0 V to 10 V ranges −82 dB Differential mode; ±10 V range −77 dB Single-ended/pseudo differential mode; ±5 V range −79 dB Single-ended/pseudo differential mode; ±2.5 V range −80 dB Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges Peak Harmonic or Spurious −81 dB Differential mode; ±2.5 V and ±5 V ranges Noise (SFDR)2 −80 dB Differential mode; 0 V to 10 V ranges −82 dB Differential mode; ±10 V ranges −78 dB Single-ended/pseudo differential mode; ±5 V range −80 Single-ended/pseudo differential mode; ±2.5 V range −79 dB Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges Intermodulation Distortion fa = 50 kHz, fb = 30 kHz (IMD)2 Second-Order Terms −88 dB Third-Order Terms −90 dB Aperture Delay3 7 ns Aperture Jitter3 50 ps Common-Mode Rejection −79 dB Up to 100 kHz ripple frequency; see Figure 17 (CMRR)2 Channel-to-Channel −72 dB f on unselected channels up to 100 kHz; see Figure 14 IN Isolation2 Full Power Bandwidth 22 MHz At 3 dB 5 MHz At 0.1 dB Rev. B | Page 3 of 36

AD7323 Data Sheet B Version Parameter1 Min Typ Max Unit Test Conditions/Comments DC ACCURACY Single-ended/pseudo differential mode: 1 LSB = FSR/4096; unless otherwise noted Differential mode: 1 LSB = FSR/8192; unless otherwise noted Resolution 13 Bits No Missing Codes 12-bit plus Bits Differential mode sign (13 bits) 11-bit plus Bits Single-ended/pseudo differential mode sign (12 bits) Integral Nonlinearity2 ±1.1 LSB Differential mode; VCC = 3 V to 5.25 V, typ for VCC = 2.7 V ±1 LSB Single-ended/pseudo differential mode, V = 3 V to 5.25 V, CC typical for V = 2.7 V CC −0.7/+1.2 LSB Single-ended/pseudo differential mode (LSB = FSR/8192) Differential Nonlinearity2 −0.9/+1.2 LSB Differential mode; guaranteed no missing codes to 13 bits ±0.9 LSB Single-ended mode; guaranteed no missing codes to 12 bits −0.7/+1 LSB Single-ended/pseudo differential mode (LSB = FSR/8192) Offset Error2, 4 −4/+9 LSB Single-ended/pseudo differential mode −7/+10 LSB Differential mode Offset Error Match2, 4 ±0.6 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Gain Error2, 4 ±8 LSB Single-ended/pseudo differential mode ±14 LSB Differential mode Gain Error Match2, 4 ±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Positive Full-Scale Error2, 5 ±4 LSB Single-ended/pseudo differential mode ±7 LSB Differential mode Positive Full-Scale Error ±0.5 LSB Single-ended/pseudo differential mode Match2, 5 ±0.5 LSB Differential mode Bipolar Zero Error2, 5 ±8.5 LSB Single-ended/pseudo differential mode ±7.5 LSB Differential mode Bipolar Zero Error Match2, 5 ±0.5 LSB Single-ended/pseudo differential mode ±0.5 LSB Differential mode Negative Full-Scale Error2, 5 ±4 LSB Single-ended/pseudo differential mode ±6 LSB Differential mode Negative Full-Scale Error ±0.5 LSB Single-ended/pseudo differential mode Match2, 5 ±0.5 LSB Differential mode ANALOG INPUT Input Voltage Ranges Reference = 2.5 V; see Table 6 (Programmed via Range ±10 V V = 10 V min, V = −10 V min, V = 2.7 V to 5.25 V DD SS CC Register) ±5 V V = 5 V min, V = −5 V min, V = 2.7 V to 5.25 V DD SS CC ±2.5 V V = 5 V min, V = −5 V min, V = 2.7 V to 5.25 V DD SS CC 0 to 10 V V = 10 V min, V = AGND min, V = 2.7 V to 5.25 V DD SS CC Pseudo Differential VIN(−) VDD = 16.5 V, VSS = −16.5 V, VCC = 5 V; see Figure 40 and Input Range Figure 41 ±3.5 V Reference = 2.5 V; range = ±10 V ±6 V Reference = 2.5 V; range = ±5 V ±5 V Reference = 2.5 V; range = ±2.5 V +3/−5 V Reference = 2.5 V; range = 0 V to +10 V DC Leakage Current ±80 nA V = V or V IN DD SS 3 nA Per input channel, V = V or V IN DD SS Rev. B | Page 4 of 36

Data Sheet AD7323 B Version Parameter1 Min Typ Max Unit Test Conditions/Comments Input Capacitance3 13.5 pF When in track, ±10 V range 16.5 pF When in track, ±5 V and 0 V to +10 V ranges 21.5 pF When in track, ±2.5 V range 3 pF When in hold, all ranges REFERENCE INPUT/OUTPUT Input Voltage Range 2.5 3 V Input DC Leakage Current ±1 µA Input Capacitance 10 pF Reference Output Voltage 2.5 V Reference Output Voltage ±5 mV Error at 25°C Reference Output Voltage ±10 mV T to T MIN MAX Reference Temperature 3 25 ppm/°C Coefficient Reference Output 7 Ω Impedance LOGIC INPUTS Input High Voltage, V 2.4 V INH Input Low Voltage, V 0.8 V V = 4.75 V to 5.25 V INL CC 0.4 V V = 2.7 V to 3.6 V CC Input Current, I ±1 µA V = 0 V or V IN IN DRIVE Input Capacitance, C 3 10 pF IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V V I = 200 µA OH DRIVE SOURCE Output Low Voltage, V 0.4 V I = 200 µA OL SINK Floating-State Leakage ±1 µA Current Floating-State Output 5 pF Capacitance3 Output Coding Straight natural binary Coding bit set to 1 in control register Twos complement Coding bit set to 0 in control register CONVERSION RATE Conversion Time 1.6 µs 16 SCLK cycles with SCLK = 10 MHz Track-and-Hold Acquisition 305 ns Full-scale step input; see the Terminology section Time2, 3 Throughput Rate 500 kSPS See the Serial Interface section POWER REQUIREMENTS Digital inputs = 0 V or V DRIVE VDD 12 16.5 V See Table 6 VSS −12 −16.5 V See Table 6 VCC 2.7 5.25 V See Table 6 V 2.7 5.25 V DRIVE Normal Mode (Static) 0.9 mA V /V = ±16.5 V, V /V = 5.25 V DD SS CC DRIVE Normal Mode (Operational) f = 500 kSPS S I 180 µA V = 16.5 V DD DD I 205 µA V = −16.5 V SS SS I and I 2.2 mA V /V = 5.25 V CC DRIVE CC DRIVE Autostandby Mode f = 250 kSPS S (Dynamic) I 100 µA V = 16.5 V DD DD I 110 µA V = −16.5 V SS SS I and I 0.75 mA V /V = 5.25 V CC DRIVE CC DRIVE Rev. B | Page 5 of 36

AD7323 Data Sheet B Version Parameter1 Min Typ Max Unit Test Conditions/Comments Autoshutdown Mode (Static) SCLK on or off I 1 µA V = 16.5 V DD DD I 1 µA V = −16.5 V SS SS I and I 1 µA V /V = 5.25 V CC DRIVE CC DRIVE Full Shutdown Mode SCLK on or off I 1 µA V = 16.5 V DD DD I 1 µA V = −16.5 V SS SS I and I 1 µA V /V = 5.25 V CC DRIVE CC DRIVE POWER DISSIPATION Normal Mode (Operational) 18 mW V = 16.5 V, V = −16.5 V, V = 5.25 V DD SS CC Full Shutdown Mode 38.25 µW V = 16.5 V, V = −16.5 V, V = 5.25 V DD SS CC 1 Temperature range is −40°C to +85°C. 2 See the Terminology section. 3 Sample tested during initial release to ensure compliance. 4 Unipolar 0 V to 10 V range with straight binary output coding. 5 Bipolar range with twos complement output coding. Rev. B | Page 6 of 36

Data Sheet AD7323 TIMING SPECIFICATIONS V = 12 V to 16.5 V, V = −12 V to −16.5 V, V = 2.7 V to 5.25 V, V = 2.7 V to 5.25 V, V ≤ V , V = 2.5 V to 3.0 V DD SS CC DRIVE DRIVE CC REF internal/external, T = T to T . Timing specifications apply with a 32 pF load, unless otherwise noted.1 A MAX MIN Table 3. Limit at T , T MIN MAX Parameter V < 4.75 V V = 4.75 V to 5.25 V Unit Description CC CC f 50 50 kHz min SCLK 10 10 MHz max t 16 × t 16 × t ns max t = 1/f CONVERT SCLK SCLK SCLK SCLK t 75 60 ns min Minimum time between end of serial read and next falling edge of CS QUIET t 12 5 ns min Minimum CS pulse width 1 t 2 25 20 ns min CS to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V) 2 45 35 ns min Unipolar input range (0 V to 10 V) t 26 14 ns max Delay from CS until DOUT three-state disabled 3 t 57 43 ns max Data access time after SCLK falling edge 4 t 0.4 × t 0.4 × t ns min SCLK low pulse width 5 SCLK SCLK t 0.4 × t 0.4 × t ns min SCLK high pulse width 6 SCLK SCLK t 13 8 ns min SCLK to data valid hold time 7 t 40 22 ns max SCLK falling edge to DOUT high impedance 8 10 9 ns min SCLK falling edge to DOUT high impedance t 4 4 ns min DIN set-up time prior to SCLK falling edge 9 t 2 2 ns min DIN hold time after SCLK falling edge 10 t 750 750 ns max Power-up from autostandby POWER-UP 500 500 µs max Power-up from full shutdown/autoshutdown mode, internal reference 25 25 µs typ Power-up from full shutdown/autoshutdown mode, external reference 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2 When using the 0 V to 10 V unipolar range, running at 500 kSPS throughput rate with t2 at 20 ns, the mark space ratio must be limited to 50:50. t1 CS tCONVERT t2 t6 SCLK 1 2 3 4 5 13 14 15 16 2t 3IDENTIFICATIONBITS t4 t7 t5 t8 tQUIET DOUT ADD1 ADD0 SIGN DB11 DB10 DB2 DB1 DB0 TSHTRAETEE- ZERO t9 t10 THREE-STATE DIN WRITE SREELG1 SREELG2 MSB LSB DCOANR’ET 05400-002 Figure 2. Serial Interface Timing Diagram Rev. B | Page 7 of 36

AD7323 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted A Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to AGND, DGND −0.3 V to +16.5 V rating only; functional operation of the device at these or any DD V to AGND, DGND +0.3 V to −16.5 V other conditions above those indicated in the operational SS V to V V − 0.3 V to 16.5 V section of this specification is not implied. Exposure to absolute DD CC CC V to AGND, DGND −0.3 V to +7 V maximum rating conditions for extended periods may affect CC V to AGND, DGND −0.3 V to +7 V device reliability. DRIVE AGND to DGND −0.3 V to +0.3 V ESD CAUTION Analog Input Voltage to AGND1 V − 0.3 V to V + 0.3 V SS DD Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to V + 0.3 V DRIVE REFIN/OUT to AGND −0.3 V to V + 0.3 V CC Input Current to Any Pin ±10 mA Except Supplies2 Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package θJA Thermal Impedance 150°C/W θ Thermal Impedance 27.6°C/W JC Pb-Free Temperature, Soldering Reflow 260(0)°C ESD 2.5 kV 1 If the analog inputs are driven from alternative VDD and VSS supply circuitry, Schottky diodes should be placed in series with the AD7323’s VDD and VSS supplies. See the Power Supply Configuration section. 2 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. B | Page 8 of 36

Data Sheet AD7323 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CS 1 16 SCLK DIN 2 15 DGND DGND 3 AD7323 14 DOUT AGND 4 TOPVIEW 13 VDRIVE (NottoScale) REFIN/OUT 5 12 VCC VSS 6 11 VDD VIN0 7 10 VIN2 VIN1 8 9 VIN3 05400-003 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7323 and frames the serial data transfer. 2 DIN Data Input. Data to be written to the on-chip registers is provided on this input and is clocked into the register on the falling edge of SCLK (see the Registers section). 3, 15 DGND Digital Ground. Ground reference point for all digital circuitry on the AD7323. The DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 4 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7323. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 5 REFIN/OUT Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the AD7323. The nominal internal reference voltage is 2.5 V, which appears at this pin. A 680 nF capacitor should be placed on the reference pin (see the Reference section). Alternatively, the internal reference can be disabled and an external reference applied to this input. On power-up, the external reference mode is the default condition. 6 V Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. SS 7, 8, 9, 10 V 0 to V 3 Analog Input 0 to Analog Input 3. The analog inputs are multiplexed into the on-chip track-and-hold. IN IN The analog input channel for conversion is selected by programming the ADD1 and ADD0 channel address bits in the control register. The inputs can be configured as four single-ended inputs, two true differential input pairs, two pseudo differential inputs, or three pseudo differential inputs (see Table 10). The configuration of the analog inputs is selected by programming the mode bits, Mode 1 and Mode 0, in the control register. The input range on each input channel is controlled by programming the range register. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected on each analog input channel when a 2.5 V reference voltage is used (see the Registers section). 11 V Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. DD 12 V Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7323. CC This supply should be decoupled to AGND. 13 V Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface DRIVE operates. This pin should be decoupled to DGND. The voltage at this pin may be different from that at V , but it should not exceed V by more than 0.3 V. CC CC 14 DOUT Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The data stream consists of a leading zero, two channel identification bits, the sign bit, and 12 bits of conversion data. The data is provided MSB first (see the Serial Interface section). 16 SCLK Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the AD7323. This clock is also used as the clock source for the conversion process. Rev. B | Page 9 of 36

AD7323 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 1.0 4096 POINT FFT VCC=VDRIVE=5V INT/EXT2.5VREFERENCE VCC = VDRIVE = 5V 0.8 TA=25°C ±10VRANGE –20 VDD, VSS = ±15V VDD,VSS=±15V +INL=+0.55LSB TA = 25°C 0.6 –INL=–0.68LSB INT/EXT 2.5V REFERENCE –40 ±10V RANGE 0.4 fIN = 50kHz B) dB) –60 SSNINRA =D 7=7 7.360.8d5BdB R (LS 0.2 NR ( TSHFDDR = =– 8–68.89.62d2BdB RRO 0 S –80 L E–0.2 N I –100 –0.4 –0.6 –120 –0.8 –140 –1.0 0 50 FR10E0QUENCY (1k5H0z) 200 250 05400-004 0 51210241536204825603072358C44O09D64E6085120563261446656716876808192 05400-007 Figure 4. FFT True Differential Mode Figure 7. Typical INL True Differential Mode 1.0 0 4096 POINT FFT 0.8 VCC = VDRIVE = 5V –20 VDD, VSS = ±15V 0.6 TA = 25°C INT/EXT 2.5V REFERENCE 0.4 –40 ±10V RANGE B) fIN = 50kHz LS 0.2 dB) –60 SSNINRA =D 7=4 7.647.0d3BdB ROR ( 0 SNR ( –80 TSHFDDR = =– 8–28.56.84d0BdB NL ER–0.2 D –0.4 –100 –0.6 VCC=VDRIVE=5V ±10VRANGE TA=25°C +DNL=+0.79LSB –120 –0.8 VDD,VSS=±15V –DNL=–0.38LSB INT/EXT2.5VREFERENCE –1.0 –1400 50 FR10E0QUENCY (1k5H0z) 200 250 05400-005 0 51210241536204825603072358C44O09D64E6085120563261446656716876808192 05400-043 Figure 5. FFT Single-Ended Mode Figure 8. Typical DNL Single-Ended Mode 1.0 1.0 0.8 0.8 0.6 0.6 0.4 SB) 0.4 LSB) 0.2 ROR (L 0.20 RROR ( 0 L ER–0.2 NL E–0.2 DN––00..46 IVTVNACDTCD=/,E=2VX5VST°SDC2R=.I5V±VE15R=VE5FVERENCE I––00..46 TVIVNACDTCD=/,E=2VX5VST°SDC2R=.I5V±VE15R=VE5FVERENCE –0.8 ±+1D0NVLR=A+N0G.7E2LSB –0.8 ±+1IN0LV=RA+0N.G87ELSB –DNL=–0.22LSB –1.0 –INL=–0.49LSB –1.00 51210241536204825603072358C44O09D64E6085120563261446656716876808192 05400-006 0 51210241536204825603072358C44O09D64E6085120563261446656716876808192 05400-044 Figure 6. Typical DNL True Differential Mode Figure 9. Typical INL Single-Ended Mode Rev. B | Page 10 of 36

Data Sheet AD7323 –50 80 VCC=VDRIVE=3V ±5VDIFF –55 VDD/VSS=±12V ±2.5VDIFF TA=25°C 75 –60 fS=500kSPS ±5VSE INTERNALREFERENCE 0VTO+10VSE –65 ±2.5VSE ±10VSE 70 ±10VDIFF THD (dB) –––778050 0VT±O10+V1D0VIFDFIFF SINAD (dB) 65 ±10VSE 0VTO+100VVTSOE+10VDIFF ±5VSE ±5VDIFF 60 –85 ±2.5VDIFF VCC=VDRIVE=5V –90 55 VDD/VSS=±12V ±2.5VSE TA=25°C –95 fS=500kSPS INTERNALREFERENCE –100 50 10 ANALOG INPUT1F0R0EQUENCY(kHz) 1000 05400-060 10 ANALOG INPUT1F0R0EQUENCY(kHz) 1000 05400-063 Figure 10. THD vs. Analog Input Frequency for Single-Ended (SE) and True Figure 13. SINAD vs. Analog Input Frequency for Single-Ended (SE) and True Differential Mode (Diff) at 3 V VCC Differential Mode (Diff) at 5 V VCC –50 –50 VCC=VDRIVE=5V ––5650 VTfSAD=D=/5V20S50S°kC=SP±S12V 0VTO+10VSE ON (dB) ––5650 VCC=3V –65 INTERNALREFERENCE ±10VSE OLATI –65 VCC=5V S D (dB) ––7705 ±10VDIFF NNEL I –70 TH –80 0VTO+10VDIFF CHA –75 ±5VSE TO- –80 –85 ±5VDIFF NEL- –85 VSDINDG/VLSES-E=N±D1E2VDMODE –90 N –95 ±2.5VSE CHA –90 5TfS0Ak==H5z20 5O0°kCNSPSSELECTEDCHANNEL ±2.5VDIFF –10010 ANALOG INPUT1F0R0EQUENCY(kHz) 1000 05400-061 –950 100 FREQU20E0NCY OF3 I0N0PUTNO4IS00E(kHz)500 600 05400-012 Figure 11. THD vs. Analog Input Frequency for Single-Ended (SE) and True Figure 14. Channel-to-Channel Isolation Differential Mode (Diff) at 5 V VCC 80 10k 9469 ±5VDIFF VCC=5V ±2.5VDIFF 9k VDD/VSS=±12V 75 ±±52V.5SVESE CES 8k R1T0AAkN=SG2A5EM°C=P±L1E0SV 0V TO+10VDIFF N 7k 70 E ±10VDIFF R B) UR 6k NAD (d 65 ±10VSE F OCC 5k SI 0VTO+10VSE R O 4k 60 MBE 3k VCC=VDRIVE=3V NU 55 VTADD=/V2S5S°C=±12V 2k IfNST=E5R0N0kASLPRSEFERENCE 1k 0 228 303 0 5010 ANALOG INPUT1F0R0EQUENCY(kHz) 1000 05400-062 0 –2 –1 CO0DE 1 2 05400-013 Figure 12.SINAD vs. Analog Input Frequency for Single-Ended (SE) and True Figure 15. Histogram of Codes, True Differential Mode Differential Mode (Diff) at 3 V VCC Rev. B | Page 11 of 36

AD7323 Data Sheet 8k 7600 2.0 VCC = 5V 7k VRDADN/GVSES = = ± ±1102VV 1.5 10k SAMPLES S CE 6k TA = 25°C 1.0 N RRE 5k SB) 0.5 F OCCU 4k RROR (L 0 INL=500kSPS O E R 3k L –0.5 E N B I M U 2k –1.0 N 1201 1165 ±5VRANGE 1k –1.5 VCC=VDRIVE=5V INTERNALREFERENCE 0 23 11 0 SINGLE-ENDEDMODE 0 –2.0 –3 –2 –1 CO0DE 1 2 3 05400-014 5 7 ±V9DD/VSSS1U1PPLYV1O3LTAGE1(5V) 17 19 05400-050 Figure 16. Histogram of Codes, Single-Ended Mode Figure 19. INL Error vs. Supply Voltage at 500 kSPS –50 –50 –55 –55 1N0O0mDEVCpO-pUSPILNINEGWAVE ONEACHSUPPLY SINGLE-ENDEDMODE –60 –60 fS=500kSPS –65 –65 VCC=5V CMRR (dB) –––778050 VCC =V C5VC = 3V PSRR (dB) –––778050 VVCDCD==31V2V –85 DIFFERENTIAL MODE –85 fIN = 50kHz VSS=–12V –90 VDD/VSS = ±12V –90 fS = 500kSPS –95 TA = 25°C –95 –100 –100 0 200 R4IP0P0LE FRE6Q00UENCY (8k0H0z) 1000 1200 05400-055 0 200 SUPP4L0Y0RIPPLE6F0R0EQUEN8C0Y0(kHz)1000 1200 05400-054 Figure 17. CMRR vs. Common-Mode Ripple Frequency Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling 2.0 –50 VCC=VDRIVE=5V 1.5 –55 VDD/VSS=±12V TA=25°C ±10VRANGE R (LSB) 10..05 DNL=500kSPS B) –––667050 DIRfNSIAFT=NFE5GER0REN0EkA=SNL±PT1RSI0AEVLFAMNODD±E2.5V RRRRRRIIIIIINNNNNN======43211100000200000Ω0000ΩΩΩΩΩ DNL ERRO –0.50 THD (d ––7850 R±R2IINN.5==V95R05A00N00ΩΩGE –85 RIN=2000Ω –1.0 RIN=100Ω ±5VRANGE –90 RIN=12Ω –1.5 VCC=VDRIVE=5V INTERNALREFERENCE –95 SINGLE-ENDEDMODE –2.0 –100 5 7 ±V9DD/VSSS1U1PPLYV1O3LTAGE1(5V) 17 19 05400-049 10 INPUTFREQ10U0ENCY(kHz) 1000 05400-064 Figure 18. DNL Error vs. Supply Voltage at 500 kSPS Figure 21. THD vs. Analog Input Frequency for Various Source Impedances, True Differential Mode Rev. B | Page 12 of 36

Data Sheet AD7323 –50 VCC=VDRIVE=+5V –55 VDD/VSS=±12V TA=25°C ±10VRANGE ––6605 IRfNSAT=NE5GR0EN0kA=SL±P1RS0EVFAND±2.5V RRRIIINNN===421000000000ΩΩΩ SINGLE-ENDEDMODE RIN=100Ω –70 RIN=50Ω B) d D ( –75 ±2.5VRANGE TH –80 RRIINN==43700000ΩΩ RIN=1000Ω –85 RIN=100Ω RIN=50Ω –90 –95 –100 10 INPUTFREQ10U0ENCY(kHz) 1000 05400-065 Figure 22. THD vs. Analog Input Frequency for Various Source Impedances, Single-Ended Mode Rev. B | Page 13 of 36

AD7323 Data Sheet TERMINOLOGY Differential Nonlinearity Negative Full-Scale Error This is the difference between the measured and the ideal 1 LSB This applies when using twos complement output coding and change between any two adjacent codes in the ADC. any of the bipolar analog input ranges. This is the deviation of the first code transition (10…000) to (10…001) from the ideal Integral Nonlinearity (that is, −4 × V + 1 LSB, −2 × V + 1 LSB, −V + 1 LSB) REF REF REF This is the maximum deviation from a straight line passing after adjusting for the bipolar zero code error. through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (a point 1 LSB Negative Full-Scale Error Match below the first code transition) and full scale (a point 1 LSB This is the difference in negative full-scale error between any above the last code transition). two input channels. Offset Code Error Track-and-Hold Acquisition Time This applies to straight binary output coding. It is the deviation The track-and-hold amplifier returns into track mode after the of the first code transition (00…000) to (00…001) from the 14th SCLK rising edge. Track-and-hold acquisition time is the ideal, that is, AGND + 1 LSB. time required for the output of the track-and-hold amplifier to reach its final value, within ±½ LSB, after the end of a conversion. Offset Error Match For the ±2.5 V range, the specified acquisition time is the time This is the difference in offset error between any two input required for the track-and-hold amplifier to settle to within ±1 LSB. channels. Signal-to-(Noise + Distortion) Ratio Gain Error This is the measured ratio of signal-to-(noise + distortion) at This applies to straight binary output coding. It is the deviation the output of the ADC. The signal is the rms amplitude of the of the last code transition (111…110) to (111…111) from the fundamental. Noise is the sum of all nonfundamental signals up ideal (that is, 4 × V − 1 LSB, 2 × V − 1 LSB, V −1 LSB) REF REF REF to half the sampling frequency (f/2), excluding dc. The ratio is S after adjusting for the offset error. dependent on the number of quantization levels in the digitization process. The more levels there are, the smaller the quantization Gain Error Match noise becomes. Theoretically, the signal-to-(noise + distortion) This is the difference in gain error between any two input ratio for an ideal N-bit converter with a sine wave input is given by channels. Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Bipolar Zero Code Error For a 13-bit converter, this is 80.02 dB. This applies when using twos complement output coding and a bipolar analog input. It is the deviation of the midscale transi- Total Harmonic Distortion tion (all 1s to all 0s) from the ideal input voltage, that is, AGND Total harmonic distortion (THD) is the ratio of the rms sum of − 1 LSB. harmonics to the fundamental. For the AD7323, it is defined as Bipolar Zero Code Error Match V 2 +V 2 +V 2 +V 2 +V 2 This refers to the difference in bipolar zero code error between THD(dB)=20log 2 3 4 5 6 V any two input channels. 1 where V is the rms amplitude of the fundamental, and V, V, 1 2 3 Positive Full-Scale Error V, V, and V are the rms amplitudes of the second through the 4 5 6 This applies when using twos complement output coding and sixth harmonics. any of the bipolar analog input ranges. It is the deviation of the last code transition (011…110) to (011…111) from the ideal Peak Harmonic or Spurious Noise (4 × V − 1 LSB, 2 × V − 1 LSB, V − 1 LSB) after adjusting Peak harmonic or spurious noise is defined as the ratio of the REF REF REF for the bipolar zero code error. rms value of the next largest component in the ADC output spectrum (up to f/2, excluding dc) to the rms value of the S Positive Full-Scale Error Match fundamental. Normally, the value of this specification is This is the difference in positive full-scale error between any determined by the largest harmonic in the spectrum, but for two input channels. ADCs where the harmonics are buried in the noise floor, the largest harmonic can be a noise peak. Rev. B | Page 14 of 36

Data Sheet AD7323 terms are usually at a frequency close to the input frequencies. Channel-to-Channel Isolation As a result, the second- and third-order terms are specified Channel-to-channel isolation is a measure of the level of separately. The calculation of the intermodulation distortion is crosstalk between any two channels. It is measured by applying a per the THD specification, where it is the ratio of the rms sum full-scale, 100 kHz sine wave signal to all unselected input channels of the individual distortion products to the rms amplitude of and determining the degree to which the signal attenuates in the the sum of the fundamentals, expressed in decibels. selected channel with a 50 kHz signal. Figure 14 shows the worst- case across all eight channels for the AD7323. The analog input PSR (Power Supply Rejection) range is programmed to be the same on all channels. Variations in power supply affect the full-scale transition but not the linearity of the converter. Power supply rejection is the Intermodulation Distortion maximum change in the full-scale transition point due to a With inputs consisting of sine waves at two frequencies, fa and change in power supply voltage from the nominal value (see the fb, any active device with nonlinearities creates distortion Typical Performance Characteristics section). products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms CMRR (Common-Mode Rejection Ratio) are those for which neither m nor n are equal to 0. For example, CMRR is defined as the ratio of the power in the ADC output at the second-order terms include (fa + fb) and (fa − fb), whereas full-scale frequency, f, to the power of a 100 mV sine wave the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), applied to the common-mode voltage of the V + and V − IN IN and (fa − 2fb). frequency, f, as S The AD7323 is tested using the CCIF standard where two input CMRR (dB) = 10 log (Pf/Pf) S frequencies near the top end of the input bandwidth are used. where Pf is the power at frequency f in the ADC output, and Pf In this case, the second-order terms are usually distanced in S is the power at frequency f in the ADC output (see Figure 17). frequency from the original sine waves, whereas the third-order S Rev. B | Page 15 of 36

AD7323 Data Sheet THEORY OF OPERATION CIRCUIT INFORMATION The analog inputs can be configured as four single-ended inputs, two true differential inputs, two pseudo differential The AD7323 is a fast, 4-channel, 12-bit plus sign, bipolar input, inputs, or three pseudo differential inputs. Selection can be serial ADC. The AD7323 can accept bipolar input ranges that made by programming the mode bits, Mode 0 and Mode 1, include ±10 V, ±5 V, and ±2.5 V; it can also accept a 0 V to in the control register. +10 V unipolar input range. A different analog input range can be programmed on each analog input channel via the on-chip The serial clock input accesses data from the part and provides registers. The AD7323 has a high speed serial interface that can the clock source for the successive approximation ADC. The operate at throughput rates up to 500 kSPS. AD7323 has an on-chip 2.5 V reference. However, the AD7323 can also work with an external reference. On power-up, the The AD7323 requires V and V dualsupplies for the high voltage DD SS external reference operation is the default option. If the internal analog input structures. These supplies must be equal to or greater reference is the preferred option, the user must write to the than the largest analog input range selected. See Table 6 for the reference bit in the control register to select the internal refer- requirements of these supplies for each analog input range. The ence operation. AD7323 requires a low voltage 2.7 V to 5.25 V V supply to CC power the ADC core. The AD7323 also features power-down options to allow power savings between conversions. The power-down modes are Table 6. Reference and Supply Requirements for Each selected by programming the on-chip control register, as Analog Input Range described in the Modes of Operation section. Selected Full-Scale Analog Input Reference Input Minimum CONVERTER OPERATION Range (V) Voltage (V) Range (V) V (V) V /V (V)1 CC DD SS The AD7323 is a successive approximation ADC built around ±10 2.5 ±10 3/5 ±10 two capacitive DACs. Figure 23 and Figure 24 show simplified 3.0 ±12 3/5 ±12 schematics of the ADC in single-ended mode during the acquisi- ±5 2.5 ±5 3/5 ±5 tion and conversion phases, respectively. Figure 25 and Figure 26 3.0 ±6 3/5 ±6 show simplified schematics of the ADC in differential mode ±2.5 2.5 ±2.5 3/5 ±5 3.0 ±3 3/5 ±5 during acquisition and conversion phases, respectively. The 0 to +10 2.5 0 to +10 3/5 +10/AGND ADC is composed of control logic, a SAR, and capacitive DACs. 3.0 0 to +12 3/5 +12/AGND In Figure 23 (the acquisition phase), SW2 is closed and SW1 is 1 Guaranteed performance for VDD = 12 V to 16.5 V and VSS = −12 V to −16.5 V. in Position A, the comparator is held in a balanced condition, and the sampling capacitor array acquires the signal on the input. The performance specifications are guaranteed for V = 12 V DD to 16.5 V and V = −12 V to −16.5 V. With V and V supplies SS DD SS CAPACITIVE outside this range, the AD7323 is fully functional but performance DAC is not guaranteed. It may be necessary to decrease the throughput B CS COMPARATOR FVraiSgtSe us wureph p3el1nie ssth h(osewe Aes t Dthh7ee 3T c2yh3pa iincs agcleo P nienfri gfTouHrrmeDda nwasci etth hC ethh Vaer DmaDc itanenirmids tuVicmSsS sVseucDptDip oalnnie)ds. VINx AGNADSW1 SW2 COLNOTGRICOL 05400-017 are reduced. For ac performance at the maximum throughput Figure 23. ADC Acquisition Phase (Single-Ended) rate, the THD degrades slightly as V and V are reduced. It may DD SS therefore be necessary to reduce the throughput rate when using When the ADC starts a conversion (see Figure 24), SW2 opens minimum V and V supplies so that there is less degradation and SW1 moves to Position B, causing the comparator to become DD SS of THD and the specified performance can be maintained. The unbalanced. The control logic and the charge redistribution degradation is due to an increase in the on resistance of the DAC are used to add and subtract fixed amounts of charge from input multiplexer when the V and V supplies are reduced. the capacitive DAC to bring the comparator back into a balanced DD SS Figure 18 and Figure 19 show the change in INL and DNL as condition. When the comparator is rebalanced, the conversion the V and V voltages are varied. For dc performance when is complete. The control logic generates the ADC output code. DD SS operating at the maximum throughput rate, as the V and V DD SS supply voltages are reduced, the typical INL and DNL error CAPACITIVE DAC remains constant. B CS COMPARATOR VINx ASW1 SW2 CONTROL AGND LOGIC 05400-018 Figure 24. ADC Conversion Phase (Single-Ended) Rev. B | Page 16 of 36

Data Sheet AD7323 Figure 25 shows the differential configuration during the The ideal transfer characteristic for the AD7323 when twos acquisition phase. For the conversion phase, SW3 opens and complement coding is selected is shown in Figure 27. The ideal SW1 and SW2 move to Position B (see Figure 26). The output transfer characteristic for the AD7323 when straight binary impedances of the source driving the V + and V − inputs IN IN coding is selected is shown in Figure 28. must match; otherwise, the two inputs have different settling times, resulting in errors. 011...111 011...110 CAPACITIVE DAC E D COMPARATOR O000...001 VIN+ BASW1CS SW3 CONTROL ADC C010101......010101 ASW2 LOGIC VIN– B CS 100...010 100...001 VREF CAPACITIVE 100...000 N1.O VTINE+S CAN BE VIN0 OR VIN2, AND VIN– CAN BE VIND1A OCR VIN3.05400-019 –AFGSRN/D2++11LLSSBB AGNDA–N1ALLSOBG I++NFFPSSURRT/2––1L1SLBSB BUINPIOPOLALRARRARNAGNGESE 05400-021 Figure 25. ADC Differential Configuration During Acquisition Phase Figure 27. Twos Complement Transfer Characteristic CAPACITIVE DAC 111...111 111...110 COMPARATOR B CS VVIINN+– BAASSWW12CS SW3 COLNOTGRICOL ADC CODE101111......010101 VREF CAPACITIVE DAC 000...010 FiguN1r.eO V 2TINE6+.S ACDANC BDEif fVeIrNe0n OtiRa lV CINo2n, AfigNuDr VaItNi–o nC ADNu BriEn gV ICNo1 nOvRe rVsIiNo3n. P05400-020h ase 000000......000010 –AFGSRN/D2++11LLSSBBANALOG I++NFFPSSURRT/–21–L1SLBSB BUINPIOPOLALRARRARNAGNGESE 05400-022 Output Coding Figure 28. Straight Binary Transfer Characteristic The AD7323 default output coding is set to twos complement. ANALOG INPUT STRUCTURE The output coding is controlled by the coding bit in the control The analog inputs of the AD7323 can be configured as single- register. To change the output coding to straight binary coding, ended, true differential, or pseudo differential via the control the coding bit in the control register must be set. When operat- register mode bits (see Table 9). The AD7323 can accept true ing in sequence mode, the output coding for each channel in bipolar input signals. On power-up, the analog inputs operate as the sequence is the value written to the coding bit during the four single-ended analog input channels. If true differential or last write to the control register. pseudo differential is required, a write to the control register is Transfer Functions necessary after power-up to change this configuration. The designed code transitions occur at successive integer Figure 29 shows the equivalent analog input circuit of the LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is AD7323 in single-ended mode. Figure 30 shows the equivalent dependent on the analog input range selected. analog input structure in differential mode. The two diodes provide ESD protection for the analog inputs. Table 7. LSB Sizes for Each Analog Input Range Input Range Full-Scale Range/8192 Codes LSB Size VDD ±10 V 20 V 2.441 mV D R1 C2 ±5 V 10 V 1.22 mV VINx ±2.5 V 5 V 0.61 mV C1 D 0 V to +10 V 10 V 1.22 mV VSS 05400-023 Figure 29. Equivalent Analog Input Circuit (Single-Ended) Rev. B | Page 17 of 36

AD7323 Data Sheet VDD The AD7323 enters track mode on the 14th SCLK rising edge. D R1 C2 When running the AD7323 at a throughput rate of 1 MSPS with VIN+ a 10 MHz SCLK signal, the ADC has approximately C1 D 1.5 SCLK + t + t 8 QUIET VSS to acquire the analog input signal. The ADC goes back into VDD hold mode on the CS falling edge. D R1 C2 As the V /V supply voltage is reduced, the on resistance VIN– DD SS C1 D of the input multiplexer increases. Therefore, based on the equation for t , it is necessary to increase the amount of ACQ N1.O VTINE+S CAN BE VIN0 OR VVINSS2, AND VIN– CAN BE VIN1 OR VIN3. 05400-024 athcqe uoivsietrioanll ttihmroe upgrhovpiudte rda ttoe .t Fhieg AurDe 73312 s3h, oanwds tthhearte afos rteh de eVcrDeDa asne d Figure 30. Equivalent Analog Input Circuit (Differential) V supplies are reduced, the specified THD performance SS degrades slightly. If the throughput rate is reduced when operating Care should be taken to ensure that the analog input does not with the minimum V and V supplies, the specified THD DD SS exceed the V and V supply rails by more than 300 mV. Exceed- DD SS performance is maintained. ing this value causes the diodes to become forward biased and to start conducting into either the VDD supply rail or VSS supply –75 VCC = VDRIVE = 5V rail. These diodes can conduct up to 10 mA without causing INTERNAL REFERENCE TA = 25°C irreversible damage to the part. fIN = 10kHz –80 ±5V RANGE SE MODE In Figure 29 and Figure 30, Capacitor C1 is typically 4 pF and can primarily be attributed to pin capacitance. Resistor R1 is a B) d lumped component made up of the on resistance of the input D ( –85 H multiplexer and the track-and-hold switch. Capacitor C2 is the T sampling capacitor; its capacitance varies depending on the analog input range selected (see the Specifications section). –90 500kSPS Track-and-Hold Section The track-and-hold on the analog input of the AD7323 allows –95 athmep AliDtuCd et oto a 1cc3u-braitt ealcyc cuornacvye.r Tt ahne iinnppuutt sbianned wwaivdet ho fo ffu tlhl-es tcraalcek - 5 7 9±VDD/V1S1S SUPP1L3IES (V)15 17 19 05400-051 and-hold is greater than the Nyquist rate of the ADC. The Figure 31. THD vs. ±VDD/VSS Supply Voltage at 500 kSPS AD7323 can handle frequencies up to 22 MHz. Unlike other bipolar ADCs, the AD7323 does not have a resistive analog input structure. On the AD7323, the bipolar The track-and-hold enters its tracking mode on the 14th SCLK analog signal is sampled directly onto the sampling capacitor. rising edge after the CS falling edge. The time required to This gives the AD7323 high analog input impedance. An acquire an input signal depends on how quickly the sampling approximation for the analog input impedance can be capacitor is charged. With zero source impedance, 305 ns is calculated from the following formula: sufficient to acquire the signal to the 13-bit level. The acquisition time required is calculated using the following Z = 1/(fS × CS) formula: where f is the sampling frequency and C is the sampling S S tACQ = 10 × ((RSOURCE + R) C) capacitor value. where C is the sampling capacitance and R is the resistance seen C depends on the analog input range chosen (see the S by the track-and-hold amplifier looking back on the input. For Specifications section). When operating at 500 kSPS, the the AD7323, the value of R includes the on resistance of the analog input impedance is typically 145 kΩ for the ±10 V input multiplexer and is typically 300 Ω. RSOURCE should include range. As the sampling frequency is reduced, the analog input any extra source impedance on the analog input. impedance further increases. As the analog input impedance increases, the current required to drive the analog input therefore decreases. Rev. B | Page 18 of 36

Data Sheet AD7323 V+ 5V TYPICAL CONNECTION DIAGRAM Figure 32 shows a typical connection diagram for the AD7323. AGND In this configuration, the AGND pin is connected to the analog VINx VDD VCC ground plane of the system, and the DGND pin is connected to AD73231 the digital ground plane of the system. The analog inputs on the VSS AD7323 can be configured to operate in single-ended, true differential, or pseudo differential mode. The AD7323 can operate with either an internal or external reference. In Figure 32, the AA D68703 2n3F i sd ceocnoufipgulirnegd c taop oapceitroart ei sw riethq uthiree din wtehrneanl o2p.5e Vra trienfegr wenitche . 1ADDIVT–IONAL PINS OMITTED FOR CLARITY. 05400-026 the internal reference. Figure 33. Single-Ended Mode Typical Connection Diagram True Differential Mode The V pin can be connected to either a 3 V supply voltage or a CC 5 V supply voltage. VDD and VSS are the dual supplies for the The AD7323 can have a total of two true differential analog high voltage analog input structures. The voltage on these pins input pairs. Differential signals have some benefits over single- must be equal to or greater than the highest analog input range ended signals, including better noise immunity based on the selected on the analog input channels (see Table 6). The VDRIVE device’s common-mode rejection and improvements in distor- pin is connected to the supply voltage of the microprocessor. tion performance. Figure 34 defines the configuration of the The voltage applied to the VDRIVE input controls the voltage of true differential analog inputs of the AD7323. the serial interface. V can be set to 3 V or 5 V. DRIVE +15V VCC+2.7VTO5.25V VIN+ + + 0.1µF 10µF 10µF 0.1µF AD73231 VDD1 VCC +3VSUPPLY VIN– AD7323 VDRIVE 10µF + 0.1µF 1N1A.O VDTIDNEI+ST CIOANNA BLE P VININS0 O OMRI TVTINE2D, AFONDR VCILNA– RCIATYN. BE VIN1 OR VIN3. 05400-027 CS A±1N0AVL,O±5GV ,IN±P2.U5TVS VVIINN01 DSOCLUKT µC/µP Figure 34. True Differential Inputs 0VTO+10V VVIINN23 DIN The amplitude of the differential signal is the difference between the signals applied to the V + and V − inputs in IN IN DGND REFIN/OUT INTSEERRFIAALCE each differential pair (VIN+ − VIN−). VIN+ and VIN− should 680nF VSS1 AGND be simultaneously driven by two signals, each of amplitude ±4 × V (depending on the input range selected) that are 180° REF –15V out of phase. Assuming the ±4 × V mode, the amplitude of 0.1µF +10µF 1MDRAEINPNIEMGNUEDMS OEVLNDEDTCHATENEDHDI.VGSHSESSUTPAPNLYALVOOGLT IANGPUETS 05400-025 rthegea dridflfeesrse notfi athl esi cgonmalm iso −n2 m0 Vod teo. +R2E0F V p-p (2 × 4 × VREF), Figure 32. Typical Connection Diagram ANALOG INPUT The common mode is the average of the two signals Single-Ended Inputs (VIN+ + VIN−)/2 The AD7323 has a total of four analog inputs when operating and is therefore the voltage on which the two input signals are the AD7323 in single-ended mode. Each analog input can be centered. independently programmed to one of the four analog input ranges. In applications where the signal source is high This voltage is set up externally, and its range varies with impedance, it is recommended to buffer the signal before reference voltage. As the reference voltage increases, the applying it to the ADC analog inputs. Figure 33 shows the common-mode range decreases. When driving the differential configuration of the AD7323 in single-ended mode. inputs with an amplifier, the actual common-mode range is determined by the amplifier’s output swing. If the differential inputs are not driven from an amplifier, the common-mode range is determined by the supply voltage on the V supply pin DD and the V supply pin. SS Rev. B | Page 19 of 36

AD7323 Data Sheet When a conversion takes place, the common mode is rejected, 8 resulting in a noise-free signal of amplitude −2 × (4 × VREF) 6 ±10V ±2.5V ±5VRANGE RANGE RANGE to +2 × (4 × V ) corresponding to Digital Code −4096 to REF 4 Digital Code +4095. ±10V 5 E (V) 2 RANGE 4 ±5VRANGE ANG 0 3 ±2.5V ±5VRANGE ROM RANGE C –2 2 V E (V) 1 –4 ±5VRANGE V RANGCOM –––1230 R±A1N0GVE R±A1N0GVE R±A2N.5GVE ––68 VVCRCEF==52V.5V ±16.5VVDD/VSS ±12VVDD/VSS R±A2N.5GVE 05400-048 Figure 38. Common-Mode Range for VCC = 5 V and REFIN/OUT = 2.5 V –4 –5 VVCRCEF==33VV Pseudo Differential Inputs –6 ±16.5VVDD/VSS ±12VVDD/VSS 05400-045 pTsheeu AdoD d7i3f2fe3r ecnanti ahl aivnep utwtso r pefseeruednoc eddi ftfoe rae ncotimal mpaoinrs V oIrN −th irnepe ut. Figure 35. Common-Mode Range for VCC = 3 V and REFIN/OUT = 3 V The V + inputs are coupled to the signal source and must have IN 8 an amplitude within the selected range for that channel as programmed in the range register. A dc input is applied to the ±5VRANGE ±5VRANGE 6 VIN− input. The voltage applied to this input provides an offset ±2.5V ±2.5V for the VIN+ input from ground or a pseudo ground. Pseudo RANGE RANGE V) 4 ±10V differential inputs separate the analog input signal ground from GE ( RANGE the ADC ground, allowing cancellation of dc common-mode N A 2 voltages. R M ±10V O RANGE C V 0 When a conversion takes place, the pseudo ground corresponds to Code −4096 and the maximum amplitude corresponds to –2 Code +4095. VCC=5V VREF=3V V+ 5V –4 ±16.5VVDD/VSS ±12VVDD/VSS 05400-046 Figure 36. Common-Mode Range for VCC = 5 V and REFIN/OUT = 3 V VIN+ VDD VCC 6 AD73231 4 VIN– VSS ±5VRANGE ±5VRANGE 2 V) NGE ( 0 NOTES V– V RACOM –2 ±10V R±A2N.5GVE R±A1N0GVE ±2.5V 11A.VODIDRNI +TV ICIONA3NN.A BL EP IVNINS0 O, VMINIT1T, EODR FVOINR2 ,C ALNADR IVTIYN.– CAN BE VIN1 05400-028 –4 RANGE RANGE Figure 39. Pseudo Differential Inputs –6 Figure 40 and Figure 41 show the typical voltage range on the VCC=3V –8 VREF=2.5V ±16.5VVDD/VSS ±12VVDD/VSS 05400-047 VcoINn−fi ginupreudt fionr t thhee p dsiefufedroen dti affnearelongti ianl pmuot draen. g es when Figure 37. Common-Mode Range for VCC = 3 V and REFIN/OUT = 2.5 V For example, when the AD7323 is configured to operate in pseudo differential mode and the ±5 V range is selected with ±16.5 V V /V supplies and 5 V V , the voltage on the V − DD SS CC IN input can vary from −6.5 V to +6.5 V. Rev. B | Page 20 of 36

Data Sheet AD7323 8 The driver amplifier must be able to settle for a full-scale step ±5V RANGE ±5V RANGE GE (V) 6 ±10V R±A2N.5GVE R±A2N.5GVE ttoim ae 1 o3f- bthite l eAvDel7, 302.031. 2A2n% o, pin a lmesps sthuacnh tahs et hspe eAcDifi8e0d2 a1c mqueiestitsi othni s AN 4 RANGE requirement when operating in single-ended mode. The AD8021 R GE 2 needs an external compensating NPO type of capacitor. The TA AD8022 can also be used in high frequency applications where L O 0 V a dual version is required. For lower frequency applications, op T PU–2 amps such as the AD797, AD845, and AD8610 can be used with N ±10V O I RANGE the AD7323 in single-ended mode configuration. D–4 U E S Differential operation requires that V + and V − be simulta- P–6 0VTO +10V 0VTO +10V IN IN VCC = 5V RANGE RANGE neously driven with two signals of equal amplitude that are 180° –8 VREF = 2.5V ±16.5V VDD/VSS ±12V VDD/VSS 05400-039 oAuDt 7o3f 2p3h.a Tseh.e T choem cmomonm-omno mdeo rdaen mgeu isst dbeet esremt uinpe edx tbeyr nthaell yR tEoF tIhNe/ Figure 40. Pseudo Input Range with VCC = 5 V OUT voltage, the V supply voltage, and the particular amplifier CC 4 used to drive the analog inputs. Differential mode with either an ±5V RANGE ac input or a dc input provides the best THD performance over a E (V) 2 ±5V RANGE R±A2N.5GVE wide frequency range. Because not all applications have a signal NG preconditioned for differential operation, there is often a need to A E R 0 perform the single-ended-to-differential conversion. G A LT This single-ended-to-differential conversion can be performed O–2 UT V R±A1N0GVE using an op amp pair. Typical connection diagrams for an op NP–4 ±10V R±A2N.5GVE amp pair are shown in Figure 42 and Figure 43. In Figure 42, O I RANGE the common-mode signal is applied to the noninverting input D EU 0VTO +10V 0VTO +10V of the second amplifier. PS–6 RANGE RANGE –8 VVCRCEF = = 3 2V.5V ±16.5V VDD/VSS ±12V VDD/VSS 05400-040 VIN 3kΩ 1.5AkDΩ845 Figure 41. Pseudo Input Range with VCC = 3 V V+ DRIVER AMPLIFIER CHOICE 1.5kΩ 1.5kΩ In applications where the harmonic distortion and signal-to- 1.5kΩ noise ratio are critical specifications, the analog input of the AD7323 should be driven from a low impedance source. Large V– source impedances significantly affect the ac performance of the 10kΩ VCOM AD845 ADC and can necessitate the use of an input buffer amplifier. 20kΩ 05400-029 When no amplifier is used to drive the analog input, the source Figure 42. Single-Ended-to-Differential Configuration with the AD845 impedance should be limited to low values. The maximum 442Ω source impedance depends on the amount of THD that can be tolerated in the application. The THD increases as the source 442Ω AD8021 VIN impedance increases and performance degrades. Figure 21 and V+ Figure 22 show graphs of the THD vs. the analog input frequency for various source impedances. Depending on the 442Ω input range and analog input configuration selected, the 442Ω AD7323 can handle source impedances of up to 5.5 kΩ before 442Ω the THD starts to degrade. 442Ω Due to the programmable nature of the analog inputs on the V– AD7323, the choice of op amp used to drive the inputs is a AD8021 fcuonncfitgiounra otifo tnh ea npda rtthiec ualnaarl oapg pinlipcautti ovonl taangde rdaenpgeensd sse loenct tehde. input 100Ω 05400-030 Figure 43. Single-Ended-to-Differential Configuration with the AD8021 Rev. B | Page 21 of 36

AD7323 Data Sheet REGISTERS write bit determines if the data on the DIN line following the The AD7323 has three programmable registers: the control register select bits loads into the addressed register. If the write register, sequence register, and range register. These registers bit is 1, the bits load into the register addressed by the register are write-only registers. select bits. If the write bit is 0, the data on the DIN line does not ADDRESSING REGISTERS load into any register. A serial transfer on the AD7323 consists of 16 SCLK cycles. The Combinations of the write bit, the Register Select 1 bit, and the three MSBs on the DIN line during the 16 SCLK transfer are Register Select 2 bit other than those specified in Table 8 access decoded to determine which register is addressed. The three registers for Analog Devices internal use only. Accessing these MSBs consist of the write bit, the Register Select 1 bit, and the registers may lead to unspecified operation of the device. Register Select 2 bit. The register select bits are used to determine which of the three on-board registers is selected. The Table 8. Decoding Register Select Bits and Write Bit Write Register Select 1 Register Select 2 Description 0 0 0 Data on the DIN line during this serial transfer is ignored. 1 0 0 This combination selects the control register. The subsequent 12 bits are loaded into the control register. 1 0 1 This combination selects the range register. The subsequent eight bits are loaded into the range register. 1 1 1 This combination selects the sequence register. The subsequent four bits are loaded into the sequence register. Rev. B | Page 22 of 36

Data Sheet AD7323 CONTROL REGISTER register and the sequence register have been initialized. The bit The control register is used to select the analog input channel, functions of the control register are shown in Table 9 (the power- analog input configuration, reference, coding, and power mode. up status of all bits is 0). The control register is a write-only, 12-bit register. Data loaded on the DIN line corresponds to the AD7323 configuration for The four analog input channels can be configured as four single- the next conversion. If the sequence register is being used, data ended analog inputs, two true differential input pairs, two should be loaded into the control register after the range pseudo differential inputs, or three pseudo differential inputs. MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Register Select 1 Register Select 2 Zero ADD1 ADD0 Mode 1 Mode 0 PM1 PM0 Coding Ref Seq1 Seq2 Zero 0 Table 9. Control Register Details Bit Mnemonic Description 12, 1 Zero A 0 should be written to these bits. 11, 10 ADD1, ADD0 These two channel address bits are used to select the analog input channel for the next conversion if the sequencer is not being used. If the sequencer is being used, the two channel address bits are used to select the final channel in a consecutive sequence. 9, 8 Mode 1, Mode 0 These two mode bits are used to select the configuration of the four analog input pins, V 0 to V 3. These IN IN pins are used in conjunction with the channel address bits. On the AD7323, the analog inputs can be configured as four single-ended inputs, two true differential input pairs, two pseudo differential inputs, or three pseudo differential inputs (see Table 10). 7, 6 PM1, PM0 The power management bits are used to select different power mode options on the AD7323 (see Table 11). 5 Coding This bit is used to select the type of output coding the AD7323 uses for the next conversion result. If coding = 0, the output coding is twos complement. If coding = 1, the output coding is straight binary. When operating in sequence mode, the output coding for each channel is the value written to the coding bit during the last write to the control register. 4 Ref The reference bit is used to enable or disable the internal reference. If Ref = 0, the external reference is enabled and used for the next conversion, and the internal reference is disabled. If Ref = 1, the internal reference is used for the next conversion. When operating in sequence mode, the reference used for each channel is the value written to the Ref bit during the last write to the control register. 3, 2 Seq1, Seq2 The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Table 12). Table 10. Analog Input Configuration Selection Channel Mode 1 = 1, Mode 0 = 1 Mode 1 = 1, Mode 0 = 0 Mode 1 = 0, Mode 0 = 1 Mode 1 = 0, Mode 0 = 0 Address Bits 3 Pseudo Differential Inputs 2 Fully Differential Inputs 2 Pseudo Differential Inputs 4 Single-Ended Inputs ADD1 ADD0 V + V − V + V − V + V − V + V − IN IN IN IN IN IN IN IN 0 0 V 0 V 3 V 0 V 1 V 0 V 1 V 0 AGND IN IN IN IN IN IN IN 0 1 V 1 V 3 V 0 V 1 V 0 V 1 V 1 AGND IN IN IN IN IN IN IN 1 0 V 2 V 3 V 2 V 3 V 2 V 3 V 2 AGND IN IN IN IN IN IN IN 1 1 Not allowed V 2 V 3 V 2 V 3 V 3 AGND IN IN IN IN IN Rev. B | Page 23 of 36

AD7323 Data Sheet Table 11. Power Mode Selection PM1 PM0 Description 1 1 Full shutdown mode. In this mode, all internal circuitry on the AD7323 is powered down. Information in the control register is retained when the AD7323 is in full shutdown mode. 1 0 Autoshutdown mode. The AD7323 enters autoshutdown on the 15th SCLK rising edge when the control register is updated. All internal circuitry is powered down in autoshutdown. 0 1 Autostandby mode. In this mode, all internal circuitry is powered down, excluding the internal reference. The AD7323 enters autostandby mode on the 15th SCLK rising edge after the control register is updated. 0 0 Normal mode. All internal circuitry is powered up at all times. Table 12. Sequencer Selection Seq1 Seq2 Description 0 0 The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the control register, selects the next channel for conversion. 0 1 Uses the sequence of channels previously programmed into the sequence register for conversion. The AD7323 starts converting on the lowest channel in the sequence. The channels are converted in ascending order. If uninterrupted, the AD7323 keeps converting the sequence. The range for each channel defaults to the range previously written into the range register. 1 0 Used in conjunction with the channel address bits in the control register. This allows continuous conversions on a consecutive sequence of channels, from Channel 0 through a final channel selected by the channel address bits in the control register. The range for each channel defaults to the range previously written into the range register. 1 1 The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the control register, selects the next channel for conversion. Rev. B | Page 24 of 36

Data Sheet AD7323 SEQUENCE REGISTER dedicated range bits for each of the analog input channels from Channel 0 to Channel 3. There are four analog input ranges, The sequence register on the AD7323 is a 4-bit, write-only register. ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V. A write to the range Each of the four analog input channels has one corresponding register is selected by setting the write bit to 1 and the register bit in the sequence register. To select a channel for inclusion in select bits to 0 and 1. After the initial write to the range register the sequence, set the corresponding channel bit to 1 in the occurs, each time an analog input is selected, the AD7323 sequence register. automatically configures the analog input to the appropriate RANGE REGISTER range, as indicated by the range register. The ±10 V input range is selected by default on each analog input channel (see Table 13). The range register is used to select one analog input range per analog input channel. It is an 8-bit, write-only register with two MSB LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Write Register Select 1 Register Select 2 V 0 V 1 V 2 V 3 0 0 0 0 0 0 0 0 0 IN IN IN IN MSB LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Write Register Select 1 Register Select 2 V 0A V 0B V 1A V 1B V 2A V 2B V 3A V 3B 0 0 0 0 0 IN IN IN IN IN IN IN IN Table 13. Range Selection V xA V xB Description IN IN 0 0 This combination selects the ±10 V input range on V x. IN 0 1 This combination selects the ±5 V input range on V x. IN 1 0 This combination selects the ±2.5 V input range on V x. IN 1 1 This combination selects the 0 V to +10 V input range on V x. IN Rev. B | Page 25 of 36

AD7323 Data Sheet SEQUENCER OPERATION The AD7323 can be configured to automatically cycle through This initial serial transfer is only necessary if input ranges other a number of selected channels using the on-chip sequence than the default ranges are required. After the analog input register with the Seq1 bit and the Seq2 bit in the control register. ranges are configured, a write to the sequence register is Figure 44 shows how to program the AD7323 register to necessary to select the channels to be included in the sequence. operate in sequence mode. When the channels for the sequence have been selected, the sequence can be initiated by writing to the control register and After power-up, all of the three on-chip registers contain default setting Seq1 = 0 and Seq2 = 1. The AD7323 continues to values. Each analog input has a default input range of ±10 V. If convert the selected sequence without interruption provided different analog input ranges are required, a write to the range that the sequence register remains unchanged, and Seq1 = 0 and register is required. This is shown in the first serial transfer of Seq2 = 1 in the control register. Figure 44. POWER ON. CS DIN:WRITETORANGEREGISTERTOSELECTTHERANGE FOREACHANALOG INPUTCHANNEL. DOUT:CONVERSIONRESULTFROMCHANNEL0,±10V RANGE,SINGLE-ENDEDMODE. CS DIN:WRITETOSEQUENCEREGISTERTOSELECTTHE ANALOG INPUTCHANNELSTOBE INCLUDED IN THESEQUENCE. DOUT:CONVERSIONRESULTFROMCHANNEL0, SINGLE-ENDEDMODE,RANGESELECTED IN RANGEREGISTER. CS DIN:WRITETOCONTROLREGISTERTOSTARTTHE SEQUENCE,Seq1=0,Seq2=1. DOUT:CONVERSIONRESULTFROMCHANNEL0, SINGLE-ENDEDMODE,RANGESELECTED IN RANGEREGISTER. CS DIN:TIEDINLOW/WRITEBIT=0TOCONTINUETOCONVERT THROUGHTHESEQUENCE OFCHANNELS. CS DOUT:CONVERSIONRESULTFROMFIRSTCHANNEL IN THESEQUENCE. DINTIEDLOW/WRITEBIT=0. DIN:WRITETOCONTROL REGISTERTOSTOPTHE SEQUENCE,Seq1=0,Seq2=0. STOPPING CONTINUOUSLYCONVERT ASEQUENCE. ONTHESELECTEDSEQUENCE DOUT:CONVERSIONRESULT OFCHANNELS. FROMCHANNEL INSEQUENCE. SELECTINGANEWSEQUENCE. CS DIN:WRITETOSEQUENCEREGISTERTOSELECTTHE NEWSEQUENCE. DOUT:CONVERSIONRESULTFROMCHANNELX IN THEFIRSTSEQUENCE. 05400-031 Figure 44. Programmable Sequence Flowchart Rev. B | Page 26 of 36

Data Sheet AD7323 If a change to the range register is required during a sequence, it Once the control register is configured to operate the AD7323 is necessary to first stop the sequence by writing to the control in this mode, the DIN line can be held low, or the write bit can register and setting Seq1 to 0 and Seq2 to 0. Next, the write to be set to 0. To return to traditional multichannel operation, a the range register should be completed to change the required write to the control register to set Seq1 to 0 and Seq2 to 0 is range. The previously selected sequence can be initiated again necessary. by writing to the control register and setting Seq1 to 0 and Seq2 to 1. The ADC converts on the first channel in the sequence. When Seq1 and Seq2 are both set to 0, or when both are set to 1, the AD7323 is configured to operate in traditional multi- The AD7323 can be configured to convert a sequence of channel mode, in which a write to Channel Address Bit ADD1 consecutive channels (see Figure 45). This sequence begins by to Bit ADD0 in the control register selects the next channel for converting on Channel 0 and ends with a final channel as conversion. selected by Bit ADD1 to Bit ADD0 in the control register. In this configuration, there is no need for a write to the sequence register. To operate the AD7323 in this mode, set Seq1 to 1 and Seq2 to 0, and then select the final channel in the sequence by programming Bit ADD1 to Bit ADD0 in the control register. POWER ON. CS DIN:WRITETORANGEREGISTERTOSELECTTHERANGE FORANALOG INPUTCHANNELS. DOUT:CONVERSIONRESULTFROMCHANNEL0,±10V RANGE,SINGLE-ENDEDMODE. CS DIN:WRITETOCONTROLREGISTERTOSELECTTHEFINAL CHANNEL INTHECONSECUTIVESEQUENCE,SETSeq1=1 ANDSeq2=0.SELECT OUTPUTCODINGFORSEQUENCE. DOUT:CONVERSIONRESULTFROMCHANNEL0, RANGESELECTED INRANGEREGISTER, SINGLE-ENDEDMODE. CS DIN:WRITEBIT=0 ORDINLINEHELDLOWTOCONTINUE TOCONVERTTHROUGHTHESEQUENCE OF CONSECUTIVECHANNELS. DOUT:CONVERSIONRESULTFROMCHANNEL0, RANGESELECTED INRANGEREGISTER. CS DIN:WRITEBIT=0 ORDINLINEHELDLOWTOCONTINUE THROUGHSEQUENCE OFCONSECUTIVECHANNELS. DOUT:CONVERSIONRESULTFROMCHANNEL1, RANGESELECTED INRANGEREGISTER. DINTIEDLOW/WRITEBIT=0. CONTINUOUSLYCONVERT STOPPING ONCONSECUTIVESEQUENCE ASEQUENCE. OFCHANNELS. CS DIN:WRITETOCONTROL REGISTERTOSTOPTHE SEQUENCE,Seq1=0,Seq2=0. FDROOUMTC:HCAONNNVEELR SINIOSNEQREUSEUNLCTE. 05400-032 Figure 45. Flowchart for Consecutive Sequence of Channels Rev. B | Page 27 of 36

AD7323 Data Sheet REFERENCE conversion result from the first initial conversion is invalid. The reference buffer requires 500 µs to power up and charge the The AD7323 can operate with either the internal 2.5 V on-chip 680 nF decoupling capacitor during the power-up time. reference or an externally applied reference. The internal reference is selected by setting the Ref bit in the control register The AD7323 is specified for a 2.5 V to 3 V reference range. to 1. On power-up, the Ref bit is 0, which selects the external When a 3 V reference is selected, the ranges are ±12 V, ±6 V, reference for the AD7323 conversion. Suitable reference sources ±3 V, and 0 V to +12 V. For these ranges, the V and V supply DD SS for the AD7323 include AD780, AD1582, ADR431, REF193, must be equal to or greater than the maximum analog input and ADR391. range selected (see Table 6). The internal reference circuitry consists of a 2.5 V band gap VDRIVE reference and a reference buffer. When operating the AD7323 The AD7323 has a V feature to control the voltage at which DRIVE in internal reference mode, the 2.5 V internal reference is available the serial interface operates. V allows the ADC to easily DRIVE at the REFIN/OUT pin, which should be decoupled to AGND interface to both 3 V and 5 V processors. For example, if the using a 680 nF capacitor. It is recommended that the internal AD7323 is operated with a V of 5 V, the V pin can be CC DRIVE reference be buffered before applying it elsewhere in the system. powered from a 3 V supply. This allows the AD7323 to accept The internal reference is capable of sourcing up to 90 μA. large bipolar input signals with low voltage digital processing. On power-up, if the internal reference operation is required for the ADC conversion, a write to the control register is necessary to set the Ref bit to 1. During the control register write, the Rev. B | Page 28 of 36

Data Sheet AD7323 MODES OF OPERATION The AD7323 has several modes of operation that are designed The AD7323 remains fully powered up at the end of the to provide flexible power management options. These options conversion if both PM1 and PM0 contain 0 in the control can be chosen to optimize the power dissipation/throughput register. rate ratio for different application requirements. The mode of To complete the conversion and access the conversion result, operation of the AD7323 is controlled by the power management 16 serial clock cycles are required. At the end of the conversion, bits, Bit PM1 and Bit PM0, in the control register as shown in CS can idle either high or low until the next conversion. Table 11. The default mode is normal mode, where all internal circuitry is fully powered up. Once the data transfer is complete, another conversion can be NORMAL MODE (PM1 = PM0 = 0) initiated after the quiet time, tQUIET, has elapsed. This mode is intended for the fastest throughput rate performance FULL SHUTDOWN MODE (PM1 = PM0 = 1) with the AD7323 being fully powered up at all times. Figure 46 In this mode, all internal circuitry on the AD7323 is powered shows the general operation of the AD7323 in normal mode. down. The part retains information in the registers during full shutdown. The AD7323 remains in full shutdown mode until The conversion is initiated on the falling edge of CS, and the the power management bits, Bit PM1 and Bit PM0, in the track-and-hold section enters hold mode, as described in the control register are changed. Serial Interface section. Data on the DIN line during the 16 SCLK transfer is loaded into one of the on-chip registers if the write A write to the control register with PM1 = 1 and PM0 = 1 places bit is set. The register is selected by programming the register the part into full shutdown mode. The AD7323 enters full shut- select bits (see Table 8). down mode on the 15th SCLK rising edge once the control register is updated. CS 1 16 If a write to the control register occurs while the part is in full SCLK shutdown mode with the power management bits, Bit PM1 and Bit PM0, set to 0 (normal mode), the part begins to power up DOUT LEADINGZERCOO,N2VCEHRASNIONNELR IE.DS.UBLITTS,SIGNBIT+ on the 15th SCLK rising edge once the control register is DIN DATA INTOCONTROL/SEQUENCE/RANGEREGISTER 05400-035 ufupldl ashteudt.d Foiwgunr me 4o7d es.h Toow es nhsouwre t hthee A ADD77332233 i sis c founllfyig puorwede rteod e uxipt, Figure 46. Normal Mode tPOWER-UP should elapse before the next CS falling edge. THEPART ISFULLYPOWEREDUP PART IS INFULL ONCEtPOWER-UPHASELAPSED SHUTDOWN PARTBEGINSTOPOWERUP ONTHE15TH SCLKRISINGEDGEASPM1=PM0=0 tPOWER-UP CS 1 16 1 16 SCLK SDATA INVALIDDATA CHANNEL IDENTIFIERBITS+CONVERSIONRESULT DIN DATA INTOCONTROLREGISTER DATA INTOCONTROLREGISTER CONTROLREGISTER IPSML1O=A0D,EPDM O0N=T0HEFIRST15CLOCKS, TOKEEPTHEPARITN INCONNOTRRMOALLRMEOGDISET,ELROADPM1=PM0=0 05400-041 Figure 47. Exiting Full Shutdown Mode Rev. B | Page 29 of 36

AD7323 Data Sheet AUTOSHUTDOWN MODE (PM1 = 1, PM0 = 0) As is the case with autoshutdown mode, the AD7323 enters standby on the 15th SCLK rising edge once the control register is Once the autoshutdown mode is selected, the AD7323 auto- matically enters shutdown on the 15th SCLK rising edge. In updated (see Figure 48). The part retains information in the registers during standby. The AD7323 remains in standby until autoshutdown mode, all internal circuitry is powered down. The AD7323 retains information in the registers during it receives a CS rising edge. The ADC begins to power up on the autoshutdown. The track-and-hold is in hold mode during CS rising edge. On the CS rising edge, the track-and-hold, which autoshutdown. On the rising CS edge, the track-and-hold, was in hold mode while the part was in standby, returns to track. which was in hold during shutdown, returns to track as the The power-up time from standby is 750 ns. The user should AD7323 begins to power up. The power-up from autoshutdown ensure that 750 ns have elapsed before bringing CS low to attempt is 500 µs. a valid conversion. Once this valid conversion is complete, the When the control register is programmed to transition to AD7323 again returns to standby on the 15th SCLK rising edge. autoshutdown mode, it does so on the 15th SCLK rising edge. The CS signal must remain low to keep the part in standby mode. Figure 48 shows the part entering autoshutdown mode. The Figure 48 shows the part entering autoshutdown mode. The AD7323 automatically begins to power up on the CS rising sequence of events is the same when entering autostandby mode. edge. The t is required before a valid conversion, initiated POWER-UP In Figure 48, the power management bits are configured for by bringing the CS signal low, can take place. Once this valid autoshutdown. For autostandby mode, the power management conversion is complete, the AD7323 powers down again on the bits, PM1 and PM0, should be set to 0 and 1, respectively. 15th SCLK rising edge. The CS signal must remain low again to keep the part in autoshutdown mode. AUTOSTANDBY MODE (PM1 = 0, PM0 = 1) In autostandby mode, portions of the AD7323 are powered down, but the on-chip reference remains powered up. The reference bit in the control register should be 1 to ensure that the on-chip reference is enabled. This mode is similar to auto- shutdown but allows the AD7323 to power up much faster, which allows faster throughput rates. PARTBEGINSTOPOWER THEPART ISFULLYPOWEREDUP UP ONCSRISINGEDGE ONCEtPOWER-UPHASELAPSED PARTENTERSSHUTDOWNMODE tPOWER-UP ONTHE15THRISINGSCLKEDGE CS ASPM1=1,PM0=0 1 15 16 1 15 16 SCLK SDATA VALIDDATA VALIDDATA DIN DATA INTOCONTROLREGISTER DATA INTOCONTROLREGISTER CONTROLREGISTER IPSML1O=A1D,EPDM O0N=T0HEFIRST15CLOCKS, 05400-042 Figure 48. Entering Autoshutdown/Autostandby Mode Rev. B | Page 30 of 36

Data Sheet AD7323 POWER vs. THROUGHPUT RATE 20 The power consumption of the AD7323 varies with throughput VCC=5V rate. The static power consumed by the AD7323 is very low, and 18 VDD/VSS=±12V TA=25°C significant power savings can be achieved as the throughput 16 INTERNALREFERENCE rate is reduced. Figure 49 and Figure 50 shows the power vs. mW) 14 throughput rate for the AD7323 at a VCC of 3 V and 5 V, respec- ER ( 12 tively. Both plots clearly show that the average power consumed W PO 10 by the AD7323 is greatly reduced as the sample frequency is E reduced. This is true whether a fixed SCLK value is used or if it RAG 8 E is scaled with the sampling frequency. Figure 49 and Figure 50 AV 6 VARIABLESCLK show the power consumption when operating in normal mode 4 for a variable SCLK that scales with the sampling frequency. 2 1102 VVTINACDTCD=E/=VR2S5N3S°VAC=L±R1E2FVERENCE 00 Figure 5100.0 PowTHeRr OvsU2.0 GT0HhProUuTgRhApT3uE0t0 (RkSaPteS w) ith40 50 V VCC 500 05400-053 W) m 8 ER ( W PO 6 E G A ER 4 VARIABLESCLK V A 2 0 0 100 THROU20G0HPUTRAT3E00(kSPS) 400 500 05400-052 Figure 49. Power vs. Throughput Rate with 3 V VCC Rev. B | Page 31 of 36

AD7323 Data Sheet SERIAL INTERFACE Figure 51 shows the timing diagram for the serial interface of Data is clocked into the AD7323 on the SCLK falling edge. The the AD7323. The serial clock applied to the SCLK pin provides three MSBs on the DIN line are decoded to select which register the conversion clock and controls the transfer of information to is being addressed. The control register is a 12-bit register. If the and from the AD7323 during a conversion. control register is addressed by the three MSBs, the data on the DIN line is loaded into the control on the 15th SCLK falling The CS signal initiates the data transfer and the conversion edge. If the sequence register or the range register is addressed, process. The falling edge of CS puts the track-and-hold into the data on the DIN line is loaded into the addressed register on hold mode and takes the bus out of three-state. Then the analog the 11th SCLK falling edge. input signal is sampled. When the conversion is initiated, it requires 16 SCLK cycles to complete. Conversion data is clocked out of the AD7323 on each SCLK falling edge. Data on the DOUT line consists of a zero bit, two The track-and-hold goes back into track mode on the 14th SCLK channel identifier bits, a sign bit, and a 12-bit conversion result. rising edge. On the 16th SCLK falling edge, the DOUT line returns The channel identifier bits are used to indicate which channel to three-state. If the rising edge of CS occurs before 16 SCLK corresponds to the conversion result. The zero bit is clocked out cycles have elapsed, the conversion is terminated, and the on the CS falling edge, and the ADD1 bit is clocked out on the DOUT line returns to three-state. Depending on where the CS first SCLK falling edge. signal is brought high, the addressed register may be updated. t1 CS tCONVERT t2 t6 SCLK 1 2 3 4 5 13 14 15 16 2t 3IDENTIFICATIONBITS t4 t7 t5 t8 tQUIET DOUT ADD1 ADD0 SIGN DB11 DB10 DB2 DB1 DB0 TSHTRAETEE- ZERO t9 t10 THREE-STATE DIN WRITE SREELG1 SREELG2 MSB LSB DCOANR’ET 05400-036 Figure 51. Serial Interface Timing Diagram (Control Register Write) Rev. B | Page 32 of 36

Data Sheet AD7323 MICROPROCESSOR INTERFACING The serial interface on the AD7323 allows the part to be directly The frequency of the serial clock is set in the SCLKDIV register. connected to a range of different microprocessors. This section When the instruction to transmit with TFS is given (AX0 = TX0), explains how to interface the AD7323 with some common the state of the serial clock is checked. The DSP waits until the microcontroller and DSP serial interface protocols. SCLK has gone high, low, and high again before starting the transmission. If the timer and SCLK are chosen so that the AD7323 TO ADSP-21xx instruction to transmit occurs on or near the rising edge of SCLK, The ADSP-21xx family of DSPs interface directly to the AD7323 data can be transmitted immediately or at the next clock edge. without requiring glue logic. The V pin of the AD7323 takes DRIVE For example, the ADSP-2111 has a master clock frequency of the same supply voltage as that of the ADSP-21xx. This allows 16 MHz. If the SCLKDIV register is loaded with the value 3, an the ADC to operate at a higher supply voltage than its serial SCLK of 2 MHz is obtained, and eight master clock periods elapse interface. The SPORT0 on the ADSP-21xx should be configured for every one SCLK period. If the timer registers are loaded with as shown in Table 14. the value 803, 100.5 SCLKs occur between interrupts and, sub- sequently, between transmit instructions. This situation leads to Table 14. SPORT0 Control Register Setup nonequidistant sampling because the transmit instruction occurs Setting Description on an SCLK edge. If the number of SCLKs between interrupts is TFSW = RFSW = 1 Alternative framing an integer of N, equidistant sampling is implemented by the DSP. INVRFS = INVTFS = 1 Active low frame signal DTYPE = 00 Right justify data AD7323 TO ADSP-BF53x SLEN = 1111 16-bit data-word The ADSP-BF53x family of DSPs interfaces directly to the ISCLK = 1 Internal serial clock AD7323 without requiring glue logic, as shown in Figure 53. TFSR = RFSR = 1 Frame every word The SPORT0 Receive Configuration 1 register should be set up IRFS = 0 Internal receive frame sync as outlined in Table 15. ITFS = 1 Internal transmit frame sync The connection diagram is shown in Figure 52. The ADSP-21xx AD73231 ADSP-BF53x1 has TFS0 and RFS0 tied together. TFS0 is set as an output, and SCLK RSCLK0 RFS0 is set as an input. The DSP operates in alternative framing mode, and the SPORT0 control register is set up as described in CS RFS0 Table 14. The frame synchronization signal generated on the TFS DIN DT0 is tied to CS, and, as with all signal processing applications, requires equidistant sampling. However, as in this example, the timer DOUT DR0 interrupt is used to control the sampling rate of the ADC, and VDRIVE under certain conditions equidistant sampling cannot be achieved. AD73231 ADSP-21xx1 1ADDITIONALPINS OMITTEDFORCLARITY. VDD 05400-038 SCLK SCLK0 Figure 53. Interfacing the AD7323 to the ADSP-BF53x CS TFS0 RFS0 Table 15. SPORT0 Receive Configuration 1 Register Setting Description DIN DT0 RCKFE = 1 Sample data with falling edge of RSCLK DOUT DR0 VDRIVE LRFS = 1 Active low frame signal RFSR = 1 Frame every word IRFS = 1 Internal RFS used 1ADDITIONALPINS OMITTEDFORCLARITY. VDD 05400-037 RRLDSTBYIPTE = = 0 0 0 RZeercoe ifvilel MSB first Figure 52. Interfacing the AD7323 to the ADSP-21xx IRCLK = 1 Internal receive clock RSPEN = 1 Receive enable The timer registers are loaded with a value that provides an SLEN = 1111 16-bit data-word interrupt at the required sampling interval. When an interrupt TFSR = RFSR = 1 Transmit and receive frame sync is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS, and therefore the reading of data. Rev. B | Page 33 of 36

AD7323 Data Sheet APPLICATION HINTS LAYOUT AND GROUNDING POWER SUPPLY CONFIGURATION The printed circuit board that houses the AD7323 should be It is recommended that Schottky diodes be placed in series with designed so that the analog and digital sections are confined to the AD7323 V and V supply signals. Figure 54 shows this DD SS certain areas of the board. This design facilitates the use of Schottky diode configuration. BAT43 Schottky diodes are used. ground planes that can easily be separated. V+ 3V/5V To provide optimum shielding for ground planes, a minimum etch technique is generally best. All AGND pins on the AD7323 VDD VCC should be connected to the AGND plane. Digital and analog VIN0 AD73231 CS ground pins should be joined in only one place. If the AD7323 VIN1 SCLK is in a system where multiple devices require an AGND and VIN2 DOUT VIN3 DIN DGND connection, the connection should still be made at only VSS one point. A star point should be established as close as possible to the ground pins on the AD7323. Good connections should be made to the power and ground 1ADDITIONAL PINSV –OMITTED FOR CLARITY.05400-056 planes. This can be done with a single via or multiple vias for Figure 54. Schottky Diode Connection each supply and ground pin. In an application where nonsymmetrical V and V supplies DD SS Avoid running digital lines under the AD7323 device because are being used, adhere to the following guidelines. Table 16 this couples noise onto the die. However, the analog ground outlines the V supply range that can be used for particular V SS DD plane should be allowed to run under the AD7323 to avoid voltages when nonsymmetrical supplies are required. When noise coupling. The power supply lines to the AD7323 device operating the AD7323 with low V and V voltages, it is recom- DD SS should use as large a trace as possible to provide low impedance mended that these supplies be symmetrical. paths and reduce the effects of glitches on the power supply line. For the 0 V to 4 × V range, V can be tied to AGND as per REF SS To avoid radiating noise to other sections of the board, com- minimum supply recommendations outlined in Table 6. ponents with fast switching signals, such as clocks, should be shielded with digital ground and never run near the analog inputs. Table 16. Nonsymmetrical V and V Requirements DD SS Avoid crossover of digital and analog signals. To reduce the effects V Typical V Range DD SS of feedthrough within the board, traces should be run at right 5 V −5 V to −5.5 V angles to each other. A microstrip technique is the best method, 6 V −5 V to −8.5 V but its use may not be possible with a double-sided board. In 7 V −5 V to −11.5 V this technique, the component side of the board is dedicated to 8 V −5 V to −15 V ground planes, and signals are placed on the other side. 9 V −5 V to −16.5 V 10 V to 16.5 V −5 V to −16.5 V Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum capacitors in parallel with 0.1 µF capacitors to AGND. To achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 µF capacitors should have a low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic and surface mount types of capacitors. These low ESR, low ESI capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Rev. B | Page 34 of 36

Data Sheet AD7323 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0.S6C5 0.19 SPELAANTIENG 0° 0.45 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 55. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions show in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD7323BRUZ –40°C to +85°C 16-Lead TSSOP RU-16 AD7323BRUZ-REEL –40°C to +85°C 16-Lead TSSOP RU-16 AD7323BRUZ-REEL7 –40°C to +85°C 16-Lead TSSOP RU-16 1 Z = RoHS Compliant Part. Rev. B | Page 35 of 36

AD7323 Data Sheet NOTES ©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05400-0-12/13(B) Rev. B | Page 36 of 36

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