3 V/5 V, Rail-to-Rail Quad, 8-Bit DAC AD7304/AD7305 FEATURES FUNCTIONAL BLOCK DIAGRAMS Four 8-bit DACs in one package VDD VREFB VREFA +3 V, +5 V, and ±5 V operation Rail-to-rail REF input to voltage output swing PRWERS-EOTN RINEPGU AT 8 DRAECG A 8 DAC A VOUTA 2.6 MHz reference multiplying bandwidth 8 Internal power-on reset RINEPGU BT 8 DRAECG B 8 DAC B VOUTB SPI serial interface-compatible—AD7304 Fast parallel interface—AD7305 CS SERIAL RINEPGU CT 8 DRAECG C 8 DAC C VOUTC SDI/SHDN REG 40 µA power shutdown CLK RINEPGU DT 8 DRAECG D 8 DAC D VOUTD AAuPtPomLIoCtAivTe IoOuNtpSu t span voltage AD7304 01114-001 Instrumentation, digitally controlled calibration VSS GND CLR LDACVREFCVREFD Pin-compatible AD7226 replacement when V < 5.5 V Figure 1. DD GENERAL DESCRIPTION VDD VREF The AD7304/AD73051 are quad, 8-bit DACs that operate from PRWERS-EOTN RINEPGU AT 8 DRAECG A 8 DAC A VOUTA a single +3 V to +5 V supply, or ±5 V supplies. The AD7304 has DB0 8 a serial interface, while the AD7305 has a parallel interface. DDBB12 RINEPGU BT 8 DRAECG B 8 DAC B VOUTB DB3 Irnantegren ianlc pluredceiss iboont hb usuffpeprsly s rwaiinlsg, arlaloilw-tion-gr afiolr. Tpohsei trievfee roern nceeg iantpivuet DDBB45 RINEPGU CT 8 DRAECG C 8 DAC C VOUTC DB6 8 full-scale output voltages. Operation is guaranteed over the WR RINEPGU DT 8 DRAECG D 8 DAC D VOUTD supply voltage range of 2.7 V to 5.5 V, consuming less than 9 mW from a 3 V supply. A0/SHDAN1 DECODE AD7305 01114-002 LDAC VSS GND The full-scale voltage output is determined by the external Figure 2. reference input voltage applied. The rail-to-rail V input to REF DAC VOUT allows for a full-scale voltage set equal to the positive When operating from less than 5.5 V, the AD7305 is supply, VDD, the negative supply, VSS, or any value in between. pin-compatible with the popular industry-standard AD7226. The AD7304’s doubled-buffered serial data interface offers high An internal power-on reset places both parts in the zero-scale speed, 3-wire, SPI®-, and microcontroller-compatible inputs state at turn-on. A 40 µA power shutdown (SHDN) feature is using data in (SDI), clock (CLK), and chip select (CS) pins. activated on both parts by three-stating the SDI/SHDN pin on Additionally, an internal power-on reset sets the output to zero the AD7304 and three-stating the A0/SHDN address pin on the scale. AD7305. The parallel input AD7305 uses a standard address decode The AD7304/AD7305 are specified over the extended industrial along with the WR control line to load data into the input −40°C to +85°C and the automotive −40°C to +125°C registers. temperature ranges. AD7304s are available in a wide-body 16-lead SOIC (R-16) package. The parallel input AD7305 is The double-buffered architecture allows all four input registers available in the wide-body 20-lead SOIC (R-20) surface-mount to be preloaded with new values, followed by an LDAC control package. For ultracompact applications, the thin 1.1 mm, strobe that copies all the new data into the DAC registers, 16-lead TSSOP (RU-16) package is available for the AD7304, thereby updating the analog output values. while the 20-lead TSSOP (RU-20) houses the AD7305. _____________________________________________________ 1 Protected under Patent No. 5684481. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

AD7304/AD7305 TABLE OF CONTENTS Specifications.....................................................................................3 AD7304/AD7305 Power-On Reset..........................................15 Timing Specifications..................................................................4 Power up sequence.....................................................................15 Absolute Maximum Ratings............................................................5 AD7305 Parallel Data Interface....................................................16 ESD Caution..................................................................................5 AD7226 Pin Compatibility.......................................................16 Pin Configurations and Function Descriptions...........................8 AD7305 Hardware Shutdown SHDN......................................16 Typical Performance Characteristics...........................................10 ESD Protection Circuits............................................................16 Circuit Operation...........................................................................14 Applications.....................................................................................17 DAC Section................................................................................14 Outline Dimensions.......................................................................18 AD7304 Serial Data Interface.......................................................15 Ordering Guide..........................................................................19 AD7304 Hardware Shutdown SHDN......................................15 Revision History 11/04—Data Sheet Changed from Rev. B to Rev. C Update Format....................................................................Universal Update Features................................................................................1 Changes to Figure 35......................................................................15 Add Power-Up Sequence...............................................................15 Changes to Figure 36......................................................................16 Change to Figure 37.......................................................................16 Updated Outline Dimensions.......................................................18 2/04—Data Sheet Changed from Rev. A to Rev. B Renumber TPCs and Figures............................................Universal Deleted N-16 and N-20 packages.....................................Universal Changes to Absolute Maximum Ratings.......................................3 Changes to Ordering Guide............................................................4 Updated Outline Dimensions.......................................................14 3/98—Changed from Rev. 0 to Rev. A 2/98—Revision 0: Initial Version Rev. C | Page 2 of 20

AD7304/AD7305 SPECIFICATIONS @ V = 3 V or 5 V, V = 0 V; or V = +5 V and V = –5 V, V ≤ V ≤ V , −40°C < T < +85°C/+125°C, unless otherwise noted. DD SS DD SS SS REF DD A Table 1. Parameter Symbol Condition 3 V ± 10% 5 V ± 10% ±5 V ± 10% Unit STATIC PERFORMANCE Resolution1 N 8 8 8 Bits Integral Nonlinearity2 INL ±1 ±1 ±1 LSB max Differential Nonlinearity DNL Monotonic, all codes 0 to 0xFF ±1 ±1 ±1 LSB max Zero-Scale Error V Data = 0x00 15 15 ±15 mV max ZSE Full-Scale Voltage Error V Data = 0xFF ±4 ±4 ±4 LSB max FSE Full-Scale Temperature TCVFS 5 5 5 ppm/°C typ4 Coefficient3 REFERENCE INPUT VREFIN Range VREFIN VSS/VDD VSS/VDD VSS/VDD V min/max Input Resistance (AD7304) R Code = 0x55 28 28 28 kΩ typ REFIN Input Resistance (AD7305) R All DACs at code = 0x55 7.5 7.5 7.5 kΩ typ REFIN Input Capacitance3 CREFIN 5 5 5 pF typ ANALOG OUTPUTS Output Voltage Range VOUT VSS/VDD VSS/VDD VSS/VDD V min/max Output Current Drive I Code = 0x80, ∆V < 1 LSB ±3 ±3 ±3 mA typ OUT OUT Shutdown Resistance R DAC outputs placed in shutdown 120 120 120 kΩ typ OUT state Capacitive Load3 CL No oscillation 200 200 200 pF typ LOGIC INPUTS Logic Input Low Voltage VIL 0.6 0.8 0.8 V min Logic Input High Voltage VIH 2.1 2.4 2.4 V max Input Leakage Current5 IIL ±10 ±10 ±10 µA max Input Capacitance3 CIL 8 8 8 pF max AC CHARACTERISTICS3 Output Slew Rate SR Code = 0x00 to 0xFFto 0x00 1/2.7 1/3.6 1.0/3.6 V/µs min/typ Reference Multiplying BW Small signal, VSS = –5 V 2.6 MHz typ Total Harmonic Distortion THD VREF = 4 V p-p, VSS = –5 V, f = 1 kHz 0.025 % Settling Time6 t To ±0.1% of full scale 1.1/2 1.0/2 1.0/2 µs typ/max S Shutdown Recovery Time t To ±0.1% of full scale 2 2 2 µs max SDR Time to Shutdown tSDN 15 15 15 µs typ DAC Glitch Q 15 15 15 nVs typ Digital Feedthrough Q 2 2 2 nVs typ Feedthrough VOUT/VREF Code = 0x00, VREF = 1 V p-p, f = 100 kHz −65 dB SUPPLY CHARACTERISTICS Positive Supply Current I V = 0 V or V , no load 6 6 6 mA max DD LOGIC DD Negative Supply Current ISS VSS = –5 V 6 mA max Power Dissipation P V = 0 V or V , no load 15 30 60 mW max DISS LOGIC DD Power Down I SDI/SHDN = floating 40 40 40 µA typ DD_SD Power Supply Sensitivity PSS ∆V = ±10% 0.004 0.004 0.004 %/% DD 1 One LSB = VREF/256. 2 The first three codes (0x00, 0x01, 0x10) are excluded from the integral nonlinearity error measurement in single-supply operation 3 V or 5 V. 3 These parameters are guaranteed by design and not subject to production testing. 4 Typical specifications represent average readings measured at 25°C. 5 The SDI/SHDN and A0/SHDN pins have a 30 µA maximum IIL input leakage current. 6 The settling time specification does not apply for negative going transitions within the last three LSBs of ground in single-supply operation. Rev. C | Page 3 of 20

AD7304/AD7305 +5V VREF = 10V p-p f = 20kHz +5V 0V 0V –5V VOUT = 10V p-p (O–U5TV) (IN) 01114-003 Figure 3. Rail-to-Rail Reference Input to Output at 20 kHz TIMING SPECIFICATIONS @ V = 3 V or 5 V, V = 0 V; or V = +5 V and V = –5 V, V ≤ V ≤ V , –40°C < T < +85°C/+125°C, unless otherwise noted. DD SS DD SS SS REF DD A Table 2. Parameter Symbol 3 V ± 10% 5 V ± 10% ±5 V ± 10% Unit INTERFACE TIMING SPECIFICATIONS1, 2 AD7304 Only Clock Width High t 70 55 55 ns min CH Clock Width Low t 70 55 55 ns min CL Data Setup t 50 40 40 ns min DS Data Hold t 30 20 20 ns min DH Load Pulse Width t 70 60 60 ns min LDW Load Setup t 40 30 30 ns min LD1 Load Hold t 40 30 30 ns min LD2 Clear Pulse Width t 60 60 60 ns min CLWR Select t 30 20 20 ns min CSS Deselect t 60 40 40 ns min CSH AD7305 Only Data Setup t 60 40 40 ns min DS Data Hold t 30 20 20 ns min DH Address Setup t 60 40 40 ns min AS Address Hold t 30 20 20 ns min AH Write Width t 60 50 50 ns min WR Load Pulse Width t 60 50 50 ns min LDW Load Setup t 60 40 40 ns min LS Load Hold t 30 20 20 ns min LH 1 These parameters are guaranteed by design and not subject to production testing. 2 All input control signals are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Rev. C | Page 4 of 20

AD7304/AD7305 ABSOLUTE MAXIMUM RATINGS Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress VDD to GND −0.3 V, +8 V rating only; functional operation of the device at these or any VSS to GND +0.3 V, −8 V other conditions above those indicated in the operational V to GND V , V sections of this specification is not implied. Exposure to REFX SS DD Logic Inputs to GND −0.3 V, VDD + 0.3 V absolute maximum rating conditions for extended periods may affect device reliability. VOUTX to GND −0.3 V, VDD + 0.3 V I Short-Circuit to GND 50 mA OUT Package Power Dissipation (TJ MAX – TA)/θJA Thermal Resistance θJA 16-Lead SOIC Package (R-16) 73°C/W 16-Lead TSSOP Package (RU-16) 180°C/W 20-Lead SOIC Package (R-20) 74°C/W 20-Lead TSSOP Package (RU-20) 155°C/W Maximum Junction Temperature (T ) 150°C J MAX Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature R-16, R-20, RU-16, RU-20 (Vapor Phase, 60 sec) 235°C R-16, R-20, RU-16, RU-20 (Infrared, 15 sec) 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 5 of 20

AD7304/AD7305 SDI SA SI A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 CLK tCSS tCSH CS t LD2 LDAC t LD1 SDI t t DS DH t CLK CL t CH t LDAC LDW t CLR t CLRW S FS VOUT ERR±O1 RL SBBAND ZS tS 01114-004 Figure 4. AD7304 General Timing Diagram t SDN SDI/SHDN tSDR IDD Figure 5. AD7304 Timing Diagram Zoom In 01114-005 Table 4. AD7304 Control Logic Truth Table CS 1 CLK1 LDAC CLR1 Serial Shift Register Function Input REG Function DAC Register Function H X H H No effect No effect No effect L ↑+ H H Data advanced 1 bit No effect No effect ↑+ L H H No effect Updated with SR contents2 No effect H X L H No effect Latched with SR contents2 All input register contents transferred3 H X H ↓– No effect Loaded with 0x00 Loaded with 0x00 H X H ↑+ No effect Latched with 0x00 Latched with 0x00 1 ↑+ positive logic transition; ↓– negative logic transition; X Don’t Care. 2 One input register receives the data bits D7–D0 decoded from the SR address bits (A1, A0), where REG A = (0, 0), B = (0, 1), C = (1, 0), and D = (1, 1). 3 LDAC is a level-sensitive input. Table 5. AD7304 Serial Input Register Data Format, Data is Loaded in MSB-First Format MSB LSB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 AD7304 SAC SDC A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 If B11 (SAC), Shutdown All Channels, is set to logic low, all DACs are placed in a power shutdown mode, and all output voltages become high resistance. If B10 (SDC), Shutdown Decoded Channel, is set to logic low, only the DAC decoded by Address Bits A1 and A0 is placed in shutdown mode. Rev. C | Page 6 of 20

AD7304/AD7305 Table 6. AD7305 Control Logic Truth Table WR 1 A1 A0 LDAC2 Input Register Function DAC Register Function L L L H Register A loaded with DB0 to DB7 Latched with previous contents, no change ↑+ L L H Register A latched with DB0 to DB7 Latched with previous contents, no change L L H H Register B loaded with DB0 to DB7 Latched with previous contents, no change ↑+ L H H Register B latched with DB0 to DB7 Latched with previous contents, no change L H L H Register C loaded with DB0 to DB7 Latched with previous contents, no change ↑+ H L H Register C latched with DB0 to DB7 Latched with previous contents, no change L H H H Register D loaded with DB0 to DB7 Latched with previous contents, no change ↑+ H H H Register D latched with DB0 to DB7 Latched with previous contents, no change H X X L No effect All input register contents loaded, register transparent L X X L Input register x transparent to DB0 to DB7 Register transparent H X X ↑+ No effect All input register contents latched H X X H No effect, device not selected No effect, device not selected 1 ↑+ positive logic transition; ↓– negative logic transition; X don’t care. 2 LDAC is a level-sensitive input. t WR WR tAS tAH A0, A1 tDS tDH D0–D7 tLS tLH tLDW LDAC t S VOUT ERR±O1 RL SBBAND 01114-006 Figure 6. AD7305 General Timing Diagram t SDN A0/SHDN tSDR IDD 01114-007 Figure 7. AD7305 Timing Diagram Zoom In Rev. C | Page 7 of 20

AD7304/AD7305 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUTB 1 16 VOUTC VOUTA 2 15 VOUTD VSS 3 AD7304 14 VDD VREFA 4 TOP VIEW 13 VREFC VREFB 5 (Not to Scale) 12 VREFD GND 6 11 SDI/SHDN LDCALRC 78 190 CCLSK 01114-008 Figure 8. AD7304 Pin Configuration Table 7. AD7304 Pin Function Descriptions Pin No. Mnemonic Description 1 V B Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V B pin. OUT REF Output is open circuit when SHDN is enabled. 2 V A Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V A pin. OUT REF Output is open circuit when SHDN is enabled. 3 VSS Negative Power Supply Input. Specified range of operation is 0 V to −5.5 V. 4 V A Channel A Reference Input. Establishes V Afull-scale voltage. Specified range of operation is V < V A < V . REF OUT SS REF DD 5 V B Channel B Reference Input. Establishes V B full-scale voltage. Specified range of operation is V < V B < V . REF OUT SS REF DD 6 GND Common Analog and Digital Ground. 7 LDAC Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the corresponding DAC registers. Asynchronous active low input. DAC register is transparent when LDAC = 0. See Table 4 for operation. 8 CLR Clears All Input and DAC Registers to the Zero Condition. Asynchronous active low input. The serial register is not effected. 9 CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial input register data to the decoded input register when CS returns high. Does not effect LDAC operation. 10 CLK Clock Input, Positive Edge Clocks Data into Shift Register. Disabled by chip select CS. 11 SDI/SHDN Serial Data Input Loads Directly into the Shift Register, MSB First. Hardware shutdown (SHDN) control input, active when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as power is present on V . DD 12 V D Channel D Reference Input. Establishes V Dfull-scale voltage. Specified range of operation is V < V D < V . REF OUT SS REF DD 13 V C Channel C Reference Input. Establishes V C full-scale voltage. Specified range of operation is V V C < V . REF OUT SS REF DD 14 V Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V. DD 15 V D Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V D pin. OUT REF Output is open circuit when SHDN is enabled. 16 V C Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V C pin. OUT REF Output is open circuit when SHDN is enabled. Rev. C | Page 8 of 20

AD7304/AD7305 VOUTB 1 20 VOUTC VOUTA 2 19 VOUTD VSS 3 AD7305 18 VDD VREF 4 TOP VIEW 17 A0/SHDN (Not to Scale) GND 5 16 A1 LDAC 6 15 WR DB7 7 14 DB0 DB6 8 13 DB1 DB5 9 12 DB2 DB4 10 11 DB3 01114-009 Figure 9. AD7305 Pin Configuration Table 8. AD7305 Pin Function Description Pin No. Mnemonic Description 1 V B Channel B Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V B pin. Output is OUT REF open circuit when SHDN is enabled. 2 V A Channel A Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V A pin. Output is OUT REF open circuit when SHDN is enabled. 3 V Negative Power Supply Input. Specified range of operation is 0 V to –5.5 V. SS 4 V Channel B Reference Input. Establishes V full-scale voltage. Specified range of operation is V < V < V . REF OUT SS REF DD 5 GND Common Analog and Digital Ground. 6 LDAC Load DAC Register Strobe, Active Low. Simultaneously transfers data from all four input registers into the corresponding DAC registers. Asynchronous active low input. DAC register is transparent when LDAC = 0. See Table 6 for operation. 7 DB7 MSB Digital Input Data Bit. 8 DB6 Data Bit 6. 9 DB5 Data Bit 5. 10 DB4 Data Bit 4. 11 DB3 Data Bit 3. 12 DB2 Data Bit 2. 13 DB1 Data Bit 1. 14 DB0 LSB Digital Input Data Bit. 15 WR Write Data into Input Register Control Line, Active Low. See Table 6 for operation. 16 A1 Address Bit 1. 17 A0/SHDN Address Bit 0/Hardware Shutdown (SHDN) Control Input, Active When Pin Is Left Floating by a Three-State Logic Driver. Does not effect DAC register contents as long as power is present on V . DD 18 V Positive Power Supply Input. Specified range of operation is 2.7 V to 5.5 V. DD 19 V D Channel D Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V D pin. Output is OUT REF open circuit when SHDN is enabled. 20 V C Channel C Rail-to-Rail Buffered DAC Voltage Output. Full-scale set by reference voltage applied to V C pin. Output is OUT REF open circuit when SHDN is enabled. Rev. C | Page 9 of 20

AD7304/AD7305 TYPICAL PERFORMANCE CHARACTERISTICS 144 1.0 VDD = +5V 120 VVSRSE F= =– V5VDD 0.6 DATA = 0x00 mA) DAC D T ( 96 CURREN 72 L (LSB) 0.2 K N N I –0.2 DAC C I SIOUT 48 VVDSSD == –+55VV DAC B DAC A –0.6 DATA = 0x80 240 01114-010 –1.0 TA = +25°C 01114-013 0 3 6 9 12 15 –5.0 –3.0 –1.0 1.0 3.0 5.0 VOUT (mV) REFERENCE INPUT VOLTAGE (V) Figure 10. IOUT Sink vs. VOUT Rail-to-Rail Performance Figure 13. INL vs. Reference Input Voltage –35 0.500 mA) –28 VVVDDSRASDET F A== = –+= V55 0VDVxDFF 00..327550 VVVDSRSDE F == = –+ 5+5V2V.5V T ( N E CURRE –21 L (LSB) 0.1205 C N R –14 D U –0.125 O S UT –0.250 O I –7 0 01114-011 ––00..530705 01114-014 4.0 4.2 4.4 4.6 4.8 5.0 0 32 64 96 128 160 192 224 256 VOUT OUTPUT VOLTAGE (V) CODE (Decimal) Figure 11. IOUT SOURCE vs. VOUT Rail-to-Rail Performance Figure 14. DNL vs. Code +1 4.0 0 VDD = 5.5V DAC A VSS = 0V –1 3.6 VREF = 5.45V V) +1 m E ( 0 G SB) –1 DAC B OLTA 3.2 L (L +1 E V N L I A 2.8 –01 DAC C VVDSSD == –+55VV RO-SC +1 VTAR E=F +=2 +5°2C.5V ZE 2.4 –01 DAC D 01114-012 2.0 01114-015 0 32 64 96 128 160 192 224 256 –55 –35 –15 5 25 45 65 85 105 125 CODE (Decimal) TEMPERATURE (°C) Figure 12. INL vs. Code, All DAC Channels Figure 15. Zero-Scale Voltage vs. Temperature Rev. C | Page 10 of 20

AD7304/AD7305 CS VOUT VVDDRADETF A= = 5= 4V 0Vx00 0xFF NORL L =O 7A0DkΩ VCDL D= =1 550VpF RL = 10kΩ 0V 5V VOUT CS 0V 01114-016 01114-019 2µs/DIV 5µs/DIV Figure 16. Large-Signal Settling Time Figure 19. Time to Shutdown CS +5V (V±R5VEF @IN DATA = 0xFF 0V IDD 1mA/V 50kHz) –5V +5V VOUTA 0V VDD = 5V VOUT –5V 01114-017 01114-020 2µs/DIV Figure 17. Multiplying Mode Step Response and Output Slew Rate Figure 20. Shutdown Recovery Time (Wakeup) 6 10 VDD = +5V VDSAST A= –=5 0VxFF VDD = +5V 4 VREF = 100mV rms VSS =–5V 1 dB) 0 %) N ( D ( 0.1 GAI f–3dB = 2.6MHz TH –4 0.01 –6 –8 01114-018 0.001 01114-021 10k 100k 1M 10M 10m 1 2 3 4 5 6 7 8 9 10 FREQUENCY (Hz) VREF AMPLITUDE (V p-p) Figure 18. Multiplying Mode Gain vs. Frequency Figure 21. THD vs. Reference Input Amplitude Rev. C | Page 11 of 20

AD7304/AD7305 1 VDD = +5V VSS =–5V VDD = +5V VSS =–5V 0.1 VOUT VF R=E 1FM =H +z2.5V DATA = 0x80 0x7F %) D ( H T 0.01 CS 0.001 01114-022 01114-025 20 100 1k 10k 100k FREQUENCY (Hz) Figure 22. THD vs. Frequency Figure 25. Midscale Transition Glitch 3.0 40 VDD = +5V 20 VDD = +5V VSS =–5V VSS =–5V 2.4 VREF = +4V 0 VREF = 50mV rms DATA = 0xFF DAC A DATA = 0xFF Hz) –20 DAC B, DAC C, DAC D DATA = 0x00 SITY (V/ µ 1.8 TALK (dB) ––4600 E DEN 1.2 ROSS –80 S C OI –100 N VOUTB CT = 20 LOG 0.6 –120 VREF 0 01114-023 ––116400 01114-026 1 10 100 1k 10k 100k 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 23. Output Noise Voltage Density vs. Frequency Figure 26. Crosstalk vs. Frequency 60 –PSRR, VSS =–5V±∆10% 50 +PSRR, VDD = +5V±∆10% 40 VOUTB B) –PSRR, VSS =–3V±∆10% VVVDSRSDE F == = –+ +55V2V.5V SRR (d 30 +PSRR, VDD = +3V±∆10% DAC A = 0xFF P DAC B = 0x00 20 F = 2MHz CLK 10 DATA = 0x80 01114-024 0 TA = +25°C 01114-027 50ns/DIV 10 100 1k 10k 100k 50ns/DIV FREQUENCY (Hz) Figure 27. Power-Supply Rejection vs. Frequency Figure 24. Digital Feedthrough Rev. C | Page 12 of 20

AD7304/AD7305 12 80 VDD = +5V VDD = +5.5V 10 VVSRSE F= =– +5V2.5V 70 VVSRSE F= =– +5.25.V5V A0 = +5V PIN A0 FLOATING T (mA) 8 APILNLS O VTAHREYRIN DGIGITAL LY (A)µ 60 N P E P R U SUPPLY CUR 64 IDD SHUTDOWN S 5400 ISS 2 30 0 01114-028 20 01114-031 0 1 2 3 4 5 –55 –35 –15 5 25 45 65 85 105 125 DIGITAL INPUT VOLTAGE (V) TEMPERATURE (°C) Figure 28. Supply Current vs. Digital Input Voltage Figure 31. Shutdown Supply Current vs. Temperature 10 0.08 READING MADE AT TA = +25°C D SAMPLE SIZE = 924 UNITS E 1 T SUPPLY CURRENT (mA) 00.0.11 IDD VVVAEDSRXLSDELC F E==D =P –I+ GT+55I V2VTA.5A0V L= P+I5NVS VARY, MALIZED TOTAL UNADJUSERROR DRIFT (LSB)–00..00440 VDDV D=D + =5 .+52V.7V 0.001 ISS OR N 0.0001 01114-029 –0.08 01114-032 0 1 2 3 4 5 0 84 168 252 336 420 504 DIGITAL INPUT VOLTAGE (V) TEMPERATURE (°C) Figure 29. Shutdown Supply Current vs. Digital Input Voltage (A0 Only) Figure 32. Normalized TUE Drift Accelerated by Burn-In Hours of Operation @ 150°C 5.0 VDD = +5V VSS =–5V 4.4 VREF = +2.5V A) m NT ( 3.8 IDD AND ISS E R R U C LY 3.2 P P U S 2.6 2.0 01114-030 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 30. Supply Current vs. Temperature Rev. C | Page 13 of 20

AD7304/AD7305 CIRCUIT OPERATION The AD7304/AD7305 are 4-channel, 8-bit, voltage output These DACs are also designed to accommodate ac reference DACs, differing primarily in digital logic interface and number input signals. As long as the ac signals are maintained between of reference inputs. Both parts share the same internal DAC V < V < V , the user can expect 50 kHz of full power, SS REF DD design and true rail-to-rail output buffers. The AD7304 contains multiplying bandwidth performance. In order to use negative four independent multiplying reference inputs, while the input reference voltages, the V pin must be biased with a SS AD7305 has one common reference input. The AD7304 uses a negative voltage of equal or greater magnitude than the 3-wire SPI-compatible serial data interface, while the AD7305 reference voltage. offers an 8-bit parallel data interface. The reference inputs are code dependent, exhibiting worst-case DAC SECTION minimum resistance values specified in the parametric specifi- cation table. The DAC outputs V A, V B, V C, and V D Each part contains four voltage-switched R-2R ladder DACs. OUT OUT OUT OUT are each capable of driving 2 kΩ loads in parallel with up to 500 pF Figure 33 shows a typical equivalent DAC. These DACs are loads. Output sink current and source current are shown in designed to operate both single-supply or dual-supply, Figure 10 and Figure 11, respectively. The output slew rate is depending on whether the user supplies a negative voltage on nominally 3.6 V/µs while operating from ±5 V supplies. The the V pin. In a single-supply application, the V is tied to SS SS low output impedance of the buffers minimizes crosstalk ground. In either mode, the DAC output voltage is determined between analog input channels. At 100 kHz, 65 dB of channel- by the V input voltage and the digital data (D) loaded into REF to-channel isolation exists (Figure 26). Output voltage noise is the corresponding DAC register according to Equation 1. plotted in Figure 23. In order to maintain good analog perform- VOUT = VREF D/256 (1) ance, power supply bypassing of 0.01 µF in parallel with 1 µF is recommended. The true rail-to-rail capability of the AD7304/AD7305 Note that the output full-scale polarity is the same as the V REF allows the user to connect the reference inputs directly to the polarity for dc reference voltages. same supply as the V or V pin (Figure 34). Under these DD SS VDD conditions, clean power supply voltages (low ripple, avoid switching supplies) appropriate for the application should be VREF DB72R VOUT used. DB62R R VSS VDD Q1 DB0 VOUTX 2R 120kΩ Q2 2R 01114-033 VSS 01114-034 Figure 33. Typical Equivalent DAC Channel Figure 34. Equivalent DAC Amplifier Output Circuit Rev. C | Page 14 of 20

AD7304/AD7305 AD7304 SERIAL DATA INTERFACE The AD7304 uses a 3-wire (CS, SDI, CLK) SPI-compatible VREFA VREFB VREFC VREFD VDD serial data interface. New serial data is clocked into the serial CS EN AD7304 input register in a 12-bit data-word format. MSB bits are loaded CLK first. SDI DD01 REINGPISUTTERR REDGAICST AERR DACO AE VOUTA D2 Table 5 defines the 12 data-word bits. Data is placed on the D3 8 D4 DQ SDI/SHDN pin and clocked into the register on the positive D5 clock edge of CLK subject to the data setup and data hold time DD67 DAC BA REINGPISUTTERR REDGAICST BERR DACO BE VOUTB requirements specified in the Timing Specifications section. A0 2:4 C A1 DECODED DQ Data can only be clocked in while the CS chip select pin is SDC active low. Only the last 12-bits clocked into the serial register SAC VDD REINGPISUTTERR REDGAICST CERR DACO CE VOUTC are interrogated when the CS pin returns to the logic high state, 640kΩ 680kΩ DQ extra data bits are ignored. Since most microcontrollers output serial data in 8-bit bytes, two right-justified data bytes can be REINGPISUTTERR REDGAICST DERR DACO DE VOUTD written to the AD7304. Keeping the CS line low between the 80kΩ DQ first and second byte transfer results in a successful serial POWER- register update. 280kΩ 320kΩ ON RESET Oponscitei vthe ee ddgaeta o ifs tphreo CpeSr ilny iatilaigtense edi tihne trh teh seh tirfat nresfgeirs toefr ,n tehwe data GND LDAC CLR VSS 01114-035 Figure 35. AD7304 Equivalent Logic Interface to the target DAC register, determined by the decoding of AD7304 HARDWARE SHUTDOWN SHDN Address Bits A1 and A0, or the shutdown features is activated based on the SAC or SDC bits. When either SAC or SDC pins If a three-state driver is used on the SDI/SHDN pin, the are set (Logic 0), the loading of new data determined by Bits B9 AD7304 can be placed into a power shutdown mode when the to B0 are still loaded, but the results do not appear on the buffer SDI/ SHDN pin is placed in a high impedance state. For proper outputs until the device is brought out of the shutdown state. operation, no other termination voltages should be present on The selected DAC output voltages become high impedance with this pin. An internal window comparator detects when the logic a nominal resistance of 120 kΩ to ground, see Figure 34. If voltage on the SHDN pin is between 28% and 36% of VDD. A both the SAC and SDC pins are set, all channels are still placed high impedance internal bias generator provides this voltage on in shutdown mode. When the AD7304 has been programmed the SHDN pin. The four DAC output voltages become high into the power shutdown state, the present DAC register data is impedance with a nominal resistance of 120 kΩ to ground (see maintained as long as V remains greater than 2.7 V. The Figure 34 for an equivalent circuit). DD remaining characteristics of the software serial interface are AD7304/AD7305 POWER-ON RESET defined by Table 4, Table 5, and Figure 5. When the V power supply is turned on, an internal reset DD Two additional pins, CLR and LDAC, on the AD7304 provide strobe forces all the input and DAC registers to the zero-code hardware control over the clear function and the DAC register state. The V power supply should have a monotonically DD loading. If these functions are not needed, the CLR pin can be increasing ramp in order to have consistent results, especially in tied to logic high, and the LDAC pin can be tied to logic low. the region of VDD = 1.5 V to 2.3 V. The VSS supply has no effect The asynchronous input CLR pin forces all input and DAC on the power-on reset performance. The DAC register data registers to the zero-code state. The asynchronous LDAC pin stays at zero until a valid serial register software load takes place. In the case of the double-buffered AD7305, the output can be strobed to active low when all DAC registers need to be updated simultaneously from their respective input registers. DAC register can only be changed once the LDAC strobe is initiated. The LDAC pin places the DAC register in a transparent mode POWER-UP SEQUENCE while in the logic low state. It is recommended to power V /V first before applying any DD SS voltage to the reference terminals to avoid potential latch up. The ideal power-up sequence is in the following order: GND, V , V , Digital Inputs, and V . The order of powering DD SS REFx digital inputs and reference inputs is not important as long as they are powered after V /V . DD SS Rev. C | Page 15 of 20

AD7304/AD7305 AD7305 PARALLEL DATA INTERFACE LDAC is tied to Logic Low, the DAC registers become The AD7305 has an 8-bit parallel interface DB7 = MSB, DB0 = LSB. Two address bits, A1 and A0, are decoded when an active transparent and the input register data determines the DAC low write strobe is placed on the WR pin, see Table 6. The WR output voltage (see Figure 36 for an equivalent interface logic diagram). is a level-sensitive input pin, therefore, the data setup and data hold times defined in the Timing Specifications section need to AD7226 PIN COMPATIBILITY be adhered to. By tying the LDAC pin to ground, the AD7305 has the same pin VREF VDD configuration and functionality as the AD7226, with the exception of a lower power supply operating voltage. DATA 8 AD7305 DB0–DB7 AD7305 HARDWARE SHUTDOWN SHDN WR REINGPISUTTERR REDGAICST AERR DACO AE VOUTA If a three-state driver is used on the A0/SHDN pin, the AD7305 can be placed into a power shutdown mode when the A0/SHDN pin is placed in a high impedance state. For proper operation, DAC A A1 B REINGPISUTTERR REDGAICST BERR DACO BE VOUTB no other termination voltages should be present on this pin. An 2:4 C internal window comparator detects when the logic voltage on A0/SHDN DECODED the SHDN pin is between 28% and 36% of V . A high imped- DD VDD REINGPISUTTERR REDGAICST CERR DACO CE VOUTC apninc.e T, ihnet efronuarl -DbAiaCs goeuntepruatt ovro lptraogveisd beesc tohmis ev holitgahg eim opne tdhaen ScHe DN with a nominal resistance of 120 kΩ to ground. 640kΩ 680kΩ REINGPISUTTERR REDGAICST DERR DACO DE VOUTD ESD PROTECTION CIRCUITS 80kΩ All logic input pins contain back-biased ESD protection Zeners POWER- 280kΩ 320kΩ REOSNET connected to ground (GND). The VREF pins also contain a back- biased ESD protection Zener connected to V (see Figure 37). DD GND LDAC VSS 01114-036 DIGITAL Figure 36. AD7305 Equivalent Logic Interface INPUTS VDD Turephgdeis aLtteiDnrsAg a Catl ltp hDienA spCarmo rveeig dtiiesmtse etr.hs T ew hciaitshp r anebseiuwliltt yds aointfa s tfhirmeo umalnt taahnloeeg oi nuopusultypt uts all GND VREFX 01114-037 Figure 37. Equivalent ESD Protection Circuits changing to their new values at the same time. The LDAC pin is a level-sensitive input. If the simultaneous update feature is not required, the LDAC pin can be tied to logic low. When the Rev. C | Page 16 of 20

AD7304/AD7305 APPLICATIONS The AD7304/AD7305 are inherently 2-quadrant multiplying the input data (D) is incremented from code zero (V = –5 V) OUT DACs. That is, they can easily be set up for unipolar output to midscale (V = 0 V) to full scale (V = +5 V). OUT OUT operation. The full-scale output polarity is the same as the D reference input voltage polarity. V = ×V (2) OUT 128−1 REF In some applications, it may be necessary to generate the full 4-quadrant multiplying capability or a bipolar output swing. +5V This is easily accomplished using an external true rail-to-rail op 10kΩ 10kΩ amp, such as the OP295. Connecting the external amplifier with two equal value resistors, as shown in Figure 38, results in a full 2.2pF 4p-rqouviaddersa na tg mainu lotifp tlwyion,g w chiriccuhi tin. Icnre tahsiess c tihrceu oitu, ttphuet asmpapnli fier REF AD7304 –5V< VOUT< +5V 01114-038 magnitude to 10 V. The transfer equation of this circuit shows Figure 38. 4-Quadrant Multiplying Application Circuit that both negative and positive output voltages are created as Rev. C | Page 17 of 20

AD7304/AD7305 OUTLINE DIMENSIONS 10.50 (0.4134) 5.10 10.10 (0.3976) 5.00 4.90 16 9 7.60 (0.2992) 16 9 7.40 (0.2913) 10.65 (0.4193) 4.50 6.40 1 8 10.00 (0.3937) 4.40 BSC 4.30 1 8 1.27 (0.0500) BSC 2.65 (0.1043) 0.75 (0.0295)× 45° PIN 1 2.35 (0.0925) 0.25 (0.0098) 0.30 (0.0118) 1.20 MAX 0.10 (0.0039) 0.15 0.20 8° 0.05 0.09 0.75 COPL0A.1N0ARITY 00..5311 ((00..00210212)) SPELAANTIENG 00..3230 ((00..00103709)) 0° 10..2470 ((00..00510507)) 0.65 00..3109 SEATING 80°° 00..6405 BSC PLANE COMPLIANT TO JEDEC STANDARDS MS-013AA COPLANARITY CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS 0.10 (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR COMPLIANT TO JEDEC STANDARDS MO-153AB REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 39. 16-Lead Standard Small Outline Package [SOIC] Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP] Wide Body (R-16) (RU-16) Dimensions shown in millimeters and (inches) Dimensions shown in millimeters 13.00 (0.5118) 6.60 12.60 (0.4961) 6.50 6.40 20 11 7.60 (0.2992) 20 11 7.40 (0.2913) 4.50 10.65 (0.4193) 1 10 10.00 (0.3937) 44..4300 6.40 BSC 1 10 2.65 (0.1043) 0.75 (0.0295) 0.30 (0.0118) 2.35 (0.0925) 0.25 (0.0098)× 45° PIN 1 0.65 0.10 (0.0039) BSC 8° 0.15 1.20 MAX 0.20 COPL0A.1N0ARITY (0B1.0.S25C700) 00..5311 ((00..00210212)) SPELAANTIENG 00..3230 ((00..00103709)) 0° 10..2470 ((00..00510507)) 0.05 0.30 0.09 8° 00..7650 COPLANARITY 0.19 SEATING 0° 0.45 COMPLIANT TO JEDEC STANDARDS MS-013AC 0.10 PLANE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR COMPLIANT TO JEDEC STANDARDS MO-153AC REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 42. 20-Lead Thin Shrink Small Outline Package [TSSOP] Figure 40. 20-Lead Standard Small Outline Package [SOIC] (RU-20) Wide Body (R-20) Dimensions shown in millimeters Dimensions shown in millimeters and (inches) Rev. C | Page 18 of 20

AD7304/AD7305 ORDERING GUIDE Model Temperature Range Package Description Package Options AD7304BR –40°C to +85°C 16-Lead SOIC R-16 AD7304BR-REEL –40°C to +85°C 16-Lead SOIC R-16 AD7304BRZ1 –40°C to +85°C 16-Lead SOIC R-16 AD7304BRZ-REEL1 –40°C to +85°C 16-Lead SOIC R-16 AD7304YR –40°C to +125°C 16-Lead SOIC R-16 AD7304YRZ1 –40°C to +125°C 16-Lead SOIC R-16 AD7304BRU –40°C to +85°C 16-Lead TSSOP RU-16 AD7304BRU-REEL7 –40°C to +85°C 16-Lead TSSOP RU-16 AD7305BR –40°C to +85°C 20-Lead SOIC R-20 AD7305BR-REEL –40°C to +85°C 20-Lead SOIC R-20 AD7305YR –40°C to +125°C 20-Lead SOIC R-20 AD7305YR-REEL –40°C to +125°C 20-Lead SOIC R-20 AD7305BRU –40°C to +85°C 20-Lead TSSOP RU-20 AD7305BRU-REEL7 –40°C to +85°C 20-Lead TSSOP RU-20 AD7305BRUZ1 –40°C to +85°C 20-Lead TSSOP RU-20 AD7305BRUZ-REEL71 –40°C to +85°C 20-Lead TSSOP RU-20 1 Z = Pb-free part. Rev. C | Page 19 of 20

AD7304/AD7305 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. Printed in the U.S.A. C01114-0-11/04(C) Rev. C | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7304BRU-REEL7 AD7305BRUZ AD7305BRZ-REEL AD7305BR-REEL AD7305BRU-REEL7 AD7304BRZ AD7305YRZ AD7305BRUZ-REEL7 AD7304BRUZ-REEL7 AD7305BRZ AD7304BRUZ AD7304BRZ-REEL AD7304YRZ AD7305YRZ-REEL AD7305BRU AD7304BRU AD7305BR