8-Channel, 1 MSPS, 10-Bit SAR ADC AD7298-1 FEATURES FUNCTIONAL BLOCK DIAGRAM 10-bit SAR ADC VDD GND 8 single-ended inputs Channel sequencer functionality VREF Fast throughput of 1 MSPS REF BUF Analog input range: 0 V to 2.5 V Temperature range: −40°C to +125°C 10-BIT VIN0 SUCCESSIVE Specified for VDD of 2.8 V to 3.6 V T/H APPROXIMATION Logic voltage V = 1.65 V to 3.6 V ADC DRIVE Power-down current: <10 µA INPUT VIN7 MUX AD7298-1 Internal 2.5 V reference Internal power-on reset SEQUENCER SCLK High speed serial interface SPI DOUT CONTROL DIN 20-lead LFCSP LOGIC CS PD/RST VDRIVE 09321-001 Figure 1. GENERAL DESCRIPTION The AD7298-1 is a 10-bit, high speed, low power, 8-channel, PRODUCT HIGHLIGHTS successive approximation ADC. The part operates from a single 1. Ideally Suited to Monitoring System Variables in a Variety 3.3 V power supply and features throughput rates up to 1 MSPS. of Systems. This includes telecommunications, and process The device contains a low noise, wide bandwidth track-and-hold and industrial control. amplifier that can handle input frequencies in excess of 30 MHz. 2. High Throughput Rate of 1 MSPS with Low Power The AD7298-1 offers a programmable sequencer, which enables Consumption. the selection of a preprogrammable sequence of channels for 3. Eight Single-Ended Inputs with a Channel Sequencer. A conversion. The device has an on-chip, 2.5 V reference that can consecutive sequence of channels can be selected on which be disabled to allow the use of an external reference. the ADC cycles and converts. The device offers a 4-wire serial interface compatible with SPI and DSP interface standards. The AD7298-1 uses advanced design techniques to achieve very low power dissipation at high throughput rates. The part also offers flexible power/throughput rate management options. The part is offered in a 20-lead LFCSP package. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved.

AD7298-1 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input ............................................................................... 13 Functional Block Diagram .............................................................. 1 V ............................................................................................ 14 DRIVE General Description ......................................................................... 1 The Internal or External Reference .......................................... 14 Product Highlights ........................................................................... 1 Control Register .............................................................................. 15 Revision History ............................................................................... 2 Modes of Operation ....................................................................... 16 Specifications ..................................................................................... 3 Traditional Multichannel Mode of Operation ........................ 16 Timing Specifications .................................................................. 5 Repeat Operation ....................................................................... 17 Absolute Maximum Ratings ............................................................ 6 Power-Down Modes .................................................................. 18 Thermal Resistance ...................................................................... 6 Powering Up the AD7298-1 ...................................................... 19 ESD Caution .................................................................................. 6 Reset ............................................................................................. 19 Pin Configuration and Function Description .............................. 7 Serial Interface ................................................................................ 20 Typical Performance Characteristics ............................................. 9 Layout and Configuration ............................................................. 21 Terminology .................................................................................... 12 Outline Dimensions ....................................................................... 22 Circuit Information ........................................................................ 13 Ordering Guide .......................................................................... 22 Converter Operation .................................................................. 13 REVISION HISTORY 1/11—Rev. 0 to Rev. A Removed Input Impedance Parameter .......................................... 3 Added Input Capacitance Parameter of 8 pF ................................ 3 Changes to Figure 10 ...................................................................... 10 Changed C1 Value to 8 pF in Analog Input Section .................. 13 Changes to Figure 22 ...................................................................... 14 10/10—Revision 0: Initial Version Rev. A | Page 2 of 24

AD7298-1 SPECIFICATIONS V = 2.8 V to 3.6 V, V = 1.65 V to 3.6 V, f = 1 MSPS, f = 20 MHz, V = 2.5 V internal, T = −40°C to +125°C, unless DD DRIVE SAMPLE SCLK REF A otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 50 kHz sine wave IN Signal-to-Noise Ratio (SNR)1 61 61.5 dB Signal-to-Noise-(and-Distortion) Ratio (SINAD)2 61 61.5 dB Total Harmonic Distortion (THD)2 −82 −75 dB Spurious-Free Dynamic Range (SFDR) −83 −76 dB Intermodulation Distortion (IMD) f = 40.1 kHz, f = 41.5 kHz A B Second-Order Terms −86 dB Third-Order Terms −86 dB Channel-to-Channel Isolation −90 dB f = 50 kHz, f = 60 kHz IN NOISE SAMPLE AND HOLD Aperture Delay3 12 ns Aperture Jitter3 40 ps Full Power Bandwidth 30 MHz At 3 dB 10 MHz At 0.1 dB DC ACCURACY Resolution 10 Bits Integral Nonlinearity (INL)2 ±0.25 ±0.5 LSB Differential Nonlinearity (DNL)2 ±0.3 ±0.5 LSB Guaranteed no missed codes to 10 bits Offset Error2 ±0.5 ±1.125 LSB Offset Error Matching2 ±0.625 ±1.125 LSB Offset Temperature Drift 4 ppm/°C Gain Error2 ±0.25 ±1 LSB Gain Error Matching2 ±0.16 ±0.625 LSB Gain Temperature Drift 0.5 ppm/°C ANALOG INPUT Input Voltage Ranges 0 V V REF DC Leakage Current ±0.01 ±1 μA Input Capacitance 32 pF When in track mode 8 pF When in hold mode REFERENCE INPUT/OUTPUT Reference Output Voltage4 2.4925 2.5 2.5075 V ±0.3% maximum at 25°C Long-Term Stability 150 ppm For 1000 hours Output Voltage Hysteresis 50 ppm Reference Input Voltage Range 1 2.5 V DC Leakage Current ±0.01 ±1 μA External reference applied to the V pin REF V Output Impedance 1 Ω REF V Temperature Coefficient 12 35 ppm/°C REF V Noise 60 μV rms Bandwidth = 10 MHz REF LOGIC INPUTS Input High Voltage, V 0.7 × V V INH DRIVE Input Low Voltage, V 0.3 × V V INL DRIVE Input Current, I ±0.01 ±1 μA V = 0 V or V IN IN DRIVE Input Capacitance, C 3 3 pF IN Rev. A | Page 3 of 24

AD7298-1 Parameter Min Typ Max Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, V V − 0.3 V V < 1.8 OH DRIVE DRIVE V − 0.2 V V ≥ 1.8 DRIVE DRIVE Output Low Voltage, V 0.4 V OL Floating State Leakage Current ±0.01 ±1 μA Floating State Output Capacitance3 8 pF CONVERSION RATE Conversion Time 1 t + (16 × t ) μs For V to V with one cycle latency 2 SCLK IN0 IN7 Track-and-Hold Acquisition Time2, 3 100 ns Full-scale step input Throughput Rate 1 MSPS f = 20 MHz; for analog voltage SCLK conversions, one cycle latency POWER REQUIREMENTS Digital inputs = 0 V or V DRIVE V 2.8 3 3.6 V DD V 1.65 3 3.6 V DRIVE I 5 V = 3.6 V, V = 3.6 V TOTAL DD DRIVE Normal Mode (Operational) 5.8 6.4 mA Normal Mode (Static) 4.1 4.6 mA Partial Power-Down Mode 2.7 3.3 mA Full Power-Down Mode 1 1.6 μA T = −40°C to +25°C A 10 μA T = −40°C to +125°C A Power Dissipation6 Normal Mode (Operational) 17.4 19.2 mW V = 3 V, V = 3 V DD DRIVE 23 mW Normal Mode (Static) 14.8 16.6 mW Partial Power-Down Mode 9.8 11.9 mW Full Power-Down Mode 3.6 5.8 μW T = −40°C to +25°C A 36 μW T = −40°C to +125°C A 1 All specifications expressed in decibels are referred to full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 2 See the Terminology section. 3 Sample tested during initial release to ensure compliance. 4 Refers to the VREF pin specified for 25°C. 5 ITOTAL is the total current flowing in VDD and VDRIVE. 6 Power dissipation is specified with VDD = VDRIVE = 3.6 V, unless otherwise noted. Rev. A | Page 4 of 24

AD7298-1 TIMING SPECIFICATIONS V = 2.8 V to 3.6 V, V = 1.65 V to 3.6 V, V = 2.5 V internal, T = −40°C to +125°C, unless otherwise noted. Sample tested during DD DRIVE REF A initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level DRIVE of 1.6 V. Table 2. Parameter Limit at T , T Unit Test Conditions/Comments MIN MAX t t + (16 × t ) µs max Conversion time CONVERT 2 SCLK 820 ns typ Each ADC channel V to V , f = 20 MHz IN0 IN7 SCLK f 1 50 kHz min Frequency of external serial clock SCLK 20 MHz max Frequency of external serial clock t 6 ns min Minimum quiet time required between the end of the serial read and the start of QUIET the next voltage conversion in repeat and nonrepeat mode. t 10 ns min CS to SCLK setup time 2 t1 15 ns max Delay from CS (falling edge) until DOUT three-state disabled 3 t1 Data access time after SCLK falling edge 4 35 ns max V = 1.65 V to 3 V DRIVE 28 ns max V = 3 V to 3.6 V DRIVE t 0.4 × t ns min SCLK low pulse width 5 SCLK t 0.4 × t ns min SCLK high pulse width 6 SCLK t1 14 ns min SCLK to DOUT valid hold time 7 t1 16/34 ns min/ns max SCLK falling edge to DOUT high impedance 8 t 5 ns min DIN setup time prior to SCLK falling edge 9 t 4 ns min DIN hold time after SCLK falling edge 10 t 1 30 ns max Delay from CS rising edge to DOUT high impedance 11 t 6 ms max Internal reference power-up time from full power-down POWER-UP 1 Measured with a load capacitance on DOUT of 15 pF. Rev. A | Page 5 of 24

AD7298-1 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Table 4. Thermal Resistance Parameter Rating Package Type θ θ Unit JA JC V to GND, GND1 −0.3 V to +5 V 20-Lead LFCSP 52 6.5 °C/W DD V to GND, GND1 −0.3 V to + 5 V DRIVE Analog Input Voltage to GND1 −0.3 V to +3 V ESD CAUTION Digital Input Voltage to GND −0.3 V to V + 0.3 V DRIVE Digital Output Voltage to GND −0.3 V to V + 0.3 V DRIVE V to GND1 −0.3 V to +3 V REF AGND to GND −0.3 V to +0.3 V Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Pb-free Temperature, Soldering Reflow 260(0)°C ESD 3.5 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 6 of 24

AD7298-1 PIN CONFIGURATION AND FUNCTION DESCRIPTION V2NI V1NI V0NI TSR/DP VEVRID 02 91 81 71 61 VIN3 1 15 SCLK VIN4 2 AD7298-1 14 DOUT VIN5 3 TOP VIEW 13DIN VIN6 4 (Not to Scale) 12 NC VIN7 5 11 CS 6 7 8 9 01 1DNG VFER DPAC DNG VDD NOTES 1. NC = NO CONNECT. 2.THE EXPOSED METAL PADDLE ON THE BOTTOM AOTONFD TP HHCEEB A LGTFR CDOSISUPSN PIDPA AFCTOKIROA NGP.ER OSPHEORU LFDU NBCET SIOONLADLEIRTYED 09321-003 Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 to 5, V , V Analog Inputs. The AD7298-1 has eight single-ended analog inputs that are multiplexed into the on-chip track- IN3 IN4 18 to 20 V , V , and-hold. Each input channel can accept analog inputs from 0 V to 2.5 V. Any unused input channels should be IN5 IN6 V , V , connected to GND1 to avoid noise pickup. IN7 IN0 V , V IN1 IN2 6 GND1 Ground. Ground reference point for the internal reference circuitry on the AD7298-1. The external reference signals and all analog input signals should be referred to the GND1 voltage. The GND1 pin should be connected to the ground plane of a system. All ground pins should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. The V pin should be decoupled to this ground pin via a 10 µF REF decoupling capacitor. 7 V Internal Reference/External Reference Supply. The nominal internal reference voltage of 2.5 V appears at this pin. REF Provided the output is buffered, the on-chip reference can be taken from this pin and applied externally to the rest of a system. Decoupling capacitors should be connected to this pin to decouple the reference buffer. For best performance, it is recommended to use a 10 µF decoupling capacitor on this pin to GND1. The internal reference can be disabled and an external reference supplied to this pin, if required. The input voltage range for the external reference is 2.0 V to 2.5 V. 8 D Decoupling Capacitor Pins. Decoupling capacitors (1 µF recommended) are connected to this pin to decouple CAP the internal LDO. 9 GND Ground. Ground reference point for all analog and digital circuitry on the AD7298-1. The GND pin should be connected to the ground plane of the system. All ground pins should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Both the D and V pins should be decoupled to this CAP DD GND pin. 10 V Supply Voltage, 2.8 V to 3.6 V. This supply should be decoupled to GND with 10 µF and 100 nF decoupling capacitors. DD 11 CS Chip Select, Active Low Logic Input. This pin is edge triggered on the falling edge of this input, the track-and- hold goes into hold mode, and a conversion is initiated. This input also frames the serial data transfer. When CS is low, the output bus is enabled and the conversion result becomes available on the DOUT output. 12 NC No Connect. 13 D Data In, Logic Input. Data to be written to the AD7298-1 control register is provided on this input and is clocked IN into the register on the falling edge of SCLK. 14 DOUT Serial Data Output. The conversion result from the AD7298-1 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7298-1 consists of four address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of conversion data (MSB first). 15 SCLK Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7298-1. Rev. A | Page 7 of 24

AD7298-1 Pin No. Mnemonic Description 16 V Logic Power Supply Input. The voltage supplied at this pin determines the voltage at which the interface DRIVE operates. This pin should be decoupled to ground. The voltage range on this pin is 1.65 V to 3.6 V and may be less than the voltage at V but should never exceed it by more than 0.3 V. DD 17 PD/RST Power-Down Pin. This pin places the part into full power-down mode and enables power conservation when operation is not required. This pin can be used to reset the device by toggling the pin low for a minimum of 1 ns and a maximum of 100 ns. If the maximum time is exceeded, the part enters power-down mode. When placing the AD7298-1 into full power-down mode, the analog inputs must return to 0 V. EPAD The exposed metal paddle on the bottom of the LFCSP package should be soldered to PCB ground for proper functionality and heat dissipation. Rev. A | Page 8 of 24

AD7298-1 TYPICAL PERFORMANCE CHARACTERISTICS 0 0.50 VDD = VDRIVE = 3V –10 fSAMPLE = 1.17647MHz 0.40 fIN = 50kHz –20 fSCLK = 20MHz 0.30 SNR = 61.83dB B) –30 THD = –80.23dB 0.20 INL (Positive) d ER ( –40 B)0.10 W –50 S L PO –60 NL (L 0 INL (Negative) A I–0.10 GN –70 SI –0.20 –80 –0.30 –90 –100 –0.40 –1100 100 200FREQUE3N0C0Y (MHz4)00 500 600 09321-047 –0.501.0 1.2 1.4 1.6 VRE1F.8 (V) 2.0 2.2 2.4 2.6 09321-038 Figure 3. Typical FFT Figure 6. INL vs. V REF 1.0 0.50 VDD = 3V 0.8 VDRIVE = 3V 0.40 0.6 0.30 INL (Positive) 0.4 0.20 B) 0.2 B) 0.10 S S NL (L 0 NL (L 0 I 0.2 D–0.10 INL (Negative) 0.4 –0.20 –0.6 –0.30 –0.8 –0.40 –1.01 101 201 301 401 C5O01DE601 701 801 901 1001 09321-040 –0.501.0 1.2 1.4 1.6 VRE1F.8 (V) 2.0 2.2 2.4 2.6 09321-039 Figure 4. Typical ADC INL Figure 7. DNL vs. V REF 1.0 11 VDD = 3V 0.8 VDRIVE = 3V 10 0.6 S 9 T 0.4 BI B) OF 8 L (LS 0.2 BER 7 N 0 M D U N 6 0.2 E V TI 5 –0.4 C E F –0.6 EF 4 –0.8 3 VDD = 3V VDRIVE = 3V –1.01 101 201 301 401 C5O01DE601 701 801 901 1001 09321-041 20 0E.5XTERNAL 1V.O0LTAGE RE1F.5ERENCE (V2).0 2.5 09321-042 Figure 5. Typical ADC DNL Figure 8. Effective Number of Bits vs. V REF Rev. A | Page 9 of 24

AD7298-1 3.0 62.0 VDD = VDRIVE = 3V VDD = 3V VDRIVE = 3V 61.5 2.5 61.0 60.5 V) dB) V (REF 2.0 SINAD (60.0 59.5 1.5 59.0 RSOURCE = 0Ω RSOURCE = 10Ω RSOURCE = 33Ω 58.5 RSOURCE = 47Ω RSOURCE = 100Ω RSOURCE = 200Ω 1.00 0.5 1.0 1C.5URRE2.N0T LO2A.5D (mA3.)0 3.5 4.0 4.5 09321-109 58.010 INPUT FREQUEN1C0Y0 (kHz) 09321-046 Figure 9. V vs. Reference Output Current Drive Figure 12. SINAD vs. Analog Input Frequency for Various Source Impedances REF –90 62.00 VDD=3V VDD = 3V –92 VDRIVE=3V VDRIVE = 3V 61.75 –94 –96 61.50 PSRR(dB)––11–009208 SINAD (dB)61.25 61.00 –104 –106 60.75 –108 –1101k 10k RIPP1L0E0kFREQUEN1CMY(Hz) 10M 100M 09321-110 60.501.0 EXTERN1A.5L REFERENCE VOL2T.0AGE (V) 2.5 09321-043 Figure 10. PSRR vs. Supply Ripple Frequency Without Supply Decoupling Figure 13. SINAD vs. Reference Voltage 110 –80 VDD = 3V –81 VDRIVE = 3V 105 –82 100 –83 dB) 95 –84 N ( B) OLATIO 90 THD (d ––8865 S 85 I –87 80 –88 75 –89 700 50 100 150 200fN2O5I0SE (3k0H0z)350 400 450 500 550 09321-111 –901.0 EXTERN1A.5L REFERENCE VO2L.T0AGE (V) 2.5 09321-044 Figure 11. Channel-to-Channel Isolation, f = 50 kHz Figure 14. THD vs. Reference Voltage IN Rev. A | Page 10 of 24

AD7298-1 –60 19 RRSSOOUURRCCEE == 01Ω0Ω VDD = VDRIVE = 3V RSOURCE = 33Ω 18 –65 RSOURCE = 47Ω RRSSOOUURRCCEE == 210000ΩΩ 17 –70 16 W) HD (dB)–75 WER (m 1145 T O P –80 13 12 –85 VDD = 3V 11 VDRIVE = 3V –9010 INPUT FREQUEN1C0Y0 (kHz) 09321-045 100 100 200 300THR40O0UGH50P0UT (6k0S0PS)700 800 900 1000 09321-118 Figure 15. THD vs. Analog Input Frequency for Various Source Impedances Figure 17. Power vs. Throughput in Normal Mode with V = 3 V DD 6 4.0 VDD = VDRIVE = 3V –40°C +85°C VDRIVE = 3V 0°C +105°C 3.5 +25°C +125°C 5 3.0 VDD CURRENT A) mA) 4 NT (µ 2.5 URRENT ( 3 L CURRE 2.0 C 2 OTA 1.5 T 1.0 1 VDRIVE CURRENT 0.5 00 200 4T00HROUGH60P0UT (kSP8S0)0 1000 1200 09321-114 02.8 2.9 3.0 3.1 VD3D. 2(V) 3.3 3.4 3.5 3.6 09321-119 Figure 16. Average Supply Current vs. Throughput Rate Figure 18. Full Shutdown Current vs. Supply Voltage for Various Temperatures Rev. A | Page 11 of 24

AD7298-1 TERMINOLOGY Differential Nonlinearity Signal-to-Noise-and-Distortion Ratio (SINAD) The difference between the measured and the ideal 1 LSB The measured ratio of signal-to-noise and distortion at the change between any two adjacent codes in the ADC. output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up Offset Error to half the sampling frequency (f/2), excluding dc. The ratio is The deviation of the first code transition (00…000) to S dependent on the number of quantization levels in the digitization (00…001) from the ideal—that is, GND1 + 1 LSB. process; the more levels, the smaller the quantization noise. The Offset Error Matching theoretical signal-to-noise-and-distortion ratio for an ideal N- The difference in offset error between any two channels. bit converter with a sine wave input is given by Gain Error Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB The deviation of the last code transition (111…110) to Thus, the SINAD is 61.96 dB for an ideal 10-bit converter. (111…111) from the ideal (that is, V − 1 LSB) after the offset REF error has been adjusted out. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For Gain Error Matching the AD7298-1, it is defined as The difference in gain error between any two channels. V 2+V 2+V 2+V 2+V 2 Track-and-Hold Acquisition Time THD(dB)=20log 2 3 4 5 6 The track-and-hold amplifier returns to track mode at the end V 1 of the conversion. The track-and-hold acquisition time is the where: time required for the output of the track-and-hold amplifier to V is the rms amplitude of the fundamental. reach its final value, within ±1 LSB, after the end of the conversion. 1 V, V, V, V, and V are the rms amplitudes of the second 2 3 4 5 6 Power Supply Rejection Ratio (PSRR) through sixth harmonics. PSRR is defined as the ratio of the power in the ADC output at Peak Harmonic or Spurious Noise full-scale frequency, f, to the power of a 100 mV p-p sine wave The ratio of the rms value of the next largest component in the applied to the ADC V supply of frequency, f. The frequency DD S ADC output spectrum (up to f/2 and excluding dc) to the rms of the input varies from 5 kHz to 25 MHz. S value of the fundamental. Typically, the value of this specification PSRR (dB) = 10 log(Pf/Pf) is determined by the largest harmonic in the spectrum, but for S where: ADCs where the harmonics are buried in the noise floor, it is a Pf is the power at frequency, f, in the ADC output. noise peak. Pf is the power at frequency, f, in the ADC output. Integral Nonlinearity S S The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Rev. A | Page 12 of 24

AD7298-1 CIRCUIT INFORMATION The AD7298-1 is a high speed, 8-channel, 10-bit ADC. The part CAPACITIVE can be operated from a 2.8 V to 3.6 V supply and is capable of DAC throughput rates of 1 MSPS per analog input channel. A VIN The AD7298-1 provides the user with an on-chip, track-and-hold SW1 CONTROL AADD7C2 a9n8d-1 a h saesr ieailg ihntt, esrifnagclee -heonudseedd iinnp au t2 0ch-laenande LlsF wCiStPh. cThhaen nel GND1 B SW2 COMPARATOR LOGIC 09321-005 Figure 20. ADC Conversion Phase repeat functionality, which allows the user to select a channel sequence through which the ADC can cycle with each consecutive ANALOG INPUT CS falling edge. The serial clock input accesses data from the Figure 21 shows an equivalent circuit of the analog input structure part, controls the transfer of data written to the ADC, and of the AD7298-1. The two diodes, D1 and D2, provide ESD provides the clock source for the successive approximation protection for the analog inputs. Care must be taken to ensure ADC. The analog input range for the AD7928-1 is 0 V to VREF. that the analog input signal never exceeds the internally generated The AD7298-1 operates with one cycle latency, which means LDO voltage of 2.5 V (D ) by more than 300 mV. This causes CAP that the conversion result is available in the serial transfer the diodes to become forward-biased and to start conducting following the cycle in which the conversion is performed. current into the substrate. The maximum current these diodes The AD7298-1 provides flexible power management options to can conduct without causing irreversible damage to the part is allow the user to achieve the best power performance for a given 10 mA. Capacitor C1, in Figure 21, is typically about 8 pF and throughput rate. These options are selected by programming can primarily be attributed to pin capacitance. The R1 resistor is the partial power-down bit, PPD, in the control register and a lumped component made up of the on resistance of a switch using the PD/RST pin. (track-and-hold switch) and includes the on resistance of the input multiplexer. The total resistance is typically about 155 Ω. CONVERTER OPERATION The capacitor, C2, is the ADC sampling capacitor and has a The AD7298-1 is a 10-bit successive approximation ADC based capacitance of 34 pF typically. around a capacitive DAC. Figure 19 and Figure 20 show simplified DCAP(2.5V) schematics of the ADC. The ADC is comprised of control logic, SAR, and a capacitive DAC that are used to add and subtract C2 D1 pF fixed amounts of charge from the sampling capacitor to bring R1 VIN the comparator back into a balanced condition. Figure 19 shows C1 D2 CONVERSION PHASE: SWITCH OPEN the ADC during its acquisition phase. SW2 is closed and SW1 is pF TRACK PHASE: SWITCH CLOSED iann dP othsiet isoanm Ap.l iTnhge c caopmacpitaorra taocrq uisi rheesl dth ien saig bnaalal nocne tdh ceo sneldeictitoedn 09321-006 V channel. Figure 21. Equivalent Analog Input Circuit IN For ac applications, removing high frequency components from CAPACITIVE DAC the analog input signal is recommended by using an RC low-pass filter on the relevant analog input pin. In applications where A VIN harmonic distortion and signal-to-noise ratios are critical, the SW1 CONTROL GND1 B SW2 COMPARATOR LOGIC 08754-004 asonualrocge iinmppuet dshaonucelds bsieg dnriifviceann ftrloym af afe lcotw t hime apce dpaenrcfoe rsmouarnccee. Loafr tghee Figure 19. ADC Acquisition Phase ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application When the ADC starts a conversion (see Figure 20), SW2 opens performance criteria. and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the capacitive DAC are used to add and subtract fixed amounts of charge to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 22 shows the transfer function of the ADC. Rev. A | Page 13 of 24

AD7298-1 ADC Transfer Function This enables the AD7298-1 to operate with a larger dynamic range with a V of 3.3 V while still being able to interface to The output coding of the AD7298-1 is straight binary for the DD 1.8 V processors. Take care to ensure V does not exceed analog input channel conversion results. The designed code DRIVE V by more than 0.3 V (see the Absolute Maximum Ratings transitions occur at successive LSB values (that is, 1 LSB, 2 LSBs, DD section). and so forth). The LSB size is V /1024 for the AD7298-1. The REF ideal transfer characteristic for the AD7298-1 for straight binary THE INTERNAL OR EXTERNAL REFERENCE coding is shown in Figure 22. The AD7298-1 can operate with either the internal 2.5 V on-chip reference or an externally applied reference. The EXT_REF bit in the control register is used to determine whether the internal 111...111 111...110 reference is used. If the EXT_REF bit is selected in the control register, an external reference can be supplied through the V REF pin. At power-up, the internal reference is enabled. Suitable ODE 111...000 external reference sources for the AD7298-1 include AD780, C DC 011...111 1LSB=VREF/1024 AD1582, ADR431, REF193, and ADR391. A The internal reference circuitry consists of a 2.5 V band gap reference and a reference buffer. When the AD7298-1 is operated 000...010 000...001 in internal reference mode, the 2.5 V internal reference is 000...000 available at the V pin, which should be decoupled to GND1 0V REF 1LSB +VREF–1LSB using a 10 µF capacitor. It is recommended that the internal N1.OVTREESFIS2.5V. ANALOGINPUT 09321-007 rTehfeer ienntceer nbael breuffefreernedce b iesf ocarep aabplpel yoifn sgo uitr eclisnegw uhpe rteo i2n m thAe osyf sctuermre.n t Figure 22. Straight Binary Transfer Characteristic when the converter is static. The reference buffer requires 5.5 ms to V DRIVE power up and charge the 10 µF decoupling capacitor during the The AD7298-1 also provides the V feature. V controls power-up time. DRIVE DRIVE the voltage at which the serial interface operates. VDRIVE allows the ADC to easily interface to both 1.8 V and 3 V processors. For example, if the AD7298-1 were operated with a V of DD 3.3 V, the V pin could be powered from a 1.8 V supply. DRIVE Rev. A | Page 14 of 24

AD7298-1 CONTROL REGISTER The control register of the AD7298-1 is a 16-bit, write-only 16 serial clocks for every data transfer. Only the information register. Data is loaded from the DIN pin of the AD7298-1 on provided on the first 16 falling clock edges (after the falling the falling edge of SCLK. The data is transferred on the DIN edge of CS) is loaded to the control register. MSB denotes the line at the same time that the conversion result is read from the first bit in the data stream. The bit functions are outlined in part. The data transferred on the DIN line corresponds to the Table 6 and Table 7. At power-up, the default content of the AD7298-1 configuration for the next conversion. This requires control register is all zeros. Table 6. Control Register Bit Functions MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 WRITE REPEAT CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 0 DONTC DONTC EXT_REF DONTC PPD Table 7. Control Register Bit Function Description Bit Mnemonic Description D15 WRITE The value written to this bit determines whether the subsequent 15 bits are loaded to the control register. If this bit is a 1, the following 15 bits are written to the control register. If this bit is a 0, then the remaining 15 bits are not loaded to the control register, and it remains unchanged. D14 REPEAT This bit enables the repeated conversion of the selected sequence of channels. D13 to CH0 to These eight channel selection bits are loaded at the end of the current conversion and select which analog input D6 CH7 channel is to be converted in the next serial transfer, or they can select the sequence of channels for conversion in the subsequent serial transfers. Each CHx bit corresponds to an analog input channel. A channel or sequence of channels is selected for conversion by writing a 1 to the appropriate CHx bit/bits. Channel address bits corresponding to the conversion result are output on DOUT prior to the 10 bits of data. The next channel to be converted is selected by the mux on the 14th SCLK falling edge. D5 0 Zero should be written to this bit. D4, D3, DONTC Don’t care. D1 D2 EXT_REF Writing Logic 1 to this bit, enables the use of an external reference. The input voltage range for the external reference is 1 V to 2.5 V. The external reference should not exceed 2.5 V or the device performance is affected. D0 PPD This partial power-down mode is selected by writing a 1 to this bit in the control register. In this mode, some of the internal analog circuitry is powered down. The AD7298-1 retains the information in the control register while in partial power-down mode. The part remains in this mode until a 0 is written to this bit. Table 8. Channel Address Bits ADD3 ADD2 ADD1 ADD0 Analog Input Channel 0 0 0 0 V IN0 0 0 0 1 V IN1 0 0 1 0 V IN2 0 0 1 1 V IN3 0 1 0 0 V IN4 0 1 0 1 V IN5 0 1 1 0 V IN6 0 1 1 1 V IN7 Rev. A | Page 15 of 24

AD7298-1 MODES OF OPERATION The AD7298-1 offers different modes of operation that are subsequent (second) CS falling edge; and the third CS falling edge designed to provide additional flexibility for the user. These will have the result (V ) available for reading. The AD7298-1 IN2 options can be chosen by programming the content of the operates with one cycle latency, therefore the conversion result control register to select the desired mode. corresponding to each conversion is available one serial read TRADITIONAL MULTICHANNEL MODE OF cycle after the cycle in which the conversion was initiated. OPERATION As the device operates with one cycle latency, the control register configuration sets up the configuration for the next The AD7298-1 can operate as a traditional multichannel ADC, conversion, which is initiated on the next CS falling edge, but where each serial transfer selects the next channel for conversion. One must write to the control register to configure and select the first bit of the corresponding result is not clocked out until the desired input channel prior to initiating any conversions. In the subsequent falling CS edge, as shown in Figure 23. the traditional mode of operation, the CS signal is used to frame If more than one channel is selected in the control register, the the first write to the converter on the DIN pin. In this mode of AD7298-1 converts all selected channels sequentially in ascending operation, the REPEAT bit in the control register is set to a low order on successive CS falling edges. Once all the selected channels logic level (0), therefore the REPEAT function is not in use. The in the control register are converted, the AD7298-1 ceases converting data, which appears on the DOUT pin during the initial write to until the user rewrites to the control register to select the next the control register, is invalid. The first CS falling edge initiates a channel for conversion. This operation is shown in Figure 24. write to the control register to configure the device; a conversion is DOUT returns all 1s if the sequence of conversions is completed or then initiated for the selected analog input channel (VIN0) on the if no channel is selected. CS 1 10 16 1 16 1 16 1 16 SCLK DOUT INVALID DATA INVALID DATA COFNOVRER CSHIOANNN REELS 1ULT COFNOVRER CSHIOANNN REELS 4ULT DIN REDGAITSAT EWRR CITHTAENNN TEOL 1C OSENLTERCOTLED REDGAITSAT EWRR CITHTAENNN TEOL 4C OSENLTERCOTLED CNOON TWRROILT ER ETGOI STHTEER CNOON TWRROILT ER ETGOI STHTEER 09321-009 Figure 23. Configuring a Conversion and Read with the AD7298-1, One Channel Selected for Conversion CS 1 10 16 1 16 1 16 SCLK DOUT INVALID DATA INVALID DATA COFNOVRER CSHIOANNN REELS 1ULT DIN DATA WRITTEN TO CONTROL NO WRITE TO THE DATA WRITTEN TO CONTROL REGISTER CH 1 AND 2 SELECTED CONTROL REGISTER REGISTER CHANNEL 5 SELECTED CS 1 16 1 16 SCLK DOUT COFNOVRER CSHIOANNN REELS 2ULT COFNOVRER CSHIOANNN REELS 5ULT DIN CNOON TWRROILT ER ETGOI STHTEER CNOON TWRROILT ER ETGOI STHTEER 09321-010 Figure 24. Configuring a Conversion and Read with the AD7298-1, Numerous Channels Selected for Conversion Rev. A | Page 16 of 24

AD7298-1 CS 1 10 16 1 16 1 16 SCLK DOUT INVALID DATA INVALID DATA COFNOVRER CSHIOANNN REELS 0ULT DIN NO WRITE TO THE NO WRITE TO THE CONTROL REGISTER CONTROL REGISTER DATA WRITTEN TO CONTROL REGISTER CH0, CH1, AND CH2 SELECTED: REPEAT = 1 CS 1 16 1 16 1 16 SCLK DOUT COFNOVRER CSHIOANNN REELS 1ULT COFNOVRER CSHIOANNN REELS 2ULT COFNOVRER CSHIOANNN REELS 0ULT DIN CNOON TWRROILT ER ETGOI STHTEER CNOON TWRROILT ER ETGOI STHTEER CNOON TWRROILT ER ETGOI STHTEER 09321-011 Figure 25. Configuring a Conversion and Read in Repeat Mode REPEAT OPERATION The REPEAT bit in the control register allows the user to select To select a sequence of channels, the associated channel bit a sequence of channels on which the AD7298-1 continuously must be set to a logic high state (1) for each analog input whose converts. When the REPEAT bit is set in the control register, the conversion is required. For example, if the REPEAT bit = 1, then AD7298-1 continuously cycles through the selected channels in CH0, CH1, and CH2 = 1. The V analog input is converted on IN0 ascending order, beginning with the lowest channel and converting the first CS falling edge following the write to the control register, all channels selected in the control register. On completion of the V channel is converted on the subsequent CS falling edge, IN1 the sequence, the AD7298-1 returns to the first selected channel and the V conversion result is available for reading. The third IN0 in the control register and recommences the sequence. CS falling edge following the write operation initiates a conversion The conversion sequence of the selected channels in the repeat on V and has the V result available for reading. The AD7298-1 IN2 IN1 mode of operation continues until the control register of the operates with one cycle latency, therefore the conversion result AD7298-1 is reprogrammed. It is not necessary to write to the corresponding to each conversion is available one serial read control register once a repeat operation is initiated unless a change cycle after the cycle in which the conversion is initiated. in the AD7298-1 configuration is required. The WRITE bit This mode of operation simplifies the operation of the device by must be set to zero, or the DIN line tied low to ensure that the allowing consecutive channels to be converted without having control register is not accidentally overwritten or the automatic to reprogram the control register or write to the part on each conversion sequence interrupted. serial transfer. Figure 25 illustrates how to set up the AD7298-1 A write to the control register during the repeat mode of operation to continuously convert on a particular sequence of channels. resets the cycle even if the selected channels are unchanged. To exit the repeat mode of operation and revert to the traditional Thus, the next conversion by the AD7298-1 after a write mode of operation of a multichannel ADC, ensure that the operation will be the first selected channel in the sequence. REPEAT bit = 0 on the next serial write. Rev. A | Page 17 of 24

AD7298-1 POWER-DOWN MODES Partial Power-Down Mode The AD7298-1 has a number of power conservation modes of In this mode, part of the internal circuitry on the AD7298-1 operation that are designed to provide flexible power management is powered down. The AD7298-1 enters partial power-down options. These options can be chosen to optimize the power on the CS rising edge once the current serial write operation dissipation/throughput rate ratio for different application containing 16 SCLK clock cycles is completed. To enter partial requirements. The power-down modes of operation of the power-down, the PPD bit in the control register should be set to AD7298-1 are controlled by the power-down (PPD) bit in the 1 on the last required read transfer from the AD7298-1. Once in control register and the PD/RST pin on the device. When power partial power-down mode, the AD7298-1 transmits all 1s on the supplies are first applied to the AD7298-1, care should be taken DOUT pin if CS is toggled low. to ensure that the part is placed in the required mode of operation. The AD7298-1 remains in partial power-down until the power- Normal Mode down bit, PPD, in the control register is changed to Logic Level 0. Normal mode is intended for the fastest throughput rate The AD7298-1 begins powering up on the rising edge of CS performance because the user does not have to be concerned following the write to the control register disabling the power- about any power-up times since the AD7298-1 remains fully down bit. Once t has elapsed, a full 16 SCLK writes to the QUIET powered on at all times. Figure 26 shows the general diagram control register must be completed to update its content with of the normal mode operation of the AD7298-1. The conversion the desired channel configuration for the subsequent conversion. is initiated on the falling edge of CS and the track-and-hold enters A valid conversion is then initiated on the next CS falling edge. hold mode. On the 14th SCLK falling edge, the track-and-hold Because the AD7298-1 has one cycle latency, the first conversion returns to track mode and starts acquiring the analog input, as result after exiting partial power-down mode is available in the described in the Serial Interface section. The data presented to fourth serial transfer, as shown in Figure 27. The first cycle updates the AD7298-1 on the DIN line during the first 16 clock cycles of the PPD bit, the second cycle updates the configuration and the data transfer are loaded into the control register (provided the Channel ID bits, the third completes the conversion, and the WRITE bit is 1). The part remains fully powered up in normal fourth accesses the DOUT valid result. The use of this mode mode at the end of the conversion as long as the PPD bit is set enables a reduction in the overall power consumption of the device. to 0 in the write transfer during that conversion. Full Power-Down Mode To ensure continued operation in normal mode, the PPD bit In this mode, all internal circuitry on the AD7298-1 is powered should be loaded with 0 on every data write operation. Sixteen down, and no information is retained in the control register or any serial clock cycles are required to complete the conversion and other internal register. access the conversion result. For specified performance, the throughput rate should not exceed 1 MSPS. When a conversion The AD7298-1 is placed into full power-down mode by bringing is complete and the CS has returned high, a minimum of the quiet the logic level on the PD/RST pin low for greater than 100 ns. time, t , must elapse before bringing CS low again to initiate When placing the AD7298-1 in full power-down mode, the ADC QUIET inputs must return to 0 V. The PD/RST pin is asynchronous to the another conversion and access the previous conversion result. clock; therefore, it can be triggered at any time. The part can be CS powered up for normal operation by bringing the PD/RST pin 1 16 logic level back to a high logic state. SCLK DOUT 4 +C HCAONNNVEELR SAIDODNR REESSSU BLITTS The full power-down feature can be used to reduce the average DIN DATRAE GWISRTITETRE NIF TROE QCUOINRTERDOL 09321-012 pthorwoeurg hcopnustu rmateesd. bTyh teh ues AerD s7h2o9u8ld-1 e wnshuerne othpaetr atPtOinWgER a-UtP l ohwase r Figure 26. Normal Mode Operation elapsed prior to programming the control register and initiating a valid conversion. THE PART IS FULLY PART IS IN PART BEGINS TO POWERED UP ONCE THE PARTIAL POWER UP ON CS WRITE TO THE CONTROL POWER DOWN RISING EDGE. REGISTER IS COMPLETED. tQUIET tQUIET CS 1 10 16 1 16 1 16 SCLK DOUT INVALID DATA INVALID DATA DIN WRITE TO CONTROL WRITE TO THE CONTROL NO WRITE TO REGISTER, PPD = 0. REGISTER, SELECT CH1, PPD = 0 CONTROL REGISTER CONTRTOOL P ROEWGEISRT UERP DCEOVNIFCIEG.URED PROFWSOGEILRRLL EAC CCMOOTMN NAVEVNEDEAR RILSNTOI O TTGHNH I.IES NT PFWHUIERRT SIN TCTEE HXC OATHNP ACNENYRENCLAELSTLEION. RAEDSN7UE2LX9TT8 ACCVYOACNILLVEAE BRHLTAEISN FGCOH CRAH NRANENEANLDE I1LN G1. 09321-213 Figure 27. Partial Power-Down Mode of Operation Rev. A | Page 18 of 24

AD7298-1 POWERING UP THE AD7298-1 RESET The AD7298-1 contains a power-on reset circuit that sets the The AD7298-1 includes a reset feature that can be used to reset control register to its default setting of all zeros; therefore, the the device and the contents of all internal registers, including internal reference is enabled and the device is configured for the the control register, to their default state. normal mode of operation. At power-up, the internal reference is To activate the reset operation, the PD/RST pin should be brought by default enabled, which takes up to 6 ms (maximum) to power up. low for no longer than 100 ns. It is asynchronous with the clock; If an external reference is being used, the user does not need to therefore, it can be triggered at any time. If the PD/RST pin is wait for the internal reference to power up fully. The AD7298-1 held low for greater than 100 ns, the part enters full power-down digital interface is fully functional after 500 µs from the initial mode. It is imperative that the PD/RST pin be held at a stable power-up. Therefore, the user can write to the control register logic level at all times to ensure normal operation. after 500 µs to switch to external reference mode. The AD7298-1 is then immediately ready to convert once the external reference is available on the V pin. REF When supplies are first applied to the AD7298-1, the user must wait the specified 500 µs before programming the control register to select the desired channels for conversion. Rev. A | Page 19 of 24

AD7298-1 SERIAL INTERFACE Figure 28 shows the detailed timing diagram for the serial interface When CS goes low, it provides the first address bit to be read in to the AD7298-1. The serial clock provides the conversion clock by the microcontroller or DSP. The remaining data is then clocked and controls the transfer of information to and from the AD7298-1 out by subsequent SCLK falling edges, beginning with a second during each conversion. address bit. Thus, the first falling clock edge on the serial clock The CS signal initiates the data transfer and conversion process. has the first address bit provided for reading and also clocks out the second address bit. The three remaining address bits and 12 The falling edge of CS puts the track-and-hold into hold mode data bits are clocked out by subsequent SCLK falling edges. The at which point the analog input is sampled and the bus is taken final bit in the data transfer is valid for reading on the 16th falling out of three-state. The conversion is also initiated at this point edge having been clocked out on the previous (15th) falling edge. and requires 16 SCLK cycles to complete. The track-and-hold goes back into track mode on the 14th SCLK falling edge as shown In applications with a slower SCLK, it may be possible to read in in Figure 28 at Point B. On the 16th SCLK falling edge or on the data on each SCLK rising edge depending on the SCLK frequency. rising edge of CS, the DOUT line goes back into three-state. The first rising edge of SCLK after the CS falling edge would have the first address bit provided, and the 15th rising SCLK If the rising edge of CS occurs before 16 SCLKs have elapsed, edge would have last data bit provided. the conversion is terminated, the DOUT line goes back into three-state, and the control register is not updated; otherwise, Writing information to the control register takes place on the DOUT returns to three-state on the 16th SCLK falling edge. first 16 falling edges of SCLK in a data transfer, assuming the Sixteen serial clock cycles are required to perform the conversion MSB (that is, the WRITE bit) has been set to 1. The 16-bit word process and to access data from the AD7298-1. read from the AD7298-1 always contains four channel address bits that the conversion result corresponds to, followed by the For the AD7298-1, four channel address bits (ADD3 to ADD0) 12-bit conversion result. that identify which channel the conversion result corresponds to, precede the 10 bits of data (see Table 8). tQUIET CS tACQUISITION t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t5 t3 t4 t7 t8 THREE- STATE DOUT THREE- ADD3 ADD2 ADD1 ADD0 DB9 DB8 DB0 DCOANR’ET DCOANR’ET STATE t9 t10 DIN WRITE REPEAT CH0 CH1 CH2 CH3 EXT_REF DONTC PPD 09321-014 Figure 28. Serial Interface Timing Diagram Rev. A | Page 20 of 24

AD7298-1 LAYOUT AND CONFIGURATION For optimum performance, carefully consider the power supply The power supply line should have as large a trace as possible to and ground return layout on any PCB where the AD7298-1 is provide a low impedance path and reduce glitch effects on the used. The PCB containing the AD7298-1 should have separate supply line. Shield clocks and other components with fast switching analog and digital sections, each having its own area of the board. digital signals from other parts of the board by a digital ground. The AD7298-1 should be located in the analog section on any PCB. Avoid crossover of digital and analog signals, if possible. When traces cross on opposite sides of the board, ensure that they run Decouple the power supply to the AD7298-1 to ground with at right angles to each other to reduce feedthrough effects on 10 µF and 0.1 µF capacitors. Place the capacitors as physically the board. close as possible to the device, with the 0.1 µF capacitor ideally right up against the device. It is important that the 0.1 µF The best board layout technique is the microstrip technique where capacitor has low effective series resistance (ESR) and low the component side of the board is dedicated to the ground effective series inductance (ESL); common ceramic types of plane only, and the signal traces are placed on the solder side; capacitors are suitable. The 0.1 µF capacitors provide a low however, this is not always possible with a 2-layer board. impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The 10 µF capacitors are the tantalum bead type. Rev. A | Page 21 of 24

AD7298-1 OUTLINE DIMENSIONS 4.10 0.30 4.00 SQ 0.25 PIN 1 3.90 0.18 INDICATOR PIN 1 16 20 INDICATOR 0.50 BSC 15 1 EXPOSED 2.75 PAD 2.60 SQ 2.35 11 5 0.50 10 6 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 0.80 FOR PROPER CONNECTION OF 0.75 THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANTTOJEDEC STANDARDS MO-220-WGGD. 020509-B Figure 29. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very, Very Thin Quad (CP-20-8) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD7298-1BCPZ −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-8 AD7298-1BCPZ-RL −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-8 1 Z = RoHS Compliant Part. Rev. A | Page 22 of 24

AD7298-1 NOTES Rev. A | Page 23 of 24

AD7298-1 NOTES ©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09321-0-1/11(A) Rev. A | Page 24 of 24

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7298-1BCPZ AD7298-1BCPZ-RL