3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT Data Sheet AD7276/AD7277/AD7278 FEATURES FUNCTIONAL BLOCK DIAGRAM Throughput rate: 3 MSPS VDD Specified for V of 2.35 V to 3.6 V DD Power consumption 12.6 mW at 3 MSPS with 3 V supplies 12-/10-/8-BIT Wide input bandwidth VIN T/H APSPURCOCXEISMSAITVIEON 70 dB SNR at 1 MHz input frequency ADC Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI-/QSPI™-/MICROWIRE™-/DSP compatible SCLK Temperature range: −40°C to +125°C AD7276/ CONTROL SDATA Power-down mode: 0.1 µA typical AD7277/ LOGIC AD7278 CS 6-lead TSOT package 8A-Dle7a4d7 M6 aSnOdP A pDac7k4a7g6eA pin compatible GND 04903-001 GENERAL DESCRIPTION Figure 1. The AD7276/AD7277/AD7278 are 12-/10-/8-bit, high speed, Table 1. low power, successive approximation analog-to-digital converters Part Number Resolution Package (ADCs), respectively. The parts operate from a single 2.35 V AD7276 12 8-Lead MSOP 6-Lead TSOT to 3.6 V power supply and feature throughput rates of up to AD7277 10 8-Lead MSOP 6-Lead TSOT 3 MSPS. The parts contain a low noise, wide bandwidth track- AD7278 8 8-Lead MSOP 6-Lead TSOT and-hold amplifier that can handle input frequencies in excess AD72741 12 8-Lead MSOP 8-Lead TSOT of 55 MHz. AD72731 10 8-Lead MSOP 8-Lead TSOT The conversion process and data acquisition are controlled 1 Part contains external reference pin. using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on PRODUCT HIGHLIGHTS the falling edge of CS, and the conversion is initiated at this 1. 3 MSPS ADCs in a 6-lead TSOT package. point. There are no pipeline delays associated with the part. 2. AD7476/AD7477/AD7478 and AD7476A/AD7477A/ The AD7276/AD7277/AD7278 use advanced design techniques AD7478A pin compatible. to achieve very low power dissipation at high throughput rates. 3. High throughput with low power consumption. 4. Flexible power/serial clock speed management. This allows The reference for the part is taken internally from VDD. This maximum power efficiency at low throughput rates. allows the widest dynamic input range to the ADC; therefore, 5. Reference derived from the power supply. the analog input range for the part is 0 to VDD. The conversion 6. No pipeline delay. The parts feature a standard successive rate is determined by the SCLK. approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7276/AD7277/AD7278 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 General Description ......................................................................... 1 Circuit Information .................................................................... 16 Functional Block Diagram .............................................................. 1 Converter Operation .................................................................. 16 Product Highlights ........................................................................... 1 ADC Transfer Function ............................................................. 16 Revision History ............................................................................... 2 Typical Connection Diagram ................................................... 16 Specifications ..................................................................................... 3 Modes of Operation ................................................................... 18 AD7276 Specifications ................................................................. 3 Power vs. Throughput Rate ....................................................... 21 AD7277 Specifications ................................................................. 5 Serial Interface ................................................................................ 22 AD7278 Specifications ................................................................. 7 AD7278 in a 10 SCLK Cycle Serial Interface .......................... 24 Timing Specifications—AD7276/AD7277/AD7278 ............... 8 Microprocessor Interfacing ....................................................... 24 Timing Examples ........................................................................ 10 Application Hints ........................................................................... 25 Absolute Maximum Ratings .......................................................... 11 Grounding and Layout .............................................................. 25 ESD Caution ................................................................................ 11 Evaluating Performance .............................................................. 25 Pin Configurations and Function Descriptions ......................... 12 Outline Dimensions ....................................................................... 26 Typical Performance Characteristics ........................................... 13 Ordering Guide .......................................................................... 27 Terminology .................................................................................... 15 REVISION HISTORY 7/15—Rev. C. to Rev. D Changes to Table 4 ............................................................................. 7 Changes to Differential Nonlinearity Parameter, Table 2 ........... 3 Changes to Ordering Guide .......................................................... 27 Changes to Typical Connection Diagram Section ..................... 16 Changes to AD7276/AD7277/AD7278 to Blackfin Processor 10/05—Rev. 0 to Rev. A Section and Figure 36 ..................................................................... 24 Updated Format .................................................................. Universal Changes to Ordering Guide .......................................................... 27 Changes to Table 2 ............................................................................. 3 Changes to Table 5 ............................................................................. 8 5/11—Rev. B to Rev. C Changes to the Partial Power-Down Mode Section .................. 18 Changes to Figure 21 ...................................................................... 16 Changes to the Power vs. Throughput Rate Section .................. 21 Changes to Ordering Guide .......................................................... 27 Updated Outline Dimensions ....................................................... 26 Changes to Endnote 5 .................................................................... 27 Changes to Ordering Guide .......................................................... 26 11/09—Rev. A to Rev. B 7/05—Revision 0: Initial Version Changes to Table 2 ............................................................................ 3 Changes to Table 3 ............................................................................ 5 Rev. D | Page 2 of 28

Data Sheet AD7276/AD7277/AD7278 SPECIFICATIONS AD7276 SPECIFICATIONS V = 2.35 V to 3.6 V, B Grade and A Grade: f = 48 MHz, f = 3 MSPS, Y Grade:1 f = 16 MHz, f = 1 MSPS, T = T to DD SCLK SAMPLE SCLK SAMPLE A MIN T , unless otherwise noted. MAX Table 2. Parameter A Grade2, 3 B, Y Grade2, 3 Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 1 MHz sine wave, B Grade IN f = 100 kHz sine wave, Y Grade IN Signal-to-Noise + Distortion (SINAD)4 68 68 dB min Signal-to-Noise Ratio (SNR) 69 69 dB min 70 70 dB typ Total Harmonic Distortion (THD)4 −73 −73 dB max −78 −78 dB typ Peak Harmonic or Spurious Noise (SFDR)4 −80 −80 dB typ Intermodulation Distortion (IMD)4 Second-Order Terms −82 −82 dB typ fa = 1 MHz, fb = 0.97 MHz Third-Order Terms −82 −82 dB typ fa = 1 MHz, fb = 0.97 MHz Aperture Delay 5 5 ns typ Aperture Jitter 18 18 ps typ Full Power Bandwidth 55 55 MHz typ @ 3 dB 8 8 MHz typ @ 0.1 dB DC ACCURACY Resolution 12 12 Bits Integral Nonlinearity4 ±1.5 ±1 LSB max Differential Nonlinearity4 +1.2/−0.99 +1.2/−0.99 LSB max Guaranteed no missed codes to 12 bits Offset Error4 ±4 ±3 LSB max Gain Error4 ±3.5 ±3.5 LSB max Total Unadjusted Error4 (TUE) ±5 ±3.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to V 0 to V V DD DD DC Leakage Current ±1 ±1 µA max −40°C to +85°C ±5.5 ±5.5 µA max 85°C to 125°C Input Capacitance 42 42 pF typ When in track 10 10 pF typ When in hold LOGIC INPUTS Input High Voltage, V 1.7 1.7 V min 2.35 V ≤ V ≤ 2.7 V INH DD 2 2 V min 2.7 V < V ≤ 3.6 V DD Input Low Voltage, V 0.7 0.7 V max 2.35 V ≤ V ≤ 2.7 V INL DD 0.8 0.8 V max 2.7 V < V ≤ 3.6 V DD Input Current, I ±1 ±1 µA max Typically 10 nA, V = 0 V or V IN IN DD Input Capacitance, C 5 2 2 pF typ IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V − 0.2 V min I = 200 µA, V = 2.35 V to 3.6 V OH DD DD SOURCE DD Output Low Voltage, V 0.2 0.2 V max I = 200 µA OL SINK Floating-State Leakage Current ±2.5 ±2.5 µA max Floating-State Output Capacitance5 4.5 4.5 pF typ Output Coding Straight (natural) binary Rev. D | Page 3 of 28

AD7276/AD7277/AD7278 Data Sheet Parameter A Grade2, 3 B, Y Grade2, 3 Unit Test Conditions/Comments CONVERSION RATE Conversion Time 291 291 ns max 14 SCLK cycles with SCLK at 48 MHz, B Grade 875 875 ns max 14 SCLK cycles with SCLK at 16 MHz, Y Grade Track-and-Hold Acquisition Time4 60 60 ns min Throughput Rate 3 3 MSPS max See the Serial Interface section POWER REQUIREMENTS V 2.35/3.6 2.35/3.6 V min/max DD I Digital I/Ps 0 V or V DD DD Normal Mode (Static) 1 1 mA typ V = 3.6 V, SCLK on or off DD Normal Mode (Operational) 5.5 5.5 mA max V = 2.35 V to 3.6 V, f = 3 MSPS, B Grade DD SAMPLE 2.5 2.5 mA max V = 2.35 V to 3.6 V, f = 1 MSPS, Y Grade DD SAMPLE 4.2 4.2 mA typ V = 3 V, f = 3 MSPS, B Grade DD SAMPLE 1.6 1.6 mA typ V = 3 V, f = 1 MSPS, Y Grade DD SAMPLE Partial Power-Down Mode (Static) 34 34 µA typ Full Power-Down Mode (Static) 2 2 µA max −40°C to +85°C, typically 0.1 µA 10 10 µA max 85°C to 125°C Power Dissipation6 Normal Mode (Operational) 19.8 19.8 mW max V = 3.6 V, f = 3 MSPS, B Grade DD SAMPLE 9 9 mW max V = 3.6 V, f = 1 MSPS, Y Grade DD SAMPLE 12.6 12.6 mW typ V = 3 V, f = 3 MSPS, B Grade DD SAMPLE 4.8 4.8 mW typ V = 3 V, f = 1 MSPS, Y Grade DD SAMPLE Partial Power-Down 102 102 µW typ V = 3 V DD Full Power-Down 7.2 7.2 µW max V = 3.6 V, −40°C to +85°C DD 1 Y grade specifications are guaranteed by characterization. 2 Temperature range from −40°C to +125°C. 3 Typical specifications are tested with V = 3 V and at 25°C. DD 4 See the Terminology section. 5 Guaranteed by characterization. 6 See the Power vs. Throughput Rate section. Rev. D | Page 4 of 28

Data Sheet AD7276/AD7277/AD7278 AD7277 SPECIFICATIONS V = 2.35 V to 3.6 V, f = 48 MHz, f = 3 MSPS, T = T to T , unless otherwise noted. DD SCLK SAMPLE A MIN MAX Table 3. Parameter A Grade1, 2 B Grade1, 2 Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 1 MHz sine wave IN Signal-to-Noise + Distortion (SINAD)3 60.5 60.5 dB min Total Harmonic Distortion (THD)3 −70 −1 dB max −76 −76 dB typ Peak Harmonic or Spurious Noise (SFDR)3 −80 −80 dB typ Intermodulation Distortion (IMD)3 Second-Order Terms −82 −82 dB typ fa = 1 MHz, fb = 0.97 MHz Third-Order Terms −82 −82 dB typ fa = 1 MHz, fb = 0.97 MHz Aperture Delay 5 5 ns typ Aperture Jitter 18 18 ps typ Full Power Bandwidth 74 74 MHz typ @ 3 dB 10 10 MHz typ @ 0.1 dB DC ACCURACY Resolution 10 10 Bits Integral Nonlinearity3 ±0.5 ±0.5 LSB max Differential Nonlinearity3 ±0.5 ±0.5 LSB max Guaranteed no missed codes to 10 bits Offset Error3 ±1.5 ±1 LSB max Gain Error3 ±2 ±1.5 LSB max Total Unadjusted Error (TUE)3 ±2.5 ±2.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to V 0 to V V DD DD DC Leakage Current ±1 ±1 µA max −40°C to +85°C ±5.5 ±5.5 µA max 85°C to 125°C Input Capacitance 42 42 pF typ When in track 10 10 pF typ When in hold LOGIC INPUTS Input High Voltage, V 1.7 1.7 V min 2.35 V ≤ V ≤ 2.7 V INH DD 2 2 V min 2.7 V < V ≤ 3.6 V DD Input Low Voltage, V 0.7 0.7 V max 2.35 V ≤ V ≤ 2.7 V INL DD 0.8 0.8 V max 2.7 V < V ≤ 3.6 V DD Input Current, I ±1 ±1 µA max Typically 10 nA, V = 0 V or V IN IN DD Input Capacitance, C 4 2 2 pF typ IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V − 0.2 V min I = 200 µA, V = 2.35 V to 3.6 V OH DD DD SOURCE DD Output Low Voltage, V 0.2 0.2 V max I = 200 µA OL SINK Floating-State Leakage Current ±2.5 ±2.5 µA max Floating-State Output Capacitance4 4.5 4.5 pF typ Output Coding Straight (natural) binary CONVERSION RATE Conversion Time 250 250 ns max 12 SCLK cycles with SCLK at 48 MHz Track-and-Hold Acquisition Time3 60 60 ns min Throughput Rate 3.45 3.45 MSPS max SCLK at 48 MHz Rev. D | Page 5 of 28

AD7276/AD7277/AD7278 Data Sheet Parameter A Grade1, 2 B Grade1, 2 Unit Test Conditions/Comments POWER REQUIREMENTS V 2.35/3.6 2.35/3.6 V min/max DD I Digital I/Ps 0 V or V DD DD Normal Mode (Static) 0.6 0.6 mA typ V = 3.6 V, SCLK on or off DD Normal Mode (Operational) 5.5 5.5 mA max V = 2.35 V to 3.6 V, f = 3 MSPS DD SAMPLE 3.5 3.5 mA typ V = 3 V DD Partial Power-Down Mode (Static) 34 34 µA typ Full Power-Down Mode (Static) 2 2 µA max −40°C to +85°C, typically 0.1 µA 10 10 µA max 85°C to 125°C Power Dissipation5 Normal Mode (Operational) 19.8 19.8 mW max V = 3.6 V, f = 3 MSPS DD SAMPLE 10.5 10.5 mW typ V = 3 V DD Partial Power-Down 102 102 µW typ V = 3 V DD Full Power-Down 7.2 7.2 µW max V = 3.6 V, −40°C to +85°C DD 1 Temperature range from −40°C to +125°C. 2 Typical specifications are tested with V = 3 V and at 25°C. DD 3 See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section. Rev. D | Page 6 of 28

Data Sheet AD7276/AD7277/AD7278 AD7278 SPECIFICATIONS V = 2.35 V to 3.6 V, f = 48 MHz, f = 3 MSPS, T = T to T , unless otherwise noted. DD SCLK SAMPLE A MIN MAX Table 4. Parameter A Grade1, 2 B Grade1, 2 Unit Test Conditions/Comments DYNAMIC PERFORMANCE f = 1 MHz sine wave IN Signal-to-Noise + Distortion (SINAD)3 49 49 dB min Total Harmonic Distortion (THD)3 −66 −67 dB max −73 −73 dB typ Peak Harmonic or Spurious Noise (SFDR)3 −69 −69 dB typ Intermodulation Distortion (IMD)3 Second-Order Terms −76 −76 dB typ fa = 1 MHz, fb = 0.97 MHz Third-Order Terms −76 −76 dB typ fa = 1 MHz, fb = 0.97 MHz Aperture Delay 5 5 ns typ Aperture Jitter 18 18 ps typ Full Power Bandwidth 74 74 MHz typ @ 3 dB Full Power Bandwidth 10 10 MHz typ @ 0.1 dB DC ACCURACY Resolution 8 8 Bits Integral Nonlinearity3 ±0.2 ±0.2 LSB max Differential Nonlinearity3 ±0.3 ±0.3 LSB max Guaranteed no missed codes to 8 bits Offset Error3 ±0.9 ±0.5 LSB max Gain Error3 ±1.2 ±1 LSB max Total Unadjusted Error (TUE)3 ±1.5 ±1.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to V 0 to V V DD DD DC Leakage Current ±1 ±1 µA max −40°C to +85°C ±5.5 ±5.5 µA max 85°C to 125°C Input Capacitance 42 42 pF typ When in track 10 10 pF typ When in hold LOGIC INPUTS Input High Voltage, V 1.7 1.7 V min 2.35 V ≤ V ≤ 2.7 V INH DD 2 2 V min 2.7 V < V ≤ 3.6 V DD Input Low Voltage, V 0.7 0.7 V max 2.35 V ≤ V ≤ 2.7 V INL DD 0.8 0.8 V max 2.7 V < V ≤ 3.6 V DD Input Current, I ±1 ±1 µA max IN Input Capacitance, C 4 2 2 pF typ IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V − 0.2 V min I = 200 µA, V = 2.35 V to 3.6 V OH DD DD SOURCE DD Output Low Voltage, V 0.2 0.2 V max I = 200 µA OL SINK Floating-State Leakage Current ±2.5 ±2.5 µA max Floating-State Output Capacitance4 4.5 4.5 pF typ Output Coding Straight (natural) binary CONVERSION RATE Conversion Time 208 208 ns max 10 SCLK cycles with SCLK at 48 MHz Track-and-Hold Acquisition Time3 60 60 ns min Throughput Rate 4 4 MSPS max SCLK at 48 MHz Rev. D | Page 7 of 28

AD7276/AD7277/AD7278 Data Sheet Parameter A Grade1, 2 B Grade1, 2 Unit Test Conditions/Comments POWER REQUIREMENTS V 2.35/3.6 2.35/3.6 V min/max DD I Digital I/Ps = 0 V or V DD DD Normal Mode (Static) 0.5 0.5 mA typ V = 3.6 V, SCLK on or off DD Normal Mode (Operational) 5.5 5.5 mA max V = 2.35 V to 3.6 V, f = 3 MSPS DD SAMPLE 3.5 3.5 mA typ V = 3 V DD Partial Power-Down Mode (Static) 34 34 µA typ Full Power-Down Mode (Static) 2 2 µA max −40°C to +85°C, typically 0.1 µA 10 10 µA max +85°C to +125°C Power Dissipation5 Normal Mode (Operational) 19.8 19.8 mW max V = 3.6 V, f = 3 MSPS DD SAMPLE 10.5 10.5 mW typ V = 3 V DD Partial Power-Down 102 102 µW typ V = 3 V DD Full Power-Down 7.2 7.2 µW max V = 3.6 V, −40°C to +85°C DD 1 Temperature range from −40°C to +125°C. 2 Typical specifications are tested with V = 3 V and at 25°C. DD 3 See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section. TIMING SPECIFICATIONS—AD7276/AD7277/AD7278 V = 2.35 V to 3.6 V, T = T to T , unless otherwise noted.1 DD A MIN MAX Table 5. Parameter2 Limit at T , T Unit Description MIN MAX f 3 500 kHz min4 SCLK 48 MHz max B grade 16 MHz max Y grade t 14 × t AD7276 CONVERT SCLK 12 × t AD7277 SCLK 10 × t AD7278 SCLK t 4 ns min Minimum quiet time required between the bus relinquish and the QUIET start of the next conversion t 3 ns min Minimum CS pulse width 1 t 6 ns min CS to SCLK setup time 2 t5 4 ns max Delay from CS until SDATA three-state disabled 3 t5 15 ns max Data access time after SCLK falling edge 4 t 0.4 t ns min SCLK low pulse width 5 SCLK t 0.4 t ns min SCLK high pulse width 6 SCLK t5 5 ns min SCLK to data valid hold time 7 t 14 ns max SCLK falling edge to SDATA three-state 8 5 ns min SCLK falling edge to SDATA three-state t 4.2 ns max CS rising edge to SDATA three-state 9 T 6 1 µs max Power-up time from full power-down POWER-UP 1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. 2 Guaranteed by characterization. All input signals are specified with tr = tf = 2 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. DD 3 Mark/space ratio for the SCLK input is 40/60 to 60/40. 4 Minimum f at which specifications are guaranteed. SCLK 5 The time required for the output to cross the V or V voltage. IH IL 6 See the Power-Up Times section. Rev. D | Page 8 of 28

Data Sheet AD7276/AD7277/AD7278 t4 t8 SCLK SCLK SDATA VVIILH 04903-002 SDATA 1.4V 04903-004 Figure 2. Access Time After SCLK Falling Edge Figure 4. SCLK Falling Edge SDATA Three-State t7 SCLK SDATA VVIIHL 04903-003 Figure 3. Hold Time After SCLK Falling Edge Rev. D | Page 9 of 28

AD7276/AD7277/AD7278 Data Sheet TIMING EXAMPLES This satisfies the requirement of 60 ns for t . Figure 6 also ACQ shows that t comprises 0.5(1/f ) + t + t , where For the AD7276, if CS is brought high during the 14th SCLK rising ACQ SCLK 8 QUIET t = 14 ns max. This allows a value of 43 ns for t , satisfying edge after the two leading zeros and 12 bits of the conversion 8 QUIET the minimum requirement of 4 ns. have been provided, the part can achieve the fastest throughput rate, 3 MSPS. If CS is brought high during the 16th SCLK rising Timing Example 2 edge after the two leading zeros and 12 bits of the conversion The example in Figure 7 uses a 16 SCLK cycle, f = 48 MHz, SCLK and two trailing zeros have been provided, a throughput rate of and the throughput is 2.97 MSPS. This produces a cycle time of 2.97 MSPS is achievable. This is illustrated in the following two t + 12.5(1/f ) + t = 336 ns, where t = 6 ns minimum and 2 SCLK ACQ 2 timing examples. t = 70 ns. Figure 7 shows that t comprises 2.5(1/f ) + t + ACQ ACQ SCLK 8 t , where t = 14 ns max. This satisfies the minimum Timing Example 1 QUIET 8 requirement of 4 ns for t QUIET. In Figure 6, using a 14 SCLK cycle, f = 48 MHz and the SCLK throughput is 3 MSPS. This produces a cycle time of t + 2 12.5(1/f ) + t = 333 ns, where t = 6 ns minimum and SCLK ACQ 2 t = 67 ns. ACQ t 1 CS t CONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t3 t4 t7 t5 t8 tQUIET SDATA Z ZERO DB11 DB10 DB9 DB1 DB0 ZERO ZERO THREE- THREE-STATE STATE 2 LEADING 2 TRAILING ZEROS 1/THROUGHPUT ZEROS 04903-005 Figure 5. AD7276 Serial Interface Timing Diagram t 1 CS t CONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 t3 t4 t7 t5 t9 tQUIET SDATA Z ZERO DB11 DB10 DB9 DB1 DB0 THREE- THREE-STATE STATE 2 LEADING ZEROS 1/THROUGHPUT 04903-034 Figure 6. AD7276 Serial Interface Timing 14 SCLK Cycle t 1 CS t CONVERT t2 B SCLK 1 2 3 4 5 12 13 14 15 16 t 8 t QUIET 12.5(1/fSCLK) 1/THROUGHPUT tACQUISITION 04903-006 Figure 7. AD7276 Serial Interface Timing 16 SCLK Cycle Rev. D | Page 10 of 28

Data Sheet AD7276/AD7277/AD7278 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 6. stress rating only; functional operation of the product at these Parameters Ratings or any other conditions above those indicated in the operational V to GND −0.3 V to +6 V DD section of this specification is not implied. Operation beyond Analog Input Voltage to GND −0.3 V to V + 0.3 V DD the maximum operating conditions for extended periods may Digital Input Voltage to GND −0.3 V to +6 V affect product reliability. Digital Output Voltage to GND −0.3 V to V + 0.3 V DD Input Current to Any Pin Except Supplies1 ±10 mA Operating Temperature Range ESD CAUTION Commercial (B grade) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 6-Lead TSOT Package θ Thermal Impedance 230°C/W JA θ Thermal Impedance 92°C/W JC 8-Lead MSOP Package θ Thermal Impedance 205.9°C/W JA θ Thermal Impedance 43.74°C/W JC Lead Temperature Soldering Reflow (10 sec to 30 sec) 255°C Lead Temperature Soldering Reflow (10 sec to 30 sec) 260°C ESD 1.5 kV 1 Transient currents of up to 100 mA cause SCR latch-up. Rev. D | Page 11 of 28

AD7276/AD7277/AD7278 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 AD7276/ 6 CS VDD 1 AD7276/ 8 VIN AD7277/ SDATA 2 AD7277/ 7 GND GND 2 AD7278 5 SDATA CS 3 AD7278 6 SCLK VIN 3 (NToOtPtoVSIEcWale) 4 SCLK 04903-007 NC 4NC(N=ToNOtOPtoCVSOIEcNWaNleE)CT5 NC 04903-008 Figure 8. 6-Lead TSOT Pin Configuration Figure 9. 8-Lead MSOP Pin Configuration Table 7. Pin Function Descriptions Pin No. 6-Lead TSOT 8-Lead MSOP Mnemonic Description 1 1 V Power Supply Input. The V range for the AD7276/AD7277/AD7278 is 2.35 V to 3.6 V. DD DD 2 7 GND Analog Ground. Ground reference point for all circuitry on the AD7276/AD7277/AD7278. All analog input signals should be referred to this GND voltage. 3 8 V Analog Input. Single-ended analog input channel. The input range is 0 V to V . IN DD 4 6 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of the AD7276/AD7277/AD7278. 5 2 SDATA Data Out. Logic output. The conversion result from the AD7276/AD7277/AD7278 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7276 consists of two leading zeros followed by 12 bits of conversion data and two trailing zeros, provided MSB first. The data stream from the AD7277 consists of two leading zeros followed by 10 bits of conversion data and four trailing zeros, provided MSB first. The data stream from the AD7278 consists of two leading zeros followed by 8 bits of conversion data and six trailing zeros, provided MSB first. 6 3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversion on the AD7276/AD7277/AD7278 and framing the serial data transfer. 4, 5 NC No Connect. Rev. D | Page 12 of 28

Data Sheet AD7276/AD7277/AD7278 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A 73.0 16,384POINTFFT –20 FFSINAM=P1LMEH=z3MSPS 72.5 VDD=3.6V SINAD=71.2dB THD=–80.9dB 72.0 –40 SFDR=–82.4dB SNR (dB) –60 VDD=3V SNR (dB)7711..50 VDD=3V VDD=2.35V 70.5 –80 70.0 –100 –120 04903-009 6699..50 04903-013 0 100 200 300 400 500 600 700 800 900100011001200130014001500 100 1000 1500 FREQUENCY(kHz) INPUTFREQUENCY(kHz) Figure 10. AD7276 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz Figure 13. AD7276 SNR vs. Analog Input Frequency at 3 MSPS for Various Supply Voltages, SCLK Frequency = 48 MHz –10 30,000 16,384POINTFFT 30,000 –20 FSAMPLE=3MSPS CODES –30 FSIINNA=D1M=H6z1.6dB 25,000 THD=–80.2dB S E –40 SVFDDDR==3V–83.4dB ENC20,000 R –50 R R (dB) –60 OCCU15,000 SN –70 OF R E10,000 –80 B M U –90 N 5,000 ––110100 04903-010 0 04903-016 0 100 200 300 400 500 600 700 800 900100011001200130014001500 2046 2047 2048 2049 2050 FREQUENCY(kHz) CODE Figure 11. AD7277 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz Figure 14. Histogram of Codes for 30,000 Samples 72.5 –72 72.0 VDD=3.6V –74 71.5 –76 71.0 VDD = 2.35V AD (dB)7700..50 VDD=2.35V VDD=3V D (dB) ––7880 VDD = 3V N H –82 SI69.5 T –84 69.0 VDD = 3.6V 68.5 –86 6678..50 04903-012 ––8980 04903-017 100 1000 1500 100 1000 1500 INPUTFREQUENCY(kHz) INPUT FREQUENCY (kHz) Figure 12. AD7276 SINAD vs. Analog Input Frequency at 3 MSPS Figure 15. THD vs. Analog Input Frequency at 3 MSPS for Various Supply Voltages, SCLK Frequency = 48 MHz for Various Supply Voltages, SCLK Frequency = 48 MHz Rev. D | Page 13 of 28

AD7276/AD7277/AD7278 Data Sheet –50 1.0 VDD=3V 0.8 –55 0.6 –60 RIN=100Ω 0.4 B) –65 S L 0.2 D (dB) –70 ROR ( 0 H R T E –75 RIN=10Ω NL –0.2 D –0.4 –80 –0.6 ––9805 RIN=0Ω 04903-015 ––01..08 04903-014 100 1000 1500 0 500 1000 1500 2000 2500 3000 3500 4000 INPUTFREQUENCY(kHz) CODE Figure 16. THD vs. Analog Input Frequency at 3 MSPS for Various Source Figure 18. AD7276 DNL Performance Impedances, SCLK Frequency = 48 MHz, Supply Voltage = 3 V 1.0 VDD=3V 0.8 0.6 0.4 B) LS 0.2 R ( O 0 R R L E–0.2 N I –0.4 –0.6 ––01..80 04903-011 0 500 1000 1500 2000 2500 3000 3500 4000 CODE Figure 17. AD7276 INL Performance Rev. D | Page 14 of 28

Data Sheet AD7276/AD7277/AD7278 TERMINOLOGY Integral Nonlinearity Total Harmonic Distortion (THD) The maximum deviation from a straight line passing through The ratio of the rms sum of harmonics to the fundamental. It is the endpoints of the ADC transfer function. For the AD7276/ defined as: AD7277/AD7278, the endpoints of the transfer function are V2 +V2+V2+V2+V2 zero scale at 0.5 LSB below the first code transition and full THD(dB)=20log 2 3 4 5 6 scale at 0.5 LSB above the last code transition. V 1 Differential Nonlinearity where: The difference between the measured and the ideal 1 LSB V is the rms amplitude of the fundamental. 1 change between any two adjacent codes in the ADC. V, V, V, V, and V are the rms amplitudes of the second 2 3 4 5 6 through sixth harmonics. Offset Error The deviation of the first code transition (00 . . . 000) to Peak Harmonic or Spurious Noise (00 . . . 001) from the ideal, that is, AGND + 0.5 LSB. The ratio of the rms value of the next largest component in the ADC output spectrum (up to f/2, excluding dc) to the rms value Gain Error S of the fundamental. Normally, the value of this specification is The deviation of the last code transition (111 . . . 110) to determined by the largest harmonic in the spectrum; however, for (111 . . . 111) from the ideal after adjusting for the offset error, ADCs with harmonics buried in the noise floor, it is determined that is, V − 1.5 LSB. REF by a noise peak. Total Unadjusted Error Intermodulation Distortion A comprehensive specification that includes gain, linearity, and With inputs consisting of sine waves at two frequencies, fa and offset errors. fb, any active device with nonlinearities creates distortion Track-and-Hold Acquisition Time products at sum and difference frequencies of mfa ± nfb, where The time required after the conversion for the output of the m and n = 0, 1, 2, 3, …. Intermodulation distortion terms are track-and-hold amplifier to reach its final value within ±0.5 LSB. those for which neither m nor n are equal to zero. For example, See the Serial Interface section for more details. the second-order terms include (fa + fb) and (fa − fb), and the Signal-to-Noise + Distortion Ratio (SINAD) third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and The measured ratio of signal to noise plus distortion at the (fa − 2fb). output of the ADC. The signal is the rms amplitude of the The AD7276/AD7277/AD7278 are tested using the CCIF fundamental, and noise is the rms sum of all nonfundamental standard in which two input frequencies are used (see fa and fb signals up to half the sampling frequency (f/2), including S in the specifications). In this case, the second-order terms are harmonics but excluding dc. The ratio is dependent on the usually distanced in frequency from the original sine waves, and number of quantization levels in the digitization process: the the third-order terms are usually at a frequency close to the input more levels, the smaller the quantization noise. For an ideal frequencies. As a result, the second- and third-order terms are N-bit converter, the SINAD is defined as specified separately. The intermodulation distortion is SINAD =6.02N +1.76dB calculated in a similar manner to the THD specification, that is, the ratio of the rms sum of the individual distortion products to According to this equation, the SINAD is 74 dB for a 12-bit the rms amplitude of the sum of the fundamentals expressed in converter and 62 dB for a 10-bit converter. However, various decibels. error sources in the ADC, including integral and differential Aperture Delay nonlinearities and internal ac noise sources, cause the measured The measured interval between the leading edge of the sampling SINAD to be less than its theoretical value. clock and the point at which the ADC takes the sample. Aperture Jitter The sample-to-sample variation when the sample is taken. Rev. D | Page 15 of 28

AD7276/AD7277/AD7278 Data Sheet THEORY OF OPERATION CIRCUIT INFORMATION CHARGE The AD7276/AD7277/AD7278 are fast, micropower, 12-/10-/ REDISTRIBUTION DAC 8-bit, single-supply ADCs, respectively. The parts can be operated SAMPLING from a 2.35 V to 3.6 V supply. When operated from a supply A CAPACITOR voltage within this range, the AD7276/AD7277/AD7278 are VIN CONTROL capable of throughput rates of 3 MSPS when provided with a SW1 ACQUISITION SW2 LOGIC B PHASE 4T8h eM AHDz7 c2lo76ck/A. D7277/AD7278 provide the user with an on- AGND VDD/2 COMPARATOR 04903-020 Figure 20. ADC Conversion Phase chip track-and-hold ADC and a serial interface housed in a tiny 6-lead TSOT or an 8-lead MSOP package, which offers the user ADC TRANSFER FUNCTION considerable space-saving advantages over alternative solutions. The output coding of the AD7276/AD7277/AD7278 is straight The serial clock input accesses data from the part and provides binary. The designed code transitions occur midway between the clock source for the successive approximation ADC. The successive integer LSB values, such as 0.5 LSB and 1.5 LSB. The analog input range is 0 V to V . An external reference is not DD LSB size is V /4,096 for the AD7276, V /1,024 for the AD7277, DD DD required for the ADC, and there is no reference on-chip. The and V /256 for the AD7278. The ideal transfer characteristic DD reference for the AD7276/AD7277/AD7278 is derived from the for the AD7276/AD7277/AD7278 is shown in Figure 21. power supply, resulting in the widest dynamic input range. The AD7276/AD7277/AD7278 also feature a power-down 111...111 option to save power between conversions. The power-down 111...110 feature is implemented across the standard serial interface as E D described in the Modes of Operation section. O 111...000 C C CONVERTER OPERATION AD 011...111 1LSB = VREF/4096 (AD7276) 1LSB = VREF/1024 (AD7277) The AD7276/AD7277/AD7278 are successive approximation 000...010 1LSB = VREF/256 (AD7278) 000...001 ADCs that are based on a charge redistribution DAC. Figure 19 000...000 ashnodw Fsi gthuer eA 2D0C sh douwri snigm iptsl iaficeqdu isscihtieomn apthicass eo,f w thhee rAe DSWC. 2F iisg uclroes e1d9, 0V0.5LSBANALOG INPUT +VDD – 1.5LSB 04903-021 Figure 21. AD7276/AD7277/AD7278 Transfer Characteristics SW1 is in Position A, the comparator is held in a balanced con- TYPICAL CONNECTION DIAGRAM dition, and the sampling capacitor acquires the signal on V . IN Figure 22 shows a typical connection diagram for the AD7276/ CHARGE AD7277/AD7278. VREF is taken internally from VDD; therefore, REDISTRIBUTION DAC VDD should be decoupled. This provides an analog input range of 0 V to V . The conversion result is output in a 16-bit word SAMPLING DD A CAPACITOR with two leading zeros followed by the 12-bit, 10-bit, or 8-bit VIN SW1 ACQUISITION SW2 COLNOTGRICOL result. The 12-bit result from the AD7276 is followed by two B PHASE trailing zeros; the 10-bit and 8-bit results from the AD7277 and AGND VDD/2 COMPARATOR 04903-019 AAlDte7r2n7at8i vaerley ,f boellcoawuseed t bhye sfouuppr layn cdu rsriexn ttr areilqinuigr ezde rboys ,t hree sApeDc7ti2v7e6ly/. Figure 19. ADC Acquisition Phase AD7277/AD7278 is so low, a precision reference can be used as When the ADC starts a conversion, SW2 opens and SW1 moves the supply source for the AD7276/AD7277/AD7278. A REF192 to Position B, causing the comparator to become unbalanced or REF193 voltage reference (REF193 for 3 V) can be used to (see Figure 20). The control logic and the charge redistribution supply the required voltage to the ADC (see Figure 22). This DACs are used to add and subtract fixed amounts of charge configuration is especially useful if the power supply is noisy or from the sampling capacitor to bring the comparator back into the system supply voltage is a value other than 3 V (for example, a balanced condition. When the comparator is rebalanced, the 5 V or 15 V). The REF192 or REF193 outputs a steady voltage conversion is complete. The control logic generates the ADC to the AD7276/AD7277/AD7278. If the low dropout REF193 is output code. used, it must supply a current of typically 1 mA to the AD7276/ AD7277/AD7278. When the ADC is converting at a rate of 3 MSPS, the REF193 must supply a maximum of 5 mA to the AD7276/AD7277/AD7278. Rev. D | Page 16 of 28

Data Sheet AD7276/AD7277/AD7278 The load regulation of the REF193 is typically 10 ppm/mA Large source impedances significantly affect the ac performance (REF193, V = 5 V), which results in an error of 50 ppm (150 µV) of these ADCs and can necessitate the use of an input buffer S for the 5 mA drawn from it. When V = 3 V from the REF193, amplifier. The AD8021 op amp is compatible with these devices; DD it corresponds to an error of 0.204 LSB, 0.051 LSB, and 0.0128 LSB however, the choice of the op amp is a function of the particular for the AD7276, AD7277, and AD7278, respectively. For application. applications where power consumption is of concern, use the VDD power-down mode of the ADC and the sleep mode of the REF193 reference to improve power performance. See the D1 R1 C2 Modes of Operation section. VIN C1 4pF D2 0.1µF TA13NµVTF REF19130µF 0.1µF 5SVUPPLY CTROANCVKERPSHIAOSNEP—HSAWSEIT—CSHWCILTOCSHE ODPEN04903-023 680nF Figure 23. Equivalent Analog Input Circuit VDD When no amplifier is used to drive the analog input, the source 0VINTPOUVTDD VIN AD7276/ SCLK impedance should be limited to a low value. The maximum source AD7277/ SDATA DSP/ AD7278 CS µC/µP impedance depends on the amount of THD that can be tolerated. GND The THD increases as the source impedance increases and per- formance degrades. Figure 16 shows a graph of the THD vs. the INTSEERRFIAALCE 04903-022 aunsianlog ga isnuppuptl yfr veqoulteangec yo ffo 3r Vdi affnedre snatm sopulirncge aimt ap readtaen ocfe 3s wMhSePnS . Figure 22. REF193 as Power Supply to the AD7276/AD7277/AD7278 Digital Inputs Table 8 provides typical performance data with various references used as a V source with the same setup conditions. The digital inputs applied to the AD7276/AD7277/AD7278 are DD not limited by the maximum ratings that limit the analog inputs. Table 8. AD7276 Performance (Various Voltage References IC) Instead, the digital inputs applied to the AD7276/AD7277/ Reference Tied to VDD SNR Performance, 1 MHz Input AD7278 can be 6 V and are not restricted by the VDD + 0.3 V AD780 @ 3 V 71.3 dB limit of the analog inputs. For example, if the AD7276/AD7277/ AD780 @ 2.5 V 70.1 dB AD7278 are operated with a V of 3 V, then 5 V logic levels can DD REF193 70.9 dB be used on the digital inputs. However, it is important to note that the data output on SDATA still has 3 V logic levels when Analog Input V = 3 V. Another advantage of SCLK and CS not being restricted DD Figure 23 shows an equivalent circuit of the analog input structure by the V + 0.3 V limit is that power supply sequencing issues are DD of the AD7276/AD7277/AD7278. The two diodes, D1 and D2, avoided. For example, unlike with the analog inputs, with the provide ESD protection for the analog inputs. Care must be taken digital inputs, if CS or SCLK is applied before V , there is no DD to ensure that the analog input signal never exceeds the supply risk of latch-up. rails by more than 300 mV. Signals exceeding this value cause these diodes to become forward biased and to start conducting current into the substrate. These diodes can conduct a maximum current of 10 mA without causing irreversible damage to the part. Capacitor C1 in Figure 23 is typically about 4 pF and can primarily be attributed to pin capacitance. Resistor R1 is a lumped component made up of the on resistance of a switch. This resistor is typically about 75 Ω. Capacitor C2 is the ADC sampling capacitor and has a capacitance of 4 pF typically when in hold mode and 32 pF typically when in track mode. For ac applications, removing high frequency components from the analog input signal is recommended by using a band-pass filter on the relevant analog input pin. In applications where the harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Rev. D | Page 17 of 28

AD7276/AD7277/AD7278 Data Sheet MODES OF OPERATION CS can idle high until the next conversion or low until CS returns The mode of operation of the AD7276/AD7277/AD7278 is high before the next conversion (effectively idling CS low). selected by controlling the logic state of the CS signal during a Once a data transfer is complete (SDATA has returned to three- conversion. There are three possible modes of operation: normal state), another conversion can be initiated after the quiet time, mode, partial power-down mode, and full power-down mode. tQUIET, has elapsed by bringing CS low again. The point at which CS is pulled high after the conversion has Partial Power-Down Mode been initiated determines which power-down mode, if any, the This mode is intended for use in applications where slower device enters. Similarly, if the device is already in power-down throughput rates are required. An example of this is when either mode, CS can control whether the device returns to normal the ADC is powered down between each conversion or a series operation or remains in power-down mode. These modes of of conversions is performed at a high throughput rate and then operation are designed to provide flexible power management the ADC is powered down for a relatively long duration between options, which can be chosen to optimize the power dissipation/ these bursts of several conversions. When the AD7276/AD7277/ throughput rate ratio for different application requirements. AD7278 are in partial power-down mode, all analog circuitry is Normal Mode powered down except the bias-generation circuit. This mode is intended for fastest throughput rate performance To enter partial power-down mode, interrupt the conversion because the device remains fully powered at all times, eliminating process by bringing CS high between the second and 10th falling worry about power-up times. Figure 24 shows the general diagram edges of SCLK, as shown in Figure 25. of AD7276/AD7277/AD7278 operation in this mode. Once CS is brought high in this window of SCLKs, the part The conversion is initiated on the falling edge of CS as described enters partial power-down mode, the conversion that was in the Serial Interface section. To ensure that the part remains initiated by the falling edge of CS is terminated, and SDATA fully powered up at all times, CS must remain low until at least goes back into three-state. If CS is brought high before the 10 SCLK falling edges elapse after the falling edge of CS. If CS is second SCLK falling edge, the part remains in normal mode and brought high after the 10th SCLK falling edge but before the 16th does not power down. This prevents accidental power-down due SCLK falling edge, the part remains powered up, but the con- to glitches on the CS line. version is terminated and SDATA goes back into three-state. For the AD7276, a minimum of 14 serial clock cycles are required to complete the conversion and access the complete conversion result. For the AD7277 and AD7278, a minimum of 12 and 10 serial clock cycles are required to complete the conversion and to access the complete conversion result, respectively. AD7276/ AD7677/AD7278 CS 1 10 12 14 16 SCLK SDATA VALID DATA 04903-024 Figure 24. Normal Mode Operation CS 1 2 10 16 SCLK SDATA THREE-STATE 04903-025 Figure 25. Entering Partial Power-Down Mode Rev. D | Page 18 of 28

Data Sheet AD7276/AD7277/AD7278 To exit this mode of operation and power up the AD7276/ Power-Up Times AD7277/AD7278, users should perform a dummy conversion. The AD7276/AD7277/AD7278 have two power-down modes, On the falling edge of CS, the device begins to power up and partial power-down and full power-down, which are described continues to power up as long as CS is held low until after the in detail in the Modes of Operation section. This section deals falling edge of the 10th SCLK. The device is fully powered up with the power-up time required when coming out of either of once 16 SCLKs elapse; valid data results from the next conversion, these modes. as shown in Figure 26. If CS is brought high before the 10th falling To power up from partial power-down mode, one cycle is edge of SCLK, the AD7276/AD7277/AD7278 go into full power- required. Therefore, with an SCLK frequency of up to 48 MHz, down mode. Therefore, although the device can begin to power one dummy cycle is sufficient to allow the device to power up up on the falling edge of CS, it powers down on the rising edge from partial power-down mode. Once the dummy cycle is of CS as long as this occurs before the 10th SCLK falling edge. complete, the ADC is fully powered up and the input signal is If the AD7276/AD7277/AD7278 are already in partial power- acquired properly. The quiet time, tQUIET, must still be allowed down mode and CS is brought high before the 10th falling edge from the point where the bus goes back into three-state after the of SCLK, the device enters full power-down mode. For more dummy conversion to the next falling edge of CS. information on the power-up times associated with partial To power up from full power-down, approximately 1 μs should power-down mode in various configurations, see the Power-Up be allowed from the falling edge of CS, shown in Figure 28 as Times section. t . POWER UP Full Power-Down Mode Note that during power-up from partial power-down mode, the This mode is intended for use in applications where throughput track-and-hold, which is in hold mode while the part is powered rates slower than those in the partial power-down mode are down, returns to track mode after the first SCLK edge, follow- required because power-up from a full power-down takes ing the falling edge of CS. This is shown as Point A in Figure 26. substantially longer than that from a partial power-down. This When power supplies are first applied to the AD7276/AD7277/ mode is suited to applications where a series of conversions AD7278, the ADC can power up in either of the power-down performed at a relatively high throughput rate are followed by a modes or in normal mode. Because of this, it is best to allow a long period of inactivity and thus, power down. dummy cycle to elapse to ensure that the part is fully powered When the AD7276/AD7277/AD7278 are in full power-down up before attempting a valid conversion. Likewise, if the part is mode, all analog circuitry is powered down. To enter full power- to be kept in partial power-down mode immediately after the down mode, put the device into partial power-down mode by supplies are applied, then two dummy cycles must be initiated. bringing CS high between the second and 10th falling edges of The first dummy cycle must hold CS low until after the 10th SCLK. In the next conversion cycle, interrupt the conversion SCLK falling edge; in the second cycle, CS must be brought high process in the same way as shown in Figure 27 by bringing CS between the second and 10th SCLK falling edges (see Figure 25). high before the 10th SCLK falling edge. Once CS is brought high Alternatively, if the part is to be placed into full power-down in this window of SCLKs, the part powers down completely. mode when the supplies are applied, three dummy cycles must Note that it is not necessary to complete the 16 SCLKs once CS is be initiated. The first dummy cycle must hold CS low until after brought high to enter either of the power-down modes. Glitch the 10th SCLK falling edge; the second and third dummy cycles protection is not available when entering full power-down mode. place the part into full power-down mode (see Figure 27). See To exit full power-down mode and to power up the AD7276/ the Modes of Operation section. AD7277/AD7278, users should perform a dummy conversion, similar to when powering up from partial power-down mode. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The required power-up time must elapse before a conversion can be initiated, as shown in Figure 28. See the Power-Up Times section for the power-up times associated with the AD7276/AD7277/AD7278. Rev. D | Page 19 of 28

AD7276/AD7277/AD7278 Data Sheet THEPART BEGINS THEPART IS FULLY TO POWER UP POWERED UP, SEE THE POWER- UP TIMES SECTION CS 1 10 16 1 16 SCLK A SDATA INVALID DATA VALID DATA 04903-026 Figure 26. Exiting Partial Power-Down Mode THEPART ENTERS THEPART BEGINS THEPART ENTERS PARTIAL POWER-DOWN TO POWER UP FULL POWER-DOWN CS 1 2 10 16 1 10 16 SCLK SDATA INVALID DATA THREE-STATE VALID DATA THREE-STATE 04903-027 Figure 27. Entering Full Power-Down Mode THEPART BEGINS THEPART IS TO POWER UP FULLY POWERED UP t POWER UP CS 1 10 16 1 16 SCLK SDATA INVALID DATA VALID DATA 04903-028 Figure 28. Exiting Full Power-Down Mode Rev. D | Page 20 of 28

Data Sheet AD7276/AD7277/AD7278 POWER VS. THROUGHPUT RATE 7.4 7.2 7.0 50MHzSCLK Figure 29 shows the power consumption of the device in 6.8 6.6 normal mode, in which the part is never powered down. By 6.4 6.2 using the power-down mode of the AD7276/AD7277/AD7278 6.0 VARIABLE when not performing a conversion, the average power consump- W) 5.8 SCLK m 5.6 tion of the ADC decreases as the throughput rate decreases. ER ( 55..42 Figure 30 shows that as the throughput rate is reduced, the W 5.0 O 4.8 device remains in its power-down state longer, and the average P 4.6 4.4 power consumption over time drops accordingly. For example, 4.2 4.0 if the AD7276/AD7277/AD7278 are operated in continuous 3.8 soaf m48p lMinHg zm (oVdDeD w= i3th V a) tahnrdo uthgeh pduevt ircaetse a orfe 2p0l0a ckeSdP iSn aton dp oanw eSrC-LK 3333....0642 04903-029 down mode between conversions, then the power consumption 0 200 400 600 800 1000 1200 1400 1600 1800 2000 THROUGHPUT(kSPS) is calculated as follows. The power dissipation during normal Figure 29. Power vs. Throughput Normal Mode operation is 12.6 mW (VDD = 3 V). If the power-up time is one 8.0 dummy cycle, that is, 333 ns, and the remaining conversion 7.5 VDD=3V 7.0 time is 290 ns, then the AD7276/AD7277/AD7278 can be said 6.5 to dissipate 12.6 mW for 623 ns during each conversion cycle. If 6.0 the throughput rate is 200 kSPS, then the cycle time is 5 µs and 5.5 the average power dissipated during each cycle is 623/5,000 × W) 5.0 m 4.5 12.6 mW = 1.56 mW. Figure 29 shows the power vs. throughput ER ( 4.0 rate when using the partial power-down mode between conver- OW 3.5 P 3.0 sions at 3 V. The power-down mode is intended for use with 2.5 throughput rates of less than 600 kSPS, because at higher 2.0 sampling rates, there is no power saving achieved by using the 1.5 power-down mode. 10..050 04903-035 0 200 400 600 800 1000 THROUGHPUT(kSPS) Figure 30. Power vs. Throughput Partial Power-Down Mode Rev. D | Page 21 of 28

AD7276/AD7277/AD7278 Data Sheet SERIAL INTERFACE Figure 31 through Figure 34 show the detailed timing diagrams If 16 SCLKs are considered in the cycle, then the AD7278 clocks for serial interfacing to the AD7276, AD7277, and AD7278. The out six trailing zeros for the last six bits and SDATA returns to serial clock provides the conversion clock and controls the transfer three-state on the 16th SCLK falling edge, as shown in Figure 34. of information from the AD7276/AD7277/AD7278 during If the user considers a 14 SCLK cycle serial interface for the conversion. AD7276/AD7277/AD7278, then CS must be brought high after The CS signal initiates the data transfer and conversion process. the 14th SCLK falling edge. Then the last two trailing zeros are The falling edge of CS puts the track-and-hold into hold mode ignored, and SDATA goes back into three-state. In this case, the and takes the bus out of three-state. The analog input is sampled 3 MSPS throughput can be achieved by using a 48 MHz clock and the conversion is initiated at this point. frequency. For the AD7276, the conversion requires completing 14 SCLK CS going low clocks out the first leading zero to be read by the cycles. Once 13 SCLK falling edges have elapsed, the track-and- microcontroller or DSP. The remaining data is then clocked out hold goes back into track mode on the next SCLK rising edge, by subsequent SCLK falling edges, beginning with the second as shown in Figure 31 at Point B. If the rising edge of CS occurs leading zero. Therefore, the first falling clock edge on the serial before 14 SCLKs have elapsed, the conversion is terminated and clock provides the first leading zero and clocks out the second the SDATA line goes back into three-state. If 16 SCLKs are leading zero. The final bit in the data transfer is valid on the 16th considered in the cycle, the last two bits are zeros and SDATA falling edge, because it is clocked out on the previous (15th) returns to three-state on the 16th SCLK falling edge, as shown in falling edge. Figure 32. In applications with a slower SCLK, it is possible to read data on For the AD7277, the conversion requires completing 12 SCLK each SCLK rising edge. In such cases, the first falling edge of SCLK cycles. Once 11 SCLK falling edges elapse, the track-and-hold clocks out the second leading zero and can be read on the first goes back into track mode on the next SCLK rising edge, as rising edge. However, the first leading zero clocked out when shown in Figure 33 at Point B. If the rising edge of CS occurs CS goes low is missed if read within the first falling edge. The before 12 SCLKs elapse, the conversion is terminated and the 15th falling edge of SCLK clocks out the last bit and can be read SDATA line goes back into three-state. If 16 SCLKs are considered on the 15th rising SCLK edge. in the cycle, the AD7277 clocks out four trailing zeros for the If CS goes low just after one SCLK falling edge elapses, then CS last four bits and SDATA returns to three-state on the 16th SCLK clocks out the first leading zero and can be read on the SCLK falling edge, as shown in Figure 33. rising edge. The next SCLK falling edge clocks out the second For the AD7278, the conversion requires completing 10 SCLK leading zero and can be read on the following rising edge. cycles. Once 9 SCLK falling edges elapse, the track-and-hold goes back into track mode on the next rising edge. If the rising edge of CS occurs before 10 SCLKs elapse, the part enters power- down mode. t 1 CS t CONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 t3 t4 t7 t5 t9 tQUIET SDATA Z ZERO DB11 DB10 DB9 DB1 DB0 THREE- THREE-STATE STATE 2 LEADING ZEROS 1/THROUGHPUT 04903-099 Figure 31. AD7276 Serial Interface Timing Diagram 14 SCLK Cycle Rev. D | Page 22 of 28

Data Sheet AD7276/AD7277/AD7278 t 1 CS t CONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t t t3 t4 t7 5 8 t QUIET SDATA Z ZERO DB11 DB10 DB9 DB1 DB0 ZERO ZERO THREE- THREE-STATE STATE 2 LEADING 2 TRAILING ZEROS 1/THROUGHPUT ZEROS 04903-030 Figure 32. AD7276 Serial Interface Timing Diagram 16 SCLK Cycle t 1 CS t CONVERT t2 B t6 SCLK 1 2 3 4 10 11 12 13 14 15 16 t3 t4 t5 t7 t8 tQUIET SDATA Z ZERO DB9 DB8 DB1 DB0 ZERO ZERO ZERO ZERO THREE- THREE-STATE STATE 2Z ELREOASDING 1/THROUGHPUT 4 TRAILING ZEROS 04903-031 Figure 33. AD7277 Serial Interface Timing Diagram t 1 CS t CONVERT t2 t6 B SCLK 1 2 3 4 8 9 10 11 14 15 16 t3 t4 t5 t7 t8 t QUIET SDATA Z ZERO DB7 DB6 DB1 DB0 ZERO ZERO ZERO THREE- THREE-STATE STATE 2Z ELREOASDING 1/THROUGHPUT 6 TRAILING ZEROS 04903-032 Figure 34. AD7278 Serial Interface Timing Diagram t 1 CS t CONVERT t2 t6 B SCLK 1 2 3 4 5 9 10 t 8 t QUIET 8.5 (1/fSCLK) tACQ SDATA Z ZERO DB7 DB6 DB5 DB1 DB0 THREE- THREE-STATE STATE 2 LEADING ZEROS 1/THROUGHPUT 04903-033 Figure 35. AD7278 in a 10 SCLK Cycle Serial Interface Rev. D | Page 23 of 28

AD7276/AD7277/AD7278 Data Sheet AD7278 IN A 10 SCLK CYCLE SERIAL INTERFACE Table 9. The SPORT0 Receive Configuration 1 Register (SPORT0_RCR1) For the AD7278, if CS is brought high during the 10th rising Setting Description edge after the two leading zeros and eight bits of the conversion RCKFE = 1 Sample data with falling edge of RSCLK are provided, then the part can achieve a 4 MSPS throughput LRFS = 1 Active low frame signal rate. For the AD7278, the track-and-hold goes back into track RFSR = 1 Frame every word mode on the ninth rising edge. In this case, a f = 48 MHz and SCLK IRFS = 1 Internal RFS used throughput of 4 MSPS result in a cycle time of t + 8.5(1/f ) + 2 SCLK RLSBIT = 0 Receive MSB first t = 250 ns, where t = 6 ns minimum and t = 67 ns. This ACQ 2 ACQ RDTYPE = 00 Zero fill satisfies the requirement of 60 ns for t . Figure 35 shows that ACQ IRCLK = 1 Internal receive clock t comprises 0.5(1/f ) + t + t , where t = 14 ns max. ACQ SCLK 8 QUIET 8 RSPEN = 1 Receive enabled This allows a value of 43 ns for t , satisfying the minimum QUIET SLEN = 1111 16-bit data-word (or can be set to 1101 for requirement of 4 ns. 14-bit data-word) MICROPROCESSOR INTERFACING TFSR = RFSR = 1 AD7276/AD7277/AD7278 to Blackfin Processor To implement the power-down modes, SLEN should be set to The Analog Devices, Inc., family of Blackfin DSPs, including 1001 to issue an 8-bit SCLK burst. the ADSP-BF531, ADSP-BF532, ADSP-BF533, ADSP-BF534, ADSP-BF535, ADSP-BF536, ADSP-BF537, ADSP-BF538, ADSP-BF538F, ADSP-BF539, and ADSP-BF539F, interfaces directly to the AD7276/AD7277/AD7278 without requiring glue logic. (These DSPs are represented by the ADSP-BF531 in Figure 36.) Set up the SPORT0 Receive Configuration 1 Register up as outlined in Table 9. AD7276/ ADSP-BF531* AD7277/ AD7278* SPORT0 SCLK RSCLK0 DOUT DR0PRI CS RFS0 DIN DT0PRI *ADDITIONAL PINS OMITTED FOR CLARITY 04903-098 Figure 36. Interfacing with the ADSP-BF531 Rev. D | Page 24 of 28

Data Sheet AD7276/AD7277/AD7278 APPLICATION HINTS GROUNDING AND LAYOUT Good decoupling is also important. All analog supplies should be decoupled with 10 µF ceramic capacitors in parallel with The printed circuit board that houses the AD7276/AD7277/ 0.1 µF capacitors to GND. To achieve the best results from these AD7278 should be designed so that the analog and digital decoupling components, they must be placed as close as possible sections are separated and confined to certain areas of the to the device, ideally right up against the device. The 0.1 µF board. This design facilitates using ground planes that can easily capacitors should have low effective series resistance (ESR) and be separated. low effective series inductance (ESI), such as is typical of common To provide optimum shielding for ground planes, a minimum ceramic or surface-mount types of capacitors. Capacitors with etch technique is generally best. All AGND pins of the AD7276/ low ESR and low ESI provide a low impedance path to ground AD7277/AD7278 should be sunk into the AGND plane. Digital at high frequencies, which allow them to handle transient and analog ground planes should be joined in one place only. If currents due to internal logic switching. the AD7276/AD7277/AD7278 are in a system where multiple EVALUATING PERFORMANCE devices require an AGND-to-DGND connection, the connection The recommended layout for the AD7276/AD7277/AD7278 is should still be made at only one point, a star ground point established as close as possible to the ground pin on the outlined in the evaluation board documentation. The evaluation AD7276/AD7277/AD7278. board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board Avoid running digital lines under the device because this from the PC via the evaluation board controller. To demonstrate/ couples noise onto the die. However, the analog ground plane evaluate the ac and dc performance of the AD7276/AD7277, should be allowed to run under the AD7276/AD7277/AD7278 the evaluation board controller can be used in conjunction with to avoid noise coupling. The power supply lines to the AD7276/ the AD7276/AD7277 evaluation board, as well as with many AD7277/AD7278 should use as large a trace as possible to provide other Analog Devices evaluation boards ending in the CB low impedance paths and reduce the effects of glitches on the designator, power supply line. The software allows the user to perform ac (fast Fourier To avoid radiating noise to other sections of the board, transform) and dc (histogram of codes) tests on the AD7276/ components with fast-switching signals, such as clocks, should AD7277. The software and documentation are on a CD shipped be shielded with digital ground, and they should never be run with the evaluation board. near the analog inputs. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough within the board, traces on opposite sides of the board should run at right angles to each other. A microstrip technique is by far the best method, but it is not always possible to use this approach with a double- sided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the solder side. Rev. D | Page 25 of 28

AD7276/AD7277/AD7278 Data Sheet OUTLINE DIMENSIONS 2.90 BSC 6 5 4 2.80 BSC 1.60 BSC 1 2 3 PIN 1 INDICATOR 0.95 BSC 1.90 BSC *0.90 0.87 0.84 0.20 *1.00 MAX 0.08 0.10 MAX SEATING 8° 0.60 0.50 PLANE 4° 0.45 0.30 0° 0.30 *CTOHEM PELXICAENPTT TIOON J OEDFE PCA SCTKAANGDEA HREDISG HMTO A-1N9D3- TAHAICWKINTHESS. 102808-A Figure 37. 6-Lead Thin Small Outline Transistor Package [TSOT] (UJ-6) Dimensions shown in millimeters 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN1 IDENTIFIER 0.65BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L5ANARITY 0.25 0° 0.09 0.40 0.10 B COMPLIANTTOJEDECSTANDARDSMO-187-AA 100709- Figure 38. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. D | Page 26 of 28

Data Sheet AD7276/AD7277/AD7278 ORDERING GUIDE Temperature Linearity Package Model1, 2 Notes Range Error (LSB)3 Package Description Option Branding AD7276BRM −40°C to +125°C ±1 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C1W AD7276BRMZ −40°C to +125°C ±1 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C30 AD7276BRMZ-REEL −40°C to +125°C ±1 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C30 AD7276BUJZ-REEL7 −40°C to +125°C ±1 max 6-Lead Thin Small Outline Transistor Package UJ-6 C30 (TSOT) AD7276BUJZ-500RL7 −40°C to +125°C ±1 max 6-Lead Thin Small Outline Transistor Package UJ-6 C30 (TSOT) AD7276YUJZ-500RL7 −40°C to +125°C ±1 max 6-Lead Thin Small Outline Transistor Package UJ-6 C4W (TSOT) AD7276YUJZ-REEL7 −40°C to +125°C ±1 max 6-Lead Thin Small Outline Transistor Package UJ-6 C4W (TSOT) AD7276ARMZ −40°C to +125°C ±1.5 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C6S AD7276ARMZ-REEL −40°C to +125°C ±1.5 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C6S AD7276AUJZ-500RL7 −40°C to +125°C ±1.5 max 6-Lead Thin Small Outline Transistor Package UJ-6 C6S (TSOT) AD7276AUJZ-REEL7 −40°C to +125°C ±1.5 max 6-Lead Thin Small Outline Transistor Package UJ-6 C6S (TSOT) AD7277BRMZ −40°C to +125°C ±0.5 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C31 AD7277BRMZ-REEL −40°C to +125°C ±0.5 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C31 AD7277BUJZ-500RL7 −40°C to +125°C ±0.5 max 6-Lead Thin Small Outline Transistor Package UJ-6 C31 (TSOT) AD7277BUJZ-REEL7 −40°C to +125°C ±0.5 max 6-Lead Thin Small Outline Transistor Package UJ-6 C31 (TSOT) AD7277ARMZ −40°C to +125°C ±0.5 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C6T AD7277ARMZ-RL −40°C to +125°C ±0.5 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C6T AD7277AUJZ-500RL7 −40°C to +125°C ±0.5 max 6-Lead Thin Small Outline Transistor Package UJ-6 C6T (TSOT) AD7278BRMZ −40°C to +125°C ±0.3 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C32 AD7278BRMZ-REEL −40°C to +125°C ±0.3 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C32 AD7278BUJZ-500RL7 −40°C to +125°C ±0.3 max 6-Lead Thin Small Outline Transistor Package UJ-6 C32 (TSOT) AD7278BUJZ-REEL7 −40°C to +125°C ±0.3 max 6-Lead Thin Small Outline Transistor Package UJ-6 C32 (TSOT) AD7278ARMZ −40°C to +125°C ±0.3 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C6U AD7278ARMZ-RL −40°C to +125°C ±0.3 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C6U AD7278AUJZ-500RL7 −40°C to +125°C ±0.3 max 6-Lead Thin Small Outline Transistor Package UJ-6 C6U (TSOT) EVAL-AD7276SDZ Evaluation Board EVAL-CONTROL BRD2 Control Board 1 Z = RoHS Compliant Part. 2 For Y grade devices, f = 1 MSPS. SAMPLE 3 Linearity error refers to integral nonlinearity. Rev. D | Page 27 of 28

AD7276/AD7277/AD7278 Data Sheet NOTES ©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04903-0-7/15(D) Rev. D | Page 28 of 28