3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT AD7273/AD7274 FEATURES FUNCTIONAL BLOCK DIAGRAM Throughput rate: 3 MSPS VDD AGND Specified for V of 2.35 V to 3.6 V DD Power consumption 11.4 mW at 3 MSPS with 3 V supplies 10-/12-BIT Wide input bandwidth SUCCESSIVE VIN T/H APPROXIMATION 70 dB SNR at 1 MHz input frequency ADC Flexible power/serial clock speed management VREF No pipeline delays High speed serial interface SCLK SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Temperature range: −40°C to +125°C CONTROL SDATA LOGIC Power-down mode: 0.1 μA typ CS 8-lead TSOT package AD7273/AD7274 8 -lead MSOP package DGND 04973-001 Figure 1. GENERAL DESCRIPTION Table 1. The AD7273/AD7274 are 10-/12-bit, high speed, low power, Part Number Resolution Package successive approximation ADCs, respectively. The parts operate AD72731 10 8-lead MSOP 8-Lead TSOT from a single 2.35 V to 3.6 V power supply and feature AD72741 12 8-lead MSOP 8-Lead TSOT throughput rates of up to 3 MSPS. Each part contains a low AD7276 12 8-lead MSOP 6-Lead TSOT noise, wide bandwidth track-and-hold amplifier that can handle AD7277 10 8-lead MSOP 6-Lead TSOT input frequencies in excess of 55 MHz. AD7278 8 8-lead MSOP 6-Lead TSOT The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface 1 Parts contain external reference pin. with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, and the conversion is also initiated at this PRODUCT HIGHLIGHTS point. The conversion rate is determined by the SCLK. There 1. 3 MSPS ADCs in an 8-lead TSOT package. are no pipeline delays associated with these parts. 2. High throughput with low power consumption. The AD7273/AD7274 use advanced design techniques to achieve very low power dissipation at high throughput rates. 3. Flexible power/serial clock speed management. Allows maximum power efficiency at low throughput rates. The reference for the parts is applied externally and can be in the range of 1.4 V to V . This allows the widest dynamic input DD 4. Reference can be driven up to the power supply. range to the ADC. 5. No pipeline delay. 6. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

AD7273/AD7274 TABLE OF CONTENTS Features..............................................................................................1 ADC Transfer Function.............................................................15 General Description.........................................................................1 Typical Connection Diagram.......................................................16 Functional Block Diagram..............................................................1 Analog Input...............................................................................16 Product Highlights...........................................................................1 Digital Inputs..............................................................................16 Revision History...............................................................................2 Modes of Operation.......................................................................17 Specifications.....................................................................................3 Normal Mode..............................................................................17 AD7274 Specifications.................................................................3 Partial Power-Down Mode.......................................................17 AD7273 Specifications.................................................................5 Full Power-Down Mode............................................................17 Timing Specifications..................................................................7 Power-Up Times.........................................................................18 Timing Examples..........................................................................8 Power vs. Throughput Rate.......................................................20 Absolute Maximum Ratings............................................................9 Serial Interface................................................................................21 ESD Caution..................................................................................9 Microprocessor Interfacing.......................................................23 Pin Configurations and Function Descriptions.........................10 Application Hints...........................................................................24 Typical Performance Characteristics...........................................11 Grounding and Layout..............................................................24 Terminology....................................................................................14 Evaluating the AD7273/AD7274 Performance.........................24 Circuit Information........................................................................15 Outline Dimensions.......................................................................25 Converter Operation..................................................................15 Ordering Guide..........................................................................25 REVISION HISTORY 9/05—Revision 0: Initial Version Rev. 0 | Page 2 of 28

AD7273/AD7274 SPECIFICATIONS AD7274 SPECIFICATIONS V = 2.35 V to 3.6 V, V = 2.35 V to V , f = 48 MHz, f = 3 MSPS, T = T to T , unless otherwise noted. DD REF DD SCLK SAMPLE A MIN MAX Table 2. Parameter B Grade1 Unit2 Test Conditions/Comments DYNAMIC PERFORMANCE f = 1 MHz sine wave IN Signal-to-Noise + Distortion (SINAD)3 68 dB min Signal-to-Noise Ratio (SNR) 69.5 dB min Total Harmonic Distortion (THD)3 −73 dB max −78 dB typ Peak Harmonic or Spurious Noise (SFDR)3 −80 dB typ Intermodulation Distortion (IMD) Second-Order Terms −82 dB typ fa = 1 MHz, fb = 0.97 MHz Third-Order Terms −82 dB typ fa = 1 MHz, fb = 0.97 MHz Aperture Delay 5 ns typ Aperture Jitter 18 ps typ Full Power Bandwidth 55 MHz typ @ 3 dB 8 MHz typ @ 0.1 dB Power Supply Rejection Ratio (PSRR) 82 dB typ DC ACCURACY Resolution 12 Bits Integral Nonlinearity3 ±1 LSB max Differential Nonlinearity3 ±1 LSB max Guaranteed no missed codes to 12 bits Offset Error3 ±3 LSB max Gain Error3 ±3.5 LSB max Total Unadjusted Error (TUE)3 ±3.5 LSB max ANALOG INPUT Input Voltage Range 0 to V V REF DC Leakage Current ±1 μA max −40°C to +85°C ±5.5 μA max 85°C to 125°C Input Capacitance 42 pF typ When in track 10 pF typ When in hold REFERENCE INPUT V Input Voltage Range 1.4 to V V min/V max REF DD DC leakage Current ±1 μA max Input Capacitance 20 pF typ Input Impedance 32 Ω typ LOGIC INPUTS Input High Voltage, V 1.7 V min 2.35 V ≤ V ≤ 2.7 V INH DD 2 V min 2.7 V < V ≤ 3.6 V DD Input Low Voltage, V 0.7 V max 2.35 V ≤ V < 2.7 V INL DD 0.8 V max 2.7 V ≤ V ≤ 3.6 V DD Input Current, I ±1 μA max Typically 10 nA, V = 0 V or V IN IN DD Input Capacitance, C 4 2 pF max IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V min I = 200 μA, V = 2.35 V to 3.6 V OH DD SOURCE DD Output Low Voltage, V 0.2 V max I = 200 μA OL SINK Floating-State Leakage Current ±2.5 μA max Floating-State Output Capacitance4 4.5 pF max Output Coding Straight (natural) binary Rev. 0 | Page 3 of 28

AD7273/AD7274 Parameter B Grade1 Unit2 Test Conditions/Comments CONVERSION RATE Conversion Time 291 ns max 14 SCLK cycles with SCLK at 48 MHz Track-and-Hold Acquisition Time3 60 ns max Throughput Rate 3 MSPS max See the Serial Interface section POWER RQUIREMENTS V 2.35/3.6 V min/V max DD I Digital I/Ps = 0 V or V DD DD Normal Mode (Static) 1 mA typ V = 3 V, SCLK on or off DD Normal Mode (Operational) 5 mA max V = 2.35 V to 3.6 V, f = 3 MSPS DD SAMPLE 3.8 mA typ V = 3 V DD Partial Power-Down Mode (Static) 34 μA typ Full Power-Down Mode (Static) 2 μA max −40°C to +85°C, typically 0.1 μA 10 μA max 85°C to 125°C Power Dissipation5 Normal Mode (Operational) 18 mW max V = 3.6 V , f = 3 MSPS DD SAMPLE 11.4 mW typ V = 3 V DD Partial Power-Down 102 μW max V = 3 V DD Full Power-Down 7.2 μW max V = 3.6 V, −40°C to +85°C DD 1 Temperature range from −40°C to +125°C. 2 Typical specifications are tested with VDD = 3 V and VREF = 3 V at 25°C. 3 See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section. Rev. 0 | Page 4 of 28

AD7273/AD7274 AD7273 SPECIFICATIONS V = 2.35 V to 3.6 V, V = 2.35 V to V , f = 48 MHz, f = 3 MSPS, T = T to T , unless otherwise noted. DD REF DD SCLK SAMPLE A MIN MAX Table 3. Parameter B Grade1 Unit2 Test Conditions/Comments DYNAMIC PERFORMANCE f = 1 MHz sine wave IN Signal-to-Noise + Distortion (SINAD)3 61 dB min Total Harmonic Distortion (THD)3 −72 dB max −77 dB typ Peak Harmonic or Spurious Noise (SFDR)3 −80 dB typ Intermodulation Distortion (IMD) Second-Order Terms −81 dB typ fa = 1 MHz, fb = 0.97 MHz Third-Order Terms −81 dB typ fa = 1 MHz, fb = 0.97 MHz Aperture Delay 5 ns typ Aperture Jitter 18 ps typ Full Power Bandwidth 74 MHz typ @ 3 dB 10 MHz typ @ 0.1 dB Power Supply Rejection Ratio (PSRR) 82 dB typ DC ACCURACY Resolution 10 Bits Integral Nonlinearity3 ±0.5 LSB max Differential Nonlinearity3 ±0.5 LSB max Guaranteed no missed codes to 10 bits Offset Error3 ±1 LSB max Gain Error3 ±1.5 LSB max Total Unadjusted Error (TUE)3 ±2.5 LSB max ANALOG INPUT Input Voltage Range 0 to V V REF DC Leakage Current ±1 μA max −40°C to +85°C ±5.5 μA max 85°C to 125°C Input Capacitance 42 pF typ When in track 10 pF typ When in hold REFERENCE INPUT V Input Voltage Range 1.4 to V V min/V max REF DD DC leakage Current ±1 μA max Input Capacitance 20 pF typ Input Impedance 32 Ω typ LOGIC INPUTS Input High Voltage, V 1.7 V min 2.35 V ≤ V ≤ 2.7 V INH DD 2 V min 2.7 V < V ≤ 3.6 V DD Input Low Voltage, V 0.7 V max 2.35 V ≤ V < 2.7 V IN DD 0.8 V max 2.7 V ≤ V ≤ 3.6 V DD Input Current, I ±1 μA max Typically 10 nA, V = 0 V or V IN IN DD Input Capacitance, C 4 2 pF max IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V min I = 200 μA; V = 2.35 V to 3.6 V OH DD SOURCE DD Output Low Voltage, V 0.2 V max I = 200 μA OL SINK Floating-State Leakage Current ±2.5 μA max Floating-State Output Capacitance4 4.5 pF max Output Coding Straight (natural) binary CONVERSION RATE Conversion Time 250 ns max 12 SCLK cycles with SCLK at 48 MHz Track-and-Hold Acquisition Time3 60 ns max Throughput Rate 3.45 MSPS max See the Serial Interface section Rev. 0 | Page 5 of 28

AD7273/AD7274 Parameter B Grade1 Unit2 Test Conditions/Comments POWER RQUIREMENTS V 2.35/3.6 V min/V max DD I Digital I/Ps = 0 V or V DD DD Normal Mode (Static) 0.6 mA typ V = 3 V, SCLK on or off DD Normal Mode (Operational) 5 mA max V = 2.35 V to 3.6 V, f = 3 MSPS DD SAMPLE 3.2 mA typ V = 3 V DD Partial Power-Down Mode (Static) 34 μA typ Full Power-Down Mode (Static) 2 μA max −40°C to +85°C, typically 0.1 μA 10 μA max 85°C to 125°C Power Dissipation5 Normal Mode (Operational) 18 mW max V = 3.6 V , f = 3 MSPS DD SAMPLE 9.6 mW typ V = 3 V DD Partial Power-Down 102 μW max V = 3 V DD Full Power-Down 7.2 μW max V = 3.6 V, −40°C to +85°C DD 1 Temperature range from −40°C to +125°C. 2 Typical specifications are tested with VDD = 3 V and VREF = 3 V at 25°C. 3 See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section. Rev. 0 | Page 6 of 28

AD7273/AD7274 TIMING SPECIFICATIONS V = 2.35 V to 3.6 V; V = 2.35 to V ; T = T to T , unless otherwise noted.1 Guaranteed by characterization. All input signals DD REF DD A MIN MAX are specified with tr = tf = 2 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. DD Table 4. Limit at T , T MIN MAX Parameter AD7273/AD7274 Unit Description f 2 500 kHz min3 SCLK 48 MHz max t 14 × t AD7274 CONVERT SCLK 12 × t AD7273 SCLK t 4 ns min Minimum quiet time required between bus relinquish and start of QUIET next conversion t 3 ns min Minimum CS pulse width 1 t 6 ns min CS to SCLK setup time 2 t 4 4 ns max Delay from CS until SDATA three-state disabled 3 t4 15 ns max Data access time after SCLK falling edge 4 t 0.4 t ns min SCLK low pulse width 5 SCLK t 0.4 t ns min SCLK high pulse width 6 SCLK t4 5 ns min SCLK to data valid hold time 7 t 14 ns max SCLK falling edge to SDATA three-state 8 5 ns min SCLK falling edge to SDATA three-state t 4.2 ns max CS rising edge to SDATA three-state 9 t 5 1 μs max Power-up time from full power-down POWER-UP 1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Minimum fSCLK at which specifications are guaranteed. 4 The time required for the output to cross the VIH or VIL voltage. 5 See the Power-Up Times section t 4 t 8 SCLK SCLK VIH SDATA VIL 04973-002 SDATA 1.4V 04973-004 Figure 2. Access Time After SCLK Falling Edge Figure 4. SCLK Falling Edge SDATA Three-State t 7 SCLK VIH SDATA VIL 04973-003 Figure 3. Hold Time After SCLK Falling Edge Rev. 0 | Page 7 of 28

AD7273/AD7274 TIMING EXAMPLES Timing Example 2 For the AD7274, if CS is brought high during the 14th SCLK The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz, rising edge after the two leading zeros and 12 bits of the and the throughput is 2.97 MSPS. This produces a cycle time conversion are provided, the part can achieve the fastest of t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns min and throughput rate, 3 MSPS. If CS is brought high during the 16th tACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) + t + t , where t = 14 ns max. This satisfies the minimum SCLK rising edge after the two leading zeros, 12 bits of the 8 QUIET 8 requirement of 4 ns for t conversion, and two trailing zeros are provided, a throughput QUIET. rate of 2.97 MSPS is achievable. This is illustrated in the following two timing examples. Timing Example 1 In Figure 6, using a 14 SCLK cycle, f = 48 MHz, and SCLK the throughput is 3 MSPS. This produces a cycle time of t + 12.5(1/f ) + t = 333 ns, where t = 6 ns min and 2 SCLK ACQ 2 t = 67 ns. This satisfies the requirement of 60 ns for t . ACQ ACQ Figure 6 also shows that t comprises 0.5(1/f ) + t + t , ACQ SCLK 9 QUIET where t = 4.2 ns max. This allows a value of 52.8 ns for t , 9 QUIET satisfying the minimum requirement of 4 ns. t 1 CS t CONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t3 t4 t7 t5 t8 tQUIET SDATA Z ZERO DB11 DB10 DB9 DB1 DB0 ZERO ZERO THREE- THREE-STATE STATE TWO LEADING TWO TRAILING ZEROS 1/THROUGHPUT ZEROS 04973-005 Figure 5. AD7274 Serial Interface Timing 16 SCLK Cycle t 1 CS t CONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 t 5 t3 t4 t7 t9 tQUIET SDATA Z ZERO DB11 DB10 DB9 DB1 DB0 THREE- THREE-STATE STATE TWO LEADING ZEROS 1/THROUGHPUT 04973-006 Figure 6.AD7274 Serial Interface Timing 14 SCLK Cycle t 1 CS t CONVERT t2 B SCLK 1 2 3 4 5 12 13 14 15 16 t 8 t QUIET 12.5(1/fSCLK) 1/THROUGHPUT tACQUISITION 04973-007 Figure 7. Serial Interface Timing 16 SCLK Cycle Rev. 0 | Page 8 of 28

AD7273/AD7274 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 5. Stresses above those listed under Absolute Maximum Ratings Parameters Ratings may cause permanent damage to the device. This is a stress V to AGND/DGND −0.3 V to +6 V DD rating only; functional operation of the device at these or any Analog Input Voltage to AGND −0.3 V to V + 0.3 V DD other conditions above those indicated in the operational Digital Input Voltage to DGND −0.3 V to +6 V section of this specification is not implied. Exposure to absolute Digital Output Voltage to DGND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect Input Current to Any Pin Except Supplies1 ±10 mA device reliability. Operating Temperature Range Commercial (B Grade) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 6-Lead TSOT Package θ Thermal Impedance 230°C/W JA θ Thermal Impedance 92°C/W JC 8-Lead MSOP Package θ Thermal Impedance 205.9°C/W JA θ Thermal Impedance 43.74°C/W JC Lead Temperature Soldering Reflow (10 to 30 sec) 255°C Lead Temperature Soldering Reflow (10 to 30 sec) 260°C ESD 1.5 kV 1 Transient currents of up to 100 mA cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 9 of 28

AD7273/AD7274 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 8 VIN VDD 1 AD7273/ 8 AGND AD7273/ SDATA 2 7 CS SDATA 2 7 DGND AD7274 AGNCDS 34 (NAToOtD Pto7 V 2SIEc7aW4le) 56 SVRCELFK04973-008 DGVNIDN 34 (NToOt Pto V SIEcaWle) 65 SVCRELFK04973-009 Figure 8. 8-Lead MSOP Pin Configuration Figure 9. 8-Lead TSOT Pin Configuration Table 6. Pin Function Descriptions Pin No. MSOP TSOT Mnemonic Description 1 1 V Power Supply Input. The V range for the AD7273/AD7274 is from 2.35 V to 3.6 V. DD DD 2 2 SDATA Data Out. Logic output. The conversion result from the AD7273/AD7274 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7274 consists of two leading zeros followed by the 12 bits of conversion data and two trailing zeros, provided MSB first. The data stream from the AD7273 consists of two leading zeros followed by the 10 bits of conversion data and four trailing zeros, provided MSB first. 3 7 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversion on the AD7273/AD7274 and framing the serial data transfer. 4 8 AGND Analog Ground. Ground reference point for all circuitry on the AD7273/AD7274. All analog signals and any external reference signal should be referred to this AGND voltage. 5 5 V Voltage Reference Input. This pin becomes the reference voltage input. An external reference should REF be applied at this pin. The external reference input range is 1.4 V to V . A 10 μF capacitor should be DD tied between this pin and AGND. 6 6 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of AD7273/AD7274. 7 3 DGND Digital Ground. Ground reference point for all digital circuitry on the AD7273/AD7274. The DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 8 4 V Analog Input. Single-ended analog input channel. The input range is 0 to V . IN REF Rev. 0 | Page 10 of 28

AD7273/AD7274 TYPICAL PERFORMANCE CHARACTERISTICS 72.2 –20 16384 POINT FFT VDD = 3V FSAMPLE = 3MSPS FSAMPLE = 3MSPS 72.0 FSIINN A= D1 M= H7z1.05 71.8 VDD = 2.5V –40 THD =–80.9 VDD = 3.6V SFDR =–82.2 71.6 SNR (dB) ––6800 SNR (dB) 777111...420 70.8 –100 70.6 70.4 –120 70.2 0 100 200 300 400 500FR600EQU700ENC800Y (k900Hz)1000 1100 1200 1300 1400 1500 04973-010 100 INPUT FREQUENCY (kHz) 1000 150004973-013 Figure 10. AD7274 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz Figure 13. AD7274 SNR vs. Analog Input Frequency at 3 MSPS for Various Supply Voltages, SCLK Frequency = 48 MHz –72 –20 16384 POINT FFT FSAMPLE = 3MSPS –74 FIN = 1MHz SINAD = 66.56 –76 –40 THD =–77.4 VDD = 3V SFDR =–78.2 –78 SNR (dB) –60 THD (dB) ––8802 VDD = 2.5V –80 –84 –100 –86 VDD = 3.6V –88 –120 –90 0 100 200 300 400 500FR600EQU700ENC800Y (k900Hz)1000 1100 1200 1300 1400 1500 04973-011 100 INPUT FREQUENCY (kHz) 1000 150004973-014 Figure 11. AD7273 Dynamic Performance at 3 MSP, Input Tone = 1 MHz Figure 14. THD vs. Analog Input Frequency at 3 MSPS for Various Supply Voltages, SCLK Frequency = 48 MHz 72.2 –40 72.0 FSAMPLE = 3MSPS 71.8 71.6 –50 71.4 VDD = 3.6V 71.2 71.0 RIN = 100Ω dB) 70.8 B) –60 AD ( 70.6 D (d SIN 70.4 TH –70 70.2 70.0 VDD = 2.5V RIN = 10Ω 69.8 69.6 –80 6699..42 VDD = 3V RIN = 0Ω 69.0 –90 100 INPUT FREQUENCY (kHz) 1000 150004973-012 100 INPUT FREQUENCY (kHz) 1000 150004973-015 Figure 12. AD7274 SINAD vs. Analog Input Frequency at 3 MSPS Figure 15. THD vs. Analog Input Frequency at 3 MSPS for Various Source for Various Supply Voltages, SCLK Frequency = 48 MHz Impedance, SCLK Frequency = 48 MHz, Supply Voltage = 3 V Rev. 0 | Page 11 of 28

AD7273/AD7274 –70 1.0 0.8 0.6 –80 0.4 POSITIVE INL B) PSRR (dB) –90 L ERROR (LS –00..022 N I –0.4 NEGATIVE INL –100 –0.6 100mV p-p SINE WAVE ON AVDD –0.8 NO DECOUPLING –110 –1.0 0 500SUPP1L0Y0 0RIPPLE1 5F0R0EQUEN2C00Y0 (MHz)2500 300004973-016 1.4 1.6 1.8 2.0REF2E.2REN2C.4E V2O.L6TAG2.E8 (V)3.0 3.2 3.4 3.604973-019 Figure 16. Power Supply Rejection Ratio (PSRR) vs. Supply Ripple Figure 19. Change in INL vs. Reference Voltage, 3 V Supply Frequency Without Decoupling 1.0 1.0 VDD = 3V 0.8 0.8 0.6 0.6 POSITIVE DNL 0.4 0.4 INL ERROR (LSB) ––000...0242 DNL ERROR (LSB) ––000...0242 NEGATIVE DNL –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 500 1000 1500 C2O00D0ES2500 3000 3500 400004973-017 1.4 1.6 1.8 2.0REF2E.2REN2C.4E V2O.L6TAG2.E8 (V)3.0 3.2 3.4 3.604973-020 Figure 17. AD7274 INL Performance Figure 20. Change in DNL vs. Reference Voltage, 3 V Supply 1.0 3.60 VDD = 3V 3.40 0.8 3.20 0.6 3.00 2.80 VDD = 3V B) 0.4 mA) 2.60 DNL ERROR (LS ––000...0242 MAX CURRENT ( 22211.....4208600000 VDD = 3.6VVDD = 2.5V 1.40 –0.6 1.20 1.00 –0.8 0.80 –1.0 0.60 0 500 1000 1500 C2O00D0ES2500 3000 3500 400004973-018 0 10 SCLK2 F0REQUENC3Y0 (MHz) 40 5004973-021 Figure 18. AD7274 DNL Performance Figure 21. Maximum Current vs. Supply Voltage for Different SCLK Frequencies Rev. 0 | Page 12 of 28

AD7273/AD7274 18000 12.0 30,000 CODES 16000 14000 TS BI 11.5 ES 12000 OF F COD 10000 BERS O M 11.0 ER 8000 NU B E M V U 6000 TI N C E F 10.5 4000 F E 2000 0 10.0 2045 2046 2047CODE2048 2049 2050 04973-022 1.4 1.6 1.8 2.0 2.2 2V.R4EF (2V.6) 2.8 3.0 3.2 3.4 3.604973-023 Figure 22. Histogram of Codes for 30,000 Samples Figure 23. ENOB/SINAD vs. Reference Voltage Rev. 0 | Page 13 of 28

AD7273/AD7274 TERMINOLOGY where V is the rms amplitude of the fundamental, and V, V, Integral Nonlinearity (INL) 1 2 3 V, V, and V are the rms amplitudes of the second through the The maximum deviation from a straight line passing through 4 5 6 sixth harmonics. the endpoints of the ADC transfer function. For the AD7273/ AD7274, the endpoints of the transfer function are zero scale at Peak Harmonic or Spurious Noise (SFDR) 0.5 LSB below the first code transition and full scale at 0.5 LSB The ratio of the rms value of the next largest component in the above the last code transition. ADC output spectrum (up to f/2, excluding dc) to the rms value S of the fundamental. Normally, the value of this specification is Differential Nonlinearity (DNL) determined by the largest harmonic in the spectrum; however, The difference between the measured and the ideal 1 LSB for ADCs with harmonics buried in the noise floor, it is deter- change between any two adjacent codes in the ADC. mined by a noise peak. Offset Error Intermodulation Distortion (IMD) The deviation of the first code transition (00 . . . 000) to (00 . . . With inputs consisting of sine waves at two frequencies, fa and fb, 001) from the ideal, that is, AGND + 0.5 LSB. any active device with nonlinearities creates distortion products Gain Error at sum and difference frequencies of mfa ± nfb, where m and The deviation of the last code transition (111 . . . 110) to n = 0, 1, 2, 3, …. Intermodulation distortion terms are those for (111 . . . 111) from the ideal, that is, VREF – 1.5 LSB, after which neither m nor n are equal to zero. For example, the second- adjusting for the offset error. order terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). Total Unadjusted Error (TUE) The AD7273/AD7274 are tested using the CCIF standard in A comprehensive specification that includes gain, linearity, and which two input frequencies are used (see fa and fb in the offset errors. Specifications section). In this case, the second-order terms are Track-and-Hold Acquisition Time usually distanced in frequency from the original sine waves, and The time required for the output of the track-and-hold amplifier the third-order terms are usually at a frequency close to the input to reach its final value, within ±0.5 LSB, after the end of the frequencies. As a result, the second- and third-order terms are conversion. See the Serial Interface section for more details. specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio Signal-to-Noise + Distortion Ratio (SINAD) of the rms sum of the individual distortion products to the rms The measured ratio of signal to noise plus distortion at the amplitude of the sum of the fundamentals expressed in decibels. output of the ADC. The signal is the rms amplitude of the fundamental, and noise is the rms sum of all nonfundamental Power Supply Rejection Ratio (PSRR) signals up to half the sampling frequency (f/2), including S The ratio of the power in the ADC output at full-scale harmonics but excluding dc. The ratio is dependent on the frequency, f, to the power of a 100 mV p-p sine wave applied to number of quantization levels in the digitization process: the the ADC V supply of frequency f. DD S more levels, the smaller the quantization noise. For an ideal N-bit PSRR(dB)=10log(Pf Pf ) converter, the SINAD is S SINAD =6.02N +1.76dB where Pf is the power at frequency f in the ADC output; PfS is the power at frequency f coupled onto the ADC V supply. S DD According to this equation, the SINAD is 74 dB for a 12-bit converter and 62 dB for a 10-bit converter. However, various Aperture Delay error sources in the ADC, including integral and differential The measured interval between the leading edge of the sampling nonlinearities and internal ac noise sources, cause the measured clock and the point at which the ADC actually takes the sample. SINAD to be less than its theoretical value. Aperture Jitter Total Harmonic Distortion (THD) The sample-to-sample variation in the effective point in time at The ratio of the rms sum of harmonics to the fundamental. It is which the sample is taken. defined as: V 2 +V 2 +V 2 +V 2 +V 2 THD(dB)=20log 2 3 4 5 6 V 1 Rev. 0 | Page 14 of 28

AD7273/AD7274 CIRCUIT INFORMATION The AD7273/AD7274 are high speed, low power, 10-/12-bit, When the ADC starts a conversion, SW2 opens and SW1 moves single supply ADCs, respectively. The parts can be operated to Position B, causing the comparator to become unbalanced from a 2.35 V to 3.6 V supply. When operated from any supply (see Figure 25). The control logic and the charge redistribution voltage within this range, the AD7273/AD7274 are capable of DAC are used to add and subtract fixed amounts of charge from throughput rates of 3 MSPS when provided with a 48 MHz clock. the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the The AD7273/AD7274 provide the user with an on-chip track- conversion is complete. The control logic generates the ADC and-hold ADC and a serial interface housed in an 8-lead TSOT output code. Figure 26 shows the ADC transfer function. or an 8-lead MSOP package, which offers the user considerable space-saving advantages over alternative solutions. The serial CHARGE clock input accesses data from the part and provides the clock REDISTRIBUTION DAC source for the successive approximation ADC. The analog input range is 0 to V . An external reference in the range of 1.4 V to SAMPLING REF A CAPACITOR VDD is required by the ADC. VIN CONTROL SW1 ACQUISITION SW2 LOGIC The AD7273/AD7274 also feature a power-down option to save B PHASE pimowpleerm beentwteede nac croonssv ethrsei ostnasn. dTahred psoerwiaelr -indtoewrfna cfee aatsu dree sisc ribed in AGND VDD/2 COMPARATOR 04973-025 the Modes of Operation section. Figure 25. ADC Conversion Phase CONVERTER OPERATION ADC TRANSFER FUNCTION The AD7273/AD7274 are successive approximation ADCs The output coding of the AD7273/AD7274 is straight binary. based on a charge redistribution DAC. Figure 24 and Figure 25 The designed code transitions occur midway between show simplified schematics of the ADC. Figure 24 shows the successive integer LSB values, such as 0.5 LSB and 1.5 LSB. The ADC during its acquisition phase, where SW2 is closed, SW1 is LSB size is VREF/4,096 for the AD7274 and VREF/1,024 for the in Position A, the comparator is held in a balanced condition, AD7273. The ideal transfer characteristic for the and the sampling capacitor acquires the signal on V . AD7273/AD7274 is shown in Figure 26. IN CHARGE REDISTRIBUTION 111...111 DAC 111...110 A CSAAPMAPCLIITNOGR ODE 111...000 VIN SW1 B ACQPUHIASSITEION SW2 COLONTGRICOL ADC C 011...111 11LLSSBB == VVRREEFF//41009264 ((AADD77227743)) AGNDFigurVeD 2D4/2. ADC AcqCuOisMitPioAnR PAhTOasRe 04973-024 000000000.........0000010100V0.5LSBANALOG INPUT +VREF– 1.5LSB 04973-026 Figure 26. AD7273/AD7274 Transfer Characteristic Rev. 0 | Page 15 of 28

AD7273/AD7274 TYPICAL CONNECTION DIAGRAM on resistance of a switch. This resistor is typically about 75 Ω. Figure 27 shows a typical connection diagram for the AD7273/ Capacitor C2 is the ADC sampling capacitor and has a capacitance AD7274. An external reference must be applied to the ADC. of 32 pF typically. For ac applications, removing high frequency This reference can be in the range of 1.4 V to V . A precision DD components from the analog input signal is recommended by reference, such as the REF19x family or the ADR421, can be using a band-pass filter on the relevant analog input pin. In used to supply the reference voltage to the AD7273/AD7274. applications where harmonic distortion and signal-to-noise The conversion result is output in a 16-bit word with two leading ratio are critical, the analog input should be driven from a low zeros followed by the 12-bit or 10-bit result. The 12-bit result from impedance source. Large source impedances significantly affect the AD7274 is followed by two trailing zeros, and the 10-bit result the ac performance of the ADCs. This may necessitate the use from the AD7273 is followed by four trailing zeros. of an input buffer amplifier. The AD8021 op amp is compatible with this device; however, the choice of the op amp is a function Table 7 provides some typical performance data with various of the particular application. references under the same setup conditions for the AD7274. Table 7. AD7274 Performance (Various Voltage Reference IC) VDD AD7274 SNR Performance D1 Voltage Reference 1 MHz Input VIN R1 C2 AD780 @ 2.5 V 71.3 dB 4CpF1 D2 AD780 @ 3 V 70.1 dB CONVERSION PHASE–SWITCH OPEN REF195 70.9 dB TRACK PHASE–SWITCH CLOSED 04973-028 Figure 28. Equivalent Analog Input Circuit 3.6V SUPPLY 4.6 mA 0.1μF 10μF When no amplifier is used to drive the analog input, the source impedance should be limited to a low value. The maximum source 0V TO VREF VIN VDD impedance depends on the amount of THD that can be tolerated. INPUT The THD increases as the source impedance increases and perfor- REF195 2.5V VREF AADD77227734/ SDSACTLAK DSP/ mance degrades. Figure 14 shows a graph of the THD vs. the 10pF 0.1μF CS μC/μP analog input frequency for different source impedances when AGND/DGND using a supply voltage of 3 V and sampling at a rate of 3 MSPS. INTSEERRFIAALCE 04973-027 DIGITAL INPUTS Figure 27. AD7273/AD7274 Typical Connection Diagram The digital inputs applied to the AD7273/AD7274 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs can be applied at up to 6 V and are ANALOG INPUT not restricted by the V + 0.3 V limit of the analog inputs. For DD Figure 28 shows an equivalent circuit of the analog input example, if the AD7273/AD7274 were operated with a V of DD structure of the AD7273/AD7274. The two diodes, D1 and D2, 3 V, then 5 V logic levels could be used on the digital inputs. provide ESD protection for the analog inputs. Care must be However, it is important to note that the data output on SDATA taken to ensure that the analog input signal never exceeds the still has 3 V logic levels when V = 3 V. Another advantage of DD supply rails by more than 300 mV. Signals exceeding this value SCLK and CS not being restricted by the V + 0.3 V limit is DD cause these diodes to become forward biased and to start that power supply sequencing issues are avoided. For example, conducting current into the substrate. These diodes can unlike with the analog inputs, with the digital inputs, if CS or conduct a maximum current of 10 mA without causing SCLK are applied before V , there is no risk of latch-up. irreversible damage to the part. Capacitor C1 in Figure 28 is DD typically about 4 pF and can primarily be attributed to pin capacitance. Resistor R1 is a lumped component made up of the Rev. 0 | Page 16 of 28

AD7273/AD7274 MODES OF OPERATION The mode of operation of the AD7273/AD7274 is selected by To enter partial power-down mode, interrupt the conversion controlling the logic state of the CS signal during a conversion. process by bringing CS high between the second and 10th falling There are three possible modes of operation: normal mode, edges of SCLK, as shown in Figure 30. Once CS is brought high partial power-down mode, and full power-down mode. The in this window of SCLKs, the part enters partial power-down point at which CS is pulled high after the conversion is initiated mode, the conversion that was initiated by the falling edge of determines which power-down mode, if any, the device enters. CS is terminated, and SDATA goes back into three-state. If CS Similarly, if the device is already in power-down mode, CS can is brought high before the second SCLK falling edge, the part control whether the device returns to normal operation or remains in normal mode and does not power down. This prevents remains in power-down mode. These modes of operation are accidental power-down due to glitches on the CS line. designed to provide flexible power management options, which To exit this mode of operation and power up the AD7274/ can be chosen to optimize the power dissipation/throughput AD7273, perform a dummy conversion. On the falling edge of rate ratio for different application requirements. CS, the device begins to power up and continues to power up as NORMAL MODE long as CS is held low until after the falling edge of the 10th SCLK. This mode is intended for fastest throughput rate performance The device is fully powered up once 16 SCLKs elapse; valid data because the AD7273/AD7274 remain fully powered at all times, results from the next conversion, as shown in Figure 31. If CS is eliminating worry about power-up times. Figure 29 shows the brought high before the 10th falling edge of SCLK, the AD7274/ general diagram of the operation of the AD7273/AD7274 in AD7273 goes into full power-down mode. Therefore, although this mode. the device may begin to power up on the falling edge of CS, it powers down on the rising edge of CS as long as this occurs The conversion is initiated on the falling edge of CS as described before the 10th SCLK falling edge. in the Serial Interface section. To ensure that the part remains fully powered up at all times, CS must remain low until at least If the AD7273/AD7274 is already in partial power-down mode 10 SCLK falling edges elapse after the falling edge of CS. If CS is and CS is brought high before the 10th falling edges of SCLK, the brought high any time after the 10th SCLK falling, but before the device enters full power-down mode. For more information on 16 SCLK falling edge, the part remains powered up, but the the power-up times associated with partial power-down mode th conversion is terminated, and SDATA goes back into three-state. in various configurations, see the Power-Up Times section. For the AD7274, a minimum of 14 serial clock cycles are FULL POWER-DOWN MODE required to complete the conversion and access the complete This mode is intended for use in applications where throughput conversion result. For the AD7273, a minimum of 12 serial rates slower than those in the partial power-down mode are clock cycles are required to complete the conversion and access required, because power-up from a full power-down takes the complete conversion result. substantially longer than that from a partial power-down. This mode is suited to applications where a series of conversions CS can idle high until the next conversion or low until CS performed at a relatively high throughput rate are followed by returns high before the next conversion (effectively idling CS a long period of inactivity and thus power-down. low). Once a data transfer is complete (SDATA has returned to three-state), another conversion can be initiated after the quiet When the AD7273/AD7274 are in full power-down mode, all time, t , has elapsed by bringing CS low again. analog circuitry is powered down. To enter full power-down QUIET mode put the device into partial power-down mode by bringing PARTIAL POWER-DOWN MODE CS high between the second and 10th falling edges of SCLK. In This mode is intended for use in applications where slower the next conversion cycle, interrupt the conversion process in throughput rates are required. An example of this is when either the way shown in Figure 32 by bringing CS high before the 10th the ADC is powered down between each conversion or a series SCLK falling edge. Once CS is brought high in this window of of conversions is performed at a high throughput rate and then SCLKs, the part powers down completely. Note that it is not the ADC is powered down for a relatively long duration between necessary to complete 16 SCLKs once CS is brought high to enter these bursts of several conversions. either of the power-down modes. Glitch protection is not available when entering full power-down mode. When the AD7273/AD7274 are in partial power-down mode, all analog circuitry is powered down except the bias generation To exit full power-down mode and power up the AD7273/ circuit. AD7274 again, perform a dummy conversion, similar to when powering up from partial power-down mode. On the falling Rev. 0 | Page 17 of 28

AD7273/AD7274 edge of CS, the device begins to power up and continues to mode, the track-and-hold, which is in hold mode while the part power up until after the falling edge of the 10th SCLK as long as is powered down, returns to track mode after the first SCLK CS is held low. The power-up time required must elapse before edge is received after the falling edge of CS. This is shown as a conversion can be initiated, as shown in Figure 33. See the Point A in Figure 31. Power-Up Times section for the power-up times associated with When power supplies are first applied to the AD7273/AD7274, the AD7273/AD7274. the ADC can power up in either of the power-down modes or POWER-UP TIMES in normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before The AD7273/AD7274 has two power-down modes, partial attempting a valid conversion. Likewise, if the part is to be kept power-down and full power-down, which are described in in partial power-down mode immediately after the supplies are detail in the Modes of Operation section. This section deals applied, two dummy cycles must be initiated. The first dummy with the power-up time required when coming out of either of cycle must hold CS low until after the 10th SCLK falling edge these modes. (see Figure 29). In the second cycle, CS must be brought high To power up from partial power-down mode, one cycle is between the second and 10th SCLK falling edges (see Figure 30). required. Therefore, with a SCLK frequency of up to 48 MHz, one dummy cycle is sufficient to allow the device to power up Alternatively, if the part is to be placed into full power-down from partial power-down mode. Once the dummy cycle is mode after the supplies are applied, three dummy cycles must complete, the ADC is fully powered up and the input signal is be initiated. The first dummy cycle must hold CS low until after acquired properly. The quiet time, t , must be allowed from the 10th SCLK falling edge (see Figure 29); the second and third QUIET the point where the bus goes back into three-state after the dummy cycles place the part into full power-down mode (see dummy conversion to the next falling edge of CS. Figure 32). See also the Modes of Operation section. To power up from full power-down, approximately 1 μs should be allowed from the falling edge of CS, shown in Figure 33 as t . Note that during power-up from partial power-down POWER-UP AD7273/AD7674 CS 1 10 12 14 16 SCLK SDATA VALID DATA 04973-029 Figure 29. Normal Mode Operation Rev. 0 | Page 18 of 28

AD7273/AD7274 CS 1 2 10 16 SCLK SDATA THREE-STATE 04973-030 Figure 30. Entering Partial Power-Down Mode THE PART BEGINS THE PART IS FULLY TO POWER UP POWERED UP, SEE POWER- UP TIMES SECTION CS 1 10 16 1 16 SCLK A SDATA INVALID DATA VALID DATA 04973-031 Figure 31. Exiting Partial Power-Down Mode THE PART ENTERS THE PART BEGINS THE PART ENTERS PARTIAL POWER DOWN TO POWER UP FULL POWER DOWN CS 1 2 10 16 1 10 16 SCLK SDATA INVALID DATA THREE-STATE VALID DATA THREE-STATE 04973-032 Figure 32. Entering Full Power-Down Mode THE PART BEGINS THE PART IS TO POWER UP FULLY POWERED UP t POWER-UP CS 1 10 16 1 16 SCLK SDATA INVALID DATA VALID DATA 04973-033 Figure 33. Exiting Full Power-Down Mode Rev. 0 | Page 19 of 28

AD7273/AD7274 7.00 POWER VS. THROUGHPUT RATE VDD = 3V 6.60 Figure 34 shows the power consumption of the device in normal mode, in which the part is never powered down. By 6.20 using the power-down mode of the AD7273/AD7274 when not 5.80 performing a conversion, the average power consumption of the W) 48MHz SCLK m 5.40 ADC decreases as the throughput rate decreases. R ( E W 5.00 O Figure 35 shows that as the throughput rate is reduced, the P 4.60 device remains in its power-down state longer and the average VARIABLE SCLK power consumption over time drops accordingly. For example, 4.20 imf tohdee A wDit7h2 a7 3th/AroDu7g2h7p4u ta rrea toep oefr 2a0te0d k iSnP cSo anntdin au oSCusL sKa mofp 4li8n Mg Hz 33..4800 04973-034 (V = 3 V) and the devices are placed into power-down mode 200 400 600 800 1000 1200 1400 1600 1800 2000 DD between conversions, the power consumption is calculated as THROUGHPUT (kSPS) Figure 34. Power vs. Throughput, Normal Mode follows. The power dissipation during normal operation is 11.6 mW (V = 3 V). If the power-up time is one dummy DD cycle, that is, 333 ns, and the remaining conversion time is 7.2 6.8 VDD = 3V 290 ns, the AD7273/AD7274 can be said to dissipate 11.6 mW 6.4 for 623 ns during each conversion cycle. If the throughput rate 6.0 5.6 is 200 kSPS, the cycle time is 5 μs and the average power dissipated 5.2 during each cycle is 623/5,000 × 9.6 mW = 1.42 mW. Figure 35 4.8 W) 4.4 shows the power vs. throughput rate when using the partial m 4.0 power-down mode between conversions at 3 V. The power- R ( 3.6 E W 3.2 down mode is intended for use with throughput rates of less PO 2.8 than 600 kSPS, because at higher sampling rates there is no 2.4 2.0 power saving achieved by using the power-down mode. 1.6 1.2 00..048 04973-035 0 200 400 600 800 1000 THROUGHPUT (kSPS) Figure 35. Power vs. Throughput, Partial Power-Down Mode Rev. 0 | Page 20 of 28

AD7273/AD7274 SERIAL INTERFACE Figure 36 through Figure 38 show the detailed timing diagrams If the user considers a 14-SCLK cycle serial interface for the for serial interfacing to the AD7274 and AD7273, respectively. AD7273/AD7274, CS must be brought high after the 14th SCLK The serial clock provides the conversion clock and controls the falling edge. Then the last two trailing zeros are ignored, and transfer of information from the AD7273/AD7274 during SDATA goes back into three-state. In this case, the 3 MSPS conversion. throughput can be achieved by using a 48 MHz clock frequency. The CS signal initiates the data transfer and conversion process. CS going low clocks out the first leading zero to be read by the The falling edge of CS puts the track-and-hold into hold mode microcontroller or DSP. The remaining data is then clocked out and takes the bus out of three-state. The analog input is sampled by subsequent SCLK falling edges, beginning with the second and the conversion is initiated at this point. leading zero. Therefore, the first falling clock edge on the serial clock provides the first leading zero and clocks out the second For the AD7274, the conversion requires completing 14 SCLK leading zero. The final bit in the data transfer is valid on the 16th cycles. Once 13 SCLK falling edges have elapsed, the track-and- falling edge, because it is clocked out on the previous (15th) hold goes back into track mode on the next SCLK rising edge, falling edge. as shown in Figure 36 at Point B. If the rising edge of CS occurs before 14 SCLKs have elapsed, the conversion is terminated and In applications with a slower SCLK, it is possible to read data on the SDATA line goes back into three-state. If 16 SCLKs are each SCLK rising edge. In such cases, the first falling edge of considered in the cycle, the last two bits are zeros and SDATA SCLK clocks out the second leading zero and can be read on the returns to three-state on the 16th SCLK falling edge, as shown in first rising edge. However, the first leading zero clocked out Figure 37. when CS goes low is missed if read within the first falling edge. The 15th falling edge of SCLK clocks out the last bit and can be For the AD7273, the conversion requires completing 12 SCLK read on the 15th rising SCLK edge. cycles. Once 11 SCLK falling edges elapse, the track-and-hold goes back into track mode on the next SCLK rising edge, as If CS goes low just after one SCLK falling edge elapses, CS shown in Figure 38 at Point B. If the rising edge of CS occurs clocks out the first leading zero and can be read on the SCLK before 12 SCLKs elapse, the conversion is terminated and the rising edge. The next SCLK falling edge clocks out the second SDATA line goes back into three-state. If 16 SCLKs are leading zero and can be read on the following rising edge. considered in the cycle, the AD7273 clocks out four trailing zeros for the last four bits and SDATA returns to three-state on the 16th SCLK falling edge, as shown in Figure 38. t 1 CS t CONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 t 5 t t t7 t9 3 4 t QUIET SDATA Z ZERO DB11 DB10 DB9 DB1 DB0 THREE- THREE-STATE STATE TWOZE LREOASDING 1/THROUGHPUT 04973-036 Figure 36. AD7274 Serial Interface Timing Diagram 14 SCLK Cycle Rev. 0 | Page 21 of 28

AD7273/AD7274 t 1 CS t CONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t t t3 t4 t7 5 8 t QUIET SDATA Z ZERO DB11 DB10 DB9 DB1 DB0 ZERO ZERO THREE- THREE-STATE STATE TWO LEADING TWO TRAILING ZEROS 1/THROUGHPUT ZEROS 04973-037 Figure 37. AD7274 Serial Interface Timing Diagram 16 SCLK Cycle t 1 CS t CONVERT t2 B t6 SCLK 1 2 3 4 10 11 12 13 14 15 16 t3 t4 t5 t7 t8 tQUIET SDATA Z ZERO DB9 DB8 DB1 DB0 ZERO ZERO ZERO ZERO THREE- THREE-STATE STATE TWOZ ELREOASDING 1/THROUGHPUT FOURZE TRROASILING 04973-038 Figure 38. AD7273 Serial Interface Timing Diagram Rev. 0 | Page 22 of 28

AD7273/AD7274 MICROPROCESSOR INTERFACING Table 8. The SPORT0 Receive Configuration 1 Register (SPORT0_RCR1) AD7273/AD7274 to ADSP-BF53x Setting Description The ADSP-BF53x family of DSPs interfaces directly to the RCKFE = 1 Sample data with falling edge of RSCLK AD7273/AD7274 without requiring glue logic. The SPORT0 LRFS = 1 Active low frame signal Receive Configuration 1 register should be set up as outlined in RFSR = 1 Frame every word Table 8. IRFS = 1 Internal RFS used RLSBIT = 0 Receive MSB first AD7273/ ADSP-BF53x1 AD72741 RDTYPE = 00 Zero fill SPORT0 IRCLK = 1 Internal receive clock SCLK RCLK0 RSPEN = 1 Receive enabled DOUT DR0PRI SLEN = 1111 16-bit data-word (or can be set to 1101 for a 14-bit data-word) CS RFS0 TFSR = RFSR = 1 DIN DT0 1ADDITIONAL PINS OMITTED FOR CLARITY 04973-039 To implement the power-down modes, set SLEN to 1001 to Figure 39. Interfacing to the ADSP-BF53x issue an 8-bit SCLK burst. Rev. 0 | Page 23 of 28

AD7273/AD7274 APPLICATION HINTS GROUNDING AND LAYOUT Good decoupling is also important. All analog supplies should be decoupled with 10 μF ceramic capacitors in parallel with The printed circuit board that houses the AD7273/AD7274 0.1 μF capacitors to AGND/DGND. To achieve the best results should be designed so that the analog and digital sections are from these decoupling components, they must be placed as close separated and confined to certain areas of the board. This design as possible to the device, ideally right up against the device. The facilitates using ground planes that can be easily separated. 0.1 μF capacitors should have low effective series resistance To provide optimum shielding for ground planes, a minimum (ESR) and low effective series inductance (ESI), such as is typical etch technique is generally best. All AGND pins of the AD7273/ of common ceramic or surface-mount types of capacitors. AD7274 should be sunk into the AGND plane. Digital and Capacitors with low ESR and low ESI provide a low impedance analog ground planes should be joined in only one place. If the path to ground at high frequencies, which allows them to AD7273/AD7274 are in a system where multiple devices require handle transient currents due to internal logic switching. an AGND-to-DGND connection, the connection should be EVALUATING THE AD7273/AD7274 PERFORMANCE made at only one point, a star ground point, established as close as possible to the ground pin on the AD7273/AD7274. The recommended layout for the AD7273/AD7274 is outlined in the evaluation board documentation. The evaluation board Avoid running digital lines under the device, because this package includes a fully assembled and tested evaluation board, couples noise onto the die. However, the analog ground plane documentation, and software for controlling the board from a should be allowed to run under the AD7273/AD7274 to avoid PC via the evaluation board controller. The evaluation board noise coupling. The power supply lines to the AD7273/AD7274 controller can be used in conjunction with the AD7273/AD7274 should use as large a trace as possible to provide low impedance evaluation board, as well as many other Analog Devices evaluation paths and reduce the effects of glitches on the power supply line. boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7273/AD7274. To avoid radiating noise to other sections of the board, components with fast-switching signals, such as clocks, should The software allows the user to perform ac (fast Fourier trans- be shielded with digital ground, and they should never be run form) and dc (histogram of codes) tests on the AD7273/AD7274. near the analog inputs. Avoid crossover of digital and analog The software and documentation are on a CD shipped with the signals. To reduce the effects of feedthrough within the board, evaluation board. traces on opposite sides of the board should run at right angles to each other. A microstrip technique is by far the best method, but it is not always possible to use this approach with a double- sided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the solder side. Rev. 0 | Page 24 of 28

AD7273/AD7274 OUTLINE DIMENSIONS 2.90 BSC 3.00 BSC 8 7 6 5 1.60 BSC 2.80 BSC 8 5 1 2 3 4 3.00 4.90 PIN 1 BSC 1 BSC INDICATOR 4 0.65 BSC *0.90 1B.S9C5 PIN 1 0.87 0.65 BSC 0.84 *1.00 MAX 0.20 0.15 1.10 MAX 0.08 0.00 0.60 0.80 0.10 MAX 00..3282 SEATING 84°° 00..4350 00..3282 00..2038 80°° 00..6400 PLANE 0° COPLANARITY SEATING 0.10 PLANE *COMPLIANT TO JEDEC STANDARDS MO-193-BAWITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 40. 8-Lead Thin Small Outline Transistor Package [TSOT] Figure 41. 8-Lead Mini Small Outline Package [MSOP] (UJ-8) (RM-8) Dimensions shown in millimeters Dimensions shown in millimeters ORDERING GUIDE Temperature Linearity Package Model Range Error (LSB)1 Package Description Option Branding AD7274BRM −40°C to +125°C ±1 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C1V AD7274BRMZ2 −40°C to +125°C ±1 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C34 AD7274BRMZ-REEL2 −40°C to +125°C ±1 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C34 AD7274BUJ-500RL7 −40°C to +125°C ±1 max 8-Lead Mini Small Outline Package (MSOP) UJ-8 C1V AD7274BUJZ-500RL72 −40°C to +125°C ±1 max 8-Lead Thin Small Outline Transistor Package (TSOT) UJ-8 C34 AD7274BUJZ-REEL72 −40°C to +125°C ±1 max 8-Lead Thin Small Outline Transistor Package (TSOT) UJ-8 C34 AD7273BRMZ2 −40°C to +125°C ±0.5 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C33 AD7273BRMZ-REEL2 −40°C to +125°C ±0.5 max 8-Lead Mini Small Outline Package (MSOP) RM-8 C33 AD7273BUJ-REEL7 −40°C to +125°C ±0.5 max 8-Lead Thin Small Outline Transistor Package (TSOT) UJ-8 C1U AD7273BUJZ-500RL72 −40°C to +125°C ±0.5 max 8-Lead Thin Small Outline Transistor Package (TSOT) UJ-8 C33 EVAL-AD7274CB3 Evaluation Board EVAL-AD7273CB3 Evaluation Board EVAL-CONTROL BRD24 Control Board 1 Linearity error refers to integral nonlinearity. 2 Z = Pb-free part. 3 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes. 4 This board is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards that end in a CB designator. To order a complete evaluation kit, the particular ADC evaluation board (such as EVAL-AD7273CB/AD7274CB), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the relevant evaluation board technical note for more information. Rev. 0 | Page 25 of 28

AD7273/AD7274 NOTES Rev. 0 | Page 26 of 28

AD7273/AD7274 NOTES Rev. 0 | Page 27 of 28

AD7273/AD7274 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04973–0–9/05(0) T TTT Rev. 0 | Page 28 of 28