Differential/Single-Ended Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC Data Sheet AD7265 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual 12-bit, 3-channel ADC REF SELECT DCAPA AVDD DVDD Throughput rate: 1 MSPS Specified for VDD of 2.7 V to 5.25 V REF BUF AD7265 Power consumption 7 mW at 1 MSPS with 3 V supplies VA1 VA2 17 mW at 1 MSPS with 5 V supplies 12-BIT Pin-configurable analog inputs VVAA34 MUX T/H APSPURCOCAXEDISMCSAITVIEON DORUITVPEURTS DOUTA 12-channel single-ended inputs VA5 6-channel fully differential inputs SCLK VA6 CS 6-channel pseudo differential inputs RANGE 70 dB SINAD at 50 kHz input frequency CONTROL SGL/DIFF LOGIC A0 Accurate on-chip reference: 2.5 V A1 ±0.2% maximum at 25°C, 20 ppm/°C maximum VB1 A2 Dual conversion with read 875 ns, 16 MHz SCLK VB2 VDRIVE High speed serial interface VB3 MUX 12-BIT SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible VB4 T/H APSPURCOCXEISMSAITVIEON DORUITVPEURTS DOUTB −40°C to +125°C operation VB5 ADC Shutdown mode: 1 µA maximum VB6 32-lead LFCSP and 32-lead TQFP BUF 2G MENSPESR vAerLs iDonE,S ACDR7I2P6T6I ON AGND AGND AGND DCAPB DGND DGND 04674-001 Figure 1. The AD72651 is a dual, 12-bit, high speed, low power, successive approximation ADC that operates from a single 2.7 V to 5.25 V PRODUCT HIGHLIGHTS power supply and features throughput rates of up to 1 MSPS. The 1. Two Complete ADC Functions Allow Simultaneous device contains two ADCs, each preceded by a 3-channel Sampling and Conversion of Two Channels. multiplexer, and a low noise, wide bandwidth track-and-hold Each ADC has three fully/pseudo differential pairs, or six amplifier that can handle input frequencies in excess of 30 MHz. single-ended channels, as programmed. The conversion The conversion process and data acquisition use standard result of both channels is simultaneously available on control inputs allowing easy interfacing to microprocessors or separate data lines, or in succession on one data line if only DSPs. The input signal is sampled on the falling edge of CS; one serial port is available. conversion is also initiated at this point. The conversion time is 2. High Throughput with Low Power Consumption. determined by the SCLK frequency. The AD7265 uses advanced The AD7265 offers a 1 MSPS throughput rate with 9 mW design techniques to achieve very low power dissipation at high maximum power dissipation when operating at 3 V. throughput rates. With 5 V supplies and a 1 MSPS throughput rate, 3. The AD7265 offers both a standard 0 V to V input range the part consumes 4 mA maximum. The part also offers flexible REF and a 2 × V input range. power/throughput rate management when operating in normal REF mode, because the quiescent current consumption is so low. 4. No Pipeline Delay. The part features two standard successive approximation The analog input range for the part can be selected to be a 0 V ADCs with accurate control of the sampling instant via a CS to V (or 2 × V ) range, with either straight binary or twos REF REF input and once off conversion control. complement output coding. The AD7265 has an on-chip 2.5 V reference that can be overdriven when an external reference is 1 Protected by U.S. Patent No. 6,681,332. preferred. This external reference range is 100 mV to V . The DD AD7265 is available in 32-lead LFCSP and 32-lead TQFP. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7265 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital Inputs .............................................................................. 18 General Description ......................................................................... 1 V ............................................................................................ 18 DRIVE Functional Block Diagram .............................................................. 1 Modes of Operation ....................................................................... 19 Product Highlights ........................................................................... 1 Normal Mode .............................................................................. 19 Revision History ............................................................................... 2 Partial Power-Down Mode ....................................................... 19 Specifications ..................................................................................... 3 Full Power-Down Mode ............................................................ 20 Timing Specifications .................................................................. 5 Power-Up Times ......................................................................... 21 Absolute Maximum Ratings ............................................................ 6 Power vs. Throughput Rate ....................................................... 21 ESD Caution .................................................................................. 6 Serial Interface ................................................................................ 22 Pin Configurations and Function Descriptions ........................... 7 Microprocessor Interfacing ........................................................... 23 Typical Performance Characteristics ............................................. 9 AD7265 to ADSP-2181 .............................................................. 23 Terminology .................................................................................... 11 AD7265 to ADSP-BF531 ........................................................... 24 Theory of Operation ...................................................................... 13 AD7265 to TMS320C541 .......................................................... 24 Circuit Information .................................................................... 13 AD7265 to DSP563xx ................................................................ 25 Converter Operation .................................................................. 13 Application Hints ........................................................................... 26 Analog Input Structure .............................................................. 13 Grounding and Layout .............................................................. 26 Analog Inputs .............................................................................. 14 PCB Design Guidelines for LFCSP .......................................... 26 Analog Input Selection .............................................................. 17 Evaluating the AD7265 Performance ...................................... 26 Output Coding ............................................................................ 17 Outline Dimensions ....................................................................... 27 Transfer Functions...................................................................... 18 Ordering Guide .......................................................................... 27 REVISION HISTORY 1/2018—Rev. B to Rev. C 11/2006—Rev. 0 to Rev. A Changed CP-32-7 to CP-32-2 ...................................... Throughout Changes to Format ............................................................. Universal Changes to Figure 2 .......................................................................... 7 Changes to Reference Input/Output Section ................................. 4 Changed AD7265 to ADSP-218x Section Heading to AD7265 to Changes to Table 4 ............................................................................. 7 ADSP-2181 Section Heading ........................................................ 23 Changes to Terminology Section ................................................. 11 Changes to AD7265 to ADSP-2181 Section and Figure 43 ...... 23 Changes to Figure 24 and Differential Mode Section ............... 15 Changed AD7265 to ADSP-BF53x Section Heading to AD7265 Changes to Figure 29 ...................................................................... 16 to ADSP-BF532 Section Heading ................................................. 24 Changes to AD7265 to ADSP-BF53x Section ............................ 24 Changes to AD7265 to ADSP-BF532 Section and Figure 44 ... 24 Updated Outline Dimensions ....................................................... 27 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 27 Changes to Ordering Guide .......................................................... 27 4/2005—Revision 0: Initial Version 1/2017—Rev. A to Rev. B Changed CP-32-2 to CP-32-7 ...................................... Throughout Changes to Figure 2 .......................................................................... 7 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 27 Rev. C | Page 2 of 27

Data Sheet AD7265 SPECIFICATIONS T = T to T , V = 2.7 V to 5.25 V, f = 16 MHz, f = 1 MSPS, V = 2.7 V to 5.25 V; specifications apply using internal A MIN MAX DD SCLK S DRIVE reference or external reference = 2.5 V ± 1%, unless otherwise noted.1 Table 1. Parameter Specification Unit Test Conditions/Comments DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR)2 71 dB min f = 50 kHz sine wave; differential mode IN 69 dB min f = 50 kHz sine wave; single-ended and IN pseudo differential modes Signal-to-Noise + Distortion Ratio (SINAD)2 70 dB min f = 50 kHz sine wave; differential mode IN 68 dB min f = 50 kHz sine wave; single-ended and IN pseudo differential modes Total Harmonic Distortion (THD)2 –77 dB max f = 50 kHz sine wave; differential mode IN –73 dB max f = 50 kHz sine wave; single-ended and IN pseudo differential modes Spurious-Free Dynamic Range (SFDR)2 –75 dB max f = 50 kHz sine wave IN Intermodulation Distortion (IMD)2 fa = 30 kHz, fb = 50 kHz Second-Order Terms –88 dB typ Third-Order Terms –88 dB typ Channel-to-Channel Isolation –88 dB typ SAMPLE AND HOLD Aperture Delay3 11 ns max Aperture Jitter3 50 ps typ Aperture Delay Matching3 200 ps max Full Power Bandwidth 33/26 MHz typ at 3 dB, V = 5 V/V = 3 V DD DD 3.5/3 MHz typ at 0.1 dB, V = 5 V/V = 3 V DD DD DC ACCURACY Resolution 12 Bits Integral Nonlinearity2 ±1 LSB max ±0.5 LSB typ; differential mode ±1.5 LSB max ±0.5 LSB typ; single-ended and pseudo differential modes Differential Nonlinearity2,4 ±0.99 LSB max Differential mode −0.99/+1.5 LSB max Single-ended and pseudo differential modes Straight Binary Output Coding Offset Error ±6 LSB max Offset Error Match ±2 LSB typ Gain Error ±2.5 LSB max Gain Error Match ±0.5 LSB typ Twos Complement Output Coding Positive Gain Error ±2 LSB max Positive Gain Error Match ±0.5 LSB typ Zero Code Error ±5 LSB max Zero Code Error Match ±1 LSB typ Negative Gain Error ±2 LSB max Negative Gain Error Match ±0.5 LSB typ ANALOG INPUT5 Single-Ended Input Range 0 V to V V RANGE pin low REF 0 V to 2 × V RANGE pin high REF Pseudo Differential Input Range: V − V 6 0 to V V RANGE pin low IN+ IN− REF 2 × V V RANGE pin high REF Fully Differential Input Range: V and V V ± V /2 V V = common-mode voltage7 = V /2 IN+ IN− CM REF CM REF V and V V ± V V V = V IN+ IN− CM REF CM REF Rev. C | Page 3 of 27

AD7265 Data Sheet Parameter Specification Unit Test Conditions/Comments DC Leakage Current ±1 µA max Input Capacitance 45 pF typ When in track 10 pF typ When in hold REFERENCE INPUT/OUTPUT Reference Output Voltage8 2.5 V min/V max ±0.2% max at 25°C Long-Term Stability 150 ppm typ For 1000 hours Output Voltage Hysteresis2 50 ppm typ Reference Input Voltage Range 0.1/V V min/V max See Typical Performance Characteristics section DD DC Leakage Current ±2 µA max External reference applied to Pin D A/Pin D B CAP CAP Input Capacitance 25 pF typ D A, D B Output Impedance 10 Ω typ CAP CAP Reference Temperature Coefficient 20 ppm/°C max 10 ppm/°C typ V Noise 20 µV rms typ REF LOGIC INPUTS Input High Voltage, V 2.8 V min INH Input Low Voltage, V 0.4 V max INL Input Current, I ±15 nA typ V = 0 V or V IN IN DRIVE Input Capacitance, C 3 5 pF typ IN LOGIC OUTPUTS Output High Voltage, V V − 0.2 V min OH DRIVE Output Low Voltage, V 0.4 V max OL Floating State Leakage Current ±1 µA max Floating State Output Capacitance3 7 pF typ Output Coding Straight (natural) binary SGL/DIFF = 1 with 0 V to VREF range selected Twos complement SGL/DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × V range REF CONVERSION RATE Conversion Time 14 SCLK cycles 875 ns with SCLK = 16 MHz Track-and-Hold Acquisition Time3 90 ns max Full-scale step input; V = 5 V DD 110 ns max Full-scale step input; V = 3 V DD Throughput Rate 1 MSPS max POWER REQUIREMENTS V 2.7/5.25 V min/V max DD V 2.7/5.25 V min/V max DRIVE I Digital I/Ps = 0 V or V DD DRIVE Normal Mode (Static) 2.3 mA max V = 5.25 V DD Operational, f = 1 MSPS 4 mA max V = 5.25 V; 3.5 mA typ S DD f = 1 MSPS 3.2 mA max V = 3.6 V; 2.7 mA typ S DD Partial Power-Down Mode 500 µA max Static Full Power-Down Mode (V ) 1 µA max T = −40°C to +85°C DD A 2.8 µA max T > 85°C to 125°C A Power Dissipation Normal Mode (Operational) 21 mW max V = 5.25 V DD Partial Power-Down (Static) 2.625 mW max V = 5.25 V DD Full Power-Down (Static) 5.25 µW max V = 5.25 V, T = −40°C to +85°C DD A 1 Temperature range is −40°C to +125°C. 2 See Terminology section. 3 Sample tested during initial release to ensure compliance. 4 Guaranteed no missed codes to 12 bits. 5 VIN− or VIN+ must remain within GND/VDD. 6 VIN− = 0 V for specified performance. For full input range on VIN− pin, see Figure 28 and Figure 29. 7 For full common-mode range, see Figure 24 and Figure 25. 8 Relates to Pin DCAPA or Pin DCAPB. Rev. C | Page 4 of 27

Data Sheet AD7265 TIMING SPECIFICATIONS AV = DV = 2.7 V to 5.25 V, V = 2.7 V to 5.25 V, internal/external reference = 2.5 V, T = T to T , unless otherwise noted1. DD DD DRIVE A MAX MIN Table 2. Parameter Limit at T , T Unit Description MIN MAX f 2 1 MHz min T = −40°C to +85°C SCLK A 4 MHz min T > 85°C to 125°C A 16 MHz max t 14 × t ns max t = 1/f CONVERT SCLK SCLK SCLK 875 ns max f = 16 MHz SCLK tQUIET 30 ns min Minimum time between end of serial read and next falling edge of CS t 15/20 ns min V = 5 V/3 V, CS to SCLK setup time, T = −40°C to +85°C 2 DD A 20/30 ns min V = 5 V/3 V, CS to SCLK setup time, T > 85°C to 125°C DD A t 15 ns max Delay from CS until D A and D B are three-state disabled 3 OUT OUT t 3 36 ns max Data access time after SCLK falling edge, V = 3 V 4 DD 27 ns max Data access time after SCLK falling edge, V = 5 V DD t 0.45 t ns min SCLK low pulse width 5 SCLK t 0.45 t ns min SCLK high pulse width 6 SCLK t 10 ns min SCLK to data valid hold time, V = 3 V 7 DD 5 ns min SCLK to data valid hold time, V = 5 V DD t 15 ns max CS rising edge to D A, D B, high impedance 8 OUT OUT t 30 ns min CS rising edge to falling edge pulse width 9 t 5 ns min SCLK falling edge to D A, D B, high impedance 10 OUT OUT 50 ns max SCLK falling edge to D A, D B, high impedance OUT OUT 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Serial Interface section and Figure 41 and Figure 42. 2 Minimum SCLK for specified performance; with slower SCLK frequencies, performance specifications apply typically. 3 The time required for the output to cross 0.4 V or 2.4 V. Rev. C | Page 5 of 27

AD7265 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Stresses at or above those listed under Absolute Maximum Parameter Rating Ratings may cause permanent damage to the product. This is a V to AGND −0.3 V to +7 V stress rating only; functional operation of the product at these DD DV to DGND −0.3 V to +7 V or any other conditions above those indicated in the operational DD V to DGND −0.3 V to DV section of this specification is not implied. Operation beyond DRIVE DD V to AGND −0.3 V to AV the maximum operating conditions for extended periods may DRIVE DD AV to DV −0.3 V to +0.3 V affect product reliability. DD DD AGND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND −0.3 V to AV + 0.3 V DD ESD CAUTION Digital Input Voltage to DGND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to V + 0.3 V DRIVE V to AGND −0.3 V to AV + 0.3 V REF DD Input Current to Any Pin Except Supplies1 ±10 mA Operating Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C LFCSP/TQFP θ Thermal Impedance 108.2°C/W (LFCSP) JA 55°C/W (TQFP) θ Thermal Impedance 32.71°C/W (LFCSP) JC Lead Temperature, Soldering Reflow Temperature (10 sec to 30 sec) 255°C ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause SCR latch up. Rev. C | Page 6 of 27

Data Sheet AD7265 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DVDDVDRIVEDAOUTDGNDDBOUTSCLKCSA0 DVDDVDRIVEDAOUT DGND DBOUTSCLK CS A0 3231302928272625 32 31 30 29 28 27 26 25 DGND 1 24 A1 DGND 1 24 A1 REF SELECT 2 23 A2 REF SELECT 2 PIN 1 23 A2 DACVAPDAD 34 AD7265 2221 SRGANL/GDEIFF AVDD 3 AD7265 22 SGL/DIFF AGND 5 TOP VIEW 20 DCAPB DCAPA 4 TOP VIEW 21 RANGE AGND 6 (Not to Scale) 19 AGND AGND 5 (Not to Scale) 20 DCAPB VVAA12 78 1187 VVBB12 AGND 6 19 AGND VA1 7 18 VB1 910111213141516 VA2 8 17 VB2 N1 . O EUTTXHNEPEDSO EGSRRESODIDUPENA DOD FP. TLTHAHENEVA3 EEP VXAOA4PCFVOA5K TSAVHA6EGEVDE B6P.P VCCB5ABODV B4N UISVNSB3 EILNCOGTC MATHUTLEETD EI POPLANED TVTHIOAES. 04674-002 V9A31V0A41V1A51V2A61V3B61V4B51V5B41V6B3 04674-041 Figure 2. 32-Lead CP-32-2 Figure 3. 32-Lead SU-32-2 Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1, 29 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7265. Both DGND pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 2 REF SELECT Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference is used as the reference source for both ADC A and ADC B. In addition, Pin D A and Pin D B must be tied to CAP CAP decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7265 through the D A pin and/or the D B pin. CAP CAP 3 AV Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7265. The DD AV and DV voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a DD DD transient basis. This supply should be decoupled to AGND. 4, 20 D A, D B Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins to CAP CAP decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. The range of the external reference is dependent on the analog input range selected. 5, 6, 19 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7265. All analog input signals and any external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 7 to 12 V to V Analog Inputs of ADC A. These can be programmed as six single-ended channels or three true differential analog A1 A6 input channel pairs. See Table 6. 13 to 18 V to V Analog Inputs of ADC B. These can be programmed as six single-ended channels or three true differential analog B6 B1 input channel pairs. See Table 6. 21 RANGE Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input channels. If this pin is tied to a logic low, the analog input range is 0 V to V . If this pin is tied to a logic REF high when CS goes low, the analog input range is 2 × V . See the Analog Input Selection section for details. REF 22 SGL/DIFF Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic low selects differential operation while a logic high selects single-ended operation. See the Analog Input Selection section for details. 23 to 25 A2 to A0 Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. The pair of channels selected can be two single-ended channels or two differential pairs. The logic states of these pins need to be set up prior to the acquisition time and subsequent falling edge of CS to correctly set up the multiplexer for that conversion. See the Analog Input Selection section for further details and Table 6 for multiplexer address decoding. 26 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7265 and framing the serial data transfer. Rev. C | Page 7 of 27

AD7265 Data Sheet Pin No. Mnemonic Description 27 SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7265. This clock is also used as the clock source for the conversion process. 28, 30 D B, D A Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on OUT OUT the falling edge of the SCLK input and 14 SCLKs are required to access the data. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros followed by the 12 bits of conversion data. The data is provided MSB first. If CS is held low for 16 SCLK cycles rather than 14, then two trailing zeros appear after the 12 bits of data. If CS is held low for a further 16 SCLK cycles on either D A or D B, the data from the other ADC follows on the D pin. This allows data from a OUT OUT OUT simultaneous conversion on both ADCs to be gathered in serial format on either D A or D B using only one OUT OUT serial port. See the Serial Interface section. 31 V Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. DRIVE This pin should be decoupled to DGND. The voltage at this pin can be different than that at AV and DV but DD DD should never exceed either by more than 0.3 V. 32 DV Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7265. The DV DD DD and AV voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a DD transient basis. This supply should be decoupled to DGND. EPAD Exposed Pad. The exposed pad is located on the underside of the package. Connect the exposed pad to the ground plane of the PCB using multiple vias. Rev. C | Page 8 of 27

Data Sheet AD7265 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A –60 4096 POINT FFT INTERNAL REFERENCE –10 VDD = 5V, VDRIVE = 3V –70 FFSINA M= P2L6Ek H=z 1MSPS SINAD = 71.4dB –30 THD = –84.42dB –80 DIFFERENTIAL MODE EXTERNAL REFERENCE B) –50 R (d –90 dB) R ( S P –70 –100 –110 –90 100mV p-p SINE WAVE ON AVDD NO DECOUPLING SINGLE-ENDED MODE –1200 200 400SUP6P0L0Y R8I0P0PLE1 0F0R0EQ1U20E0NC1Y4 0(k0Hz1)600 1800 2000 04674-003 –1100 50 100 150 FR20E0QUE2N50CY (3k0H0z) 350 400 450 500 04674-006 Figure 4. PSRR vs. Supply Ripple Frequency Without Supply Decoupling Figure 7. FFT –50 1.0 VDD = 5V VDD = 5V, VDRIVE = 3V DIFFERENTIAL MODE –55 0.8 –60 0.6 –65 0.4 dB) –70 LSB) 0.2 N ( R ( O –75 O 0 ATI RR L –80 E –0.2 O L S N I –85 D –0.4 –90 –0.6 –95 –0.8 –1000 100 200 30N0OIS4E0 F0RE5Q0U0ENC60Y0 (kH7z0)0 800 900 1000 04674-004 –1.00 500 1000 1500 2C0O0D0E 2500 3000 3500 4000 04674-007 Figure 5. Channel-to-Channel Isolation Figure 8. Typical DNL 74 1.0 RANGE = 0 TO VREF VDD = 5V, VDRIVE = 3V DIFFERENTIAL MODE 0.8 72 DVDIFDF =E R5VENTIAL MODE 0.6 0.4 B) D (dB) 70 OR (LS 0.20 A R SIN VDD = 3V L ER –0.2 DIFFERENTIAL MODE N I –0.4 68 –0.6 –0.8 660 INPUT FREQ50U0ENCY (kHz) 1000 04674-005 –1.00 500 1000 1500 2C0O0D0E 2500 3000 3500 4000 04674-008 Figure 6. SINAD vs. Analog Input Frequency for Various Supply Voltages Figure 9. Typical INL Rev. C | Page 9 of 27

AD7265 Data Sheet 1.0 10000 VDD = 3V/5V INTERNAL 10000 DIFFERENTIAL 0.8 DIFFERENTIAL MODE 9000 REFERENCE CODES MODE 0.6 POSITIVE DNL 8000 B) 0.4 S7000 S E L POSITIVE INL C R ( 0.2 EN6000 O R R R R 0 U5000 E C TY –0.2 OC4000 ARI NEGATIVE INL OF NE –0.4 O. 3000 LI N –0.6 NEGATIVE DNL 2000 –0.8 1000 –1.00 0.5 1.0VREF (V)1.5 2.0 2.5 04674-009 20046 2047 2048 CODE2049 2050 04674-012 Figure 10. Linearity Error vs. VREF Figure 13. Histogram of Codes for 10k Samples in Differential Mode 12.0 10000 INTERNAL 9984 SINGLE-ENDED 11.5 9000 REFERENCE CODES MODE 11.0 8000 S R OF BIT 1100..05 SINGLEV-DEDN D= E5DV MODE ENCES76000000 E R MB 9.5 VDD = 3V UR5000 U SINGLE-ENDED MODE C N C VE 9.0 F O4000 FECTI 8.5 DIFFERVEDND T=I A3LV MODE DIFFERVEDND T=I A5LV MODE NO. O3000 EF 8.0 2000 7.5 1000 5 CODES 11 CODES 7.00 0.5 1.0 1.5 2.0VRE2F.5 (V)3.0 3.5 4.0 4.5 5.0 04674-010 20046 2047 2048 CODE2049 2050 04674-042 Figure 11. Effective Number of Bits vs. VREF Figure 14. Histogram of Codes for 10k Samples in Single-Ended Mode 2.5010 –60 DIFFERENTIAL MODE VDD = 3V/5V –65 2.5005 –70 2.5000 –75 V) dB) (F2.4995 R ( –80 VRE MR C –85 2.4990 –90 2.4985 –95 2.49800 20 40 60CUR80RENT10 L0OAD12 (0µA)140 160 180 200 04674-011 –1000 200 R4IP0P0LE FRE6Q0U0ENCY (8k0H0z) 1000 1200 04674-040 Figure 12. VREF vs. Reference Output Current Drive Figure 15. CMRR vs. Common-Mode Ripple Frequency Rev. C | Page 10 of 27

Data Sheet AD7265 TERMINOLOGY Differential Nonlinearity (DNL) Signal-to-(Noise + Distortion) Ratio (SINAD) Differential nonlinearity is the difference between the measured SINAD is the measured ratio of signal-to-(noise + distortion) at and the ideal 1 LSB change between any two adjacent codes in the output of the ADC. The signal is the rms amplitude of the the ADC. fundamental. Noise is the sum of all non-fundamental signals up to half the sampling frequency (f/2), excluding dc. The ratio is Integral Nonlinearity (INL) S dependent on the number of quantization levels in the digitization Integral nonlinearity is the maximum deviation from a straight process; the more levels, the smaller the quantization noise. The line passing through the endpoints of the ADC transfer function. theoretical signal-to-(noise + distortion) ratio for an ideal N-bit The endpoints of the transfer function are zero scale with a converter with a sine wave input is given by single (1) LSB point below the first code transition, and full scale with a 1 LSB point above the last code transition. Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB Offset Error Therefore, for a 12-bit converter, this is 74 dB. Offset error applies to straight binary output coding. It is the Total Harmonic Distortion (THD) deviation of the first code transition (00 . . . 000) to (00 . . . 001) Total harmonic distortion is the ratio of the rms sum of harmonics from the ideal (AGND + 1 LSB). to the fundamental. For the AD7265, it is defined as Offset Error Match V 2+V 2+V 2+V 2+V 2 Offset error match is the difference in offset error across all THD(dB)=20log 2 3 4 5 6 12 channels. V1 Gain Error where: Gain error applies to straight binary output coding. It is the V1 is the rms amplitude of the fundamental. deviation of the last code transition (111 . . . 110) to (111 . . . V2, V3, V4, V5, and V6 are the rms amplitudes of the second 111) from the ideal (VREF − 1 LSB) after the offset error is through the sixth harmonics. adjusted out. Gain error does not include reference error. Peak Harmonic or Spurious Noise Gain Error Match Peak harmonic, or spurious noise, is defined as the ratio of the Gain error match is the difference in gain error across all rms value of the next largest component in the ADC output 12 channels. spectrum (up to fS/2, excluding dc) to the rms value of the funda- mental. Normally, the value of this specification is determined Zero Code Error by the largest harmonic in the spectrum, but for ADCs where Zero code error applies when using twos complement output the harmonics are buried in the noise floor, it is a noise peak. coding with, for example, the 2 × VREF input range as −VREF to +VREF biased about the VREF point. It is the deviation of Channel-to-Channel Isolation the midscale transition (all 1s to all 0s) from the ideal VIN Channel-to-channel isolation is a measure of the level of crosstalk voltage (VREF). between channels. It is measured by applying a full-scale (2 × V when V = 5 V , and V when V = 3 V), 10 kHz sine Zero Code Error Match REF DD REF DD wave signal to all unselected input channels and determining Zero code error match refers to the difference in zero code error how much that signal is attenuated in the selected channel with across all 12 channels. a 50 kHz signal (0 V to V ). The result obtained is the worst- REF Positive Gain Error case across all 12 channels for the AD7265. This applies when using twos complement output coding with, Intermodulation Distortion for example, the 2 × V input range as −V to +V biased REF REF REF With inputs consisting of sine waves at two frequencies, fa and about the V point. It is the deviation of the last code transition REF fb, any active device with nonlinearities creates distortion products (011…110) to (011…111) from the ideal (+V − 1 LSB) after REF at sum, and difference frequencies of mfa ± nfb where m, n = 0, the zero code error is adjusted out. 1, 2, 3, and so on. Intermodulation distortion terms are those Track-and-Hold Acquisition Time for which neither m nor n are equal to zero. For example, the The track-and-hold amplifier returns to track mode after the second-order terms include (fa + fb) and (fa − fb), while the end of conversion. Track-and-hold acquisition time is the time third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and required for the output of the track-and-hold amplifier to reach (fa − 2fb). its final value, within ±1/2 LSB, after the end of conversion. Rev. C | Page 11 of 27

AD7265 Data Sheet The AD7265 is tested using the CCIF standard where two input Thermal Hysteresis frequencies near the top end of the input bandwidth are used. Thermal hysteresis is defined as the absolute maximum change In this case, the second-order terms are usually distanced in of reference output voltage after the device is cycled through frequency from the original sine waves, while the third-order temperature from either terms are usually at a frequency close to the input frequencies. T_HYS+ = +25°C to T to +25°C MAX As a result, the second-order and third-order terms are specified or separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms T_HYS− = +25°C to TMIN to +25°C sum of the individual distortion products to the rms amplitude It is expressed in ppm by of the sum of the fundamentals expressed in dBs. V (25°C)−V (T_HYS) Common-Mode Rejection Ratio (CMRR) V (ppm)= REF REF ×106 HYS V (25°C) CMRR is defined as the ratio of the power in the ADC output at REF full-scale frequency, f, to the power of a 100 mV p-p sine wave where: applied to the common-mode voltage of VIN+ and VIN− of VREF (25°C) is VREF at 25°C. frequency fS as VREF (T_HYS) is the maximum change of VREF at T_HYS+ or CMRR (dB) = 10 log(Pf/Pf) T_HYS−. S where: Pf is the power at frequency f in the ADC output. Pf is the power at frequency f in the ADC output. S S Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. PSRR is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see Figure 4). Rev. C | Page 12 of 27

Data Sheet AD7265 THEORY OF OPERATION CIRCUIT INFORMATION When the ADC starts a conversion (see Figure 17), SW3 opens and SW1 and SW2 move to Position B, causing the comparator The AD7265 is a fast, micropower, dual, 12-bit, single-supply, to become unbalanced. Both inputs are disconnected when the ADC that operates from a 2.7 V to a 5.25 V supply. When conversion begins. The control logic and the charge redistribution operated from either a 3 V or a 5 V supply, the AD7265 is DACs are used to add and subtract fixed amounts of charge capable of throughput rates of 1 MSPS when provided with a from the sampling capacitor arrays to bring the comparator 16 MHz clock. back into a balanced condition. When the comparator is The AD7265 contains two on-chip, differential track-and-hold rebalanced, the conversion is complete. The control logic amplifiers, two successive approximation ADCs, and a serial generates the ADC output code. The output impedances of the interface with two separate data output pins. It is housed in a sources driving the V and V pins must be matched; IN+ IN− 32-lead LFCSP or a 32-lead TQFP, offering the user considerable otherwise, the two inputs have different settling times, resulting space-saving advantages over alternative solutions. The serial in errors. clock input accesses data from the part, but also provides the clock source for each successive approximation ADC. The analog CAPACITIVE DAC input range for the part can be selected to be a 0 V to V input REF or a 2 × VREF input, configured with either single-ended or differ- B CS COMPARATOR ential analog inputs. The AD7265 has an on-chip 2.5 V reference VIN+ ASW1 SW3 CONTROL that can be overdriven when an external reference is preferred. If SW2 CS LOGIC the internal reference is to be used elsewhere in a system, then VIN– A B the output needs to be buffered first. Tsahvein AgD b7e2tw65ee anls coo fnevaetursrieosn ps.o Twheer- pdoowwenr -odpotwionn sf etaot ualrleo wis ipmowpleer- VREF CAPDAACCITIVE 04674-014 Figure 17. ADC Conversion Phase mented via the standard serial interface, as described in the Modes of Operation section. ANALOG INPUT STRUCTURE CONVERTER OPERATION Figure 18 shows the equivalent circuit of the analog input structure of the AD7265 in differential/pseudo differential modes. In single- The AD7265 has two successive approximation ADCs, each ended mode, V is internally tied to AGND. The four diodes based around two capacitive DACs. Figure 16 and Figure 17 IN− provide ESD protection for the analog inputs. Care must be show simplified schematics of one of these ADCs in acquisition taken to ensure that the analog input signals never exceed the and conversion phase, respectively. The ADC is comprised of supply rails by more than 300 mV. This causes these diodes to control logic, a SAR, and two capacitive DACs. In Figure 16 (the become forward-biased and starts conducting into the substrate. acquisition phase), SW3 is closed, SW1 and SW2 are in Position A, These diodes can conduct up to 10 mA without causing irreversible the comparator is held in a balanced condition, and the sampling damage to the part. capacitor arrays acquire the differential signal on the input. The C1 capacitors in Figure 18 are typically 4 pF and can primarily be attributed to pin capacitance. The resistors are lumped compo- CAPACITIVE DAC nents made up of the on resistance of the switches. The value of B CS COMPARATOR these resistors is typically about 100 Ω. The C2 capacitors are VIN+ ASW1 the sampling capacitors of the ADC with a capacitance of 45 pF, SW2 CS SW3 COLNOTGRICOL typically. VIN– A B For ac applications, removing high frequency components from the analog input signal is recommended by the use of an RC low- VREF CAPDAACCITIVE 04674-013 pofa s4s7 f Ωilt earn odn 1 t0h ep Fr.e lIenv aanptp alincaaltoiog nins pwuht eprien sh waritmh oonpitcim duismto rvtailoune s Figure 16. ADC Acquisition Phase and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC and can necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. Rev. C | Page 13 of 27

AD7265 Data Sheet VDD Figure 21 shows a graph of the THD vs. the analog input frequency for various supplies while sampling at 1 MSPS. In this case, the D R1 C2 source impedance is 47 Ω. VIN+ C1 D –50 FSAMPLE = 1MSPS VDD = 3V/5V –55 RANGE = 0 TO VREF VDD –60 D R1 C2 –65 VDD = 3V VIN– B) SINGLE-ENDED MODE C1 D 04674-015 THD (d ––7705 VDDIFDF =E R3VENTIAL MODE Figure 18. Equivalent Analog Input Circuit, –80 Conversion Phase—Switches Open, Track Phase—Switches Closed When no amplifier is used to drive the analog input, the source –85 VDD = 5V VDDIFDF =E R5VENTIAL MODE iimmppeeddaannccee sdheopuelndd bse o lnim thitee da mtoo luonwt voafl uTeHs.D T hthea mt caaxnim beu mto lseor-urce –900 10S0INGLEI-2NE0PN0UDTE DFR MEO3QD0U0EENCY (k4H00z) 500 600 04674-018 ated. The THD increases as the source impedance increases and Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages performance degrades. Figure 19 shows a graph of the THD vs. ANALOG INPUTS the analog input signal frequency for different source impedances in single-ended mode, while Figure 20 shows the THD vs. the The AD7265 has a total of 12 analog inputs. Each on-board analog input signal frequency for different source impedances ADC has six analog inputs that can be configured as six single- in differential mode. ended channels, three pseudo differential channels, or three fully differential channels. These can be selected as described in –50 FVSDADM =P L3EV = 1MSPS RSOURCE = 300Ω the Analog Input Selection section. –55 RANGE = 0VTO VREF Single-Ended Mode –60 The AD7265 can have a total of 12 single-ended analog input –65 channels. In applications where the signal source has high B) impedance, it is recommended to buffer the analog input before d –70 HD ( RSOURCE = 100Ω RSOURCE = 0Ω applying it to the ADC. The analog input range can be pro- T –75 RSOURCE = 47Ω grammed to be either 0 to VREF or 0 to 2 × VREF. –80 If the analog input signal to be sampled is bipolar, the internal reference of the ADC can be used to externally bias up this –85 RSOURCE = 10Ω signal to make it correctly formatted for the ADC. Figure 22 –900 100 I2N0P0UT FRE3Q0U0ENCY (k4H00z) 500 600 04674-016 sinh oswinsg ale t-yepnidceadl cmonondeec. tion diagram when operating the ADC Figure 19. THD vs. Analog Input Frequency for +2.5V Various Source Impedances, Single-Ended Mode R –60 +1.25V R 0V –65 RFVSDAADNM G=P EL3EV = = 0 1VMTSOP VSREF RSOURCE = 300Ω –1.250VV VIN 3R VA1 AD72651 R RSOURCE = 0Ω VB6 DCAPA/DCAPB –70 D (dB) –75 RSOURCE = 100Ω 0.47µF H T –80 RSOURCE = 47Ω 1ADDITIONAL PINS OMITTED FOR CLARITY. 04674-019 –85 Figure 22. Single-Ended Mode Connection Diagram RSOURCE = 10Ω –900 100 I2N0P0UT FRE3Q0U0ENCY (k4H00z) 500 600 04674-017 Figure 20. THD vs. Analog Input Frequency for Various Source Impedances, Differential Mode Rev. C | Page 14 of 27

Data Sheet AD7265 Differential Mode 3.5 TA = 25°C The AD7265 can have a total of six differential analog 3.0 input pairs. Differential signals have some benefits over single-ended E (V) 2.5 G signals, including noise immunity based on the common-mode RAN 2.0 rejection and improvements in distortion performance of the E D O device. Figure 23 defines the fully differential analog input of M 1.5 N- the AD7265. O M M 1.0 O C VREFp-p VIN+ 0.5 AD72651 COMMON VOMLOTDAEGE VREFp-p VIN– 00 0.5 1.0 1.5 2.0VRE2F.5 (V)3.0 3.5 4.0 4.5 5.0 04674-021 1ADDITIONAL PINS OMITTED FOR CLARITY. 04674-020 Figu5r.e0 24. Input Common-Mode Range vs. VREF (0 to VREF Range, VDD = 5 V) TA = 25°C Figure 23. Differential Input Definition 4.5 The amplitude of the differential signal is the difference between 4.0 the signals applied to the VIN+ and VIN− pins in each differential E (V) 3.5 pair (VIN+ − VIN−). VIN+ and VIN− should be simultaneously driven ANG 3.0 by two signals each of amplitude VREF (or 2 × VREF, depending DE R 2.5 on the range chosen) that are 180° out of phase. The amplitude O M of the differential signal is therefore (assuming the 0 to VREF ON- 2.0 range is selected) −VREF to +VREF peak-to-peak (2 × VREF), MM 1.5 O regardless of the common mode (CM). C 1.0 The common mode is the average of the two signals 0.5 and i(sV thINe+r +ef VorINe− t)h/2e voltage on which the two inputs are 00 0.5 1.0VREF (V)1.5 2.0 2.5 04674-022 centered. Figure 25. Input Common-Mode Range vs. VREF (2 × VREF Range, VDD = 5 V) This results in the span of each input being CM ± V /2. This Driving Differential Inputs REF voltage has to be set up externally, and its range varies with the Differential operation requires that V and V be simultaneously IN+ IN− reference value, V . As the value of V increases, the common- REF REF driven with two equal signals that are 180° out of phase. The mode range decreases. When driving the inputs with an amplifier, common mode must be set up externally. The common-mode the actual common-mode range is determined by the output range is determined by V , the power supply, and the particular REF voltage swing of the amplifier. amplifier used to drive the analog inputs. Differential modes of Figure 24 and Figure 25 show how the common-mode range operation with either an ac or dc input provide the best THD typically varies with V for a 5 V power supply using the 0 to performance over a wide frequency range. Because not all appli- REF V range or 2 × V range, respectively. The common mode cations have a signal preconditioned for differential operation, REF REF must be in this range to guarantee the functionality of the AD7265. there is often a need to perform single-ended-to-differential conversion. When a conversion takes place, the common mode is rejected, resulting in a virtually noise-free signal of amplitude −V to REF +V corresponding to the digital codes of 0 to 4096. If the REF 2 × V range is used, then the input signal amplitude extends REF from −2 V to +2 V after conversion. REF REF Rev. C | Page 15 of 27

AD7265 Data Sheet Using an Op Amp Pair Pseudo Differential Mode An op amp pair can be used to directly couple a differential The AD7265 can have a total of six pseudo differential pairs. In signal to one of the analog input pairs of the AD7265. The this mode, V is connected to the signal source that must have IN+ circuit configurations illustrated in Figure 26 and Figure 27 an amplitude of V (or 2 × V , depending on the range chosen) REF REF show how a dual op amp can be used to convert a single-ended to make use of the full dynamic range of the part. A dc input is signal into a differential signal for both a bipolar and unipolar applied to the V pin. The voltage applied to this input provides IN− input signal, respectively. an offset from ground or a pseudo ground for the V input. IN+ The benefit of pseudo differential inputs is that they separate The voltage applied to Point A sets up the common-mode the analog input signal ground from the ADC’s ground allowing voltage. In both diagrams, it is connected in some way to the dc common-mode voltages to be cancelled. The typical voltage reference, but any value in the common-mode range can be range for the V pin, while in pseudo differential mode, is input here to set up the common mode. The AD8022 is a IN− shown in Figure 28 and Figure 29. Figure 30 shows a connection suitable dual op amp that can be used in this configuration to diagram for pseudo differential mode. provide differential drive to the AD7265. 1.0 Take care when choosing the op amp; the selection depends on TA = 25°C the required power supply and system performance objectives. 0.8 The driver circuits in Figure 26 and Figure 27 are optimized for dc coupling applications requiring best distortion performance. 0.6 The circuit configuration shown in Figure 26 converts a unipolar, 0.4 V) single-ended signal into a differential signal. V (IN– 0.2 The differential op amp driver circuit shown in Figure 27 is configured to convert and level shift a single-ended, ground- 0 referenced (bipolar) signal to a differential signal centered at the –0.2 V level of the ADC. REF VREF 2 × VREF p4-4p0Ω 220ΩV+ 27Ω 321...7525V5VV –0.40 0.5 1.0 VRE1F.5 (V) 2.0 2.5 3.0 04674-043 GND VIN+ AD72651 Figure 28. VIN− Input Voltage Range vs. VREF in V– Pseudo Differential Mode with VDD = 3 V 220Ω 2.5 220Ω 3.75V TA = 25°C 2.5V V+ 27Ω 1.25V 2.0 VIN– DCAPA/DCAPB A V– 1.5 10kΩ 0.47µF (V)N– 1.0 1ADDITIONAL PINS OMITTED FOR CLARITY. 04674-023 VI 0.5 Figure 26. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal into a Differential Signal 0 GND 2 × VREF p4-4p0Ω 220ΩV+ 27Ω 321...7525V5VV VIN+ AD72651 –0.50 0.5 1.0 1.5 2.0VRE2F.5 (V)3.0 3.5 4.0 4.5 5.0 04674-044 Figure 29. VIN− Input Voltage Range vs. VREF in V– Pseudo Differential Mode with VDD = 5 V 220kΩ 220Ω 220Ω 32..755VV VpR–EpF AD72651 V+ 27Ω 1.25V VIN+ VIN– DCAPA/DCAPB A V– 10kΩ VIN– 20kΩ 0.47µF DVCO LINTAPGUET VREF 0.47µF Figure 27. Dual Op iAnmtop a C Diricfufeitr et1noAt CDiaoDln IUTvInOeirNptA oaLl a SPriIn NSgiSgl eOn-aMElnI TdTeEdD BFiOpRo lCaLr ASRigITnYa.l 04674-024 1ADDITIONAL PINS OMITTED FOR CLARITY. 04674-025 Figure 30. Pseudo Differential Mode Connection Diagram Rev. C | Page 16 of 27

Data Sheet AD7265 ANALOG INPUT SELECTION The channels used for simultaneous conversions are selected via the multiplexer address input pins, A0 to A2. The logic states of The analog inputs of the AD7265 can be configured as single- these pins also need to be established prior to the acquisition time; ended or true differential via the SGL/DIFF logic pin, as shown however, they can change during the conversion time, provided in Figure 31. If this pin is tied to a logic low, the analog input that the mode is not changed. If the mode is changed from fully channels to each on-chip ADC are set up as three true differen- differential to pseudo-differential, for example, then the acquisition tial pairs. If this pin is at logic high, the analog input channels to time starts again from this point. The selected input channels are each on-chip ADC are set up as six single-ended analog inputs. decoded as shown in Table 6. The required logic level on this pin needs to be established prior to the acquisition time and remain unchanged during the con- The analog input range of the AD7265 can be selected as 0 V to version time until the track-and-hold has returned to track. The VREF or 0 V to 2 × VREF via the RANGE pin. This selection is made track-and-hold returns to track on the 13th rising edge of SCLK in a similar fashion to that of the SGL/DIFF pin by setting the after the CS falling edge (see Figure 41). If the level on this pin logic state of the RANGE pin a time tacq prior to the falling edge is changed, it is recognized by the AD7265; therefore, it is of CS. Subsequent to this, the logic level on this pin can be altered necessary to keep the same logic level during acquisition and after the third falling edge of SCLK. If this pin is tied to a logic conversion to avoid corrupting the conversion in progress. low, the analog input range selected is 0 V to VREF. If this pin is tied to a logic high, the analog input range selected is 0 V to For example, in Figure 31, the SGL/DIFF pin is set at logic high 2 × V . for the duration of both the acquisition and conversion times REF so the analog inputs are configured as single ended for that OUTPUT CODING conversion (Sampling Point A). The logic level of the SGL/DIFF The AD7265 output coding is set to either twos complement or changed to low after the track-and-hold returned to track and straight binary, depending on which analog input configuration prior to the required acquisition time for the next sampling is selected for a conversion. Table 5 shows which output coding instant at Point B; therefore, the analog inputs are configured as scheme is used for each possible analog input configuration. differential for that conversion. Table 5. AD7265 Output Coding A B CS tACQ SGL/DIFF Range Output Coding 1 14 1 14 DIFF 0 V to VREF Twos complement SCLK DIFF 0 V to 2 × V Twos complement SGL/DIFF 04674-026 SGL 0 V to VREF REF Straight binary SGL 0 V to 2 × V Twos complement Figure 31. Selecting Differential or Single-Ended Configuration REF PSEUDO DIFF 0 V to V Straight binary REF PSEUDO DIFF 0 V to 2 × V Twos complement REF Table 6. Analog Input Type and Channel Selection ADC A ADC B SGL/DIFF A2 A1 A0 VIN+ VIN− VIN+ VIN− Comment 1 0 0 0 V AGND V AGND Single ended A1 B1 1 0 0 1 V AGND V AGND Single ended A2 B2 1 0 1 0 V AGND V AGND Single ended A3 B3 1 0 1 1 V AGND V AGND Single ended A4 B4 1 1 0 0 V AGND V AGND Single ended A5 B5 1 1 0 1 V AGND V AGND Single ended A6 B6 0 0 0 0 V V V V Fully differential A1 A2 B1 B2 0 0 0 1 V V V V Pseudo differential A1 A2 B1 B2 0 0 1 0 V V V V Fully differential A3 A4 B3 B4 0 0 1 1 V V V V Pseudo differential A3 A4 B3 B4 0 1 0 0 V V V V Fully differential A5 A6 B5 B6 0 1 0 1 V V V V Pseudo differential A5 A6 B5 B6 Rev. C | Page 17 of 27

AD7265 Data Sheet TRANSFER FUNCTIONS DIGITAL INPUTS The designed code transitions occur at successive integer LSB The digital inputs applied to the AD7265 are not limited by the values (1 LSB, 2 LSB, and so on). In single-ended mode, the LSB maximum ratings that limit the analog inputs. Instead, the digital size is V /4096 when the 0 V to V range is used, and the LSB inputs can be applied up to 7 V and are not restricted by the REF REF size is 2 × V /4096 when the 0 V to 2 × V range is used. In V + 0.3 V limit, as are the analog inputs. See the Absolute REF REF DD differential mode, the LSB size is 2 × V /4096 when the 0 V to Maximum Ratings section for more information. Another REF VREF range is used, and the LSB size is 4 × VREF/4096 when the advantage of the SCLK, RANGE, A0 to A2, and CS pins not 0 V to 2 × VREF range is used. The ideal transfer characteristic being restricted by the VDD + 0.3 V limit is that power supply for the AD7265 when straight binary coding is output is shown sequencing issues are avoided. If one of these digital inputs is in Figure 32, and the ideal transfer characteristic for the AD7265 applied before V , there is no risk of latch-up, as there would DD when twos complement coding is output is shown (with the 2 × be on the analog inputs if a signal greater than 0.3 V were VREF range) in Figure 33. applied prior to VDD. V DRIVE 111...111 The AD7265 also has a VDRIVE feature to control the voltage at 111...110 which the serial interface operates. V allows the ADC to DRIVE easily interface to both 3 V and 5 V processors. For example, if the AD7265 was operated with a V of 5 V, the V pin can E 111...000 DD DRIVE D CO 1LSB = VREF/4096 be powered from a 3 V supply, allowing a large dynamic range C 011...111 with low voltage digital processors. Therefore, the AD7265 can D A be used with the 2 × V input range, with a V of 5 V while REF DD still being able to interface to 3 V digital parts. 000...010 000...001 000...000 0V1LSB VREF– 1LSB ANALOG INPUT N1.O VTREEF IS EITHER VREF OR 2× VREF. 04674-027 Figure 32. Straight Binary Transfer Characteristic 1LSB = 2VREF/4096 011...111 011...110 E 000...001 D O 000...000 C C 111...111 D A 100...010 100...001 100...000 –VREF + 1LSB VREF– 1ALNSABLOG+ IVNRPEUFT– 1 LSB 04674-028 Figure 33. Twos Complement Transfer Characteristic with VREF ± VREF Input Range Rev. C | Page 18 of 27

Data Sheet AD7265 MODES OF OPERATION The mode of operation of the AD7265 is selected by controlling When 32 SCLK cycles have elapsed, the D line returns to three- OUT the (logic) state of the CS signal during a conversion. There are state on the 32nd SCLK falling edge. If CS is brought high prior three possible modes of operation: normal mode, partial power- to this, the D line returns to three-state at that point. There- OUT down mode, and full power-down mode. After a conversion is fore, CS can idle low after 32 SCLK cycles until it is brought initiated, the point at which CS is pulled high determines which high again sometime prior to the next conversion (effectively power-down mode, if any, the device enters. Similarly, if already idling CS low), if so desired, because the bus still returns to in a power-down mode, CS can control whether the device returns three-state upon completion of the dual result read. to normal operation or remains in power-down. These modes When a data transfer is complete and D A and D B have OUT OUT of operation are designed to provide flexible power management returned to three-state, another conversion can be initiated after options. These options can be chosen to optimize the power the quiet time, t , has elapsed by bringing CS low again QUIET dissipation/throughput rate ratio for differing application (assuming the required acquisition time is allowed). requirements. PARTIAL POWER-DOWN MODE NORMAL MODE This mode is intended for use in applications where slower This mode is intended for applications that need the fastest throughput rates are required. Either the ADC is powered down throughput rates because the user does not have to worry about between each conversion, or a series of conversions can be any power-up times with the AD7265 remaining fully powered performed at a high throughput rate, and the ADC is then at all times. Figure 34 shows the general diagram of the operation powered down for a relatively long duration between these of the AD7265 in this mode. bursts of several conversions. When the AD7265 is in partial power-down, all analog circuitry is powered down except for CS the on-chip reference and reference buffer. 1 10 14 SCLK To enter partial power-down mode, the conversion process must be interrupted by bringing CS high anywhere after the DDOOUUTTAB LEADING ZEROS + CONVERSION RESULT 04674-029 sSeCcLoKnd, afsa lslhinogw end igne Foifg SuCreL 3K5 a. nWdh beenf oCreS tihs eb r1o0uthg fhatl lhiniggh e ding eth oifs Figure 34. Normal Mode Operation window of SCLKs, the part enters partial power-down, the The conversion is initiated on the falling edge of CS, as described conversion that was initiated by the falling edge of CS is in the Serial Interface section. To ensure that the part remains terminated, and D A and D B go back into three-state. If OUT OUT fully powered up at all times, CS must remain low until at least CS is brought high before the second SCLK falling edge, the 10 SCLK falling edges have elapsed after the falling edge of CS. part remains in normal mode and does not power down. This If CS is brought high any time after the 10th SCLK falling edge avoids accidental power-down due to glitches on the CS line. but before the 14th SCLK falling edge, the part remains powered up, but the conversion is terminated and D A and D B go CS OUT OUT back into three-state. Fourteen serial clock cycles are required 1 2 10 14 to complete the conversion and access the conversion result. The SCLK D line does not return to three-state after 14 SCLK cycles have OUT eClSap isse ldef, tb luotw i nfostre aando dthoeesr s2o S wChLeKn c CycSl eiss b(frooru egxhat mhipglhe, aigf aoinnl.y I fa DDOOUUTTAB THREE-STATE 04674-030 Figure 35. Entering Partial Power-Down Mode 16 SCLK burst is available), two trailing zeros are clocked out after the data. If CS is left low for a further 14 (or 16) SCLK cycles, the result from the other ADC on board is also accessed on the same D line, as shown in Figure 42 (see the Serial Interface OUT section). Rev. C | Page 19 of 27

AD7265 Data Sheet To exit this mode of operation and power up the AD7265 again, When the AD7265 is in full power-down, all analog circuitry is a dummy conversion is performed. On the falling edge of CS, powered down. Full power-down is entered in a similar way as the device begins to power up and continues to power up as partial power-down, except the timing sequence shown in long as CS is held low until after the falling edge of the 10th Figure 35 must be executed twice. The conversion process must SCLK. The device is fully powered up after approximately 1 μs be interrupted in a similar fashion by bringing CS high anywhere has elapsed, and valid data results from the next conversion, as after the second falling edge of SCLK and before the 10th falling shown in Figure 36. If CS is brought high before the second edge of SCLK. The device enters partial power-down at this falling edge of SCLK, the AD7265 again goes into partial point. To reach full power-down, the next conversion cycle power-down. This avoids accidental power-up due to glitches must be interrupted in the same way, as shown in Figure 37. on the CS line. Although the device can begin to power up on When CS is brought high in this window of SCLKs, the part the falling edge of CS, it powers down again on the rising edge completely powers down. of CS. If the AD7265 is already in partial power-down mode Note that it is not necessary to complete the 14 SCLKs when CS and CS is brought high between the second and 10th falling is brought high to enter a power-down mode. edges of SCLK, the device enters full power-down mode. To exit full power-down and power up the AD7265, a dummy FULL POWER-DOWN MODE conversion is performed, as when powering up from partial power-down. On the falling edge of CS, the device begins to This mode is intended for use in applications where throughput rates slower than those in the partial power-down mode are power up and continues to power up, as long as CS is held low required, as power-up from a full power-down takes until after the falling edge of the 10th SCLK. The required power- substantially longer than that from partial power-down. This up time must elapse before a conversion can be initiated, as mode is more suited to applications where a series of shown in Figure 38. See the Power-Up Times section for the conversions performed at a relatively high throughput rate are power-up times associated with the AD7265. followed by a long period of inactivity and thus power-down. THE PART IS FULLY THE PART BEGINS POWERED UP; SEE TO POWER UP. POWER-UP TIMES tPOWER-UP1 SECTION. CS 1 10 14 1 14 SCLK DDOOUUTTAB INVALID DATA VALID DATA 04674-031 Figure 36. Exiting Partial Power-Down Mode THE PART ENTERS THE PART BEGINS THE PART ENTERS PARTIAL POWER DOWN. TO POWER UP. FULL POWER DOWN. CS 1 2 10 14 1 2 10 14 SCLK DDOOUUTTAB INVALID DATA THREE-STATE INVALID DATA THREE-STATE 04674-032 Figure 37. Entering Full Power-Down Mode Rev. C | Page 20 of 27

Data Sheet AD7265 THE PART IS FULLY POWERED UP, SEE POWER-UP TIMES SECTION. THE PART BEGINS TO POWER UP. t POWER-UP2 CS SCLK 1 10 14 1 14 DDOOUUTTAB INVALID DATA VALID DATA 04674-033 Figure 38. Exiting Full Power-Down Mode POWER-UP TIMES However, the AD7265 quiescent current is low enough that even without using the power-down options, there is a noticeable As described in detail, the AD7265 has two power-down modes, variation in power consumption with sampling rate. This is true partial power-down and full power-down. This section explains whether a fixed SCLK value is used or if it is scaled with the the power-up time required when coming out of either of these sampling rate. Figure 39 and Figure 40 show plots of power vs. modes. Note that the power-up times, as explained in this section, the throughput rate when operating in normal mode for a fixed apply with the recommended capacitors in place on the D A CAP maximum SCLK frequency, and an SCLK frequency that scales and D B pins. CAP with the sampling rate with V = 3 V and V = 5 V, respectively. DD DD To power up from full power-down (whether using an internal In all cases, the internal reference was used. or external reference), approximately 1.5 ms should be allowed 10.0 from the falling edge of CS, shown as tPOWER-UP2 in Figure 38. TA = 25°C 9.5 Powering up from partial power-down requires much less time. The power-up time from partial power-down is typically 1 μs; 9.0 however, if using the internal reference, then the AD7265 must 8.5 be in partial power-down for at least 67 μs in order for this W) 8.0 power-up time to apply. m R ( 7.5 E When power supplies are first applied to the AD7265, the ADC W 7.0 can power up in either of the power-down modes or normal mode. PO VARIABLE SCLK 16MHz SCLK 6.5 Because of this, it is best to allow a dummy cycle to elapse to 6.0 ensure that the part is fully powered up before attempting a valid conversion. Likewise, if it is intended to keep the part in 5.5 tahpep lpieadrt,i tahl epno wtweor- dduomwnm my ocydcel eims mmuesdti batee liyn iatfiateter dth. Te hsue pfpirlsite s are 5.00 100 200 300THR40O0UGH50P0UT (6k0S0PS)700 800 900 1000 04674-045 dummy cycle must hold CS low until after the 10th SCLK falling Figure 39. Power vs. Throughput in Normal Mode with VDD = 3 V edge (see Figure 34); in the second cycle, CS must be brought 25 high before the 10th SCLK edge but after the second SCLK TA = 25°C 23 falling edge (see Figure 35). Alternatively, if it is intended to 21 place the part in full power-down mode when the supplies are 19 applied, then three dummy cycles must be initiated. The first VARIABLE SCLK dummy cycle must hold CS low until after the 10th SCLK falling W) 17 m edge (see Figure 34); the second and third dummy cycles place R ( 15 E 16MHz SCLK the part in full power-down (see Figure 37). W 13 O P When supplies are applied to the AD7265, enough time must be 11 allowed for any external reference to power up and charge the 9 various reference buffer decoupling capacitors to their final values. 7 PThOeW poEwRe rv cso.n TsuHmRpOtiUonG oHf PthUe TA DR7A2T65E v aries with throughput 50 100 200 300THR40O0UGH50P0UT (6k0S0PS)700 800 900 1000 04674-046 rate. When using very slow throughput rates and as fast an Figure 40. Power vs. Throughput in Normal Mode with VDD = 5 V SCLK frequency as possible, the various power-down options can be used to make significant power savings. Rev. C | Page 21 of 27

AD7265 Data Sheet SERIAL INTERFACE Figure 41 shows the detailed timing diagram for serial inter- A minimum of 14 serial clock cycles are required to perform facing to the AD7265. The serial clock provides the conversion the conversion process and to access data from one conversion clock and controls the transfer of information from the AD7265 on either data line of the AD7265. CS going low provides the during conversion. leading zero to be read in by the microcontroller or DSP. The The CS signal initiates the data transfer and conversion process. remaining data is then clocked out by subsequent SCLK falling edges, beginning with a second leading zero. Therefore, the first The falling edge of CS puts the track-and-hold into hold mode, falling clock edge on the serial clock has the leading zero pro- at which point the analog input is sampled and the bus is taken vided and also clocks out the second leading zero. The 12-bit out of three-state. The conversion is also initiated at this point result then follows with the final bit in the data transfer valid on and requires a minimum of 14 SCLKs to complete. When the 14th falling edge, having being clocked out on the previous 13 SCLK falling edges have elapsed, the track-and-hold goes (13th) falling edge. It can also be possible to read in data on each back into track on the next SCLK rising edge, as shown in SCLK rising edge depending on the SCLK frequency or the Figure 41 at Point B. If a 16-SCLK transfer is used, then two supply voltage. The first rising edge of SCLK after the CS falling trailing zeros appear after the final LSB. On the rising edge of CS, edge would have the second leading zero provided, and the 13th the conversion is terminated and D A and D B go back into OUT OUT rising SCLK edge would have DB0 provided. three-state. If CS is not brought high but is instead held low for a further 14 (or 16) SCLK cycles on D A, the data from Note that with fast SCLK values, and thus short SCLK periods, OUT Conversion B is output on DOUTA (followed by 2 trailing zeros). to allow adequately for t2, an SCLK rising edge can occur before the first SCLK falling edge. This rising edge of SCLK can be Likewise, if CS is held low for a further 14 (or 16) SCLK cycles ignored for the purposes of the timing descriptions in this section. on D B, the data from Conversion A is output on D B. This OUT OUT If a falling edge of SCLK is coincident with the falling edge of is illustrated in Figure 42 where the case for D A is shown. In OUT CS, then this falling edge of SCLK is not acknowledged by the this case, the D line in use goes back into three-state on the OUT AD7265, and the next falling edge of SCLK is the first registered 32nd SCLK falling edge or the rising edge of CS, whichever after the falling edge of CS. occurs first. CS t 9 t2 t6 B SCLK 1 2 3 4 5 13 t t t7 t5 t8 tQUIET 3 4 DDOOUUTTAB TSHTARTEEE-2 LE0ADING0 ZEROSDB11 DB10 DB9 DB8 DB2 DB1 DB0 THREE-STATE 04674-034 Figure 41. Serial Interface Timing Diagram CS t2 t6 SCLK 1 2 3 4 5 14 15 16 17 32 t5 t10 t t t 3 4 7 DOUTATSHTARTEEE- 20 LZEEZAREDORISNOG DB11A DB10A DB9A 2 TZREARILOING ZZEERROOS2 LZEEARDOINGZ ZEERROOSDB11B Z2E TRROAILING ZZEERROOS TSHTARTEEE- 04674-035 Figure 42. Reading Data from Both ADCs on One DOUT Line with 32 SCLKs Rev. C | Page 22 of 27

Data Sheet AD7265 MICROPROCESSOR INTERFACING The serial interface on the AD7265 allows the part to be directly The connection diagram is shown in Figure 43. The ADSP-2181 connected to a range of many different microprocessors. This has the TFS0 and RFS0 of the SPORT0 and the RFS1 of SPORT1 section explains how to interface the AD7265 with some of the tied together. TFS0 is set as an output, and both RFS0 and RFS1 more common microcontroller and DSP serial interface are set as inputs. The DSP operates in alternate framing mode, protocols. and the SPORT control register is set up as described. The frame AD7265 TO ADSP-2181 synchronization signal generated on the TFS is tied to CS, and, as with all signal processing applications, equidistant sampling The ADSP-2181 family of DSPs interface directly to the AD7265 is necessary. However, in this example, the timer interrupt is without any glue logic required. The V pin of the AD7265 DRIVE used to control the sampling rate of the ADC and, under certain takes the same supply voltage as that of the ADSP-218x. This conditions, equidistant sampling may not be achieved. allows the ADC to operate at a higher supply voltage than its serial interface and, therefore, the ADSP-2181, if necessary. This AD72651 ADSP-21811 example shows both DOUTA and DOUTB of the AD7265 connected SCLK SCLK0 to both serial ports of the ADSP-2181. The SPORT0 and SCLK1 SPORT1 control registers should be set up as shown in Table 7 CS TFS0 and Table 8. RFS0 RFS1 Table 7. SPORT0 Control Register Setup Setting Description DOUTA DR0 TFSW = RFSW = 1 Alternate framing DOUTB DR1 INVRFS = INVTFS = 1 Active low frame signal VDRIVE DTYPE = 00 Right justify data SLEN = 1111 16-bit data-word (or can be set to 1101 ISCLK = 1 fInotre 1r4n-abl ist edraiatla c-wloocrkd ) 1ADDITIONAL PINS OMITTED FOR CLARITY. VDD 04674-036 TFSR = RFSR = 1 Frame every word Figure 43. Interfacing the AD7265 to the ADSP-2181 IRFS = 0 The timer registers are loaded with a value that provides an ITFS = 1 interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). Table 8. SPORT1 Control Register Setup The TFS is used to control the RFS, and hence, the reading of data. Setting Description The frequency of the serial clock is set in the SCLKDIV register. TFSW = RFSW = 1 Alternate framing When the instruction to transmit with TFS is given (AX0 = TX0), INVRFS = INVTFS = 1 Active low frame signal the state of the SCLK is checked. The DSP waits until the SCLK DTYPE = 00 Right justify data has gone high, low, and high again before transmission starts. If SLEN = 1111 16-bit data-word (or can be set to 1101 for 14-bit data-word) the timer and SCLK values are chosen such that the instruction ISCLK = 0 External serial clock to transmit occurs on or near the rising edge of SCLK, then the data may be transmitted or it may wait until the next clock edge. TFSR = RFSR = 1 Frame every word IRFS = 0 For example, the ADSP-2111 has a master clock frequency of ITFS = 1 16 MHz. If the SCLKDIV register is loaded with the value 3, then an SCLK of 2 MHz is obtained, and eight master clock To implement the power-down modes, SLEN should be set to periods elapse for every one SCLK period. If the timer registers 1001 to issue an 8-bit SCLK burst. are loaded with the value 803, then 100.5 SCLKs occur between interrupts and, subsequently, between transmit instructions. This situation yields sampling that is not equidistant, as the transmit instruction is occurring on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, then equidistant sampling is implemented by the DSP. Rev. C | Page 23 of 27

AD7265 Data Sheet AD7265 to ADSP-BF531 AD7265 TO TMS320C541 The ADSP-BF531 interfaces directly to the AD7265 without any The serial interface on the TMS320C541 uses a continuous glue logic required. The availability of secondary receive registers serial clock and frame synchronization signals to synchronize on the serial ports of the Blackfin® DSPs means only one serial the data transfer operations with peripheral devices like the port is necessary to read from both DOUT pins simultaneously. AD7265. The CS input allows easy interfacing between the Figure 44 shows both DOUTA and DOUTB of the AD7265 connected TMS320C541 and the AD7265 without any glue logic required. to Serial Port 0 of the ADSP-BF531. The SPORT0 Receive The serial ports of the TMS320C541 are set up to operate in Configuration 1 register and SPORT0 Receive Configuration 2 burst mode with internal CLKX0 (TX serial clock on Serial register should be set up as outlined in Table 9 and Table 10. Port 0) and FSX0 (TX frame sync from Serial Port 0). The serial port control registers (SPC) must have the following setup. AD72651 ADSP-BF5311 SERIAL DEVICE A SPORT0 Table 11. Serial Port Control Register Setup (PRIMARY) DOUTA DR0PRI SPC FO FSM MCM TXM SCLK RCLK0 SPC0 0 1 1 1 CS RFS0 SPC1 0 1 0 0 DOUTB DR0SEC SERIAL VDRIVE DEVICE B The format bit, FO, can be set to 1 to set the word length to (SECONDARY) 8 bits to implement the power-down modes on the AD7265. The connection diagram is shown in Figure 45. For signal proce- 1ADDITIONAL PINS OMITTED FOR CLARITY. VDD 04674-037 sssiginnga la fprpolmic atthioe nTsM, itS i3s2 im0Cp5e4ra1t ipvreo tvhidate t ehqeu firdaimstea nsyt nscahmrpolninizga.t iTohne Figure 44. Interfacing the AD7265 to the ADSP-BF531 V pin of the AD7265 takes the same supply voltage as that DRIVE Table 9. The SPORT0 Receive Configuration 1 Register of the TMS320C541. This allows the ADC to operate at a higher (SPORT0_RCR1) voltage than its serial interface, and therefore, the TMS320C541, if Setting Description necessary. RCKFE = 1 Sample data with falling edge of RSCLK AD72651 TMS320C5411 LRFS = 1 Active low frame signal SCLK CLKX0 RFSR = 1 Frame every word CLKR0 IRFS = 1 Internal RFS used CLKX1 RLSBIT = 0 Receive MSB first CLKR1 RDTYPE = 00 Zero fill IRCLK = 1 Internal receive clock DOUTA DR0 RSPEN = 1 Receive enabled DOUTB DR1 16-bit data-word (or can be set to 1101 CS FSX0 SLEN = 1111 for 14-bit data-word) FSR0 TFSR = RFSR = 1 VDRIVE FSR1 Table 10. The SPORT0 Receive Configuration 2 Register (SSePttOinRgT 0_RCR2) Description 1ADDITIONAL PINS OMITTED FOR CLARITY. VDD 04674-038 RXSE = 1 Secondary side enabled Figure 45. Interfacing the AD7265 to the TMS320C541 SLEN = 1111 16-bit data-word (or can be set to 1101 for 14-bit data-word) To implement the power-down modes, SLEN should be set to 1001 to issue an 8-bit SCLK burst. A Blackfin driver for the AD7265 is available to download at www.analog.com. Rev. C | Page 24 of 27

Data Sheet AD7265 AD7265 TO DSP563xx In the example shown in Figure 46, the serial clock is taken from the ESSI0 so the SCK0 pin must be set as an output, SCKD = 1, The connection diagram in Figure 46 shows how the AD7265 while the SCK1 pin is set as an input, SCKD = 0. The frame sync can be connected to the ESSI (synchronous serial interface) of signal is taken from SC02 on ESSI0, so SCD2 = 1, while on ESSI1, the DSP563xx family of DSPs from Motorola. There are two SCD2 = 0; therefore, SC12 is configured as an input. The V pin on-board ESSIs, and each operates in synchronous mode DRIVE of the AD7265 takes the same supply voltage as that of the (Bit SYN = 1 in CRB register) with internally generated word DSP563xx. This allows the ADC to operate at a higher voltage length frame sync for both TX and RX (Bit FSL1 = 0 and than its serial interface and therefore the DSP563xx, if necessary. Bit FSL0 = 0 in CRB). Normal operation of the ESSI is selected by making MOD = 0 AD72651 DSP563xx1 in the CRB. Set the word length to 16 by setting Bit WL1 = 1 SCLK SCK0 and Bit WL0 = 0 in CRA. SCK1 To implement the power-down modes on the AD7265, the word DOUTA SRD0 length can be changed to 8 bits by setting Bit WL1 = 0 and DOUTB SRD1 Bit WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1 CS SC02 so the frame sync is negative. It is imperative for signal processing VDRIVE SC12 applications that the frame synchronization signal from the DSP563xx provides equidistant sampling. 1ADDITIONAL PINS OMITTED FOR CLARITY. VDD 04674-039 Figure 46. Interfacing the AD7265 to the DSP563xx Rev. C | Page 25 of 27

AD7265 Data Sheet APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP The analog and digital supplies to the AD7265 are independent The lands on the chip scale package (CP-32-2) are rectangular. and separately pinned out to minimize coupling between the The PCB pad for these should be 0.1 mm longer than the analog and digital sections of the device. The printed circuit package land length, and 0.05 mm wider than the package land board (PCB) that houses the AD7265 should be designed so width, thereby having a portion of the pad exposed. To ensure that the analog and digital sections are separated and confined that the solder joint size is maximized, the land should be centered on the pad. to certain areas of the board. This design facilitates the use of ground planes that can be easily separated. The bottom of the chip scale package has a thermal pad. The To provide optimum shielding for ground planes, a minimum thermal pad on the PCB should be at least as large as the etch technique is generally best. All three AGND pins of the exposed pad. On the PCB, there should be a clearance of at least AD7265 should be sunk in the AGND plane. Digital and analog 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. ground planes should be joined in only one place. If the AD7265 is in a system where multiple devices require an AGND to DGND To improve thermal performance of the package, use thermal connection, the connection should still be made at one point vias on the PCB incorporating them in the thermal pad at only, a star ground point that should be established as close as 1.2 mm pitch grid. The via diameter should be between 0.3 mm possible to the ground pins on the AD7265. and 0.33 mm, and the via barrel should be plated with 1 oz. Avoid running digital lines under the device as this couples copper to plug the via. The user should connect the PCB thermal pad to AGND. noise onto the die. However, the analog ground plane should be allowed to run under the AD7265 to avoid noise coupling. The EVALUATING THE AD7265 PERFORMANCE power supply lines to the AD7265 should use as large a trace as The recommended layout for the AD7265 is outlined in the possible to provide low impedance paths and reduce the effects evaluation board documentation. The evaluation board package of glitches on the power supply line. includes a fully assembled and tested evaluation board, docu- To avoid radiating noise to other sections of the board, fast mentation, and software for controlling the board from the PC switching signals, such as clocks, should be shielded with digital via the evaluation board controller. The evaluation board con- ground, and clock signals should never run near the analog troller can be used in conjunction with the AD7265 evaluation inputs. Avoid crossover of digital and analog signals. To reduce board, as well as many other Analog Devices, Inc. evaluation the effects of feedthrough within the board, traces on opposite boards ending in the CB designator, to demonstrate/evaluate sides of the board should run at right angles to each other. A the ac and dc performance of the AD7265. microstrip technique is the best method but is not always The software allows the user to perform ac (fast Fourier possible with a double-sided board. In this technique, the transform) and dc (histogram of codes) tests on the AD7265. component side of the board is dedicated to ground planes, The software and documentation are on a CD shipped with the while signals are placed on the solder side. evaluation board. Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum capacitors in parallel with 0.1 µF capacitors to GND. To achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 µF capacitors should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types or surface-mount types. These low ESR and ESI capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Rev. C | Page 26 of 27

Data Sheet AD7265 OUTLINE DIMENSIONS 5.10 5.00 SQ 0.60 MAX 4.90 0.60 MAX 25 32 PIN 1 INDICATOR 24 1 0.50 PIN 1 4.75 BSC 3.25 INDICATOR BSC SQ EXPOSED 3.10 SQ PAD 2.95 17 8 0.50 16 9 0.20 MIN TOP VIEW 0.40 BOTTOM VIEW 1.00 12° MAX 0.80 MAX 0.30 3.50REF 0.65 TYP 0.85 FOR PROPER CONNECTION OF 0.80 0.05 MAX THE EXPOSED PAD, REFER TO 0.02 NOM THE PIN CONFIGURATION AND SEATING 0.30 COPL0A.0N8ARITY FSUENCCTITOIONN O DFE TSHCISR IDPATTIOAN SSHEET. PLANE 0.25 0.20 REF PKG-001050 0.18COMPLIANTTO JEDEC STANDARDS MO-220-VHHD-2 11-10-2017-B Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body and 0.85 mm Package Height (CP-32-2) Dimensions shown in millimeters 0.75 1.20 MAX 9.00 BSC SQ 0.60 0.45 32 25 1 24 PIN 1 7.00 TOP VIEW BSC SQ 1.05 0° MIN 0.20 (PINS DOWN) 1.00 0.09 0.95 7° 3.5° 8 17 0.15 SEATING 0° 9 16 0.05 PLANE 0C.O08P LMAANXARITY VIEW A 0.80 0.45 BSC ROTAVTEIEDW 90 A° CCW LEAD PITCH 00..3370 COMPLIANT TO JEDEC STANDARDS MS-026ABA Figure 48. 32-Lead Thin Plastic Quad Flat Package [TQFP] (SU-32-2) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD7265BCPZ –40°C to +125°C 32-Lead LFCSP CP-32-2 AD7265BCPZ-REEL7 –40°C to +125°C 32-Lead LFCSP CP-32-2 AD7265BSUZ –40°C to +125°C 32-Lead TQFP SU-32-2 AD7265BSUZ-REEL7 –40°C to +125°C 32-Lead TQFP SU-32-2 AD7265BSUZ-REEL –40°C to +125°C 32-Lead TQFP SU-32-2 EVAL-AD7265EDZ Evaluation Board 1 Z = RoHS Compliant Part. ©2005–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04674-0-1/18(C) Rev. C | Page 27 of 27

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7265BCPZ-REEL7 AD7265BSUZ AD7265BCPZ AD7265BSUZ-REEL7 AD7265BSUZ-REEL EVAL-AD7265EDZ