LC2MOS Quad 8-Bit D/A Converter AD7226 FEATURES FUNCTIONAL BLOCK DIAGRAM Four 8-Bit DACs with Output Amplifiers Skinny 20-Lead DIP, SOIC, SSOP, and PLCC Packages VREF VDD Microprocessor-Compatible TTL/CMOS-Compatible No User Trims LATCH A DAC A A VOUTA Extended Temperature Range Operation Single Supply Operation Possible D APPLICATIONS A LATCH B DAC B B VOUTB MSB T Process Control DATA A Automatic Test Equipment (8-BIT) LSB B Automatic Calibration of Large System Parameters, U LATCH C DAC C C VOUTC e.g., Gain/Offset S LATCH D DAC D D VOUTD WR CONTROL A1 AD7226 LOGIC A0 VSS AGND AGND GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7226 contains four 8-bit voltage-output digital-to- 1. DAC-to-DAC Matching analog converters, with output buffer amplifiers and interface Since all four DACs are fabricated on the same chip at the logic on a single monolithic chip. No external trims are required same time, precise matching and tracking between the DACs to achieve full specified performance for the part. is inherent. Separate on-chip latches are provided for each of the four D/A 2. Single-Supply Operation converters. Data is transferred into one of these data latches The voltage mode configuration of the DACs allows the through a common 8-bit TTL/CMOS (5 V) compatible input AD7226 to be operated from a single power supply rail. port. Control inputs A0 and A1 determine which DAC is 3. Microprocessor Compatibility loaded when WR goes low. The control logic is speed-compat- The AD7226 has a common 8-bit data bus with individual ible with most 8-bit microprocessors. DAC latches, providing a versatile control architecture for Each D/A converter includes an output buffer amplifier capable simple interface to microprocessors. All latch enable signals of driving up to 5 mA of output current. The amplifiers’ offsets are level triggered. are laser-trimmed during manufacture, thereby eliminating any 4. Small Size requirement for offset nulling. Combining four DACs and four op amps plus interface logic Specified performance is guaranteed for input reference voltages into a 20-pin package allows a dramatic reduction in board from 2 V to 12.5 V with dual supplies. The part is also specified space requirements and offers increased reliability in systems for single supply operation at a reference of 10 V. using multiple converters. Its pinout is aimed at optimizing board layout with all the analog inputs and outputs at one The AD7226 is fabricated in an all ion-implanted high speed Linear Compatible CMOS (LC2MOS) process, which has been end of the package and all the digital inputs at the other. specifically developed to allow high speed digital logic circuits and precision analog circuits to be integrated on the same chip. REV. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com registered trademarks are the property of their respective companies. Fax: © 20 Analog Devices, Inc. All rights reserved.

AD7226–SPECIFICATIONS (V = 11.4 V to 16.5 V, V = –5 V (cid:1) 10%, AGND = DGND = 0 V; V = +2 V to (V – 4 V)1, DD SS REF DD unless otherwise noted. All Specifications T to T unless otherwise noted.) MIN MAX DUAL SUPPLY Parameter K, B Versions2 Unit Conditions/Comments STATIC PERFORMANCE Resolution 8 Bits Total Unadjusted Error ±1 LSB max VDD = 15 V ± 5%, VREF = 10 V Relative Accuracy ±0.5 LSB max Differential Nonlinearity ±1 LSB max Guaranteed Monotonic Full-Scale Error ±0.5 LSB max Full-Scale Temperature Coefficient ±20 ppm/∞C typ VDD = 14 V to 16.5 V, VREF = +10 V Zero Code Error ±20 mV max Zero Code Error Temperature Coefficient ±50 mV/∞C typ REFERENCE INPUT Voltage Range 2 to (V – 4) V min to V max DD Input Resistance 2 kW min Input Capacitance3 50 pF min Occurs when each DAC is loaded with all 0s. 200 pF max Occurs when each DAC is loaded with all 1s. DIGITAL INPUTS Input High Voltage, V 2.4 V min INH Input Low Voltage, V 0.8 V max INL Input Leakage Current ±1 mA max VIN = 0 V or VDD Input Capacitance 8 pF max Input Coding Binary DYNAMIC PERFORMANCE Voltage Output Slew Rate4 2.5 V/ms min Voltage Output Settling Time4 4 ms max VREF = 10 V; Settling Time to ±1/2 LSB Digital Crosstalk 10 nV secs typ Minimum Load Resistance 2 kW min VOUT = 10 V POWER SUPPLIES V Range 11.4/16.5 V min/V max For Specified Performance DD I 13 mA max Outputs Unloaded; V = V or V DD IN INL INH I 11 mA max Outputs Unloaded; V = V or V SS IN INL INH SWITCHING CHARACTERISTICS4, 5 Address to Write Setup Time, t 0 ns min AS Address to Write Hold Time, t 0 ns min AH Data Valid to Write Setup Time, t 50 ns min DS Data Valid to Write Hold Time, t 0 ns min DH Write Pulsewidth, t 50 ns min WR NOTES 1Maximum possible reference voltage. 2Temperature ranges are as follows: K Version: –40∞C to +85∞C B Version: –40∞C to +85∞C 3Guaranteed by design. Not production tested. 4Sample Tested at 25∞C to ensure compliance. 5Switching Characteristics apply for single and dual supply operation. Specifications subject to change without notice. –2– REV. 4 o f 1 4

AD7226 (V = 15 V (cid:1) 5%, V = AGND = DGND = O V; V = 10 V1 unless otherwise noted. SINGLE SUPPLY DD SS REF All specifications T to T unless otherwise noted.) MIN MAX Parameter K, B Versions2 Unit Conditions/Comments STATIC PERFORMANCE Resolution 8 Bits Total Unadjusted Error ±2 LSB max Differential Nonlinearity ±1 LSB max Guaranteed Monotonic REFERENCE INPUT Input Resistance 2 kW min Input Capacitance3 50 pF min Occurs when each DAC is loaded with all 0s. 200 pF max Occurs when each DAC is loaded with all 1s. DIGITAL INPUTS Input High Voltage, V 2.4 V min INH Input Low Voltage, V 0.8 V max INL Input Leakage Current ±1 mA max VIN = 0 V or VDD Input Capacitance 8 pF max Input Coding Binary DYNAMIC PERFORMANCE Voltage Output Slew Rate4 2 V/ms min Voltage Output Settling Time4 4 ms max Settling Time to ±1/2 LSB Digital Crosstalk 10 nV secs typ Minimum Load Resistance 2 kW min VOUT = +10 V POWER SUPPLIES V Range 14.25/15.75 V min/V max For Specified Performance DD I 13 mA max Outputs Unloaded; V = V or V DD IN INL INH NOTES 1Maximum possible reference voltage. 2Temperature ranges are as follows: ABSOLUTE MAXIMUM RATINGS1 K Version: –40∞C to +85∞C V to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V B Version: –40∞C to +85∞C VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V 3Guaranteed by design. Not production tested. DD 4Sample Tested at 25∞C to ensure compliance. VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V, VDD Specifications subject to change without notice. V to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V, V SS DD V to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V DD SS AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, V DD Digital Input Voltage to DGND . . . . . . . –0.3 V, V + 0.3 V DD V to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, V REF DD V to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . V , V OUT SS DD Power Dissipation (Any Package) to 75∞C . . . . . . . . . .500 mW Derates above 75∞C by . . . . . . . . . . . . . . . . . . . . . 2.0 mW/∞C Operating Temperature Commercial (K Version) . . . . . . . . . . . . . . .–40∞C to +85∞C Industrial (B Version) . . . . . . . . . . . . . . . . .–40∞C to +85∞C Storage Temperature . . . . . . . . . . . . . . . . . . .–65∞C to +150∞C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300∞C NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Outputs may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit current to AGND is 50 mA. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7226 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. –3– 4 o f 1 4

AD7226 PIN CONFIGURATIONS DIP and SOIC/SSOP VOUTB 1 20 VOUTC VOUTA 2 19 VOUTD VSS 3 18 VDD VREF 4 17 A0 AGND 5 AD7226 16 A1 DGND 6 TOP VIEW 15 WR (Not to Scale) DB7 (MSB) 7 14 DB0(LSB) DB6 8 13 DB1 DB5 9 12 DB2 DB4 10 11 DB3 PLCC A B C D T T T T SS OU OU OU OU V V V V V 3 2 1 20 19 VREF 4 18 VDD AGND 5 17 A0 AD7226 DGND 6 TOP VIEW 16 A1 DB7 (MSB) 7 (Not to Scale) 15 WR DB8 8 14 DB0(LSB) 9 10 11 12 13 5 4 3 2 1 B B B B B D D D D D TERMINOLOGY DIFFERENTIAL NONLINEARITY Differential Nonlinearity is the difference between the measured TOTAL UNADJUSTED ERROR change and the ideal 1 LSB change between any two adjacent This is a comprehensive specification that includes full-scale error, relative accuracy and zero code error. Maximum output codes. A specified differential nonlinearity of ±1 LSB max over the operating temperature range ensures monotonicity. voltage is V – 1 LSB (ideal), where 1 LSB (ideal) is V / REF REF 256. The LSB size will vary over the V range. Hence the zero DIGITAL CROSSTALK REF code error will, relative to the LSB size, increase as V decreases. The glitch impulse transferred to the output of one converter REF Accordingly, the total unadjusted error, which includes the zero due to a change in the digital input code to another of the con- code error, will also vary in terms of LSB’s over the V range. verters. It is specified in nV secs and is measured at V = 0 V. REF REF As a result, total unadjusted error is specified for a fixed refer- FULL SCALE ERROR ence voltage of 10 V. Full-Scale Error is defined as: RELATIVE ACCURACY Measured Value – Zero Code Error – Ideal Value Relative Accuracy or endpoint nonlinearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after allowing for zero and full-scale error and is normally expressed in LSB’s or as a percentage of full-scale reading. –4– REV. 4 o f 1 4

AD7226 CIRCUIT INFORMATION In single supply operation (V = 0 V = AGND), with the out- SS D/A SECTION put approaching AGND (i.e., digital code approaching all 0s) The AD7226 contains four identical, 8-bit, voltage mode digital-to- analog converters. The output voltages from the converters have the VDD same polarity as the reference voltage allowing single supply opera- tion. A novel DAC switch pair arrangement on the AD7226 allows a I/P reference voltage range from 2 V to 12.5 V. Each DAC consists of a highly stable, thin-film, R-2R ladder and eight high speed NMOS, single-pole, double-throw O/P switches. The simplified circuit diagram for one channel is 400(cid:2)A shown in Figure 1. Note that V (Pin 4) and AGND (Pin 5) REF are common to all four DACs. VSS Figure 2.Amplifier Output Stage R R R VOUT the current load ceases to act as a current sink and begins to act as a resistive load of approximately 2 kW to AGND. This occurs 2R 2R 2R 2R 2R as the NMOS transistors come out of saturation. This means DB0 DB5 DB6 DB7 that, in single supply operation, the sink capability of the ampli- fiers is reduced when the output voltage is at or near AGND. A VREF typical plot of the variation of current sink capability with out- AGND put voltage is shown in Figure 3. SHOWN FOR ALL 1s ON DAC Figure 1.D/A Simplified Circuit Diagram 500 The input impedance at the V pin of the AD7226 is the REF VSS = –5V parallel combination of the four individual DAC reference input 400 impedances. It is code dependent and can vary from 2 kW to infinity. The lowest input impedance (i.e., 2 KW) occurs when 300 all four DACs are loaded with the digital code 01010101. A) (cid:2) Therefore, it is important that the reference presents a low (K VSS = 0 VDD = +15V N output impedance under changing load conditions. The nodal ISI 200 capacitance at the reference terminals is also code dependent and typically varies from 100 pF to 250 pF. 100 Each V pin can be considered as a digitally programmable OUT voltage source with an output voltage of: V OUTX =DX VREF (1) 00 2 4 6 8 10 VOUT (V) where D is fractional representation of the digital input code X and can vary from 0 to 255/256. Figure 3.Variation of ISINK with VOUT If the full sink capability is required with output voltages at or The source impedance is the output resistance of the buffer near AGND (= 0 V), then V can be brought below 0 V by 5 V amplifier. SS and thereby maintain the 400 mA current sink as indicated in OP AMP SECTION Figure 3. Biasing V below 0 V also gives additional headroom Each voltage-mode D/A converter output is buffered by a unity SS in the output amplifier which allows for better zero code error gain, noninverting CMOS amplifier. This buffer amplifier is performance on each output. Also improved is the slew rate and capable of developing 10 V across a 2 kW load and can drive negative-going settling time of the amplifiers (discussed later). capacitive loads of 3300 pF. The output stage of this amplifier consists of a bipolar transistor from the V line and a current Each amplifier offset is laser trimmed during manufacture to DD load to the V , the negative supply for the output amplifiers. eliminate any requirement for offset nulling. SS This output stage is shown in Figure 2. DIGITAL SECTION The digital inputs of the AD7226 are both TTL and CMOS The NPN transistor supplies the required output current drive (5 V) compatible from V = 11.4 V to 16.5 V. All logic inputs (up to 5 mA). The current load consists of NMOS transistors DD are static protected MOS gates with typical input currents of which normally act as a constant current sink of 400 mA to VSS, less than 1 nA. Internal input protection is achieved by an giving each output a current sink capability of approximately on-chip distributed diode from DGND to each MOS gate. To 400 mA if required. minimize power supply currents, it is recommended that the The AD7226 can be operated single or dual supply resulting digital input voltages be driven as close to the supply rails (V in different performance in some parameters from the output DD and DGND) as practically possible. amplifiers. REV. –5– 4 o f 1 4

AD7226 INTERFACE LOGIC INFORMATION Address lines A0 and A1 select which DAC will accept data A0 TO LATCH A from the input port. Table I shows the selection table for the four DACs with Figure 4 showing the input control logic. When the WR signal is LOW, the input latches of the selected DAC A1 TO LATCH B are transparent and its output responds to activity on the data bus. The data is latched into the addressed DAC latch on the TO LATCH C rising edge of WR. While WR is high the analog outputs remain at the value corresponding to the data held in their respective latches. TO LATCH D WR Table I. AD7226 Truth Table AD7226 Control Inputs AD7226 Figure 4.Input Control Logic WR A1 A0 Operation t t H X X No Operation Device Not Selected DS DH L L L DAC A Transparent VDD L L DAC A Latched DATA VINH VINL 0 L L H DAC B Transparent t t AH L H DAC B Latched AS L H L DAC C Transparent ADDRESS VINH VDD H L DAC C Latched VINL 0 L H H DAC D Transparent H H DAC D Latched WR tWR VDD L = Low State, H = High State, X = Don’t Care 0 NOTES 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF VDD. tr = tf = 20ns OVER VDD RANGE. 2. TIMING MEASUREMENT REFERENCE LEVEL IS VINH + VINL 2 3. SELECTED INPUT LATCH IS TRANSPARENT WHILE WR IS LOW, THUS INVALID DATA DURING THIS TIME CAN CAUSE SPURIOUS OUTPUTS. Figure 5.Write Cycle Timing Diagram –6– REV.

Typical Performance Characteristics–AD7226 (T = 25(cid:3)C, V = 15 V, V = –5 V) A DD SS AD7226K, B 2.0 4 USTED ERROR (LSBs) 110...5050 VREF = 10V NONLINEARITY (LSBs) 3210 DJ –0.5 AL –1 L UNA –1.0 RENTI –2 TOTA –1.5 DIFFE –3 –2.0 –4 0 16 32 48 64 80 96 112128144160176192208224240256 0 2 4 6 8 10 12 14 INPUT CODE (DECIMAL EQUIVALENT) VREF (V) TPC 1.Channel-to-Channel Matching TPC 3.Differential Nonlinearity vs. V REF AD7226K, B 4 2.0 3 1.5 Bs) 2 s) 1.0 S B L S CY ( 1 R (L 0.5 A O CUR 0 ERR 0 VOUTA VE AC –1 CODE –0.5 VVOOUUTTBD RELATI –2 ZERO –1.0 VOUTC –3 –1.5 –4 –2.0 0 2 4 6 8 10 12 14 0 10 20 30 40 50 60 70 80 90 100 110 120 130 VREF (V) TEMPERATURE ((cid:3)C) TPC 2.Relative Accuracy vs. V TPC 4.Zero Code Error vs. Temperature REF REV. –7–

AD7226 SPECIFICATION RANGES In order for the DACs to operate to their specifications, the reference voltage must be at least 4 V below the V power DATA DD supply voltage. This voltage differential is required for correct generation of bias voltages for the DAC switches. +1/2 LSB The AD7226 is specified to operate over a V range from DD +12 V ± 5% to +15 V ± 10% (i.e., from +11.4 V to +16.5 V) O/P with a VSS of –5 V ± 10%. Operation is also specified for a single –1/2 LSB +15 V ± 5% VDD supply. Applying a VSS of –5 V results in improved zero code error, improved output sink capability with outputs near AGND and improved negative-going settling time. Performance is specified over a wide range of reference voltages from 2 V to (V – 4 V) with dual supplies. This allows a range DD of standard reference generators to be used such as the AD780, Figure 7a.Positive Step Settling Time (V = –5 V) SS a 2.5 V band gap reference and the AD584, a precision 10 V reference. Note that in order to achieve an output voltage range of 0 V to 10 V a nominal 15 V ± 5% power supply voltage is required by the AD7226. DATA SETTLING TIME +1/2 LSB The output stage of the buffer amplifiers consists of a bipolar NPN transistor from the V line and a constant current load to DD V . V is the negative power supply for the output buffer ampli- O/P SS SS fiers. As mentioned in the op amp section, in single supply –1/2 LSB operation the NMOS transistor will come out of saturation as the output voltage approaches AGND and will act as a resistive load of approximately 2 kW to AGND. As a result, the settling time for negative-going signals approaching AGND in single supply opera- tion will be longer than for dual supply operation where the current load of 400 mA is maintained all the way down to AGND. Figure 7b.Negative Step Settling Time (VSS = –5 V) Positive-going settling-time is not affected by V . SS GROUND MANAGEMENT The settling-time for the AD7226 is limited by the slew-rate of AC or transient voltages between AGND and DGND can cause the output buffer amplifiers. This can be seen from Figure 6 noise at the analog output. This is especially true in micropro- which shows the dynamic response for the AD7226 for a full cessor systems where digital noise is prevalent. The simplest scale change. Figures 7a and 7b show expanded settling-time method of ensuring that voltages at AGND and DGND are photographs with the output waveforms derived from a differen- equal is to tie AGND and DGND together at the AD7226. In tial input to an oscilloscope. Figure 7a shows the settling time more complex systems where the AGND and DGND intertie is for a positive-going step and Figure 7b shows the settling time on the backplane, it is recommended that two diodes be con- for a negative-going output step. nected in inverse parallel between the AD7226 AGND and DGND pins (IN914 or equivalent). Unipolar Output Operation This is the basic mode of operation for each channel of the DATA AD7226, with the output voltage having the same positive polarity as +V . The AD7226 can be operated single supply REF (V = AGND) or with positive/negative supplies (see op amp SS section which outlines the advantages of having negative V ). VOUT SS The code table for unipolar output operation is shown in Table II. Note that the voltage at V must never be negative with REF respect to DGND in order to prevent parasitic transistor turn-on. Connections for the unipolar output operation are shown in Figure 8. Figure 6.Dynamic Response (V = –5 V) SS –8– REV.

AD7226 VREF VDD With R1 = R2 V OUT =(2DA –1)¥VREF (4) MSB DB7 VOUTA where DA is a fractional representation of the digital word in latch A. DAC A Mismatch between R1 and R2 causes gain and offset errors and therefore these resistors must match and track over tempera- DB0 VOUTB ture. Once again the AD7226 can be operated in single supply LSB DAC B or from positive/negative supplies. Table III shows the digital code versus output voltage relationship for the circuit of Figure 9 with R1 = R2. WR VOUTC DAC C A1 VREF R1 A0 VOUTD VREF VDD R2 DAC D AD7226* +15V VOUTA VOUT VSS AGND DGND DAC A –15V R1, R2 = 10k(cid:4) (cid:1)0.1% Figure 8. AD7226 Unipolar Output Circuit *DIGITAL INPUTS OMITTED VSS AGND DGND FOR CLARITY Table II. Unipolar Code Table Figure 9.AD7226 Bipolar Output Circuit DAC Latch Contents MSB LSB Analog Output Table III. Bipolar (Offset Binary) Code Table 1 1 1 1 1 1 1 1 + VREFÊËÁ225565ˆ¯˜ DAMCS BLatch CoLnSteBnts Analog Output 1 0 0 0 0 0 0 1 + VREFÊËÁ122596ˆ¯˜ 1 1 1 1 1 1 1 1 +VREFÊËÁ112287ˆ¯˜ 1 0 0 0 0 0 0 0 + VREFÊËÁ122586ˆ¯˜ =+VR2EF 1 0 0 0 0 0 0 1 + VREFÊËÁ1218ˆ¯˜ 1 0 0 0 0 0 0 0 0 V 0 1 1 1 1 1 1 1 + VREFÊËÁ122576ˆ¯˜ 0 1 1 1 1 1 1 1 – VREFÊËÁ1218ˆ¯˜ 0 0 0 0 0 0 0 1 + VREFÊËÁ2516ˆ¯˜ 0 0 0 0 0 0 0 1 – VREFÊËÁ112287ˆ¯˜ 0 0 0 0 0 0 0 0 0 V 0 0 0 0 0 0 0 0 – VREFÊËÁ112288ˆ¯˜ =–VREF Note:LSB=(VREF)(2–8)=VREF ÊÁ2516ˆ˜ (2) AGND BIAS Ë ¯ The AD7226 AGND pin can be biased above system GND Bipolar Output Operation (AD7226 DGND) to provide an offset “zero” analog output Each of the DACs of the AD7226 can be individually config- voltage level. Figure 10 shows a circuit configuration to achieve ured to provide bipolar output operation. This is possible using this for channel A of the AD7226. The output voltage, V A, OUT one external amplifier and two resistors per channel. Figure 9 can be expressed as: shows a circuit used to implement offset binary coding (bipolar operation) with DAC A of the AD7226. In this case VOUTA=VBIAS +DA(VIN) (5) where D is a fractional representation of the digital input word A VOUT =ÊÁ1+ RR21ˆ˜¥(DAVREF)–ÊÁRR21ˆ˜¥(VREF) (3) (0 £ D £ 255/256). Ë ¯ Ë ¯ REV. –9–

AD7226 generated in software with each D/A converter being loaded from a separate loop. The loops run through the look-up table VREF VDD producing successive triads of sinusoidal values with 120∞ AD7226* separation which are loaded to the D/A converters producing VOUTA three sine wave voltages 120∞ apart. A complete sine wave DAC A cycle is generated by stepping through the full look-up table. If a 256-element sine wave table is used then the resolution of AGND the circuit will be 1.4∞ (360∞/256). Figure 13 shows typical 5 resulting waveforms. The sine waves can be smoothed by filter- VBIAS VSS DGND ing the D/A converter outputs. The fourth D/A converter of the AD7226, DAC D, may be *DIGITAL INPUTS OMITTED FOR CLARITY used in a feedback configuration to provide a programmable reference voltage for itself and the other three converters. This Figure 10.AGND Bias Circuit configuration is shown in Figure 11. The relationship of V to REF For a given VIN, increasing AGND above system GND will VIN is dependent upon digital code and upon the ratio of RF to reduce the effective V –V which must be at least 4 V to R and is given by the formula. DD REF ensure specified operation. Note that because the AGND pin is common to all four DACs, this method biases up the output (1+G) VREF = ¥VIN (6) voltages of all the DACs in the AD7226. Note that VDD and VSS (1+G ¥DD) of the AD7226 should be referenced to DGND. where G = R /R F and D is a fractional representation of the digital word in latch D. 3-PHASE SINE WAVE D The circuit of Figure 11 shows an application of the AD7226 in Alternatively, for a given VIN and resistance ratio, the required the generation of 3-phase sine waves which can be used to con- value of DD for a given value of VREF can be determined from trol small 3-phase motors. The proper codes for synthesizing a the expression full sine wave are stored in EPROM, with the required phase- DD =(1+R/RF)¥ VIN – R (7) shift of 120∞ between the three D/A converter outputs being VREF RF generated in software. Figure 12 shows typical plots of V versus digital code for REF three different values of R . With V = 2.5 V and R = 3 R the Data is loaded into the three D/A converters from the sine F IN F peak-to-peak sine wave voltage from the converter outputs will EPROM via the microprocessor or control logic. Three loops are vary between 2.5 V and 10 V over the digital input code range of 0 to 255. ADBDURSESS VREF VIN VOUTA A0 MICROPROCESSOR A1 VOUTB CONTROORL LOGIC ESPIRNOEM ADDEDCROEDSES WR VOUTC R RF AD7226 VOUTD DATA BUS Figure 11.3-Phase Sine Wave Generation Circuit 4.0 VIN VDD = +15 V VSS = –5 V 3.5 VIN RF = 3R VOUTA 3.0 VIN VREF2.5 VIN VOUTB RF = 2R 2.0 VIN VOUTC 1.5 VIN RF = R VIN 0 16 32 48 64 80 96 112128144160176192208224240256 DIGITAL CODE (Decimal Equivalent) Figure 12.Variation of V with Feedback Configuration Figure 13.3-Phase Sine Wave Output REF –10– REV.

AD7226 STAIRCASE WINDOW COMPARATOR VTEST In many test systems, it is important to be able to determine FROM D.U.T. whether some parameter lies within defined limits. The staircase window comparator of Figure 14a is a circuit that can be used, 10k(cid:4) for example, to measure the VOH and VOL thresholds of a TTL VREF VDD 5V WINDOW 1 device under test. Upper and lower limits on both VOH and VOL VOUTA can be programmably set using the AD7226. Each adjacent pair of comparators forms a window of programmable size. If V VOUTB TEST 10k(cid:4) lies within a window, then the output for that window will be AD7226 5V WINDOW 2 high. With a reference of 2.56 V applied to the V input, the REF minimum window size is 10 mV. VOUTC VOUTD FVRTEOSMT D.U.T. AGND 5V 10k(cid:4) WINDOW 3 1/4 CA339 10k(cid:4) VREF VDD 5V WINDOW 1 Figure 15a.Overlapping Windows VOH (HIGH) VOUTA VREF 10k(cid:4) 5V WINDOW 2 WINDOW 1 VOUTB VOH (LOW) VOUTA WINDOW 2 VOUTB VOUTD 10k(cid:4) 5V WINDOW 3 VOUTC WINDOW 3 AD7226 AGND VOL (HIGH) VOUTC Figure 15b.Window Structure 10k(cid:4) 5V WINDOW 4 +15V +4V 15k(cid:4) VOL (LOW) VOUTD 10k(cid:4) –4V 10k(cid:4) AGND 5V WINDOW 5 VREF VDD *DIGITAL INPUTS OMITTED AD7226* FOR CLARITY VOUTA Figure 14a.Logic Level Measurement DAC A VREF WINDOW 1 VOUTA WINDOW 2 VSS AGND DGND VOUTB WINDOW 3 Figure 16.Varying Reference Signal VOUTC VARYING REFERENCE SIGNAL WINDOW 4 In some applications, it may be desirable to have a varying signal VOUTD applied to the reference input of the AD7226. The AD7226 has WINDOW 5 multiplying capability within upper and lower limits of reference AGND voltage when operated with dual supplies. The upper and lower limits are those required by the AD7226 to achieve its linearity Figure 14b.Window Structure specification. Figure 16 shows a sine wave signal applied to the The circuit can easily be adapted to allow for overlapping of reference input of the AD7226. For input signal frequencies up windows as shown in Figure 15a. If the three outputs from this to 50 kHz, the output distortion typically remains less than 0.1%. circuit are decoded then five different nonoverlapping program- Typical 3 dB bandwidth figure is 700 kHz. mable windows can again be defined. REV. –11–

AD7226 OFFSET ADJUST +10V Figure 17 shows how the AD7226 can be used to provide pro- grammable input offset voltage adjustment for the AD544 op +15V amp. Each output of the AD7226 can be used to trim the input VREF VDD offset voltage on one AD544. The 620 kW resistor tied to 10 V AD7226* provides a fixed bias current to one offset node. For symmetri- 7 cal adjustment, this bias current should equal the current in the VOUTA 620k(cid:4) other offset node with the half-full scale code (i.e., 10000000) DAC A 45 500k(cid:4) 1 on the DAC. Changing the code on the DAC varies the bias current and hence provides offset adjust for the AD544. For example, the input offset voltage on the AD544J, which has a VSS AGND DGND maximum of ±2 mV, can be programmably trimmed to ±10 mV. –15V *DIGITAL INPUTS OMITTED FOR CLARITY Figure 17.Offset Adjust for AD544 8085A A15 6502 A15 ADDRESS BUS ADDRESS BUS A8 A0 AD7226* A0 ADDRESS R/W EN ADDRESS A1 WR EN DECODE WR (cid:5)2 EN DECODE WR A0 AD7226* A1 DB7 DB7 ALE DS2 8212 DB0 DB0 D7 D7 ADDRESS/DATA BUS DATA BUS D0 D0 *LINEAR CIRCUITRY OMITTED FOR CLARITY *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 18.AD7226 to 8085A Interface Figure 20.AD7226 to 6502 Interface 6809 A15 Z-80 A15 ADDRESS BUS ADDRESS BUS A0 A0 A0 A0 R/W EN ADDRESS A1 ADDRESS A1 EN DECODE WR EN DECODE WR WR AD7226* AD7226* E DB7 DB7 DB0 DB0 D7 D7 DATA BUS DATA BUS D0 D0 *LINEAR CIRCUITRY OMITTED FOR CLARITY *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 19.AD7226 to 6809 Interface Figure 21.AD7226 to Z-80 Interface –12– REV.

AD7226 OUTLINE DIMENSIONS 1.060 (26.92) 1.030 (26.16) 0.980 (24.89) 20 11 0.280 (7.11) 0.250 (6.35) 1 10 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINOEFRPEANRERERENN LCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 070706-A Figure 1. 20-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-20) Dimensions shown in inches and (millimeters) 0.005 0.098 (2.49) (0.13) MAX 0.310 (7.87) MIN 20 11 0.220 (5.59) 1 10 PIN 1 0.060 (1.52) 0.320 (8.13) 0.200 (5.08) 1.060 (26.92) MAX 0.015 (0.38) MAX 0.290 (7.37) 0.150 (3.81) MIN 0.015 (0.38) 0.200 (5.08) 15° 0.008 (0.20) 0.125 (3.18) 0.100 0.070 (1.78) SPELAANTIENG 0° 0.023 (0.58) (B2.S5C4) 0.030 (0.76) 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 2. 20-Lead Ceramic Dual In-Line Package [CERDIP] (Q-20) Dimensions shown in inches and (millimeters) Rev. D | Page 1(cid:20)

AD7226 7.50 7.20 6.90 20 11 5.60 5.30 5.00 8.20 7.80 1 7.40 10 1.85 0.25 2.00 MAX 1.75 0.09 1.65 COPLA0N.0A5R MITIYN 0.65 BSC 00..3282 SPELAATNIENG 840°°° 000...975555 0.10 COMPLIANTTO JEDEC STANDARDS MO-150-AE 060106-A Figure 3. 20-Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters 13.00(0.5118) 12.60(0.4961) 20 11 7.60(0.2992) 7.40(0.2913) 1 10.65(0.4193) 10 10.00(0.3937) 0.75(0.0295) 45° 2.65(0.1043) 0.25(0.0098) 0.30(0.0118) 2.35(0.0925) 8° 0.10(0.0039) 0° COPLANARITY 0.10 (0.10.25070) 00..5311((00..00210212)) SPELAATNIENG 00..3230((00..00103709)) 10..2470((00..00510507)) BSC COMPLIANTTOJEDECSTANDARDSMS-013-AC C(RINEOFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 06-07-2006-A Figure 4. 20-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-20) Dimensions shown in millimeters and (inches) Rev. D | Page

AD7226 0.180 (4.57) 0.048 (1.22 ) 0.165 (4.19) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 0M.2IN0 (0.51) 0.020R (0.50) 3 19 0.021 (0.53) 00..004482 ((11..2027)) 4 IDEPNITNI F1IER 18 (01..02570) 0.013 (0.33)0.330 (8.38) BOTTOM TOP VIEW BSC 0.032 (0.81)0.290 (7.37) VIEW (PINS DOWN) 0.026 (0.66) (PINS UP) 8 14 9 13 0.020 0.045 (1.14) (0.R51) 00..335560 ((98..0849))SQ 0.025 (0.64) R 0.120 (3.04) 0.395 (10.03)SQ 0.090 (2.29) 0.385 (9.78) COMPLIANT TO JEDEC STANDARDS MO-047-AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 5. 20-Lead Plastic Leaded Chip Carrier [PLCC] (P-20A) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model1 Temperature Range Total Unadjusted Error2 Package Description Package Option3 AD7226BQ −40°C to +85°C ±1 LSB 20 Lead CERDIP Q-20 AD7226BRSZ −40°C to +85°C ±1 LSB 20 Lead SSOP RS-20 AD7226KN −40°C to +85°C ±1 LSB 20 Lead PDIP N-20 AD7226KNZ −40°C to +85°C ±1 LSB 20 Lead PDIP N-20 AD7226KP −40°C to +85°C ±1 LSB 20 Lead PLCC P-20A AD7226KP-REEL −40°C to +85°C ±1 LSB 20 Lead PLCC P-20A AD7226KPZ −40°C to +85°C ±1 LSB 20 Lead PLCC P-20A AD7226KPZ-REEL −40°C to +85°C ±1 LSB 20 Lead PLCC P-20A AD7226KR −40°C to +85°C ±1 LSB 20 Lead SOIC - Wide RW-20 AD7226KR-REEL −40°C to +85°C ±1 LSB 20 Lead SOIC - Wide RW-20 AD7226KRZ −40°C to +85°C ±1 LSB 20 Lead SOIC - Wide RW-20 AD7226KRZ-REEL −40°C to +85°C ±1 LSB 20 Lead SOIC - Wide RW-20 AD7226BCHIPS −40°C to +85°C ±1 LSB Chips or Die 1 Z = ROHS Compliant Part. 2 Dual supply operation. 3 N = plastic DIP; P = plastic leaded chip carrier; Q = CERDIP; RW = SPIC; RS = SSOP. REVISION HISTORY Edits to Ordering Guide ................................................................... 3 Edits to Absolute Maximum Ratings .............................................. 3 1/11—Rev. C to Rev. D Edits to Pin Configurations ............................................................. 4 Changes to Ordering Guide ........................................................... 15 Edits to Specifications Ranges ......................................................... 8 Outline Dimensions Updated ........................................................ 13 3/03—Rev. B to Rev. C RS-20 Package Added ..................................................................... 13 Title Revision ..................................................................................... 1 Updated RS-20 Package Outline Dimensions ............................. 13 3/03—Rev. A to Rev. B Edits to Features ................................................................................ 1 Edits to Specifications ....................................................................... 2 Rev. D | Page (cid:18)(cid:22)

AD7226 NOTES ©2003-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00987-0-1/11(D) Rev. D | Page (cid:18)(cid:23)

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7226TQ AD7226KPZ-REEL 5962-87802012A AD7226KNZ AD7226KPZ AD7226KR-REEL AD7226KRZ AD7226BRSZ 5962-8780201RA AD7226KP AD7226KN AD7226KRZ-REEL AD7226KR AD7226BQ