4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA AD7192 FEATURES Temperature measurement Chromatography RMS noise: 11 nV @ 4.7 Hz (gain = 128) PLC/DCS analog input modules 15.5 noise-free bits @ 2.4 kHz (gain = 128) Data acquisition Up to 22 noise-free bits (gain = 1) Medical and scientific instrumentation Offset drift: 5 nV/°C Gain drift: 1 ppm/°C GENERAL DESCRIPTION Specified drift over time The AD7192 is a low noise, complete analog front end for high 2 differential/4 pseudo differential input channels precision measurement applications. It contains a low noise, Automatic channel sequencer 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). Programmable gain (1 to 128) The on-chip low noise gain stage means that signals of small Output data rate: 4.7 Hz to 4.8 kHz amplitude can be interfaced directly to the ADC. Internal or external clock Simultaneous 50 Hz/60 Hz rejection The device can be configured to have two differential inputs or 4 general-purpose digital outputs four pseudo differential inputs. The on-chip channel sequencer Power supply allows several channels to be enabled, and the AD7192 sequentially AV : 3 V to 5.25 V converts on each enabled channel. This simplifies communication DD DV : 2.7 V to 5.25 V with the part. The on-chip 4.92 MHz clock can be used as the DD Current: 4.35 mA clock source to the ADC or, alternatively, an external clock or Temperature range: –40°C to +105°C crystal can be used. The output data rate from the part can be Package: 24-lead TSSOP varied from 4.7 Hz to 4.8 kHz. INTERFACE The device has two digital filter options. The choice of filter affects the rms noise/noise-free resolution at the programmed 3-wire serial output data rate, the settling time, and the 50 Hz/60 Hz SPI, QSPI™, MICROWIRE™, and DSP compatible rejection. For applications that require all conversions to be Schmitt trigger on SCLK settled, the AD7192 includes a zero latency feature. APPLICATIONS The part operates with a power supply from 3 V to 5.25 V. It Weigh scales consumes a current of 4.35 mA. It is housed in a 24-lead TSSOP Strain gage transducers package. Pressure measurement FUNCTIONAL BLOCK DIAGRAM AGND AVDD DVDD DGNDREFIN1(+) REFIN1(–) REFERENCE AD7192 DETECT AIN1 AVDD AIN2 AIN3 SERIAL DOUT/RDY AINCAOINM4 MUX PGA Σ-Δ INTEARNFDACE DIN ADC CONTROL SCLK LOGIC CS SYNC AGND TEMP P3 SENSOR BPDSW P2 CLOCK CIRCUITRY AGND MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+) 07822-001 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.

AD7192 TABLE OF CONTENTS Features .............................................................................................. 1 Offset Register ............................................................................ 24 Interface ............................................................................................. 1 Full-Scale Register ...................................................................... 24 Applications ....................................................................................... 1 ADC Circuit Information .............................................................. 25 General Description ......................................................................... 1 Overview ..................................................................................... 25 Functional Block Diagram .............................................................. 1 Filter, Output Data Rate, and Settling Time ........................... 25 Revision History ............................................................................... 2 Digital Interface .......................................................................... 28 Specifications ..................................................................................... 3 Circuit Description......................................................................... 32 Timing Characteristics ..................................................................... 7 Analog Input Channel ............................................................... 32 Circuit and Timing Diagrams ..................................................... 7 Programmable Gain Array (PGA) ........................................... 32 Absolute Maximum Ratings ............................................................ 9 Bipolar/Unipolar Configuration .............................................. 32 Thermal Resistance ...................................................................... 9 Data Output Coding .................................................................. 32 ESD Caution .................................................................................. 9 Clock ............................................................................................ 32 Pin Configuration and Function Descriptions ........................... 10 Burnout Currents ....................................................................... 33 Typical Performance Characteristics ........................................... 12 Reference ..................................................................................... 33 RMS Noise and Resolution ............................................................ 14 Reference Detect ......................................................................... 33 Sinc4 Chop Disabled ................................................................... 14 Reset ............................................................................................. 34 Sinc3 Chop Disabled ................................................................... 15 System Synchronization ............................................................ 34 Sinc4 Chop Enabled .................................................................... 16 Temperature Sensor ................................................................... 34 Sinc3 Chop Enabled .................................................................... 17 Bridge Power-Down Switch ...................................................... 34 On-Chip Registers .......................................................................... 18 Logic Outputs ............................................................................. 34 Communications Register ......................................................... 18 Enable Parity ............................................................................... 35 Status Register ............................................................................. 19 Calibration ................................................................................... 35 Mode Register ............................................................................. 19 Grounding and Layout .............................................................. 36 Configuration Register .............................................................. 21 Applications Information .............................................................. 37 Data Register ............................................................................... 23 Weigh Scales ................................................................................ 37 ID Register ................................................................................... 23 Outline Dimensions ....................................................................... 38 GPOCON Register ..................................................................... 24 Ordering Guide .......................................................................... 38 REVISION HISTORY 5/09—Rev. 0 to Rev. A Change to Gain Error Specification ............................................... 3 Changes to Table 3 ............................................................................ 9 5/09—Revision 0: Initial Version Rev. A | Page 2 of 40

AD7192 SPECIFICATIONS AV = 3 V to 5.25 V, DV = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = AV , REFINx(−) = AGND, MCLK = 4.92 MHz, DD DD DD T = T to T , unless otherwise noted. A MIN MAX Table 1. Parameter AD7192B Unit Test Conditions/Comments1 ADC Output Data Rate 4.7 to 4800 Hz nom Chop disabled 1.17 to 1200 Hz nom Chop enabled, sinc4 filter 1.56 to 1600 Hz nom Chop enabled, sinc3 filter No Missing Codes2 24 Bits min FS > 1, sinc4 filter3 24 Bits min FS > 4, sinc3 filter3 Resolution See the RMS Noise and Resolution section RMS Noise and Output Data Rates See the RMS Noise and Resolution section Integral Nonlinearity Gain = 12 ±10 ppm of FSR max ±2 ppm typical, AV = 5 V DD ±15 ppm of FSR max ±2 ppm typical, AV = 3 V DD Gain > 1 ±30 ppm of FSR max ±5 ppm typical, AV = 5 V DD ±30 ppm of FSR max ±12 ppm typical, AV = 3 V DD Offset Error4, 5 ±150/gain μV typ Chop disabled ±0.5 μV typ Chop enabled Offset Error Drift vs. Temperature ±150/gain nV/°C typ Gain = 1 to 16; chop disabled ±5 nV/°C typ Gain = 32 to 128; chop disabled ±5 nV/°C typ Chop enabled Offset Error Drift vs. Time 25 nV/1000 hours typ Gain > 32 Gain Error4 ±0.001 % typ AV = 5 V, gain = 1, T = 25°C (factory DD A calibration conditions) −0.39 % typ Gain = 128, before full-scale calibration (see Table 23) ±0.003 % typ Gain > 1, after internal full-scale calibration, AV ≥ 4.75 V. DD ±0.005 % typ Gain > 1, after internal full-scale calibration, AV < 4.75 V DD Gain Drift vs. Temperature ±1 ppm/°C typ Gain Drift vs. Time 10 ppm/1000 hours typ Gain = 1. Power Supply Rejection 90 dB typ Gain = 1, V = 1 V. IN 95 dB min Gain > 1, V = 1 V/gain, 110 dB typ. IN Common-Mode Rejection @ DC2 100 dB min Gain = 1, V = 1 V. IN @ DC 110 dB min Gain > 1, V = 1 V/gain. IN @ 50 Hz, 60 Hz2 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. @ 50 Hz, 60 Hz2 120 dB min 50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz (60 Hz output data rate). Normal Mode Rejection2 Sinc4 Filter Internal Clock @ 50 Hz, 60 Hz 100 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 74 dB min 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. @ 50 Hz 96 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 97 dB min 60 Hz output data rate, 60 ± 1 Hz. Rev. A | Page 3 of 40

AD7192 Parameter AD7192B Unit Test Conditions/Comments1 External Clock @ 50 Hz, 60 Hz 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 82 dB min 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. @ 50 Hz 120 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 120 dB min 60 Hz output data rate, 60 ± 1 Hz. Sinc3 Filter Internal Clock @ 50 Hz, 60 Hz 75 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 60 dB min 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. @ 50 Hz 70 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 70 dB min 60 Hz output data rate, 60 ± 1 Hz. External Clock @ 50 Hz, 60 Hz 100 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 67 dB min 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. @ 50 Hz 95 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 95 dB min 60 Hz output data rate, 60 ± 1 Hz. ANALOG INPUTS Differential Input Voltage Ranges ± V /gain V nom VREF = REFINx(+) − REFINx(−), REF gain = 1 to 128. ± (AV – 1.25 V)/gain V min/max Gain > 1. DD Absolute AIN Voltage Limits2 Unbuffered Mode AGND − 50 mV V min AV + 50 mV V max DD Buffered Mode AGND + 250 mV V min AV − 250 mV V max DD Analog Input Current Buffered Mode Input Current2 ±2 nA max Gain = 1. ±3 nA max Gain > 1. Input Current Drift ±5 pA/°C typ Unbuffered Mode Input Current ±3.5 μA/V typ Gain = 1, input current varies with input voltage. ±1 μA/V typ Gain > 1. Input Current Drift ±0.05 nA/V/°C typ External clock. ±1.6 nA/V/°C typ Internal clock. REFERENCE INPUT REFIN Voltage AV V nom REFIN = REFINx(+) − REFINx(−). DD 1 V min AV V max The differential input must be limited to DD ±(AV – 1.25 V)/gain when gain > 1. DD Absolute REFIN Voltage Limits2 GND – 50 mV V min AV + 50 mV V max DD Average Reference Input Current 4.5 μA/V typ Rev. A | Page 4 of 40

AD7192 Parameter AD7192B Unit Test Conditions/Comments1 Average Reference Input Current ±0.03 nA/V/°C typ External clock. Drift ±1.3 nA/V/°C typ Internal clock. Normal Mode Rejection2 Same as for analog inputs Common-Mode Rejection 100 dB typ Reference Detect Levels 0.3 V min 0.6 V max TEMPERATURE SENSOR Accuracy ±2 °C typ Applies after user calibration at 25°C. Sensitivity 2815 Codes/°C typ Bipolar mode. BRIDGE POWER-DOWN SWITCH R 10 Ω max ON Allowable Current2 30 mA max Continuous current. BURNOUT CURRENTS AIN Current 500 nA nom Analog inputs must be buffered and chop disabled. DIGITAL OUTPUTS (P0 to P3) Output High Voltage, V AV − 0.6 V min AV = 3 V, I = 100 μA. OH DD DD SOURCE Output Low Voltage, V 0.4 V max AV = 3 V, I = 100 μA. OL DD SINK Output High Voltage, V 4 V min AV = 5 V, I = 200 μA. OH DD SOURCE Output Low Voltage, V 0.4 V max AV = 5 V, I = 800 μA. OL DD SINK Floating-State Leakage Current2 ±100 nA max Floating-State Output 10 pF typ Capacitance INTERNAL/EXTERNAL CLOCK Internal Clock Frequency 4.92 ± 4% MHz min/max Duty Cycle 50:50 % typ External Clock/Crystal Frequency 4.9152 MHz nom 2.4576/5.12 MHz min/max Input Low Voltage V 0.8 V max DV = 5 V. INL DD 0.4 V max DV = 3 V. DD Input High Voltage, V 2.5 V min DV = 3 V. INH DD 3.5 V min DV = 5 V. DD Input Current ±10 μA max LOGIC INPUTS Input High Voltage, V 2 2 V min INH Input Low Voltage, V 2 0.8 V max INL Hysteresis2 0.1/0.25 V min/V max Input Currents ±10 μA max LOGIC OUTPUT (DOUT/RDY) Output High Voltage, V 2 DV − 0.6 V min DV = 3 V, I = 100 μA. OH DD DD SOURCE Output Low Voltage, V 2 0.4 V max DV = 3 V, I = 100 μA. OL DD SINK Output High Voltage, V 2 4 V min DV = 5 V, I = 200 μA. OH DD SOURCE Output Low Voltage, V 2 0.4 V max DV = 5 V, I = 1.6 mA. OL DD SINK Floating-State Leakage Current ±10 μA max Floating-State Output 10 pF typ Capacitance Data Output Coding Offset binary Rev. A | Page 5 of 40

AD7192 Parameter AD7192B Unit Test Conditions/Comments1 SYSTEM CALIBRATION2 Full-Scale Calibration Limit 1.05 × FS V max Zero-Scale Calibration Limit −1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max POWER REQUIREMENTS7 Power Supply Voltage AV − AGND 3/5.25 V min/max DD DV − DGND 2.7/5.25 V min/max DD Power Supply Currents AI Current 0.6 mA max 0.53 mA typical, gain = 1, buffer off. DD 0.85 mA max 0.75 mA typical, gain = 1, buffer on. 3.2 mA max 2.5 mA typical, gain = 8, buffer off. 3.6 mA max 3 mA typical, gain = 8, buffer on. 4.5 mA max 3.5 mA typical, gain = 16 to 128, buffer off. 5 mA max 4 mA typical, gain = 16 to 128, buffer on. DI Current 0.4 mA max 0.35 mA typical, DV = 3 V. DD DD 0.6 mA max 0.5 mA typical, DV = 5 V. DD 1.5 mA typ External crystal used. I (Power-Down Mode) 3 μA max DD 1 Temperature range: −40°C to +105°C. 2 Specification is not production tested but is supported by characterization data at initial product release. 3 FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. 4 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full- scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 5 The analog inputs are configured for differential mode. 6 REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection. 7 Digital inputs equal to DVDD or DGND. Rev. A | Page 6 of 40

AD7192 TIMING CHARACTERISTICS AV = 3 V to 5.25 V, DV = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV , unless otherwise noted. DD DD DD Table 2. Parameter Limit at T , T (B Version) Unit Conditions/Comments1, 2 MIN MAX t 100 ns min SCLK high pulse width 3 t 100 ns min SCLK low pulse width 4 READ OPERATION t 0 ns min CS falling edge to DOUT/RDY active time 1 60 ns max DV = 4.75 V to 5.25 V DD 80 ns max DV = 2.7 V to 3.6 V DD t 3 0 ns min SCLK active edge to data valid delay4 2 60 ns max DV = 4.75 V to 5.25 V DD 80 ns max DV = 2.7 V to 3.6 V DD t 5, 6 10 ns min Bus relinquish time after CS inactive edge 5 80 ns max t 0 ns min SCLK inactive edge to CS inactive edge 6 t 10 ns min SCLK inactive edge to DOUT/RDY high 7 WRITE OPERATION t 0 ns min CS falling edge to SCLK active edge setup time4 8 t 30 ns min Data valid to SCLK edge setup time 9 t 25 ns min Data valid to SCLK edge hold time 10 t 0 ns min CS rising edge to SCLK edge hold time 11 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 2 See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. CIRCUIT AND TIMING DIAGRAMS ISINK (1.6mA WITH DVDD = 5V, 100µA WITH DVDD = 3V) TO OUTPUT 1.6V PIN 50pF I1S0O0UµRAC WE (IT20H0 DµAV DWDI T= H3 VD)VDD = 5V, 07822-002 Figure 2. Load Circuit for Timing Characterization Rev. A | Page 7 of 40

AD7192 CS (I) t t 6 1 t 5 DOUT/RDY (O) MSB LSB t t 7 2 t 3 SCLK (I) I = INPUT, O = OUTPUT t4 07822-003 Figure 3. Read Cycle Timing Diagram CS (I) t8 t11 SCLK (I) t 9 t 10 DIN (I) MSB LSB I = INPUT, O = OUTPUT 07822-004 Figure 4. Write Cycle Timing Diagram Rev. A | Page 8 of 40

AD7192 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A THERMAL RESISTANCE Table 3. Parameter Rating θJA is specified for the worst-case conditions, that is, a device AVDD to AGND −0.3 V to +6.5 V soldered in a circuit board for surface-mount packages. DVDD to AGND −0.3 V to +6.5 V Table 4. Thermal Resistance AGND to DGND −0.3 V to +0.3 V Package Type θ θ Unit JA JC Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V 24-Lead TSSOP 128 42 °C/W Reference Input Voltage to AGND −0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND −0.3 V to DVDD + 0.3 V ESD CAUTION Digital Output Voltage to DGND −0.3 V to DVDD + 0.3 V AIN/Digital Input Current 10 mA Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature, Soldering Reflow 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 9 of 40

AD7192 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS MCLK1 1 24 DIN MCLK2 2 23 DOUT/RDY SCLK 3 22 SYNC CS 4 AD7192 21 DVDD P3 5 (NToOt Pto V SIEcaWle) 20 AVDD P2 6 19 DGND P1/REFIN2(+) 7 18 AGND P0/REFIN2(–) 8 17 BPDSW NC 9 16 REFIN1(–) AINCOM 10 15 REFIN1(+) AIN1 11 14 AIN4 AIN2 12NC = NO CONNECT13 AIN3 07822-005 Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 MCLK1 When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. 2 MCLK2 Master Clock Signal for the Device. The AD7192 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7192 can be provided externally also in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected. 3 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt- triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information transmitted to or from the ADC in smaller batches of data. 4 CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. 5 P3 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AV and AGND. DD 6 P2 Digital Output Pin. This pin can function as a general-purpose output bit referenced between AV and AGND. DD 7 P1/REFIN2(+) Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced between AV and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as REFIN2(+). DD An external reference can be applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie anywhere between AV and AGND + 1 V. The nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AV , but the part functions DD DD with a reference from 1 V to AV . DD 8 P0/REFIN2(−) Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced between AV and AGND. When the REFSEL bit in the configuration register = 1, this pin functions as REFIN2(−). DD This reference input can lie anywhere between AGND and AV − 1 V. DD 9 NC No Connect. This pin should be tied to AGND. 10 AINCOM Analog inputs AIN1 to AIN4 are referenced to this input when configured for pseudodifferential operation. 11 AIN1 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN2 or as a pseudodifferential input when used with AINCOM. 12 AIN2 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN1 or as a pseudodifferential input when used with AINCOM. Rev. A | Page 10 of 40

AD7192 Pin No. Mnemonic Description 13 AIN3 Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN4 or as a pseudodifferential input when used with AINCOM. 14 AIN4 Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN3 or as a pseudodifferential input when used with AINCOM. 15 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+) can lie anywhere between AV and AGND + 1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is DD AV , but the part functions with a reference from 1 V to AV . DD DD 16 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between AGND and AV − 1 V. DD 17 BPDSW Bridge Power-Down Switch to AGND. 18 AGND Analog Ground Reference Point. 19 DGND Digital Ground Reference Point. 20 AV Analog Supply Voltage, 3 V to 5.25 V. AV is independent of DV . Therefore, DV can be operated at 3 V with DD DD DD DD AV at 5 V or vice versa. DD 21 DV Digital Supply Voltage, 2.7 V to 5.25 V. DV is independent of AV . Therefore, AV can be operated at 3 V DD DD DD DD with DV at 5 V or vice versa. DD 22 SYNC Logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7192 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally to DV . DD 23 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDYserves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. 24 DIN Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register selection bits of the communications register identifying the appropriate register. Rev. A | Page 11 of 40

AD7192 TYPICAL PERFORMANCE CHARACTERISTICS 8,388,884 45 8,388,882 40 8,388,880 35 8,388,878 30 E C E8,388,876 EN 25 D R O R C8,388,874 CU 20 C O 8,388,872 15 8,388,870 10 8,388,868 5 8,388,866 0 0 200 400SAMPLE600 800 1000 07822-006 8,388,850 8,388,870 8,388,8C9O0DE 8,388,910 8,388,930 07822-009 Figure 6. Noise (VREF = AVDD = 5 V, Output Data Rate = 4.7 Hz, Figure 9. Noise Distribution Histogram (VREF = AVDD = 5 V, Gain = 128, Chop Disabled, Sinc4 Filter) Output Data Rate = 2400 Hz, Gain = 1, Chop Disabled, Sinc4 Filter) 200 8,389,050 8,389,000 150 8,388,950 E 8,388,900 C N E E RR 100 OD8,388,850 U C C OC 8,388,800 50 8,388,750 8,388,700 0 8,388,650 8,388,865 8,388,869 8,388,873 C8O,3D8E8,877 8,388,881 8,388,885 07822-007 0 200 400SAMPLE600 800 1000 07822-010 Figure 7. Noise Distribution Histogram (VREF = AVDD = 5 V, Figure 10. Noise (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) Gain = 128, Chop Disabled, Sinc4 Filter) 8,388,940 15 8,388,930 8,388,920 8,388,910 10 E 8,388,900 C N E E OD8,388,890 RR C U C 8,388,880 C O 5 8,388,870 8,388,860 8,388,850 8,388,840 0 0 200 400SAMPLE600 800 1000 07822-008 8,388,740 8,388,800 8,388,860COD8E,388,920 8,388,980 8,389,04007822-011 Figure 8. Noise (VREF = AVDD = 5 V, Output Data Rate = 2400 Hz, Figure 11. Noise Distribution Histogram (VREF = AVDD = 5 V, Gain = 1, Chop Disabled, Sinc4 Filter) Output Data Rate = 2400 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) Rev. A | Page 12 of 40

AD7192 5 0.4 0.2 4 0 3 R) –0.2 m of FS 2 ET (µV) –0.4 L (pp 1 OFFS –0.6 IN –0.8 0 –1.0 –1 –1.2 –2 –1.4 –4 –3 –2 –1 VIN0 (V) 1 2 3 4 07822-112 –60 –40 –20 0TEMP2E0RATU4R0E (°C6)0 80 100 120 07822-115 Figure 12. INL (Gain = 1) Figure 15. Offset Error (Gain = 128, Chop Disabled) 20 1.000008 15 1.000006 1.000004 10 1.000002 FSR) 5 1.000000 of N m 0 AI0.999998 p G p L ( –5 0.999996 N I 0.999994 –10 0.999992 –15 0.999990 –20 0.999988 –0.03 –0.02 –0.01 VIN0 (V) 0.01 0.02 0.03 07822-113 –60 –40 –20 0TEMP2E0RATU4R0E (°C6)0 80 100 120 07822-116 Figure 13. INL (Gain = 128) Figure 16. Gain Error (Gain = 1) 170 128.004 168 128.002 166 128.000 V) 164 127.998 µ ET ( 162 AIN 127.996 S G F F O 160 127.994 158 127.992 156 127.990 154 127.988 –60 –40 –20 0TEMP2E0RATU4R0E (°C6)0 80 100 120 07822-114 –60 –40 –20 0TEMP2E0RATU4R0E (°C6)0 80 100 120 07822-117 Figure 14. Offset Error (Gain = 1, Chop Disabled) Figure 17. Gain Error (Gain = 128) Rev. A | Page 13 of 40

AD7192 RMS NOISE AND RESOLUTION The AD7192 has a choice of two filter types: sinc4 and sinc3. on a single channel. The effective resolution is also shown, and In addition, the AD7192 can be operated with chop enabled the output peak-to-peak (p-p) resolution, or noise-free resolution, or chop disabled. is listed in parentheses. It is important to note that the effective resolution is calculated using the rms noise, whereas the p-p The following tables show the rms noise of the AD7192 for some resolution is calculated based on peak-to-peak noise. The p-p of the output data rates and gain settings with chop disabled resolution represents the resolution for which there is no code and enabled for the sinc4 and sinc3 filters. The numbers given flicker. These numbers are typical and are rounded to the are for the bipolar input range with the external 5 V reference. nearest ½ LSB. These numbers are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting SINC4 CHOP DISABLED Table 6. RMS Noise (nV) vs. Gain and Output Data Rate Output Settling Filter Word Data Rate Time (Decimal) (Hz) (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1023 4.7 852.5 350 50 30 18 13 11 640 7.5 533 425 62 36 21 15 13 480 10 400 490 85 43 23 17 15 96 50 80 2000 260 134 73 46 34 80 60 66.7 2100 273 139 77 48 38 40 120 33.3 2400 315 175 95 64 51 32 150 26.7 2500 335 185 110 71 58 16 300 13.3 3100 420 240 145 95 81 5 960 4.17 4800 690 390 240 170 145 2 2400 1.67 7500 1100 640 390 273 235 1 4800 0.83 16,300 2200 1200 670 427 345 Table 7. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Output Settling Filter Word Data Rate Time (Decimal) (Hz) (ms) Gain of 11 Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281 1023 4.7 852.5 24 (22) 24 (22) 24 (21.5) 24 (21.5) 23.5 (21) 22.5 (20) 640 7.5 533 24 (22) 24 (21.5) 24 (21.5) 23.5 (21) 23 (20.5) 22.5 (20) 480 10 400 24 (21.5) 23.5 (21) 23.5 (21) 23.5 (21) 23 (20.5) 22 (19.5) 96 50 80 22 (19.5) 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 21 (18.5) 80 60 66.7 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 20.5 (18) 40 120 33.3 22 (19.5) 21.5 (19) 21.5 (19) 21.5 (19) 21 (18.5) 20.5 (18) 32 150 26.7 21.5 (19) 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 20 (17.5) 16 300 13.3 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 20.5 (18) 19.5 (17) 5 960 4.17 20.5 (18) 20.5 (18) 20.5 (18) 20 (17.5) 19.5 (17) 19 (16.5) 2 2400 1.67 20 (17.5) 20 (17.5) 19.5 (17) 19.5 (17) 19 (16.5) 18 (15.5) 1 4800 0.83 19 (16.5) 19 (16.5) 19 (16.5) 18.5 (16) 18.5 (16) 17.5 (15) 1 The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. A | Page 14 of 40

AD7192 SINC3 CHOP DISABLED Table 8. RMS Noise (nV) vs. Gain and Output Data Rate Output Filter Word Data Rate Settling (Decimal) (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1023 4.7 639.4 350 51 30 18 15 12 640 7.5 400 440 62 36 22 18 15 480 10 300 500 87 45 26 19 17 96 50 60 2000 255 134 73 47 36 80 60 50 2100 273 139 77 49 40 40 120 25 2400 315 168 96 66 55 32 150 20 2500 335 185 105 73 62 16 300 10 3100 425 235 136 100 86 5 960 3.13 5300 745 415 250 180 156 2 2400 1.25 55800 7100 3600 1750 910 500 1 4800 0.625 446,000 55,400 28,000 14,000 7000 3500 Table 9. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Output Filter Word Data Rate Settling (Decimal) (Hz) Time (ms) Gain of 11 Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281 1023 4.7 639.4 24 (22) 24 (22) 24 (21.5) 24 (21.5) 23 (20.5) 22.5 (20) 640 7.5 400 24 (21.5) 24 (21.5) 24 (21.5) 23.5 (21) 23 (20.5) 22 (19.5) 480 10 300 24 (21.5) 23.5 (21) 23.5 (21) 23.5 (21) 22.5 (20) 22 (19.5) 96 50 60 22 (19.5) 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 21 (18.5) 80 60 50 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 20.5 (18) 40 120 25 22 (19.5) 21.5 (19) 21.5 (19) 21.5 (19) 21 (18.5) 20 (17.5) 32 150 20 21.5 (19) 21.5 (19) 21.5 (19) 21.5 (19) 21 (18.5) 20 (17.5) 16 300 10 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 20.5 (18) 19.5 (17) 5 960 3.13 20.5 (18) 20.5 (18) 20.5 (18) 20 (17.5) 19.5 (17) 18.5 (16) 2 2400 1.25 17 (14.5) 17 (14.5) 17 (14.5) 17 (14.5) 17 (14.5) 17 (14.5) 1 4800 0.625 14 (11.5) 14 (11.5) 14 (11.5) 14 (11.5) 14 (11.5) 14 (11.5) 1 The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. A | Page 15 of 40

AD7192 SINC4 CHOP ENABLED Table 10. RMS Noise (nV) vs. Gain and Output Data Rate Output Filter Word Data Rate Settling (Decimal) (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1023 1.175 1702 248 36 22 13 9 8 640 1.875 1067 301 44 26 15 11 10 480 2.5 800 347 61 31 17 13 11 96 12.5 160 1420 184 95 52 33 25 80 15 133 1490 194 99 55 34 27 40 30 66.7 1700 223 124 68 46 37 32 37.5 53.3 1770 237 131 78 51 42 16 75 26.7 2200 297 170 103 68 58 5 240 8.33 3400 488 276 170 121 103 2 600 3.33 5310 780 453 276 194 167 1 1200 1.67 11,600 1560 849 474 302 244 Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Output Filter Word Data Rate Settling (Decimal) (Hz) Time (ms) Gain of 11 Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281 1023 1.175 1702 24 (22.5) 24 (22.5) 24 (22) 24 (22) 24 (21.5) 23 (20.5) 640 1.875 1067 24 (22.5) 24 (22) 24 (22) 24 (21.5) 23.5 (21) 23 (20.5) 480 2.5 800 24 (22) 24 (21.5) 24 (21.5) 24 (21.5) 23.5 (21) 22.5 (20) 96 12.5 160 22.5 (20) 22.5 (20) 22.5 (20) 22.5 (20) 22 (19.5) 21.5 (19) 80 15 133 22.5 (20) 22.5 (20) 22.5 (20) 22 (19.5) 22 (19.5) 21 (18.5) 40 30 66.7 22.5 (20) 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 21 (18.5) 32 37.5 53.3 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 20.5 (18) 16 75 26.7 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 20 (17.5) 5 240 8.33 21 (18.5) 21 (18.5) 21 (18.5) 20.5 (18) 20 (17.5) 19.5 (17) 2 600 3.33 20.5 (18) 20.5 (18) 20 (17.5) 20 (17.5) 19.5 (17) 18.5 (16) 1 1200 1.67 19.5 (17) 19.5 (17) 19.5 (17) 19 (16.5) 19 (16.5) 18 (15.5) 1 The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. A | Page 16 of 40

AD7192 SINC3 CHOP ENABLED Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Output Filter Word Data Rate Settling (Decimal) (Hz) Time (ms) Gain of 1 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 1023 1.56 1282 248 37 22 13 11 9 640 2.5 800 312 44 26 16 13 11 480 3.33 600 354 62 32 19 14 13 96 16.6 120 1415 181 95 52 34 26 80 20 100 1485 194 99 55 35 29 40 40 50 1698 223 119 68 47 39 32 50 40 1768 237 131 75 52 44 16 100 20 2193 301 167 97 71 61 5 320 6.25 3748 527 294 177 128 111 2 800 2.5 39500 5020 2546 1240 644 354 1 1600 1.25 315,400 39,200 19,800 9900 4950 2500 Table 13. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Output Filter Word Data Rate Settling (Decimal) (Hz) Time (ms) Gain of 11 Gain of 81 Gain of 161 Gain of 321 Gain of 641 Gain of 1281 1023 1.56 1282 24 (22.5) 24 (22.5) 24 (22) 24 (22) 23.5 (21) 23 (20.5) 640 2.5 800 24 (22) 24 (22) 24 (22) 24 (21.5) 23.5 (21) 22.5 (20) 480 3.33 600 24 (22) 24 (21.5) 24 (21.5) 24 (21.5) 23 (20.5) 22.5 (20) 96 16.6 120 22.5 (20) 22.5 (20) 22.5 (20) 22.5 (20) 22 (19.5) 21.5 (19) 80 20 100 22.5 (20) 22.5 (20) 22.5 (20) 22 (19.5) 22 (19.5) 21 (18.5) 40 40 50 22.5 (20) 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 20.5 (18) 32 320 40 22 (19.5) 22 (19.5) 22 (19.5) 22 (19.5) 21.5 (19) 20.5 (18) 16 100 20 22(19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 20 (17.5) 5 320 6.25 21 (18.5) 20.5 (18) 20.5 (18) 20 (17.5) 19.5 (17) 18.5 (16) 2 800 2.5 17.5 (15) 17.5 (15) 17.5 (15) 17.5 (15) 17.5 (15) 17.5 (15) 1 1600 1.25 14.5 (12) 14.5 (12) 14.5 (12) 14.5 (12) 14.5 (12) 14.5 (12) 1 The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. A | Page 17 of 40

AD7192 ON-CHIP REGISTERS or write operation to the selected register is complete, the The ADC is controlled and configured via a number of on-chip interface returns to where it expects a write operation to the registers that are described on the following pages. In the communications register. This is the default state of the following descriptions, “set” implies a Logic 1 state and interface and, on power-up or after a reset, the ADC is in this “cleared” implies a Logic 0 state, unless otherwise noted. default state waiting for a write operation to the communica- COMMUNICATIONS REGISTER tions register. In situations where the interface sequence is lost, (RS2, RS1, RS0 = 0, 0, 0) a write operation of at least 40 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. The communications register is an 8-bit write-only register. All Table 14 outlines the bit designations for the communications communications to the part must start with a write operation to register. CR0 through CR7 indicate the bit location, CR denoting the communications register. The data written to the communi- that the bits are in the communications register. CR7 denotes cations register determines whether the next operation is a read the first bit of the data stream. The number in parentheses or write operation and in which register this operation takes indicates the power-on/reset default status of that bit. place. For read or write operations, when the subsequent read CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 WEN(0) R/W(0) RS2(0) RS1(0) RS0(0) CREAD(0) 0(0) 0(0) Table 14. Communications Register Bit Designations Bit Location Bit Name Description CR7 WEN Write enable bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If a 1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at this bit location until a 0 is written to this bit. After a 0 is written to the WEN bit, the next seven bits are loaded to the communications register. Idling the DIN pin high between data transfers minimizes the effects of spurious SCLK pulses on the serial interface. CR6 R/W A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position indicates that the next operation is a read from the designated register. CR5 to CR3 RS2 to RS0 Register address bits. These address bits are used to select which registers of the ADC are selected during the serial interface communication (see Table 15). CR2 CREAD Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read; that is, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete. The communications register does not have to be written to for subsequent data reads. To enable continuous read, the Instruction 01011100 must be written to the communications register. To disable continuous read, the Instruction 01011000 must be written to the communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low until an instruction is to be written to the device. CR1 to CR0 0 These bits must be programmed to Logic 0 for correct operation. Table 15. Register Selection RS2 RS1 RS0 Register Register Size 0 0 0 Communications register during a write operation 8 bits 0 0 0 Status register during a read operation 8 bits 0 0 1 Mode register 24 bits 0 1 0 Configuration register 24 bits 0 1 1 Data register/data register plus status information 24 bits/32 bits 1 0 0 ID register 8 bits 1 0 1 GPOCON register 8 bits 1 1 0 Offset register 24 bits 1 1 1 Full-scale register 24 bits Rev. A | Page 18 of 40

AD7192 STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 16 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 RDY(1) ERR(0) NOREF(0) PARITY(0) 0(0) CHD2(0) CHD1(0) CHD0(0) Table 16. Status Register Bit Designations Bit Location Bit Name Description SR7 RDY Ready bit for the ADC. This bit is cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register is read, or a period of time before the data register is updated, with a new conversion result to indicate to the user that the conversion data should not be read. It is also set when the part is placed in power-down mode or idle mode or when SYNC is taken low. The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. SR6 ERR ADC error bit. This bit is written to at the same time as the RDY bit. This bit is set to indicate that the result written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange or under- range or the absence of a reference voltage. This bit is cleared when the result written to the data register is within the allowed analog input range again. SR5 NOREF No external reference bit. This bit is set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled by setting the REFDET bit in the configuration register to 1. SR4 PARITY Parity check of the data register. If the ENPAR bit in the mode register is set, the PARITY bit is set if there is an odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data register. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. SR3 0 This bit is set to 0. SR2 to SR0 CHD2 to These bits indicate which channel corresponds to the data register contents. They do not indicate which CHD0 channel is presently being converted but indicate which channel was selected when the conversion contained in the data register was generated. MODE REGISTER (RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x080060) The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the output data rate, and the clock source. Table 17 outlines the bit designations for the mode register. MR0 through MR23 indicate the bit locations, MR denoting that the bits are in the mode register. MR23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and filter and sets the RDY bit. MR23 MR22 MR21 MR20 MR19 MR18 MR17 MR16 MD2(0) MD1(0) MD0(0) DAT_STA(0) CLK1(1) CLK0(0) 0 0 MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 SINC3(0) 0 ENPAR(0) CLK_DIV(0) SINGLE(0) REJ60(0) FS9(0) FS8(0) MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 FS7(0) FS6(1) FS5(1) FS4(0) FS3(0) FS2(0) FS1(0) FS0(0) Rev. A | Page 19 of 40

AD7192 Table 17. Mode Register Bit Designations Bit Location Bit Name Description MR23 to MR21 MD2 to MD0 Mode select bits. These bits select the operating mode of the AD7192 (see Table 18). MR20 DAT_STA This bit enables the transmission of status register contents after each data register read. When DAT_STA is set, the contents of the status register are transmitted along with each data register read. This function is useful when several channels are selected because the status register identifies the channel to which the data register value corresponds. MR19, MR18 CLK1, CLK0 These bits are used to select the clock source for the AD7192. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7192 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7192. CLK1 CLK0 ADC Clock Source 0 0 External crystal. The external crystal is connected from MCLK1 to MCLK2. 0 1 External clock. The external clock is applied to the MCLK2 pin. 1 0 Internal 4.92 MHz clock. Pin MCLK2 is tristated. 1 1 Internal 4.92 MHz clock. The internal clock is available on MCLK2. MR17, MR16 0 These bits must be programmed with a Logic 0 for correct operation. MR15 SINC3 Sinc3 filter select bit. When this bit is cleared, the sinc4 filter is used (default value). When this bit is set, the sinc3 filter is used. The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time. For a given output data rate, f , the sinc3 filter has a settling time of 3/f while the sinc4 filter has a ADC ADC settling time of 4/f when chop is disabled. The sinc4 filter, due to its deeper notches, gives better ADC 50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no missing codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc4 filter gives better performance than the sinc3 filter for rms noise and no missing codes. MR14 0 This bit must be programmed with a Logic 0 for correct operation. MR13 ENPAR Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. MR12 CLK_DIV Clock Divide by 2. When CLK_DIV is set, the master clock is divided by 2. For normal conversions, this bit should be set to 0. When performing internal full-scale calibrations, this bit must be set when AVDD is less than 4.75 V. The calibration accuracy is optimized when chop is enabled and a low output data rate is used while performing the calibration. When AVDD is greater than or equal to 4.75 V, it is not compulsory to set the CLK_DIV bit when performing internal full-scale calibrations. MR11 SINGLE Single cycle conversion enable bit. When this bit is set, the AD7192 settles in one conversion cycle so that it functions as a zero-latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected. MR10 REJ60 This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/ 60 Hz rejection. MR9 to MR0 FS9 to FS0 Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter cut-off frequency, the position of the first notch of the filter, and the output data rate for the part. In association with the gain selection, they also determine the output noise (and, therefore, the effective resolution) of the device (see Table 6 through Table 13). When chop is disabled and continuous conversion mode is selected, Output Data Rate = (MCLK/1024)/FS where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in an output data rate from 4.69 Hz to 4.8 kHz. With chop disabled, the first notch frequency is equal to the output data rate when converting on a single channel. When chop is enabled, Output Data Rate = (MCLK/1024)/(N x FS) where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter. The sinc filter’s first notch frequency is equal to N × output data rate. The chopping introduces notches at odd integer multiples of (output data rate/2). Rev. A | Page 20 of 40

AD7192 Table 18. Operating Modes MD2 MD1 MD0 Mode 0 0 0 Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in the status register go low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the commun- ications register to 1, which enables continuous read. When continuous read is enabled, the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output each conversion by writing to the communications register. After power-on, a reset, or a reconfiguration of the ADC, the complete settling time of the filter is required to generate the first valid conversion. Subsequent conversions are available at the selected output data rate, which is dependent on filter choice. 0 0 1 Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in the data register. RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register until another conversion is performed. RDY remains active (low) until the data is read or another conversion is performed. 0 1 0 Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks are still provided. 0 1 1 Power-down mode. In power-down mode, all AD7192 circuitry, except the bridge power-down switch, is powered down. The bridge power-down switch remains active because the user may need to power up the sensor prior to powering up the AD7192 for settling reasons. The external crystal, if selected, remains active. 1 0 0 Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. 1 0 1 Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize the full- scale error. When AV is less than 4.75 V, the CLK_DIV bit must be set when performing the internal full-scale DD calibration. 1 1 0 System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is required each time the gain of a channel is changed. 1 1 1 System full-scale calibration. The user should connect the system full-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed. CONFIGURATION REGISTER (RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x000117) The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel. Table 19 outlines the bit designations for the filter register. CON0 through CON23 indicate the bit locations. CON denotes that the bits are in the configuration register. CON23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. CON23 CON22 CON21 CON20 CON19 CON18 CON17 CON16 CHOP(0) 0(0) 0(0) REFSEL(0) 0(0) 0(0) 0(0) (0) CON15 CON14 CON13 CON12 CON11 CON10 CON9 CON8 CH7(0) CH6(0) CH5(0) CH4(0) CH3(0) CH2(0) CH1(0) CH0(1) CON7 CON6 CON5 CON4 CON3 CON2 CON1 CON0 BURN(0) REFDET(0) 0(0) BUF(1) U/B (0) G2(1) G1(1) G0(1) Rev. A | Page 21 of 40

AD7192 Table 19. Configuration Register Bit Designations Bit Location Bit Name Description CON23 CHOP Chop enable bit. When the CHOP bit is cleared, chop is disabled. When the CHOP bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC are continuously removed. However, this increases the conversion time and settling time of the ADC. For example, when FS = 96 decimal and the sinc4 filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an FS word of 96 decimal and the sinc4 filter selected, the conversion time is 20 ms and the settling time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and offset drift. CON22, CON21 0 These bits must be programmed with a Logic 0 for correct operation. CON20 REFSEL Reference select bits. The reference source for the ADC is selected using these bits. REFSEL Reference Voltage 0 External reference applied between REFIN1(+) and REFIN1(−). 1 External reference applied between the P1/REFIN2(+) and P0/REFIN2(−) pins. CON19 to CON16 0 These bits must be programmed with a Logic 0 for correct operation. CON15 to CON8 CH7 to CH0 Channel select bits. These bits are used to select which channels are enabled on the AD7192 (see Table 20). Several channels can be selected, and the AD7192 automatically sequences them. The conversion on each channel requires the complete settling time. When performing calibrations or when accessing the calibration registers, only one channel can be selected. CON7 BURN When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When BURN = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and when chop is disabled. CON6 REFDET Enables the reference detect function. When set, the NOREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference detect circuitry operates only when the ADC is active. CON5 0 This bit must be programmed with a Logic 0 for correct operation. CON4 BUF Enables the buffer on the analog inputs. If cleared, the analog inputs are unbuffered, lowering the power consumption of the device. If this bit is set, the analog inputs are buffered, allowing the user to place source impedances on the front end without contributing gain errors to the system. With the buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above AV . When the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin DD must be limited to 250 mV within the power supply rails. CON3 U/B Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar operation is selected. CON2 to CON0 G2 to G0 Gain select bits. These bits are written by the user to select the ADC input range as follows: G2 G1 G0 Gain ADC Input Range (5 V Reference) 0 0 0 1 ±5 V 0 0 1 Reserved 0 1 0 Reserved 0 1 1 8 ±625 mV 1 0 0 16 ±312.5 mV 1 0 1 32 ±156.2 mV 1 1 0 64 ±78.125 mV 1 1 1 128 ±39.06 mV Rev. A | Page 22 of 40

AD7192 Table 20. Channel Selection Channel Enable Bits in the Configuration Register Channel Enabled Positive Input Negative Input Status Register Calibration CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 AIN(+) AIN(−) Bits CHD[2:0] Register Pair 1 AIN1 AIN2 000 0 1 AIN3 AIN4 001 1 1 Temperature sensor 010 None 1 AIN2 AIN2 011 0 1 AIN1 AINCOM 100 0 1 AIN2 AINCOM 101 1 1 AIN3 AINCOM 110 2 1 AIN4 AINCOM 111 3 ID REGISTER DATA REGISTER (RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xX0) (RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000) The identification number for the AD7192 is stored in the ID The conversion result from the ADC is stored in this data register. This is a read-only register. register. This is a read-only, 24-bit register. On completion of a read operation from this register, the RDY pin/bit is set. When the DAT_STA bit in the mode register is set to 1, the contents of the status register are appended to each 24-bit conversion. This is advisable when several analog input channels are enabled because the three LSBs of the status register (CHD2 to CHD0) identify the channel from which the conversion originated. Rev. A | Page 23 of 40

AD7192 Table 21 outlines the bit designations for the GPOCON register. GPOCON REGISTER GP0 through GP7 indicate the bit locations. GP denotes that the (RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00) bits are in the GPOCON register. GP7 denotes the first bit of The GPOCON register is an 8-bit register from which data can the data stream. The number in parentheses indicates the be read or to which data can be written. This register is used to power-on/reset default status of that bit. enable the general-purpose digital outputs. GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0(0) BPDSW(0) GP32EN(0) GP10EN(0) P3DAT(0) P2DAT(0) P1DAT(0) P0DAT(0) Table 21. Register Bit Designations Bit Location Bit Name Description GP7 0 This bit must be programmed with a Logic 0 for correct operation. GP6 BPDSW Bridge power-down switch control bit. This bit is set by the user to close the bridge power-down switch BPDSW to AGND. The switch can sink up to 30 mA. The bit is cleared by the user to open the bridge power– down switch. When the ADC is placed in power-down mode, the bridge power-down switch remains active. GP5 GP32EN Digital Output P3 and Digital Output P2 enable. When GP32EN is set, the P3 and P2 digital outputs are active. When GP32EN is cleared, the P3 and P2 pins are tristated, and the P3DAT and P2DAT bits are ignored. GP4 GP10EN Digital Output P1 and Digital Output P0 enable. When GP10EN is set, the P1 and P0 digital outputs are active. When GP10EN is cleared, the P1 and P0 outputs are tristated, and the P1DAT and P0DAT bits are ignored. The P1 and P0 pins can be used as a reference input to REFIN2 when the REFSEL bit in the configuration register is set to 1. GP3 P3DAT Digital Output P3. When GP32EN is set, the P3DAT bit sets the value of the P3 general-purpose output pin. When P3DAT is high, the P3 output pin is high. When P3DAT is low, the P3 output pin is low. When the GPOCON register is read, the P3DAT bit reflects the status of the P3 pin if GP32EN is set. GP2 P2DAT Digital Output P2. When GP32EN is set, the P2DAT bit sets the value of the P2 general-purpose output pin. When P2DAT is high, the P2 output pin is high. When P2DAT is low, the P2 output pin is low. When the GPOCON register is read, the P2DAT bit reflects the status of the P2 pin if GP32EN is set. GP1 P1DAT Digital Output P1. When GP10EN is set, the P1DAT bit sets the value of the P1 general-purpose output pin. When P1DAT is high, the P1 output pin is high. When P1DAT is low, the P1 output pin is low. When the GPOCON register is read, the P1DAT bit reflects the status of the P1 pin if GP10EN is set. GP0 P0DAT Digital Output P0. When GP10EN is set, the P0DAT bit sets the value of the P0 general-purpose output pin. When P0DAT is high, the P0 output pin is high. When P0DAT is low, the P0 output pin is low. When the GPOCON register is read, the P0DAT bit reflects the status of the P0 pin if GP10EN is set. OFFSET REGISTER FULL-SCALE REGISTER (RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000) (RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXXX0) The offset register holds the offset calibration coefficient for the The full-scale register is a 24-bit register that holds the full-scale ADC. The power-on reset value of the offset register is calibration coefficient for the ADC. The AD7192 has four full- 0x800000. The AD7192 has four offset registers; therefore, each scale registers; therefore, each channel has a dedicated full-scale channel has a dedicated offset register (see Table 20). Each of register (see Table 20). The full-scale registers are read/write these registers is a 24-bit read/write register. This register is registers. However, when writing to the full-scale registers, the used in conjunction with its associated full-scale register to ADC must be placed in power-down mode or idle mode. These form a register pair. The power-on reset value is automatically registers are configured at power-on with factory-calibrated overwritten if an internal or system zero-scale calibration is full-scale calibration coefficients, the calibration being performed initiated by the user. The AD7192 must be placed in power- at gain = 1. Therefore, every device has different default coeffic- down mode or idle mode when writing to the offset register. ients. The default value is automatically overwritten if an internal or system full-scale calibration is initiated by the user or if the full-scale register is written to. Rev. A | Page 24 of 40

AD7192 ADC CIRCUIT INFORMATION 5V REFIN1(+)AGND AVDD DVDD DGND REFERENCE DETECT IN+ AIN1 AVDD AIN2 OUT– OUT+ AIN3 AIN4 SERIAL DOUT/RDY IN– AINCOM MUX PGA AΣD-ΔC INCTOEANRNTFDRAOCLE DSCINLK LOGIC CS SYNC AGND TEMP P3 REFIN1(–) SENSOR P2 BPDSW CLOCK AD7192 CIRCUITRY AGND MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+) 07822-012 Figure 18. Basic Connection Diagram OVERVIEW f = f /(1024 × FS[9:0]) ADC CLK The AD7192 is an ultralow noise ADC that incorporates a Σ-Δ where: modulator, a buffer, PGA, and on-chip digital filtering intended fADC is the output data rate. for the measurement of wide dynamic range signals such as f = master clock (4.92 MHz nominal). CLK those in pressure transducers, weigh scales, and strain gage FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the applications. mode register. The part can be configured to have two differential inputs or The output data rate can be programmed from 4.7 Hz to 4800 Hz; four pseudo differential inputs that can be buffered or unbuffered. that is, FS[9:0] can have a value from 1 to 1023. Figure 18 shows the basic connections required to operate the part. The previous equation is valid for both the sinc3 and sinc4 FILTER, OUTPUT DATA RATE, AND SETTLING TIME filters. The settling time for the sinc4 filter is equal to A Σ-Δ ADC consists of a modulator followed by a digital filter. tSETTLE = 4/fADC The AD7192 has two filter options: a sinc3 filter and a sinc4 and the settling time for the sinc3 filter is equal to filter. The filter is selected using the SINC3 bit in the mode t = 3/f register. When the SINC3 bit is set to 0 (default value), the sinc4 SETTLE ADC filter is selected. The sinc3 filter is selected when the SINC3 bit is Figure 19 and Figure 20 show the frequency response of the sinc4 set to 1. filter and sinc3 filter, respectively, for an output data rate of 50 Hz. At low output data rates (<1 kHz), the noise-free resolution is 0 comparable for the two filter types. However, at the higher –10 update rates, the sinc4 filter gives better noise-free resolution. –20 The sinc4 filter also leads to better 50 Hz and 60 Hz rejection. –30 B) While the notch positions are not affected by the order of the N (d –40 filter, the higher order filter has wider notches, which leads to AI G –50 better rejection in the band (±1 Hz) around the notches. It also R TE –60 gives better stop-band attenuation. The benefit of the sinc3 filter L FI –70 is its lower settling time for the same output data rate. –80 Chop Disabled –90 The output data rate (the rate at which conversions are available –100 oisn e aq usianl gtole channel when the ADC is continuously converting) 0 25 50FREQUE7N5CY (Hz)100 125 150 07822-013 Figure 19. Sinc4 Filter Response (50 Hz Output Data Rate) Rev. A | Page 25 of 40

AD7192 0 The value of FS[9:0] can be varied from 1 to 1023. This results –10 in an output data rate of 1.173 Hz to 1200 Hz for the sinc4 filter and 1.56 Hz to 1600 Hz for the sinc3 filter. The settling time for –20 sinc3 or sinc4 is equal to –30 B) N (d –40 tSETTLE = 2/fADC GAI –50 Therefore, with chop enabled, the settling time is reduced for a R TE –60 given output data rate compared to the chop disabled mode. L FI However, for a given FS[9:0] value, the output data rate is less –70 with chop enabled when compared with the chop disabled –80 mode. For either the sinc3 or sinc4 filter, the cutoff frequency f is 3dB –90 equal to –100 0 25 50FREQUE7N5CY (Hz)100 125 150 07822-014 Figurfe3d B2 1= a0n.2d4 F ×ig fuADreC 22 show the filter response for the sinc4 Figure 20. Sinc3 Filter Response (50 Hz Output Data Rate) filter and sinc3 filter, respectively, when chop is enabled. As The sinc4 filter provides 50 Hz (±1 Hz) rejection in excess of shown in the plots, the stop-band attenuation is less when 120 dB, assuming a stable master clock, and the sinc3 filter gives compared with the chop disabled modes. a rejection of 100 dB. The stop-band attenuation is, typically, 0 53 dB for the sinc4 filter but equal to 40 dB for the sinc3 filter. –10 The 3 dB frequency for the sinc4 filter is equal to –20 f3dB = 0.23 × fADC –30 B) and for the sinc3 filter, the 3 dB frequency is equal to N (d –40 AI f = 0.272 × f G –50 3dB ADC R Chop Enabled LTE –60 FI –70 With chop enabled, the ADC offset and offset drift are minimized. When chop is enabled, the analog input pins are –80 continuously swapped. Therefore, with the analog input pins –90 connected in one direction, the settling time of the sinc filter is –100 ainllpouwte pdi ntos aerlaep tshee nun itnivl ae rvtaeldid, acnodn vaenrositohne ris v aavlaidil acbolen.v Terhsei oann ailso g 0 25 50FREQUE7N5CY (Hz)100 125 150 07822-015 Figure 21. Sinc4 Filter Response (Output Data Rate =12.5 Hz, Chop Enabled) obtained. Subsequent conversions are then averaged so that the 0 offset is minimized. This continuous swapping of the analog input pins and the averaging of subsequent conversions means –10 that the offset drift is also minimized. –20 Chopping affects the output data rate and settling time of the –30 B) ADC. For sinc4, the output data rate is equal to N (d –40 AI f = f /(4 × 1024 × FS[9:0]) G –50 ADC CLK R For sinc3, the output data rate is equal to LTE –60 FI –70 f = f /(3 × 1024 × FS[9:0]) ADC CLK –80 where: –90 f is the output data rate. ADC FfCSLK[ 9=:0 m] iass tthere cdloeccikm (a4l. 9e2q uMivHalze nnto mof iBniatl )F. S9 to Bit FS0 in the –1000 25 50FREQUE7N5CY (Hz)100 125 150 07822-016 mode register. Figure 22. Sinc3 Filter Response (Output Data Rate = 16.6 Hz, Chop Enabled) Rev. A | Page 26 of 40

AD7192 50 Hz/60 Hz Rejection filter is used. Figure 25 and Figure 26 show the filter response for both output data rates when REJ60 is set to 1. Normal mode rejection is one of the main functions of the digital filter. With chop disabled, 50 Hz rejection is obtained 0 when the output data rate is set to 50 Hz, and 60 Hz rejection is –10 achieved when the output data rate is set to 60 Hz. Simulta- –20 neous 50 Hz and 60 Hz rejection is obtained when the output –30 data rate is set to 10 Hz. Simultaneous 50 Hz/60 Hz rejection B) can also be achieved using the REJ60 bit in the mode register. N (d –40 AI When the output data rate is programmed to 50 Hz and the G –50 R REJ60 bit is set to 1, notches are placed at both 50 Hz and 60 Hz. TE –60 L Figure 23 and Figure 24 show the frequency response of the FI –70 sinc4 filter and sinc3 filter, respectively, when the output data –80 rate is programmed to 50 Hz and REJ60 is set to 1. –90 0 –100 ––1200 0 25 50FREQUE7N5CY (Hz)100 125 150 07822-125 Figure 25. Sinc4 Filter Response (12.5 Hz Output Data Rate, –30 Chop Enabled, REJ60 = 1) B) N (d –40 0 AI G –50 –10 R TE –60 –20 L FI –70 –30 B) –80 N (d –40 AI –90 G –50 R –1000 25 50FREQUE7N5CY (Hz)100 125 150 07822-017 FILTE ––6700 Figure 23. Sinc4 Filter Response (50 Hz Output Data Rate, REJ60=1) –80 0 –90 –10 –100 –20 0 25 50FREQUE7N5CY (Hz)100 125 150 07822-126 –30 Figure 26. Sinc3 Filter Response (16.7 Hz Output Data Rate, N (dB) –40 Chop Enabled, REJ60 = 1) AI Zero Latency G –50 R TE –60 Zero latency is enabled by setting the SINGLE bit in the mode L FI register to 1. With zero latency, the complete settling time is –70 allowed for each conversion. Therefore, –80 f = 1/t –90 ADC SETTLE Zero latency means that the output data rate is constant –100 0 25 50FREQUE7N5CY (Hz)100 125 150 07822-018 itrhree supseecr tdivoee os fn tohte n neuemd tboe rc oonf saindaelro tgh ien epfufet ccths aonf ncehlas nennealb led; Figure 24. Sinc3 Filter Response (50 Hz Output Data Rate, REJ60=1) changes on the output data rate. The disadvantages of zero Again, the sinc4 filter provides better 50 Hz/60 Hz rejection latency are the increased noise for a given output data rate than the sinc3 filter. Also, better stop-band attenuation is compared with the nonzero latency mode. For example, when achieved with the sinc4 filter. zero latency is not enabled, the AD7192 has a noise-free When chop is enabled, lower output data rates must be used to resolution of 18.5 bits when the output data rate is 50 Hz and achieve 50 Hz and 60 Hz rejection. With REJ60 set to 1, an output the gain is set to 128. When zero latency is enabled, the ADC data rate of 12.5 Hz gives simultaneous 50 Hz/60 Hz rejection has a resolution of 17.5 bits peak-to-peak when the output data when the sinc4 filter is selected, whereas an output data rate of rate is 50 Hz. The filter response also changes. Figure 19 shows 16.7 Hz gives simultaneous 50 Hz/60 Hz rejection when the sinc3 the filter response for the sinc4 filter when the output data rate is 50 Hz (zero latency disabled). Figure 27 shows the filter response when zero latency is enabled and the output data rate Rev. A | Page 27 of 40

AD7192 is 50 Hz (sinc4 filter); 50 Hz rejection is no longer achieved. The For example, if the sinc4 filter is selected, chop is disabled, and ADC must operate with an output data rate of 12.5 Hz to obtain zero latency is disabled, the settling time for each channel is 50 Hz rejection when zero latency is enabled. To obtain equal to simultaneous 50 Hz/60 Hz rejection, the REJ60 bit in the mode t = 4/f SETTLE ADC register can be set when the output data rate is equal to 12.5 Hz. where f is the output data rate when continuously converting The stop-band attenuation is considerably reduced also (3 dB ADC on a single channel. The time required to sample N channels is compared with 53 dB in the nonzero latency mode). 0 4/(fADC × N) –10 RDY –20 CONVERSIONS N (dB) ––3400 CHANNEL A CHANN1/EfALD BC CHANNEL C 07822-019 GAI –50 Figure 28. Channel Sequencer R TE –60 DIGITAL INTERFACE L FI –70 As indicated in the On-Chip Registers section, the program- –80 mable functions of the AD7192 are controlled using a set of –90 on-chip registers. Data is written to these registers via the serial interface of the part. Read access to the on-chip registers is also –100 0 50 100 150 200FR2E50QU3E0N0CY3 5(H0z)400 450 500 550 600 07822-020 pstraorvt iwdeitdh bay w thriitse i ntot etrhfea cceo. mAmll cuonmicmatiuonnisc arteigoinst ewri. tAh fttheer ppoarwt emr-uosnt Figure 27. Sinc4 Filter Response (50 Hz Output Data Rate, Zero Latency) or reset, the device expects a write to its communications register. Channel Sequencer The data written to this register determines whether the next oper- ation is a read operation or a write operation and also determines The AD7192 includes a channel sequencer, which simplifies to which register this read or write operation occurs. Therefore, communications with the device in multichannel applications. write access to any of the other registers on the part begins with a The sequencer also optimizes the channel throughput of the write operation to the communications register, followed by a device because the sequencer switches channels at the optimum write to the selected register. A read operation from any other rate rather than waiting for instructions via the SPI interface. register (except when continuous read mode is selected) starts Bit CH0 to Bit CH7 in the configuration register are used to with a write to the communications register, followed by a read enable the required channels. In continuous conversion mode, operation from the selected register. the ADC selects each of the enabled channels in sequence and performs a conversion on the channel. The RDY pin goes low The serial interface of the AD7192 consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer when a valid conversion is available on each channel. When several channels are enabled, the contents of the status register data into the on-chip registers, and DOUT/RDY is used for should be attached to the 24-bit word so that the user can accessing data from the on-chip registers. SCLK is the serial clock identify the channel that corresponds to each conversion. To input for the device, and all data transfers (either on DIN or attach the status register value to the conversion, Bit DAT_STA DOUT/RDY) occur with respect to the SCLK signal. in the mode register should be set to 1. The DOUT/RDY pin functions as a data ready signal also, the When several channels are enabled, the ADC must allow the line going low when a new data-word is available in the output complete settling time to generate a valid conversion each time register. It is reset high when a read operation from the data that the channel is changed. The AD7192 takes care of this: register is complete. It also goes high prior to the updating of the when a channel is selected, the modulator and filter are reset data register to indicate when not to read from the device, to and the RDY pin is taken high. The AD7192 then allows the ensure that a data read is not attempted while the register is being complete settling time to generate the first conversion. RDY updated. CS is used to select a device. It can be used to decode the goes low only when a valid conversion is available. The AD7192 AD7192 in systems where several components are connected to then selects the next enabled channel and converts on that the serial bus. channel. The user can then read the data register while the Figure 3 and Figure 4 show timing diagrams for interfacing to the ADC is performing the conversion on the next channel. AD7192, with CS being used to decode the part. Figure 3 shows The time required to read a valid conversion from all enabled the timing for a read operation from the output shift register of channels is equal to the AD7192, and Figure 4 shows the timing for a write operation to the input shift register. It is possible to read the same word t × number of enabled channels SETTLE from the data register several times even though the DOUT/RDY Rev. A | Page 28 of 40

AD7192 line returns high after the first read operation. However, care Single Conversion Mode must be taken to ensure that the read operations are completed In single conversion mode, the AD7192 is placed in power- before the next output update occurs. In continuous read mode, down mode after conversions. When a single conversion is the data register can be read only once. initiated by setting MD2, MD1, and MD0 to 0, 0, 1, respectively, The serial interface can operate in 3-wire mode by tying CS low. in the mode register, the AD7192 powers up, performs a single In this case, the SCLK, DIN, and DOUT/RDY lines are used to conversion, and then returns to power-down mode. The on- communicate with the AD7192. The end of the conversion can be chip oscillator requires 1 ms, approximately, to power up. monitored using the RDY bit or pin. This scheme is suitable for DOUT/RDY goes low to indicate the completion of a conver- interfacing to microcontrollers. If CS is required as a decoding sion. When the data-word has been read from the data register, signal, it can be generated from a port pin. For microcontroller DOUT/RDY goes high. If CS is low, DOUT/RDY remains high interfaces, it is recommended that SCLK idle high between data until another conversion is initiated and completed. The data transfers. register can be read several times, if required, even when The AD7192 can be operated with CS used as a frame synchro- DOUT/RDY has gone high. nization signal. This scheme is useful for DSP interfaces. In this If several channels are enabled, the ADC sequences through the case, the first bit (MSB) is effectively clocked out by CS because enabled channels and performs a conversion on each channel. CS normally occurs after the falling edge of SCLK in DSPs. The When a conversion is started, DOUT/RDY goes high and SCLK can continue to run between data transfers, provided the remains high until a valid conversion is available. As soon as the timing numbers are obeyed. conversion is available, DOUT/RDY goes low. The ADC then The serial interface can be reset by writing a series of 1s to the selects the next channel and begins a conversion. The user can DIN input. If a Logic 1 is written to the AD7192 DIN line for at read the present conversion while the next conversion is being least 40 serial clock cycles, the serial interface is reset. This performed. As soon as the next conversion is complete, the data ensures that the interface can be reset to a known state if the register is updated; therefore, the user has a limited period in interface gets lost due to a software error or some glitch in the which to read the conversion. When the ADC has performed a system. Reset returns the interface to the state in which it expects single conversion on each of the selected channels, it returns to a write to the communications register. This operation resets the power-down mode. contents of all registers to their power-on values. Following a If the DAT_STA bit in the mode register is set to 1, the contents reset, the user should allow a period of 500 μs before addressing of the status register are output along with the conversion each the serial interface. time that the data read is performed. The four LSBs of the status The AD7192 can be configured to continuously convert or to register indicate the channel to which the conversion corresponds. perform a single conversion (see Figure 29 through Figure 31). CS 0x08 0x280060 0x58 DIN DATA DOUT/RDY SCLK 07822-021 Figure 29. Single Conversion Rev. A | Page 29 of 40

AD7192 Continuous Conversion Mode When several channels are enabled, the ADC continuously loops through the enabled channels, performing one conversion Continuous conversion is the default power-up mode. The on each channel per loop. The data register is updated as soon AD7192 converts continuously, and the RDY bit in the status as each conversion is available. The DOUT/RDY pin pulses low register goes low each time a conversion is complete. If CS is each time a conversion is available. The user can then read the low, the DOUT/RDY line also goes low when a conversion is conversion while the ADC converts on the next enabled channel. completed. To read a conversion, the user writes to the communications register, indicating that the next operation is a If the DAT_STA bit in the mode register is set to 1, the contents read of the data register. When the data-word has been read of the status register are output along with the conversion each from the data register, DOUT/RDY goes high. The user can time that the data read is performed. The status register read this register additional times, if required. However, the indicates the channel to which the conversion corresponds. user must ensure that the data register is not being accessed at the completion of the next conversion or else the new conversion word is lost. CS 0x58 0x58 DIN DATA DATA DOUT/RDY SCLK 07822-022 Figure 30. Continuous Conversion Rev. A | Page 30 of 40

AD7192 Continuous Read conversion is complete, and the new conversion is placed in the output serial register. Rather than write to the communications register each time a conversion is complete to access the data, the AD7192 can be To exit the continuous read mode, the Instruction 01011000 configured so that the conversions are placed on the DOUT/ must be written to the communications register while the RDY line automatically. By writing 01011100 to the communi- RDY pin is low. While in the continuous read mode, the ADC cations register, the user need only apply the appropriate monitors activity on the DIN line so that it can receive the number of SCLK cycles to the ADC, and the conversion word instruction to exit the continuous read mode. Additionally, a is automatically placed on the DOUT/RDY line when a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, conversion is complete. The ADC should be configured for DIN should be held low in continuous read mode until an continuous conversion mode. instruction is to be written to the device. When DOUT/RDY goes low to indicate the end of a conversion, When several channels are enabled, the ADC continuously sufficient SCLK cycles must be applied to the ADC; the data steps through the enabled channels and performs one con- conversion is then placed on the DOUT/RDY line. When the version on each channel each time that it is selected. DOUT/ conversion is read, DOUT/RDY returns high until the next RDY pulses low when a conversion is available. When the user conversion is available. In this mode, the data can be read only applies sufficient SCLK pulses, the data is automatically placed once. Also, the user must ensure that the data-word is read on the DOUT/RDY pin. If the DAT_STA bit in the mode before the next conversion is complete. If the user has not read register is set to 1, the contents of the status register are output the conversion before the completion of the next conversion, along with the conversion. The status register indicates the or if insufficient serial clocks are applied to the AD7192 to channel to which the conversion corresponds. read the word, the serial output register is reset when the next CS 0x5C DIN DATA DATA DATA DOUT/RDY SCLK 07822-023 Figure 31. Continuous Read Rev. A | Page 31 of 40

AD7192 CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL The analog input range must be limited to ±(AVDD – 1.25 V)/gain because the PGA requires some headroom. Therefore, if AV = DD The AD7192 has two differential/four pseudodifferential analog 5 V, the maximum analog input that can be applied to the input channels, which can be buffered or unbuffered. In buffered AD7192 is 0 to 3.75 V/gain in unipolar mode or ±3.75 V/gain mode (the BUF bit in the configuration register is set to 1), the in bipolar mode. input channel feeds into a high impedance input stage of the BIPOLAR/UNIPOLAR CONFIGURATION buffer amplifier. Therefore, the input can tolerate significant source impedances and is tailored for direct connection to The analog input to the AD7192 can accept either unipolar or external resistive-type sensors such as strain gages or resistance bipolar input voltage ranges. A bipolar input range does not temperature detectors (RTDs). imply that the part can tolerate negative voltages with respect to When BUF = 0, the part is operated in unbuffered mode. This system AGND. In pseudo-differential mode, signals are results in a higher analog input current. Note that this unbuffered referenced to AINCOM, while in differential mode, signals are input path provides a dynamic load to the driving source. referenced to the negative input of the differential pair. For Therefore, resistor/capacitor combinations on the input pins example, if AINCOM is 2.5 V and the AD7192 AIN1 analog can cause gain errors, depending on the output impedance of input is configured for unipolar mode with a gain of 2, the input the source that is driving the ADC input. Table 22 shows the voltage range on the AIN1 pin is 2.5 V to 3.75 V when a 2.5 V reference is used. allowable external resistance/capacitance values for unbuffered mode at a gain of 1 such that no gain error at the 20-bit level is If AINCOM is 2.5 V and the AD7192 AIN1 analog input is introduced. configured for bipolar mode with a gain of 2, the analog input range on AIN1 is 1.25 V to 3.75 V The bipolar/unipolar option Table 22. External R-C Combination for No 20-Bit Gain Error is chosen by programming the U/B bit in the configuration C (pF) R (Ω) register. 50 1.4 k 100 850 DATA OUTPUT CODING 500 300 When the ADC is configured for unipolar operation, the output 1000 230 code is natural (straight) binary with a zero differential input 5000 30 voltage resulting in a code of 00...00, a midscale voltage result- The absolute input voltage range in buffered mode is restricted ing in a code of 100...000, and a full-scale input voltage resulting to a range between AGND + 250 mV and AV − 250 mV. Care in a code of 111...111. The output code for any analog input DD must be taken in setting up the common-mode voltage so that voltage can be represented as these limits are not exceeded. Otherwise, there is degradation in Code = (2N × AIN × Gain)/V REF linearity and noise performance. When the ADC is configured for bipolar operation, the output The absolute input voltage in unbuffered mode includes the code is offset binary with a negative full-scale voltage resulting range between AGND − 50 mV and AV + 50 mV. The DD in a code of 000...000, a zero differential input voltage resulting negative absolute input voltage limit does allow the possibility in a code of 100...000, and a positive full-scale input voltage of monitoring small true bipolar signals with respect to AGND. resulting in a code of 111...111. The output code for any analog PROGRAMMABLE GAIN ARRAY (PGA) input voltage can be represented as When the gain stage is enabled, the output from the buffer is Code = 2N – 1 × [(AIN × Gain/VREF) + 1] applied to the input of the PGA. The presence of the PGA where AIN is the analog input voltage, Gain is the PGA setting means that signals of small amplitude can be gained within the (1 to 128), and N = 24. AD7192 while still maintaining excellent noise performance. CLOCK For example, when the gain is set to 128, the rms noise is 11 nV, typically, when the output data rate is 4.7 Hz, which is equivalent The AD7192 includes an internal 4.92 MHz clock on-chip. This to 22.5 bits of effective resolution or 20 bits of noise-free internal clock has a tolerance of ±4%. Either the internal clock resolution. or an external crystal/clock can be used as the clock source to the AD7192. The clock source is selected using the CLK1 and The AD7192 can be programmed to have a gain of 1, 8, 16, 32, CLK0 bits in the mode register. When an external crystal is 64, and 128 using Bit G2 to Bit G0 in the configuration register. used, it must be connected across the MCLK1 and MCLK2 Therefore, with an external 2.5 V reference, the unipolar ranges pins. The crystal manufacturer recommends the load capacitances are from 0 mV to 19.53 mV to 0 V to 2.5 V and the bipolar required for the crystal. The MCLK1 and MCLK2 pins of the ranges are from ±19.53 mV to ±2.5 V. AD7192 have a capacitance of 15 pF, typically. If an external Rev. A | Page 32 of 40

AD7192 clock source is used, the clock source must be connected to the The common-mode range for these differential inputs is from MCLK2 pin, and the MCLK1 pin can be left floating. AGND to AV . The reference input is unbuffered; therefore, DD excessive R-C source impedances introduce gain errors. The The internal clock can also be made available at the MCLK2 reference voltage REFIN (REFINx(+) − REFINx(−)) is AV pin. This is useful when several ADCs are used in an application DD nominal, but the AD7192 is functional with reference voltages and the devices must be synchronized. The internal clock from from 1 V to AV . In applications where the excitation (voltage one device can be used as the clock source for all ADCs in the DD or current) for the transducer on the analog input also drives system. Using a common clock, the devices can be synchro- the reference voltage for the part, the effect of the low frequency nized by applying a common reset to all devices, or the SYNC noise in the excitation source is removed because the application is pin can be pulsed. ratiometric. If the AD7192 is used in a nonratiometric applica- BURNOUT CURRENTS tion, a low noise reference should be used. The AD7192 contains two 500 nA constant current generators, Recommended 2.5 V reference voltage sources for the AD7192 one sourcing current from AVDD to AIN(+) and one sinking include the ADR421 and ADR431, which are low noise current from AIN(−) to AGND, where AIN(+) is the positive references. These references have low output impedances and analog input terminal and AIN(−) is the negative analog input are, therefore, tolerant to having decoupling capacitors on terminal in differential mode and AINCOM in pseudodiffer- REFINx(+) without introducing gain errors in the system. ential mode. The currents are switched to the selected analog Deriving the reference input voltage across an external resistor input pair. Both currents are either on or off, depending on the means that the reference input sees a significant external source burnout current enable (BURN) bit in the configuration impedance. External decoupling on the REFINx pins is not register. recommended in this type of circuit configuration. These currents can be used to verify that an external transducer REFERENCE DETECT is still operational before attempting to take measurements on The AD7192 includes on-chip circuitry to detect whether the that channel. After the burnout currents are turned on, they part has a valid reference for conversions or calibrations. This flow in the external transducer circuit, and a measurement of feature is enabled when the REFDET bit in the configuration the input voltage on the analog input channel can be taken. It register is set to 1. If the voltage between the selected REFINx(+) takes some time for the burnout currents to detect an open and REFINx(−) pins is between 0.3 V and 0.6 V, the AD7192 circuit condition because the currents must charge any external detects that it no longer has a valid reference. In this case, the capacitors. NOREF bit of the status register is set to 1. If the AD7192 is There are several reasons that a fault condition is detected. The performing normal conversions and the NOREF bit becomes front-end sensor may be open circuit. It could also mean that active, the conversion result is all 1s. the front-end sensor is overloaded or the reference may be Therefore, it is not necessary to continuously monitor the status absent and the NOREF bit in the status register is set, thus of the NOREF bit when performing conversions. It is only clamping the data to all 1s. necessary to verify its status if the conversion result read from The user must check these three cases before making a judgment. the ADC data register is all 1s. If the AD7192 is performing If the voltage measured is 0 V, it may indicate that the either an offset or full-scale calibration and the NOREF bit transducer has short circuited. The current sources work over becomes active, the updating of the respective calibration the normal absolute input voltage range specifications when the registers is inhibited to avoid loading incorrect coefficients to analog inputs are buffered and chop is disabled. these registers, and the ERR bit in the status register is set. If the REFERENCE user is concerned about verifying that a valid reference is in place every time a calibration is performed, the status of the The ADC has a fully differential input capability for the ERR bit should be checked at the end of the calibration cycle. reference channel. In addition, the user has the option of selecting one of two external reference options (REFIN1(x) or REFIN2(x)). The reference source for the AD7192 is selected using the REFSEL bit in the configuration register. The REFIN2(x) pins are dual purpose: they can function as two general-purpose output pins or as reference pins. When the REFSEL bit is set to 1, these pins automatically function as reference pins. Rev. A | Page 33 of 40

AD7192 RESET TEMPERATURE SENSOR The circuitry and serial interface of the AD7192 can be reset by Embedded in the AD7192 is a temperature sensor. This is writing consecutive 1s to the device; 40 consecutive 1s are selected using the CH2 bit in the configuration register. When required to perform the reset. This resets the logic, the digital the CH2 bit is set to 1, the temperature sensor is enabled. When filter, and the analog modulator, whereas all on-chip registers the temperature sensor is selected and bipolar mode is selected, are reset to their default values. A reset is automatically the device should return a code of 0x800000 when the temper- performed on power-up. When a reset is initiated, the user ature is 0 K. A one-point calibration is needed to get the optimum must allow a period of 500 μs before accessing any of the on- performance from the sensor. Therefore, a conversion at 25°C chip registers. A reset is useful if the serial interface loses should be recorded and the sensitivity calculated. The sensitivity synchronization due to noise on the SCLK line. is 2815 codes/°C, approximately. The equation for the temper- ature sensor is SYSTEM SYNCHRONIZATION Temp (K) = (Conversion – 0x800000)/2815 K The SYNC input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the Temp (°C) = Temp (K) – 273 part. This allows the user to start gathering samples of the Following the one-point calibration, the internal temperature analog input from a known point in time, that is, the rising edge sensor has an accuracy of ±2 °C, typically. of SYNC. SYNC needs to be taken low for at least four master BRIDGE POWER-DOWN SWITCH clock cycles to implement the synchronization function. In bridge applications such as strain gages and load cells, the If multiple AD7192 devices are operated from a common master bridge itself consumes the majority of the current in the system. clock, they can be synchronized so that their data registers are For example, a 350 Ω load cell requires 15 mA of current when updated simultaneously. A falling edge on the SYNC pin resets excited with a 5 V supply. To minimize the current consumption the digital filter and the analog modulator and places the AD7192 of the system, the bridge can be disconnected (when it is not into a consistent, known state. While the SYNC pin is low, the being used) using the bridge power-down switch. Figure 18 AD7192 is maintained in this state. On the SYNC rising edge, shows how the bridge power-down switch is used. The switch the modulator and filter are taken out of this reset state and, on can withstand 30 mA of continuous current, and it has an on the next clock edge, the part starts to gather input samples again. resistance of 11 Ω maximum. In a system using multiple AD7192 devices, a common signal to LOGIC OUTPUTS their SYNC pins synchronizes their operation. This is normally done after each AD7192 has performed its own calibration or The AD7192 has four general-purpose digital outputs, P0, P1, has calibration coefficients loaded into its calibration registers. P2, and P3. These are enabled using the GP32EN and GP10EN The conversions from the AD7192s are then synchronized. bits in the GPOCON register. The pins can be pulled high or low using the P0DAT to P3DAT bits in the GPOCON register; The part is taken out of reset on the master clock falling edge that is, the value at the pin is determined by the setting of the following the SYNC low to high transition. Therefore, when P0DAT to P3DAT bits. The logic levels for these pins are multiple devices are being synchronized, the SYNC pin should determined by AV rather than by DV . When the GPOCON DD DD be taken high on the master clock rising edge to ensure that all register is read, Bit P0DAT to Bit P3DAT reflect the actual value devices begin sampling on the master clock falling edge. If the at the pins. This is useful for short-circuit detection. SYNC pin is not taken high in sufficient time, it is possible to These pins can be used to drive external circuitry, for example, have a difference of one master clock cycle between the devices; an external multiplexer. If an external multiplexer is used to that is, the instant at which conversions are available differs increase the channel count, the multiplexer logic pins can be from part to part by a maximum of one master clock cycle. controlled via the AD7192 general-purpose output pins. The The SYNC pin can also be used as a start conversion command. general-purpose output pins can be used to select the active In this mode, the rising edge of SYNC starts conversion, and the multiplexer pin. Because the operation of the multiplexer is falling edge of RDY indicates when the conversion is complete. independent of the AD7192, the AD7192 modulator and filter The settling time of the filter has to be allowed for each data should be reset using the SYNC pin or by a write to the mode or register update. For example, if the ADC is configured to use configuration register each time that the multiplexer channel is the sinc4 filter, zero latency is disabled, and chop is disabled, the changed. settling time equals 4/f where f is the output data rate ADC ADC when continuously converting on a single channel. Rev. A | Page 34 of 40

AD7192 ENABLE PARITY With chop disabled, both an internal zero-scale calibration and a system zero-scale calibration require a time equal to the The AD7192 also has a parity check function on chip that settling time, t (4/f for the sinc4 filter and 3/f for the detects 1-bit errors in the serial communications between the SETTLE ADC ADC sinc3 filter). ADC and the microprocessor. When the ENPAR bit in the mode register is set to 1, parity is enabled. The contents of the With chop enabled, an internal zero-scale calibration is not status register must be transmitted along with each 24-bit con- needed because the ADC itself minimizes the offset continuously. version when the parity function is enabled. To append the However, if an internal zero-scale calibration is performed, the contents of the status register to each conversion read, the settling time, tSETTLE (2/fADC), is required to perform the DAT_STA bit in the mode register should be set to 1. For each calibration. Similarly, a system zero-scale calibration requires a conversion read, the parity bit in the status register is pro- time of tSETTLE to complete. grammed so that the overall number of 1s transmitted in the To perform an internal full-scale calibration, a full-scale input 24-bit data-word is even. Therefore, for example, if the 24-bit voltage is automatically connected to the selected analog input conversion contains eleven 1s (binary format), the parity bit is for this calibration. For a gain of 1, the time required for an set to 1 so that the total number of 1s in the serial transmission internal full-scale calibration is equal to t . For higher gains, SETTLE is even. If the microprocessor receives an odd number of 1s, it the internal full-scale calibration requires a time of 2 × t . SETTLE knows that the data received has been corrupted. A full-scale calibration is recommended each time the gain of a The parity function detects only 1-bit errors. For example, two channel is changed to minimize the full-scale error. bits of corrupt data can result in the microprocessor receiving an A system full-scale calibration requires a time of t . With SETTLE even number of 1s. Therefore, an error condition is not detected. chop disabled, the zero-scale calibration (internal or system CALIBRATION zero-scale) should be performed before the system full-scale calibration is initiated. The AD7192 provides four calibration modes that can be pro- grammed via the mode bits in the mode register. These modes An internal zero-scale calibration, system zero-scale calibration, are internal zero-scale calibration, internal full-scale calibration, and system full-scale calibration can be performed at any system zero-scale calibration, and system full-scale calibration. output data rate. An internal full-scale calibration can be A calibration can be performed at any time by setting the MD2 performed at any output data rate for which the filter word, to MD0 bits in the mode register appropriately. A calibration FS[9:0], is divisible by 16, FS[9:0] being the decimal equivalent should be performed when the gain is changed. After each of the 10-bit word written to Bit FS9 to Bit FS0 in the mode conversion, the ADC conversion result is scaled using the ADC register. Therefore, internal full-scale calibrations can be calibration registers before being written to the data register. performed at output data rates such as 10 Hz or 50 Hz when The offset calibration coefficient is subtracted from the result chop is disabled. Using these lower output data rates results in prior to multiplication by the full-scale coefficient. better calibration accuracy. To start a calibration, write the relevant value to the MD2 to The offset error is, typically, 150 μV/gain. If the gain is changed, MD0 bits. The DOUT/RDY pin and the RDY bit in the status it is advisable to perform a calibration. A zero-scale calibration register go high when the calibration is initiated. When the (an internal zero-scale calibration or a system zero-scale calibration is complete, the contents of the corresponding calibration) reduces the offset error to the order of the noise. calibration registers are updated, the RDY bit in the status The gain error of the AD7192 is factory calibrated at a gain of 1 register is reset, the DOUT/RDY pin returns low (if CS is low), with a 5 V power supply at ambient temperature. Following this and the AD7192 reverts to idle mode. calibration, the gain error is 0.001%, typically, at 5 V. Table 23 shows the typical uncalibrated gain error for the different gain During an internal zero-scale or full-scale calibration, the settings. respective zero input and full-scale input are automatically connected internally to the ADC input pins. A system Table 23. Typical Precalibration Gain Error vs. Gain calibration, however, expects the system zero-scale and system Gain Precalibration Gain Error (%) full-scale voltages to be applied to the ADC pins before 8 −0.11 initiating the calibration mode. In this way, errors external to 16 −0.20 the ADC are removed. 32 −0.23 From an operational point of view, treat a calibration like 64 −0.29 another ADC conversion. A zero-scale calibration, if required, 128 −0.39 must always be performed before a full-scale calibration. Set the An internal full-scale calibration reduces the gain error to system software to monitor the RDY bit in the status register or 0.001%, typically, when the gain is equal to 1. For higher gains, the DOUT/RDY pin to determine the end of calibration via a the gain error post internal full-scale calibration is 0.003%, polling sequence or an interrupt-driven routine. typically when AV is equal to 5 V. When AV is less than DD DD Rev. A | Page 35 of 40

AD7192 4.75 V, the gain error post internal full-scale calibration is etch technique is generally best for ground planes because it 0.005%, typically. gives the best shielding. When AV is less than 4.75 V, the CLK_DIV bit must be set Although the AD7192 has separate pins for analog and digital DD when performing internal full-scale calibrations. The accuracy ground, the AGND and DGND pins are tied together internally of the internal full-scale calibration is further increased if chop via the substrate. Therefore, the user must not tie these two is enabled and a low output data rate is used while performing pins to separate ground planes unless the ground planes are the calibration. connected together near the AD7192. A system full-scale calibration reduces the gain error to the In systems in which the AGND and DGND are connected order of the noise irrespective of the analog power supply somewhere else in the system (that is, the power supply of the voltage. system), they should not be connected again at the AD7192 because a ground loop results. In these situations, it is The AD7192 gives the user access to the on-chip calibration recommended that the ground pins of the AD7192 be tied to registers, allowing the microprocessor to read the calibration the AGND plane. coefficients of the device and also to write its own calibration coefficients from prestored values in the EEPROM. A read of In any layout, the user must keep in mind the flow of currents the registers can be performed at any time. However, the ADC in the system, ensuring that the paths for all currents are as close as must be placed in power-down or idle mode when writing to possible to the paths the currents took to reach their destinations. the registers. The values in the calibration registers are 24 bits Avoid forcing digital currents to flow through the AGND. wide. The span and offset of the part can also be manipulated Avoid running digital lines under the device, because this using the registers. couples noise onto the die, and allow the analog ground plane GROUNDING AND LAYOUT to run under the AD7192 to prevent noise coupling. The power supply lines to the AD7192 must use as wide a trace as possible Because the analog inputs and reference inputs are differential, to provide low impedance paths and reduce the effects of most of the voltages in the analog modulator are common- glitches on the power supply line. Shield fast switching signals mode voltages. The high common-mode rejection of the part like clocks with digital ground to prevent radiating noise to removes common-mode noise on these inputs. The analog and other sections of the board, and never run clock signals near the digital supplies to the AD7192 are independent and separately analog inputs. Avoid crossover of digital and analog signals. pinned out to minimize coupling between the analog and Run traces on opposite sides of the board at right angles to each digital sections of the device. The digital filter provides other. This reduces the effects of feedthrough through the rejection of broadband noise on the power supplies, except at board. A microstrip technique is by far the best but is not integer multiples of the modulator sampling frequency. always possible with a double-sided board. In this technique, Connect an R-C filter to each analog input pin to provide the component side of the board is dedicated to ground planes, rejection at the modulator sampling frequency. A 100 Ω whereas signals are placed on the solder side. resistor in series with each analog input, a 0.1 μF capacitor Good decoupling is important when using high resolution between the analog input pins, and a 0.01 μF capacitor from ADCs. Decouple all analog supplies with 10 μF tantalum each analog input to AGND are advised. capacitors in parallel with 0.1 μF capacitors to AGND. To The digital filter also removes noise from the analog and achieve the best results from these decoupling components, reference inputs provided that these noise sources do not place them as close as possible to the device, ideally right up saturate the analog modulator. As a result, the AD7192 is against the device. Decouple all logic chips with 0.1 μF ceramic more immune to noise interference than a conventional high capacitors to DGND. In systems in which a common supply resolution converter. However, because the resolution of the voltage is used to drive both the AVDD and DVDD of the AD7192 is so high and the noise levels from the converter so AD7192, it is recommended that the system AV supply be DD low, care must be taken with regard to grounding and layout. used. For this supply, place the recommended analog supply The printed circuit board (PCB) that houses the ADC must be decoupling capacitors between the AVDD pin of the AD7192 designed so that the analog and digital sections are separated and AGND and the recommended digital supply decoupling and confined to certain areas of the board. This facilitates the capacitor between the DVDD pin of the AD7192 and DGND. use of ground planes that can be easily separated. A minimum Rev. A | Page 36 of 40

AD7192 APPLICATIONS INFORMATION The AD7192 provides a low-cost, high resolution analog-to- measurements can be taken. In applications in which current digital function. Because the analog-to-digital function is consumption is being minimized, the AD7192 can be placed in provided by a Σ-Δ architecture, the part is more immune to standby mode, thus significantly reducing the power consumed noisy environments, making it ideal for use in sensor in the application. In addition, the bridge power-down switch measurement and industrial and process control applications. can be opened while in standby mode, thus avoiding unnecessary power consumption by the front-end transducer. When the part WEIGH SCALES is taken out of standby mode and the bridge power-down switch Figure 32 shows the AD7192 being used in a weigh scale is closed, the user should ensure that the front end circuitry is application. The load cell is arranged in a bridge network and fully settled before attempting a read from the AD7192. gives a differential output voltage between its OUT+ and OUT– For simplicity, external filters are not included in Figure 32. terminals. Assuming a 5 V excitation voltage, the full-scale However, an R-C antialias filter must be included on each output range from the transducer is 10 mV when the sensitivity analog input. This is required because the on-chip digital filter is 2 mV/V. The excitation voltage for the bridge can be used to does not provide any rejection around the modulator sampling directly provide the reference for the ADC because the reference frequency or multiples of this frequency. Suitable values are a input range includes the supply voltage. 100 Ω resistor in series with each analog input, a 0.1 μF A second advantage of using the AD7192 in transducer-based capacitor between the analog input pins, and a 0.01 μF applications is that the bridge power-down switch can be fully capacitor from each analog input pin to AGND. utilized to minimize the power consumption of the system. The bridge power-down switch is connected in series with the cold side of the bridge. In normal operation, the switch is closed and 5V REFIN1(+)AGND AVDD DVDD DGND REFERENCE DETECT IN+ AIN1 AVDD AIN2 OUT– OUT+ AIN3 AIN4 SERIAL DOUT/RDY IN– AINCOM MUX PGA AΣD-ΔC INCTOEANRNTFDRAOCLE DSCINLK LOGIC CS SYNC AGND TEMP P3 REFIN1(–) SENSOR P2 BPDSW CLOCK AD7192 CIRCUITRY AGND MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+) 07822-024 Figure 32. Typical Application (Weigh Scale) Rev. A | Page 37 of 40

AD7192 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8° 0.75 0.30 SEATING 0.20 0° 0.60 0.19 PLANE 0.09 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 33. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD7192BRUZ1 –40°C to +105°C 24-Lead TSSOP RU-24 AD7192BRUZ-REEL1 –40°C to +105°C 24-Lead TSSOP RU-24 1 Z = RoHS Compliant Part. Rev. A | Page 38 of 40

AD7192 NOTES Rev. A | Page 39 of 40

AD7192 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07822-0-5/09(A) Rev. A | Page 40 of 40

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