Programmable Controller for Capacitance Touch Sensors Data Sheet AD7142 FEATURES FUNCTIONAL BLOCK DIAGRAM Programmable capacitance-to-digital converter VREF–VREF+ TEST 29 28 27 36 ms update rate (at maximum sequence length) Better than 1 fF resolution CCIINN01 3301 PORLWEOESGREIC-TON 14 capacitance sensor input channels CIN2 32 No external RC tuning components required CIN3 1 13 AVCC CIN4 2 Automatic conversion sequencer CIN5 3 14 AGND OnA-cuhtoipm aauttico mcoamtipc ecnasliabtriaotnio fonr l oegnivci ronmental changes CCCIIINNN678 456 SWITCHMATRIX 1C6Σ-D-BΔCIT CALEINBGRIANTEION CIN9 7 17 DVCC Automatic adaptive threshold and sensitivity levels CIN10 8 On-chip RAM to store calibration data CIN11 9 CALIRBARMATION 18 DGND1 CIN12 10 SPI-compatible serial interface (AD7142) CIN13 11 CONTROL 19 DGND2 AND I2C-compatible serial interface (AD7142-1) DATA REGISTERS Separate V level for serial interface DRIVE Interrupt output and GPIO CSHIELD 12 32-lead, 5 mm x 5 mm LFCSP SRC 15 EX2C5I0TkAHTzION SOURCE 2.6 V to 3.6 V supply voltage SRC 16 Low operating current INTERRUPT Full power mode: less than 1 mA VDRIVE 20 ASNEDR CIAOLN ITNRTOELR FLAOCGEIC ANLDO GGIPCIO 26 GPIO Low power mode: 50 µA APPLICATIONS SD21O/ S2D2I/ SC2L3K C24S/ IN25T 05702-001 SDA ADD0 ADD1 Personal music and multimedia players Figure 1. Cell phones Digital still cameras Smart hand-held devices Television, A/V, and remote controls Gaming consoles GENERAL DESCRIPTION The AD7142 and AD7142-1 are integrated capacitance-to- The AD7142 and AD7142-1 have on-chip calibration logic to digital converters (CDCs) with on-chip environmental account for changes in the ambient environment. The calibration for use in systems requiring a novel user input calibration sequence is performed automatically and at method. The AD7142 and AD7142-1 can interface to external continuous intervals, when the sensors are not touched. This capacitance sensors implementing functions such as capacitive ensures that there are no false or nonregistering touches on the buttons, scroll bars, or wheels. external sensors due to a changing environment. The CDC has 14 inputs channeled through a switch matrix to a The AD7142 has an SPI-compatible serial interface, and the 16-bit, 250 kHz sigma-delta (∑-∆) capacitance-to-digital AD7142-1 has an I2C-compatible serial interface. Both parts converter. The CDC is capable of sensing changes in the have an interrupt output, as well as a general-purpose input/ capacitance of the external sensors and uses this information to output (GPIO). register a sensor activation. The external sensors can be The AD7142 and AD7142-1 are available in a 32-lead, 5 mm × arranged as a series of buttons, as a scroll bar or wheel, or as a 5 mm LFCSP and operate from a 2.6 V to 3.6 V supply. The combination of sensor types. By programming the registers, the operating current consumption is less than 1 mA, falling to user has full control over the CDC setup. High resolution 50 µA in low power mode (conversion interval of 400 ms). sensors require minor software to run on the host processor. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD7142 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Capacitance Sensor Behavior with Calibration ...................... 23 Applications ....................................................................................... 1 Slow FIFO .................................................................................... 24 Functional Block Diagram .............................................................. 1 SLOW_FILTER_UPDATE_LVL .............................................. 24 General Description ......................................................................... 1 Adaptive Threshold and Sensitivity ............................................. 25 Revision History ............................................................................... 3 Interrupt Output ............................................................................. 27 Specifications ..................................................................................... 4 CDC Conversion Complete Interrupt ..................................... 27 SPI Timing Specifications (AD7142) ......................................... 6 Sensor Touch Interrupt.............................................................. 27 I2C Timing Specifications (AD7142-1) ..................................... 7 GPIO INT Output Control ....................................................... 29 Absolute Maximum Ratings ............................................................ 8 Outputs ............................................................................................ 31 ESD Caution .................................................................................. 8 Excitation Source ........................................................................ 31 Pin Configurations and Function Descriptions ........................... 9 C Output ............................................................................. 31 SHIELD Typical Performance Characteristics ........................................... 10 GPIO ............................................................................................ 31 Theory of Operation ...................................................................... 12 Using the GPIO to Turn On/Off an LED ................................ 31 Capacitance Sensing Theory ..................................................... 12 Serial Interface ................................................................................ 32 Operating Modes ........................................................................ 13 SPI Interface ................................................................................ 32 Capacitance Sensor Input Configuration .................................... 14 I2C Compatible Interface ........................................................... 34 CIN Input Multiplexer Setup .................................................... 14 V Input ................................................................................. 36 DRIVE Capacitance-to-Digital Converter ................................................ 15 PCB Design Guidelines ................................................................. 37 Oversampling the CDC Output ............................................... 15 Capacitive Sensor Board Mechanical Specifications ............. 37 Capacitance Sensor Offset Control .......................................... 15 Chip Scale Packages ................................................................... 37 Conversion Sequencer ............................................................... 15 Power-Up Sequence ....................................................................... 38 CDC Conversion Sequence Time ............................................ 16 Typical Application Circuits ......................................................... 39 CDC Conversion Results ........................................................... 17 Register Map ................................................................................... 40 Noncontact Proximity Detection ................................................. 18 Detailed Register Descriptions ..................................................... 41 Recalibration ............................................................................... 18 Bank 1 Registers ......................................................................... 41 Proximity Sensitivity .................................................................. 18 Bank 2 Registers ......................................................................... 51 FF_SKIP_CNT ............................................................................ 21 Bank 3 Registers ......................................................................... 58 Environmental Calibration ........................................................... 23 Outline Dimensions ....................................................................... 70 Capacitance Sensor Behavior Without Calibration ............... 23 Ordering Guide .......................................................................... 70 Rev. B | Page 2 of 70

Data Sheet AD7142 REVISION HISTORY 9/2017—Rev. A to Rev. B Changes to Capacitance Sensor Behavior with Calibration Changes to Figure 6, Figure 7, and Table 7 .................................... 9 Section .............................................................................................. 22 Changes to Figure 59 ...................................................................... 40 Added Slow FIFO and SLOW_FILTER_UPDATE_LVL Updated Outline Dimensions ........................................................ 70 Section .............................................................................................. 23 Changes to Ordering Guide ........................................................... 70 Changes to Adaptive Threshold and Sensitivity Section ........... 24 Inserted Figure 37 and Table 13 .................................................... 25 1/2007—Rev. 0 to Rev. A Deleted Figure 42 ............................................................................ 29 Updated Format .................................................................. Universal Changes to C Output Section ............................................... 30 SHIELD Changes to Data Sheet Title ............................................................. 1 Changes to Figure 55 ...................................................................... 36 Inserted Figure 5 ................................................................................ 8 Changes to Power-up Sequence Section ...................................... 37 Changes to Figure 18 ...................................................................... 12 Changes to Figure 58 ...................................................................... 38 Changes to Operating Modes Section .......................................... 13 Changes to Table 21 ........................................................................ 42 Changes to CIN Input Multiplexer Setup Section ...................... 14 Changes to Table 24 ........................................................................ 43 Changes to Table 9 and Conversion Sequencer Section ............ 15 Changes to Table 25 ........................................................................ 44 Changes to Noncontact Proximity Detection Section ............... 18 Changes to Table 29 ........................................................................ 48 Changes to Recalibration Section and Table 12 .......................... 18 Changes to Table 31 ........................................................................ 49 Deleted FIFO Control Section ....................................................... 19 Changes to Figure 31 and Table 13 ............................................... 20 6/2006—Revision 0: Initial Version Changes to Figure 32 ...................................................................... 21 Rev. B | Page 3 of 70

AD7142 Data Sheet SPECIFICATIONS AV , DV = 2.6 V to 3.6 V, T = −40oC to +85°C, unless otherwise noted. CC CC A Table 1. Parameter Min Typ Max Unit Test Conditions/Comments CAPACITANCE-TO-DIGITAL CONVERTER Update Rate 35.45 36.86 38.4 ms 12 conversion stages in sequencer, decimation rate = 256 Resolution 16 Bit CIN Input Range1 ±2 pF No Missing Codes 16 Bit Guaranteed by design, but not production tested CIN Input Leakage 25 nA Total Unadjusted Error ±20 % Output Noise (Peak-to-Peak) 7 Codes Decimation rate = 128 3 Codes Decimation rate = 256 Output Noise (RMS) 0.8 Codes Decimation rate = 128 0.5 Codes Decimation rate = 256 Parasitic Capacitance 40 pF Parasitic capacitance to ground, per CIN input guaranteed by characterization C Offset Range1 ±20 pF BULK C Offset Resolution 156.25 fF BULK Low Power Mode Delay Accuracy 4 % % of 200 ms, 400 ms, 600 ms, or 800 ms EXCITATION SOURCE Frequency 240 250 260 kHz Output Voltage AV V CC Short-Circuit Source Current 20 mA Short-Circuit Sink Current 50 mA Maximum Output Load 250 pF Capacitance load on source to ground C Output Drive 10 µA SHIELD C Bias Level AV /2 V SHIELD CC LOGIC INPUTS (SDI, SCLK, CS, SDA, GPI TEST) V Input High Voltage 0.7 × V V IH DRIVE V Input Low Voltage 0.4 V IL I Input High Voltage −1 µA V = V IH IN DRIVE I Input Low Voltage 1 µA V = DGND IL IN Hysteresis 150 mV OPEN-DRAIN OUTPUTS (SCLK, SDA, INT) V Output Low Voltage 0.4 V I = −1 mA OL SINK I Output High Leakage Current 0.1 ±1 µA V = V OH OUT DRIVE LOGIC OUTPUTS (SDO, GPO) V Output Low Voltage 0.4 V I = 1 mA, V = 1.65 V to 3.6 V OL SINK DRIVE V Output High Voltage V − 0.6 V I = 1 mA, V = 1.65 V to 3.6 V OH DRIVE SOURCE DRIVE SDO Floating State Leakage Current ±1 µA Pin three-state, leakage measured to GND and DV CC GPO Floating State Leakage Current −5 2 µA Pin three-state, leakage measured to GND and DV CC POWER AV , DV 2.6 3.3 3.6 V CC CC V 1.65 3.6 V Serial interface operating voltage DRIVE I 0.9 1 mA In full power mode CC 20 µA Low power mode, converter idle, T = 25°C A 16 33 µA Low power mode, converter idle 4.5 µA Full shutdown, T = 25°C A 2.25 18 µA Full shutdown 1 CIN and CBULK are defined in Figure 2. Rev. B | Page 4 of 70

Data Sheet AD7142 CIN PLASTIC OVERLAY SENSOR BOARD CBULK CAPACITIVE SENSOR 05702-054 Figure 2. Table 2. Typical Average Current in Low Power Mode, AV , DV = 3.6 V, T= 25°C, Load of 50 pF on SRC Pin, No Load on SRC CC CC Number of Conversion Stages (Current Values Expressed in μA) Low Power Mode Decimation Delay Rate 1 2 3 4 5 6 7 8 9 10 11 12 200 ms 128 26.4 33.3 40.1 46.9 53.5 60 66.5 72.8 79.1 85.2 91.3 97.3 256 35.6 49.1 62.2 74.9 87.3 99.3 111 122.3 133.4 144.2 154.7 164.9 400 ms 128 21.3 24.8 28.3 31.7 35.2 38.6 42 45.4 48.7 52 55.3 58.6 256 26 32.9 39.7 46.5 53.1 59.6 66.1 72.4 78.7 84.9 91 97 600 ms 128 19.6 21.9 24.3 26.6 28.9 31.2 33.5 35.8 38.1 40.4 42.6 44.8 256 22.7 27.4 32 36.6 41.1 45.6 50 54.4 58.8 63.1 67.4 71.6 800 ms 128 18.7 20.5 22.2 24 25.7 27.5 29.2 31 32.7 34.4 36.1 37.8 256 21.1 24.6 28.1 31.5 35 38.4 41.8 45.2 48.5 51.8 55.1 58.4 Table 3. Maximum Average Current in Low Power Mode, AV , DV = 3.6 V, Load of 50 pF on SRC Pin, No Load on SRC CC CC Number of Conversion Stages (Current Values Expressed in μA) Low Power Mode Decimation Delay Rate 1 2 3 4 5 6 7 8 9 10 11 12 200 ms 128 45.4 53.6 61.5 69.4 77.1 84.7 92.2 99.6 106.8 113.9 121 127.9 256 56.2 72 87.2 102 116.3 130.2 143.7 156.8 169.5 181.8 193.8 205.5 400 ms 128 39.5 43.6 47.7 51.8 55.8 59.8 63.7 67.6 71.5 75.4 79.2 83 256 45 53.1 61.1 68.9 76.7 84.3 91.8 99.1 106.4 113.6 120.6 127.5 600 ms 128 37.5 40.3 43 45.8 48.5 51.2 53.9 56.5 59.2 61.8 64.5 67.1 256 41.2 46.7 52.1 57.4 62.7 67.9 73.1 78.2 83.3 88.3 93.3 98.2 800 ms 128 36.5 38.6 40.7 42.7 44.8 46.8 48.8 50.9 52.9 54.9 56.9 58.9 256 39.3 43.4 47.5 51.5 55.6 59.5 63.5 67.4 71.3 75.2 79 82.8 Rev. B | Page 5 of 70

AD7142 Data Sheet SPI TIMING SPECIFICATIONS (AD7142) T = −40°C to +85°C; V = 1.65 V to 3.6 V; AV , DV = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure A DRIVE CC CC compliance. All input signals are specified with t = t = 5 ns (10% to 90% of V ) and timed from a voltage level of 1.6 V. R F CC Table 4. SPI Timing Specifications Parameter Limit at T , T Unit Description MIN MAX fSCLK 5 MHz max t1 5 ns min CS falling edge to first SCLK falling edge t 20 ns min SCLK high pulse width 2 t 20 ns min SCLK low pulse width 3 t 15 ns min SDI setup time 4 t 15 ns min SDI hold time 5 t 20 ns max SDO access time after SCLK falling edge 6 t7 16 ns max CS rising edge to SDO high impedance t8 15 ns min SCLK rising edge to CS high CS t1 t2 t3 t8 1 2 3 15 16 1 2 15 16 SCLK t4 t5 SDI MSB LSB t6 t7 SDO MSB LSB 05702-002 Figure 3. SPI Detailed Timing Diagram Rev. B | Page 6 of 70

Data Sheet AD7142 I2C TIMING SPECIFICATIONS (AD7142-1) T = −40°C to +85°C; V = 1.65 V to 3.6 V; AV , DV = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure A DRIVE CC CC compliance. All input signals timed from a voltage level of 1.6 V. Table 5. I2C Timing Specifications1 Parameter Limit Unit Description f 400 kHz max SCLK t 0.6 μs min Start condition hold time, t 1 HD; STA t 1.3 μs min Clock low period, t 2 LOW t 0.6 μs min Clock high period, t 3 HIGH t 100 ns min Data setup time, t 4 SU; DAT t 300 ns min Data hold time, t 5 HD; DAT t 0.6 μs min Stop condition setup time, t 6 SU; STO t 0.6 μs min Start condition setup time, t 7 SU; STA t 1.3 μs min Bus free time between stop and start conditions, t 8 BUF t 300 ns max Clock/data rise time R t 300 ns max Clock/data fall time F 1 Guaranteed by design, not production tested. t2 tR tF t1 SCLK t1 t3 t7 t6 t5 t4 SDATA t 8 STOP START START STOP 05702-003 Figure 4. I2C Detailed Timing Diagram Rev. B | Page 7 of 70

AD7142 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Table 6. Ratings may cause permanent damage to the product. This is a Parameter Rating stress rating only; functional operation of the product at these AV to AGND, DV to DGND −0.3 V to +3.6 V CC CC or any other conditions above those indicated in the operational Analog Input Voltage to AGND −0.3 V to AV + 0.3 V CC section of this specification is not implied. Operation beyond Digital Input Voltage to DGND −0.3 V to V + 0.3 V DRIVE the maximum operating conditions for extended periods may Digital Output Voltage to DGND −0.3 V to V + 0.3 V DRIVE affect product reliability. Input Current to Any Pin Except 10 mA Supplies1 ESD Rating (Human Body Model) 2.5 kV Operating Temperature Range −40°C to +150°C 200µA IOL Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TO OUTPUT 1.6V LFCSP PIN CL 50pF Power Dissipation 450 mW IR RθeJAf Tlohwe rPmeaalk I Tmepmepdearnacteu re 123650.°7C° C(±/W0.5 °C) 200µA IOH 05702-004 Figure 5. Load Circuit for Digital Output Timing Specifications Lead Temperature (Soldering 10 sec) 300°C ESD CAUTION 1Transient currents of up to 100 mA do not cause SCR latch-up. Rev. B | Page 8 of 70

Data Sheet AD7142 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 2NIC1NIC0NICV–FERV+FERTSETOIPGTNI 2NIC1NIC0NICV–FERV+FERTSETOPIGTNI 3231302928272625 3231302928272625 CIN31 24CS CIN31 24ADD1 CIN42 23SCLK CIN42 23SCLK CCIINN5634 AD7142 2221SSDDIO CCIINN5634 AD7142-1 2221ASDDAD0 CCIINN7856 (NToOt Pto V SIEcaWle) 2109VDDGRNIVDE2 CCIINN7856 (NToOt Pto V SIEcaWle) 2109VDDGRNIVDE2 CIN97 18DGND1 CIN97 18DGND1 CIN108 17DVCC CIN108 17DVCC 910111213141516 910111213141516 123DCDCC 11NCI21NIC31NCIDLEHISVACCDNGACRSCRS 1NCI1NCI1NCICLEHISVACNGARSRS C NOTES NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER FJRTOOHEEICRN O GTINMSRC MOAREUNENNDADD SME EPADDLX TAIRMHNEAUELT.MIA TTBHHILEEI TRPYAM DAO LFB ECT AHSPEOA LSBDOIELLRIDTEEYDR I TT OIS 05702-005 JRTOHEEICN OGTMSRF MOAigEUNuNNDrDD eME PA7DL.X TAAIMHNDAUE7T.M1 T4TH2HE-E1 RP PAMiDAn L BC ECo AnSPOfiAgLBuDIErLaRITtEiYoD In TT OIS 05702-044 Figure 6. AD7142 Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1 CIN3 Capacitance Sensor Input. 2 CIN4 Capacitance Sensor Input. 3 CIN5 Capacitance Sensor Input. 4 CIN6 Capacitance Sensor Input. 5 CIN7 Capacitance Sensor Input. 6 CIN8 Capacitance Sensor Input. 7 CIN9 Capacitance Sensor Input. 8 CIN10 Capacitance Sensor Input. 9 CIN11 Capacitance Sensor Input. 10 CIN12 Capacitance Sensor Input. 11 CIN13 Capacitance Sensor Input. 12 CSHIELD CDC Shield Potential Output. Requires 10 nF capacitor to ground. Connect to external shield. 13 AVCC CDC Supply Voltage. 14 AGND Analog Ground Reference Point for All CDC Circuitry. Tie to analog ground plane. 15 SRC CDC Excitation Source Output. 16 SRC Inverted Excitation Source Output. 17 DVCC Digital Core Supply Voltage. 18 DGND1 Digital Ground. 19 DGND2 Digital Ground. 20 VDRIVE Serial Interface Operating Voltage Supply. 21 SDO (AD7142) SPI Serial Data Output. SDA (AD7142-1) I2C Serial Data Input/Output. SDA requires pull-up resistor. 22 SDI (AD7142) SPI Serial Data Input. ADD0 (AD7142-1) I2C Address Bit 0. 23 SCLK Clock Input for Serial Interface. 24 CS (AD7142) SPI Chip Select Signal. ADD1 (AD7142-1) I2C Address Bit 1. 25 INT General-Purpose Open-Drain Interrupt Output. Programmable polarity; requires pull-up resistor. 26 GPIO Programmable GPIO. 27 TEST Factory Test Pin. Tie to ground. 28 VREF+ CDC Positive Reference Input. Normally tied to analog power. 29 VREF− CDC Negative Reference Input. Tie to analog ground. 30 CIN0 Capacitance Sensor Input. 31 CIN1 Capacitance Sensor Input. 32 CIN2 Capacitance Sensor Input. EPAD Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the ground plane. Rev. B | Page 9 of 70

AD7142 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1000 2.45 980 DEVICE 1 2.30 DEVICE 2 960 940 DEVICE 3 µA) 2.15 (C µA) 920 DEVICE 2 N IC 2.00 I (CC 900 TDOW 1.85 DEVICE 1 DEVICE 3 U 880 SH 1.70 860 882400 05702-053 11..4505 05702-052 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC(V) VCC (V) Figure 8. Supply Current vs. Supply Voltage Figure 11. Shutdown Supply Current vs. Supply Voltage (VCC = AVCC + DVCC, ICC = AICC + DICC) (VCC = AVCC + DVCC, ICC = AICC + DICC) 180 1.10 LP_CONV_DELAY = 200ms DEVICE 1 160 1.05 140 1.00 A) 120 A) µ m I (CC 100 LP_CONV_DELAY = 400ms I(CC 0.95 DEVICE 3 DEVICE 2 0.90 80 LP_CONV_DELAY = 600ms 4600 LP_CONV_DELAY = 800ms 05702-051 00..8850 05702-049 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 0 50 100 150 200 250 300 350 400 450 500 VCC(V) CAPACITANCE LOAD ON SOURCE (pF) Figure 9. Low Power Supply Current vs. Supply Voltage, Figure 12. Supply Current vs. Capacitive Load on SRC (ICC = AICC + DICC) Decimation Rate = 256 (VCC = AVCC + DVCC, ICC = AICC + DICC) 120 16015 16010 DEVICE 1 100 LP_CONV_DELAY = 200ms E16005 D I (µA)CC 6800 LP_CONV_DELAY = 400ms OUTPUT CO1165090950 DEVICE 2 C D DEVICE 3 C LP_CONV_DELAY = 600ms 15990 40 20 LP_CONV_DELAY = 800ms 05702-050 1155998850 05702-048 2.7 2.8 2.9 3.0 3.10 3.2 3.3 3.4 3.5 3.6 0 50 100 150 200 250 300 350 400 450 500 VCC(V) CAPACITANCE LOAD ON SOURCE (pF) Figure 10. Low Power Supply Current vs. Supply Voltage Figure 13. Output Code vs. Capacitive Load on SRC Decimation Rate = 128 (VCC = AVCC + DVCC, ICC = AICC + DICC) Rev. B | Page 10 of 70

Data Sheet AD7142 960 2.5 100mV 300mV 200mV 400mV 940 500mV 3.6V s) 920 ode 2.0 NT (µA) 900 3.3V OISE (C 1.5 RE 880 K N R A U E C 860 P PPLY 840 K-TO- 1.0 U A S E P 820 C 0.5 D 2.7V C 788000 05702-056 0 05702-059 –40 –20 0 20 40 60 80 100 120 10 1k 100k 10M TEMPERATURE (°C) FREQUENCY (Hz) Figure 14. Supply Current vs. Temperature (Supply Current = AICC + DICC) Figure 16. Power Supply Sine Wave Rejection 12 180 160 10 s) e od 140 NT (µA) 8 OISE (C 120 RE K N 100 UR 6 EA 300mV Y C 3.6V O-P 80 PPL 4 3.3V K-T 60 U A 200mV S E P 20 2.7V 05702-057 CDC 42000 1250500mmmVVV 05702-060 –40 –20 0 20 40 60 80 100 120 100 1k 10k 100k 1M 10M TEMPERATURE (°C) SQUARE WAVE FREQUENCY (Hz) Figure 15. Shutdown Supply Current vs. Temperature Figure 17. Power Supply Square Wave Rejection (Supply Current = AICC + DICC) Rev. B | Page 11 of 70

AD7142 Data Sheet THEORY OF OPERATION The AD7142 and AD7142-1 are capacitance-to-digital CAPACITANCE SENSING THEORY converters (CDCs) with on-chip environmental compensation, The AD7142 uses a method of sensing capacitance known as intended for use in portable systems requiring high resolution the shunt method. Using this method, an excitation source is user input. The internal circuitry consists of a 16-bit, ∑-∆ con- connected to a transmitter generating an electric field to a verter that converts a capacitive input signal into a digital value. receiver. The field lines measured at the receiver are translated There are 14 input pins on the AD7142 and AD7142-1, CIN0 to into the digital domain by a ∑-∆ converter. When a finger, or CIN13. A switch matrix routes the input signals to the CDC. other grounded object, interferes with the electric field, some of The result of each capacitance-to-digital conversion is stored in the field lines are shunted to ground and do not reach the on-chip registers. The host subsequently reads the results over receiver (see Figure 18). Therefore, the total capacitance the serial interface. The AD7142 contains an SPI interface and measured at the receiver decreases when an object comes close the AD7142-1 has an I2C interface ensuring that the parts are to the induced field. compatible with a wide range of host processors. Because the AD7142 and AD7142-1 are identical parts, with the exception of the serial interface, AD7142 refers to both the AD7142 and AD7142-1 throughout this data sheet. The AD7142 interfaces with up to 14 external capacitance sensors. These sensors can be arranged as buttons, scroll bars, PLASTIC COVER wheels, or as a combination of sensor types. The external sensors consist of electrodes on a single or multiple layer PCB that interfaces directly to the AD7142. Rx PCB LAYER 1 Tx The AD7142 can be set up to implement any set of input sensors by programming the on-chip registers. The registers can 16-BIT also be programmed to control features such as averaging, Σ-Δ DATA ESIXGCNITAALTION ADC 250kHz offsets, and gains for each of the external sensors. There is a sequencer on-chip to control how each of the capacitance AD7142 05702-007 inputs is polled. Figure 18. Sensing Capacitance Method The AD7142 has on-chip digital logic and 528 words of RAM In practice, the excitation source and ∑-∆ ADC are implemented that are used for environmental compensation. The effects of on the AD7142, and the transmitter and receiver are constructed humidity, temperature, and other environmental factors can on a PCB that makes up the external sensor. effect the operation of capacitance sensors. Transparent to the Registering a Sensor Activation user, the AD7142 performs continuous calibration to compen- sate for these effects, allowing the AD7142 to give error-free When a sensor is approached, the total capacitance associated results at all times. with that sensor, measured by the AD7142, changes. When the capacitance changes to such an extent that a set threshold is The AD7142 requires some minor companion software that exceeded, the AD7142 registers this as a sensor touch. runs on the host or other microcontroller to implement high resolution sensor functions such as a scroll bar or wheel. Preprogrammed threshold levels are used to determine if a However, no companion software is required to implement change in capacitance is due to a button being activated. If the buttons, including 8-way button functionality. Button sensors capacitance exceeds one of the threshold limits, the AD7142 are implemented completely in digital logic on-chip. registers this as a true button activation. The same thresholds principle is used to determine if other types of sensors, such as The AD7142 can be programmed to operate in either full power sliders or scroll wheels, are activated. mode, or in low power automatic wake-up mode. The automatic wake-up mode is particularly suited for portable devices that require low power operation giving the user significant power savings coupled with full functionality. The AD7142 has an interrupt output, INT, to indicate when new data has been placed into the registers. INT is used to interrupt the host on sensor activation. The AD7142 operates from a 2.6 V to 3.6 V supply, and is available in a 32-lead, 5 mm × 5 mm LFCSP. Rev. B | Page 12 of 70

Data Sheet AD7142 Complete Solution for Capacitance Sensing Low Power Mode Analog Devices, Inc. provides a complete solution for When in low power mode, the AD7142 POWER_MODE bits capacitance sensing. The two main elements to the solution are are set to 10 upon device initialization. If the external sensors the sensor PCB and the AD7142. are not touched, the AD7142 reduces its conversion frequency, thereby greatly reducing its power consumption. The part If the application requires high resolution sensors, such as scroll remains in a reduced power state when the sensors are not bars or wheels, software is required that runs on the host touched. Every LP_CONV_DELAY ms (200, 400, 600 or 800 ms), processor (no software is required for button sensors). The the AD7142 performs a conversion and uses this data to update memory requirements for the host depend on the sensor, and the compensation logic. When an external sensor is touched, are typically 10 kB of code and 600 bytes of data memory. the AD7142 begins a conversion sequence every 36 ms to read SENSOR PCB back data from the sensors. In low power mode, the total current consumption of the AD7142 is an average of the current SPI OR I2C HOST PROCESSOR AD7142 1 MIPS used during a conversion, and the current used when the 10kB ROM 600 BYTES RAM 05702-008 AexDam71p4l2e, iws wheanit iLnPg_ fCorO tNheV n_eDxEt LcoAnYv el rissi o40n0 t om bse, gthine. AFDor7 142 Figure 19. Three Part Capacitance Sensing Solution typically uses 0.9 mA current for 36 ms, and 15 μA for 400 ms of the conversion interval. Note that these conversion timings Analog Devices supplies the sensor PCB footprint design can be altered through the register settings. See the CDC libraries to the customer based on the specifications of the Conversion Sequence Time section for more information. customer, and supplies any necessary software on an open- source basis. AD7142 SETUP AND INITIALIZATION POWER_MODE = 10 OPERATING MODES The AD7142 has three operating modes. Full power mode, where the device is always fully powered, is suited for applications NO TOSUEACNNHSYOEDR? YES where power is not a concern (for example, game consoles that CONVERSION SEQUENCE EVERY LP_CONV_DELAY ms CONVERSION SEQUENCE have an ac power supply). Low power mode, where the part UPDLAOTGEI CC ODAMTPAE NPSAATTHION SEEVNESROYR 3R6EmAsD FBOARCK automatically powers down, is tailored to give significant power savings over full power mode, and is suited for mobile applications where power must be conserved. In shutdown mode, the part YES ANY SENSOR shuts down completely. TOUCHED? The POWER_MODE bits (Bit 0 and Bit 1) of the control NO rreeggiisstteerr isse ta tt hAed odpreersas t0inxg0 0m0.o Tdaeb olen 8t hseh oAwDs7 t1h4e2 P. OThWe EcRon_tMroOl DE PRCOOXUIMNTIT DYO TWIMNER TIMEOUT 05702-009 settings for each operating mode. To put the AD7142 into Figure 20. Low Power Mode Operation shutdown mode, set the POWER_MODE bits to either 01 or 11. The time taken for the AD7142 to go from a full power state to Table 8. POWER_MODE Settings a reduced power state, once the user stops touching the external sensors, is configurable. The PWR_DWN_TIMEOUT bits, in POWER_MODE Bits Operating Mode Ambient Compensation Ctrl 0 Register, at Address 0x002, 00 Full power mode control the length of time the AD7142 takes before going into 01 Full shutdown mode the reduced power state, once the sensors are not touched. 10 Low power mode 11 Full shutdown mode The power-on default setting of the POWER_MODE bits is 00, full power mode. Full Power Mode In full power mode, all sections of the AD7142 remain fully powered at all times. When a sensor is being touched, the AD7142 processes the sensor data. If no sensor is touched, the AD7142 measures the ambient capacitance level and uses this data for the on-chip compensation routines. In full power mode, the AD7142 converts at a constant rate. See the CDC Conversion Sequence Time section for more information. Rev. B | Page 13 of 70

AD7142 Data Sheet CAPACITANCE SENSOR INPUT CONFIGURATION Each input connection from the external capacitance sensors to CDC, or it can be left floating. Each input can also be internally the AD7142 converter can be uniquely configured by using the connected to the C signal to help prevent cross coupling. If SHIELD registers in Table 46 and Table 47. These registers are used to an input is not used, always connect it to C SHIELD. configure input pin connection setups, sensor offsets, sensor Connecting a CINx input pin to the positive CDC input results sensitivities, and sensor limits for each stage. Each sensor can be in a decrease in CDC output code when the corresponding individually optimized. For example, a button sensor connected sensor is activated. Connecting a CINx input pin to the negative to STAGE0 can have different sensitivity and offset values than CDC input results in an increase in CDC output code when the a button with a different function that is connected to a corresponding sensor is activated. different stage. The multiplexer settings for each conversion sequence can be CIN INPUT MULTIPLEXER SETUP unique and different for each of the input pins, CIN0 to CIN13. The CIN_CONNECTION_SETUP registers in Table 45 list the For example, CIN0 is connected to the negative CDC input for different options that are provided for connecting the sensor conversion STAGE1, left floating for sequencer STAGE1, and so input pin to the CDC. on for all twelve conversion stages. The AD7142 has an on-chip multiplexer to route the input Two bits in each sequence stage register control the mux setting for signals from each pin to the input of the converter. Each input the input pin. pin can be tied to either the negative or the positive input of the CIN0 CIN_CONNECTION CIN1 _SETUP BITS CIN SETTING CIN2 CCIINN34 00 CINX FLOATING CIN5 01 CINX CONNECTEDTO CIN6 NEGATIVE CDC INPUT + CIN7 CDC CIN8 10 CINX CONNECTEDTO – CIN9 POSITIVE CDC INPUT CIN10 CCCIIINNN111231 11 CCISNHXIE LCDONNECTEDTO 05702-010 Figure 21. Input Mux Configuration Options Rev. B | Page 14 of 70

Data Sheet AD7142 CAPACITANCE-TO-DIGITAL CONVERTER The capacitance-to-digital converter on the AD7142 has a Σ-Δ +DAC 7 architecture with 16-bit resolution. There are 14 possible inputs to (20pF RANGE) POS_AFE_OFFSET the CDC that are connected to the input of the converter through a switch matrix. The sampling frequency of the CDC is 250 kHz. OVERSAMPLING THE CDC OUTPUT POS_AFE_OFFSET_SWAP BIT The decimation rate, or oversampling ratio, is determined by CIN + 16 16-BIT Bits[9:8] of the control register, as listed in Table 9. _ CDC R Table 9. CDC Decimation Rate SO NEG_AFE_OFFSET_SWAP BIT N CDC Output Rate SE Decimation Bit Value Decimation Rate Per Stage 00 256 3.072 ms SRC –DAC 7 01 128 1.536 ms (20pF RANGE) NEG_AFE_OFFSET 101 1 11 CIN_CONRNEEGCISTTIOENR_SETUP 05702-011 1 Do not use this setting. Figure 23. Analog Front-End Offset Control The decimation process on the AD7142 is an averaging process CONVERSION SEQUENCER where a number of samples are taken and the averaged result is The AD7142 has an on-chip sequencer to implement conversion output. Due to the architecture of the digital filter employed, the control for the input channels. Up to 12 conversion stages can amount of samples taken (per stage) is equal to 3 times the be performed in one sequence. Each of the 12 conversion stages decimation rate. So 3 × 256 or 3 × 128 samples are averaged to can measure the input from a different sensor. By using the obtain each stage result. Bank 2 registers, each stage can be uniquely configured to support The decimation process reduces the amount of noise present in multiple capacitance sensor interface requirements. For example, the final CDC result. However, the higher the decimation rate, a slider sensor can be assigned to STAGE1 through STAGE8, the lower the output rate per stage, thus, a trade-off is possible with a button sensor assigned to STAGE0. between a noise-free signal and speed of sampling. The AD7142 on-chip sequence controller provides conversion CAPACITANCE SENSOR OFFSET CONTROL control beginning with STAGE0. Figure 24 shows a block diagram of the CDC conversion stages and CIN inputs. A conversion There are two programmable DACs on board the AD7142 to sequence is defined as a sequence of CDC conversions starting null any capacitance sensor offsets. These offsets are associated at STAGE0 and ending at the stage determined by the value with printed circuit board capacitance or capacitance due to any programmed in the SEQUENCE_STAGE_NUM register. Depen- other source, such as connectors. In Figure 22, C is the IN ding on the number and type of capacitance sensors that are capacitance of the input sensors, and C is the capacitance BULK used, not all conversion stages are required. Use the SEQUENCE_ between layers of the sensor PCB. C can be offset using the BULK STAGE_NUM register to set the number of conversions in one on-board DACs. sequence, depending on the sensor interface requirements. For CIN example, this register would be set to 5 if the CIN inputs were PLASTIC OVERLAY mapped to only six stages. In addition, set the STAGE_CAL_EN SENSOR BOARD CBULK CAPACITIVE SENSOR 05702-054 registers according to the number of stages that are used. Figure 22. Capacitances Around the Sensor PCB A simplified block diagram in Figure 23 shows how to apply the STAGE_OFFSET registers to null the offsets. The 7-bit POS_AFE_OFFSET and NEG_AFE_OFFSET registers program the offset DAC to provide 0.16 pF resolution offset adjustment over a range of ±20 pF. Apply the positive and negative offsets to either the positive or the negative CDC input using the NEG_AFE_OFFSET register and POS_AFE_OFFSET register. This process is only required once during the initial capacitance sensor characterization. Rev. B | Page 15 of 70

AD7142 Data Sheet STAGE11 this process is available from Analog Devices free of charge, on STAGE10 signing a software license. Scroll wheels also require eight stages. STAGE9 STAGE8 STAGE7 The 8-way switch is made from two pairs of differential buttons. STAGE6 It, therefore, requires two conversion stages, one for each of the STAGE5 STAGE4 differential button pairs. It also requires a stage to measure STAGE3 STAGE2 whether the sensor is active. The buttons are orientated so that STAGE1 one pair makes up the top and bottom portions of the 8-way STAGE0 CIN0 switch; the other pair makes up the left and right portions of the CIN1 8-way switch. CIN2 CIN3 CDC CONVERSION SEQUENCE TIME CCIINN45 TRIX The time required for one complete measurement for all 12 stages A Σ-∆ CCCIIINNN678 WITCH M 1A6-DBCIT EQUENCE bSEy QthUe ECNDCCE i_s SdTeAfiGneEd_ aNsU thMe CreDgiCst ecro nanvedr sDioEnC sIeMquAeTnIcOe Ntim reeg. iTstheer CIN9 S N S determine the conversion time as listed in Table 10. CIN10 SIO CIN11 ER Table 10. CDC Conversion Times for Full Power Mode V CIN12 N CIN13 CO 05702-012 DECIMCAoTnIOvNer =si onD TEimCIeM (mATsI)O N = Figure 24. CDC Conversion Stages SEQUENCE_STAGE_NUM 128 256 0 1.536 3.072 The number of required conversion stages depends completely 1 3.072 6.144 on the number of sensors attached to the AD7142. Figure 25 2 4.608 9.216 shows how many conversion stages are required for each sensor, 3 6.144 12.288 and how many inputs each sensor requires to the AD7142. 4 7.68 15.36 AD7142 SEQUENCER 5 9.216 18.432 STAGEX 6 10.752 21.504 + CDC 8-ELEMENT SLIDER – 7 12.288 24.576 STAGEX 8 13.824 27.648 + CDC – 9 15.36 30.72 STAGEX 10 16.896 33.792 +–CDC BUTTONS AD7142 SEQUENCER 11 18.432 36.864 STAGEX +STAGEX S1 +–CDC For example, operating with a decimation rate of 128, if the CDC – STAGEX SEQUENCE_STAGE_NUM register is set to 5 for the S2 + +STAGEX –CDC conversion of six stages in a sequence, the conversion sequence CDC – S3 time is 9.216 ms. STAGEX SRC + Full Power Mode CDC Conversion Sequence Time CDC – The full power mode CDC conversion sequence time for all 12 STAGEX + CDC stages is set by configuring the SEQUENCE_STAGE_NUM – register, and DECIMATION register as outlined in Table 10. SRC STAGEX + –CDC 05702-014 FCiDguCr ec o2n6 vsehroswiosn a t ismimep. Tlifhiee dfu tlilm pionwg edri amgoradme CoDf tChe c founlvl eproswioenr Figure 25. Sequencer Setup for Sensors time, t , is set using Table 10. CONV_FP A button sensor generally requires one sequencer stage; however, t it is possible to configure two button sensors to operate differ- CONV_FP entially. Only one button from the pair can be activated at a CDC CONVERSION CONVERSION CONVERSION time; pressing both buttons together results in neither button CONVERSION SEQUENCE N SEQUENCE N+1 SEQUENCE N+2 being activated. This configuration requires one conversion stage, and is shown in Figure 25, B2 and B3. N1.OtTCOENSV_FP =VALUE SET FROMTABLE 10. 05702-015 A scroll bar or slider sensor requires eight stages. The result Figure 26. Full Power Mode CDC Conversion Sequence Time from each stage is used by the host software to determine the user’s position on the scroll bar. The algorithm that performs Rev. B | Page 16 of 70

Data Sheet AD7142 Low Power Mode CDC Conversion Sequence Time with tCONV_LP Delay The frequency of each CDC conversion operating in the low CONVERSCIODCN CSOEtCNQOVUNEEVRN_SFCPIEO NN LP_CONV_DELAY SCEOQNUVEENRCSEI ONN+1 05702-016 power automatic wake-up mode is controlled by using the LP_CONV_DELAY register located at Address 0x000[3:2], in Figure 27. Low Power Mode CDC Conversion Sequence Time addition to the registers listed in Table 10. This feature provides CDC CONVERSION RESULTS some flexibility for optimizing the conversion time to meet system requirements vs. AD7142 power consumption. Certain high resolution sensors require the host to read back the CDC conversion results for processing. The registers For example, maximum power savings is achieved when the required for host processing are located in the Bank 3 registers. LP_CONV_DELAY register is set to 3. With a setting of 3, the The host processes the data readback from these registers using AD7142 automatically wakes up, performing a conversion a software algorithm, to determine position information. every 800 ms. In addition to the results registers in the Bank 3 registers, the Table 11. LP_CONV_DELAY Settings AD7142 provides the 16-bit CDC output data directly, starting LP_CONV_DELAY Bits Delay Between Conversions at Address 0x00B of Bank 1. Reading back the CDC 16-bit 00 200 ms conversion data register allows for customer-specific application 01 400 ms data processing. 10 600 ms 11 800 ms Figure 27 shows a simplified timing example of the low power CDC conversion time. As shown, the low power CDC conversion time is set by tCONV_FP and the LP_CONV_DELAY register. Rev. B | Page 17 of 70

AD7142 Data Sheet NONCONTACT PROXIMITY DETECTION The AD7142 internal signal processing continuously monitors determined by PROXIMITY_RECAL_LVL, for a set period of all capacitance sensors for noncontact proximity detection. This time known as the recalibration timeout. In full power mode, the feature provides the ability to detect when a user is approaching recalibration timeout is controlled by FP_PROXIMITY_RECAL, a sensor, at which time all internal calibration is immediately and in low power mode, by LP_PROXIMITY_RECAL. disabled and the AD7142 is automatically configured to detect a Recalibration timeout in full power mode = valid contact. FP_PROXIMITY_RECAL × Time taken for one conversion The proximity control register bits are described in Table 12. sequence in full power mode The FP_PROXIMITY_CNT register bits and Recalibration timeout in low power mode = LP_PROXIMITY_CNT register bits control the length of the LP_PROXIMITY_RECAL × Time taken for one conversion calibration disable period after the user leaves the sensor and sequence in low power mode proximity is no longer active, in full and low power modes. The Figure 30 and Figure 31 show examples of how the calibration is disabled during this time and enabled again at the FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL end of this period provided that the user is no longer register bits control the timeout period before a recalibration, approaching, or in contact with, the sensor. Figure 28 and operating in the full and low power modes. These figures show a Figure 29 show examples of how these registers are used to set user approaching a sensor followed by the user leaving the sensor the full and low power mode calibration disable periods. and the proximity detection remains active after the user leaves the Calibration disable period in full power mode = sensor. The measured CDC value exceeds the stored ambient value FP_PROXIMITY_CNT × 16 × Time taken for one conversion by the amount set in the PROXIMITY_RECAL_LVL bits, for the sequence in full power mode entire timeout period. The sensor is automatically recalibrated Calibration disable period in low power mode = at the end of the timeout period. The forced recalibration takes LP_PROXIMITY_CNT × 4 × Time taken for one conversion two interrupt cycles, therefore, do not set it again during this sequence in low power mode interval. RECALIBRATION PROXIMITY SENSITIVITY In certain situations, the proximity flag can be set for a long The fast filter in Figure 32 is used to detect when someone is period, for example when a user hovers over a sensor for a long close to the sensor (proximity). Two conditions set the internal time. The environmental calibration on the AD7142 is proximity detection signal using Comparator 1 and suspended when proximity is detected, but changes may occur Comparator 2. Comparator 1 detects when a user is to the ambient capacitance level during the proximity event. approaching a sensor. The PROXIMITY_DETECTION_RATE This means the ambient value stored on the AD7142 no longer register controls the sensitivity of Comparator 1. For example, if represents the actual ambient value. In this case, even when the PROXIMITY_DETECTION_RATE is set to 4, the Proximity 1 user has left the sensor, the proximity flag may still be set. This signal is set when the absolute difference between WORD1 and situation could occur if the user interaction creates some WORD3 exceeds four LSB codes. Comparator 2 detects when a moisture on the sensor causing the new sensor ambient value to user hovers over a sensor or approaches a sensor very slowly. be different from the expected value. In this situation, the The PROXIMITY_RECAL_LVL register (Address 0x003) AD7142 automatically forces a recalibration internally. This controls the sensitivity of Comparator 2. For example, if ensures that the ambient values are recalibrated regardless of PROXIMITY_RECAL_LVL is set to 75, the Proximity 2 signal how long the user hovers over a sensor. A recalibration ensures is set when the absolute difference between the fast filter maximum AD7142 sensor performance. average value and the ambient value exceeds 75 LSB codes. The AD7142 recalibrates automatically when the measured CDC value exceeds the stored ambient value by an amount Table 12. Proximity Control Registers (See Figure 32) Register Length Register Address Description FP_PROXIMITY_CNT 4 bits 0x002 [7:4] Calibration disable time in full power mode LP_PROXIMITY_CNT 4 bits 0x002 [11:8] Calibration disable time in low power mode FP_PROXIMITY_RECAL 8 bits 0x004 [9:0] Full power mode proximity recalibration time LP_PROXIMITY_RECAL 6 bits 0x004 [15:10] Low power mode proximity recalibration time PROXIMITY_RECAL_LVL 8 bits 0x003 [13:8] Proximity recalibration level PROXIMITY_DETECTION_RATE 6 bits 0x003 [7:0] Proximity detection rate Rev. B | Page 18 of 70

Data Sheet AD7142 USERAPPROACHES USER LEAVES SENSOR SENSOR HERE AREA HERE tCONV_FP CDC CONVERSION SEQUENCE 1 2 3 4 5 6 7 8 9 10111213141516 (INTERNAL) tCALDIS PROXIMITY DETECTION (INTERNAL) CA(ILNIBTERRATNIAOLN) CALIBRATION DISABLED CALIBRATION ENABLED 05702-017 Figure 28. Full Power Mode Proximity Detection Example with FP_PROXIMITY_CNT = 1 USER USER LEAVES APPROACHES SENSOR SENSOR HERE AREA HERE tCONV_LP 1 2 3 4 5 6 7 8 9 101112131415161718192021222324 CDC CONVERSION SEQUENCE (INTERNAL) tCALDIS PROXIMITY DETECTION (INTERNAL) CALIBRATION (INTERNAL) CALIBRATION DISABLED CALIBRATION ENABLED NOTES 123... tSPCERAQOLDUXIEISMN=ICT (YtEC ICOSNO SVN_EVLTPE WR× SHLIEPON_NP UTRSIOMEXERIMtACIPTOPYNRV_O_CLNAPTC = H×tE C4SO) NTVH_EFP S +E NLPS_OCROANTV W_DHEILCAHY TIME THE INTERNAL CALIBRATION IS DISABLED. 05702-018 Figure 29. Low Power Mode Proximity Detection with LP_PROXIMITY_CNT = 4 USER APPROACHES SENSOR HERE tRECAL USER LEAVES SENSOR MEASURED CDC VALUE > STORED AMBIENT AREA HERE BY PROXIMITY_RECAL _LVL tCONV_FP 16 30 70 CDC CONVERSION SEQUENCE (INTERNAL) tCALDIS PROXIMITY DETECTION (INTERNAL) CALIBRATION CALIBRATION DISABLED RECALIBRATION TIME-OUT CALIBRATION ENABLED (INTERNAL) RECALIBRATION COUNTER tRECAL_TIMEOUT (INTERNAL) 05702-019 NOTES 1. SEQUENCE CONVERSION TIMEtCONV_FP DETERMINED FROM TABLE 10 2.tCALDIS=tCONV_FP × FP_PROXIMITY_CNT ×16 3.tRECAL_TIMEOUT =tCONV_FP × FP_PROXIMITY_RECAL 4.tRECAL = 2 ×tCONV_FP Figure 30. Full Power Mode Proximity Detection with Forced Recalibration Example with FP_PROXIMITY_CNT = 1 and FP_PROXIMITY_RECAL = 40 Rev. B | Page 19 of 70

AD7142 Data Sheet USER APPROACHES SENSOR HERE tRECAL USER LEAVES SENSOR AREA HERE MEASURED CDC VALUE > STORED AMBIENT BY PROXIMITY_RECAL _LVL tCONV_LP 16 30 70 CDC CONVERSION SEQUENCE (INTERNAL) PROXIMITY DETECTION (INTERNAL) tCALDIS CA(LINIBTREARTNIAOLN) CALIBRATION DISABLED RECALIBRATION TIME-OUT CALIBRATION ENABLED RECALIBRATION tRECAL_TIMEOUT (INTERNAL) NOTES 1. SEQUENCE CONVERSION TIMEtCONV_LP = tCONV_FP + LP_CONV_DELAY 234...tttRRCEEACCLDAAILLS_ =T= IM2t CE×OOtUNCTVO_ N=LVPt_C ×LOP LNPV__FPPR ×O LXPIM_PITRYO_CXINMTI T×Y 4_RECAL 05702-02005702-020 Figure 31. Low Power Mode Proximity Detection with Forced Recalibration Example with LP_PROXIMITY_CNT = 4 and LP_PROXIMITY_RECAL = 40 Rev. B | Page 20 of 70

Data Sheet AD7142 FF_SKIP_CNT samples are not used (skipped) in the proximity detection fast FIFO. The proximity detection fast FIFO is used by the on-chip logic to determine if proximity is detected. The fast FIFO expects to Determining the FF_SKIP_CNT value is required only once receive samples from the converter at a set rate. FF_SKIP_CNT during the initial setup of the capacitance sensor interface. is used to normalize the frequency of the samples going into the Table 13 shows how FF_SKIP_CNT controls the update rate to FIFO, regardless of how many conversion stages are in a the fast FIFO. Recommended value for this setting when using sequence. In Register 0x02, Bits[3:0] are the fast filter skip all 12 conversion stages on the AD7142 is FF_SKIP_CNT = control, FF_SKIP_CNT. This value determines which CDC 0000 = no samples skipped. Table 13. FF_SKIP_CNT Settings FAST FIFO Update Rate FF_SKIP_CNT DECIMATION = 128 DECIMATION = 256 0 1.536 × (SEQUENCE_STAGE_NUM + 1) ms 3.072 × (SEQUENCE_STAGE_NUM + 1) ms 1 3.072 × (SEQUENCE_STAGE_NUM + 1) ms 6.144 × (SEQUENCE_STAGE_NUM + 1) ms 2 4.608 × (SEQUENCE_STAGE_NUM + 1) ms 9.216 × (SEQUENCE_STAGE_NUM + 1) ms 3 6.144 × (SEQUENCE_STAGE_NUM + 1) ms 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 4 7.68 × (SEQUENCE_STAGE_NUM + 1) ms 15.36 × (SEQUENCE_STAGE_NUM + 1) ms 5 9.216 × (SEQUENCE_STAGE_NUM + 1) ms 18.432 × (SEQUENCE_STAGE_NUM + 1) ms 6 10.752 × (SEQUENCE_STAGE_NUM + 1) ms 21.504 × (SEQUENCE_STAGE_NUM + 1) ms 7 12.288 × (SEQUENCE_STAGE_NUM + 1) ms 24.576 × (SEQUENCE_STAGE_NUM + 1) ms 8 13.824 × (SEQUENCE_STAGE_NUM + 1) ms 27.648 × (SEQUENCE_STAGE_NUM + 1) ms 9 15.36 × (SEQUENCE_STAGE_NUM + 1) ms 30.72 × (SEQUENCE_STAGE_NUM + 1) ms 10 16.896 × (SEQUENCE_STAGE_NUM + 1) ms 33.792 × (SEQUENCE_STAGE_NUM + 1) ms 11 18.432 × (SEQUENCE_STAGE_NUM + 1) ms 36.864 × (SEQUENCE_STAGE_NUM + 1) ms 12 19.968 × (SEQUENCE_STAGE_NUM + 1) ms 39.936 × (SEQUENCE_STAGE_NUM + 1) ms 13 21.504 × (SEQUENCE_STAGE_NUM + 1) ms 43.008 × (SEQUENCE_STAGE_NUM + 1) ms 14 23.04 × (SEQUENCE_STAGE_NUM + 1) ms 46.08 × (SEQUENCE_STAGE_NUM + 1) ms 15 24.576 × (SEQUENCE_STAGE_NUM + 1) ms 49.152 × (SEQUENCE_STAGE_NUM + 1) ms Rev. B | Page 21 of 70

AD7142 Data Sheet 16 CDC FP_PROXIMITY_CNT LP_PROXIMITY_CNT REGISTER 0x002 REGISTER 0X002 STAGE_FF_WORD0 COMPARATOR 1 PROXIMITY STAGE_FF_WORD1 PROXIMITY 1 WORD0 – WORD3 PROXIMITY TIMING STAGE_FF_WORD2 CONTROL LOGIC STAGE_FF_WORD3 STAGE_FF_WORD4 STAGE_FF_WORD5 PROXIMITY_DETECTION_RATE FP_PROXIMITY_RECAL LP_PROXIMITY_RECAL STAGE_FF_WORD6 REGISTER 0x003 REGISTER 0x004 REGISTER 0X004 STAGE_FF_WORD7 2 BANK 3 REGISTERS TY MI 7 XI Σ O WORD(N) STAGE_FF_AVG PR N = 0 BANK 3 REGISTERS 8 COMPARATOR 2 STAGE_FF_WORDX AVERAGE –AMBIENT PROXIMITY SLOW_FILTER_EN SW1 E D PROXIMITY_RECAL_LVL O C REGISTER 0x003 T AMBIENT VALUE COMPARATOR 2 STAGE_SF_WORD0 PU STAGE_SF_WORDX WORD0 – WORD3 STAGE_SF_WORD1 UT O SENSOR SSTTAAGGEE__SSFF__WWOORRDD32 SBTAANGKE 3_ SRFE_GAIMSTBEIERNST CDC CONTACT SLOW_FILTER_UPDATE_LVL STAGE_SF_WORD4 TIME REGISTER 0x003 STAGE_SF_WORD5 STAGE_SF_WORD6 STAGE_SF_WORD7 BANK 3 REGISTERS NOTES 1.SLOW FILTER EN IS SETAND SW1 IS CLOSED WHEN|STAGE_SF_WORD 0–STAGE_SF_WORD 1|EXCEEDS THEVALUE PROGRAMMED IN THE SLOW_FILTER_UPDATE_LVL REGISTER PROVIDING PROXIMITY IS NOT SET. 2.PROXIMITY 1 IS SET WHEN|STAGE_FF_WORD 0– STAGE_FF_WORD 3| EXCEEDS THEVALUE PROGRAMMED IN THE PROXIMITY_DETECTION_RATE REGISTER. 3.PROXIMITY 2 IS SET WHEN|AVERAGE–AMBIENT|EXCEEDS THEVALUE PROGRAMMED IN THE PROXIMITY_RECAL_LVL REGISTER. 4. DESCRIPTION OF COMPARATOR FUNCTIONS: COMPARATOR 1: USEDTO DETECT WHEN A USER ISAPPROACHING OR LEAVING A SENSOR. COMPARATOR 2: USEDTO DETECT WHEN A USER IS HOVERING OVER A SENSOR, ORAPPROACHING A SENSOR VERY SLOWLY. ALSO USEDTO DETECT IF THE SENSORAMBIENT LEVEL HAS CHANGEDAS A RESULT OF THE USER INTERACTION. COMPARATOR 3: UFSOERD ETXOA MENPLAEB,L HEU TMHIED ISTYLO OWR FDIILRTTE RLE UFPTD BAETHEI NRDA TOEN. TSHEEN SSOLORW. FILTER IS UPDATED WHENSLOW FILTER EN IS SETANDPROXIMITY IS NOT SET. 05702-021 Figure 32. AD7142 Proximity Detection and Environmental Calibration Rev. B | Page 22 of 70

Data Sheet AD7142 ENVIRONMENTAL CALIBRATION The AD7142 provides on-chip capacitance sensor calibration to CAPACITANCE SENSOR BEHAVIOR WITHOUT automatically adjust for environmental conditions that have an CALIBRATION effect on the capacitance sensor ambient levels. Capacitance Figure 34 shows the typical behavior of a capacitance sensor sensor output levels are sensitive to temperature, humidity, and with no applied calibration. This figure shows ambient levels in some cases, dirt. The AD7142 achieves optimal and reliable drifting over time as environmental conditions change. The sensor performance by continuously monitoring the CDC ambient level drift has resulted in the detection of a missed user ambient levels and correcting for any changes by adjusting the contact on Sensor 2. This is a result of the initial low offset level STAGE_HIGH_THRESHOLD and STAGE_LOW_ THRESHOLD remaining constant when the ambient levels drifted upward register values, as described in Equation 1 and Equation 2. The beyond the detection range. CDC ambient level is defined as the capacitance sensor output The Capacitance Sensor Behavior with Calibration section level during periods when the user is not approaching or in describes how the AD7142 adaptive calibration algorithm contact with the sensor. prevents errors such as this from occurring. The compensation logic runs automatically on every conversion after configuration when the AD7142 is not being touched. This SENSOR 1 INT ASSERTED allows the AD7142 to account for rapidly changing environ- STAGE_HIGH_THRESHOLD mental conditions. S E The ambient compensation control registers give the host access COD CDCAMBIENT to general setup and controls for the compensation algorithm. T VALUE DRIFTING U P The RAM stores the compensation data for each conversion T U O stage, as well as setup information specific to each stage. C D C STAGE_LOW_THRESHOLD Figure 33 shows an example of an ideal capacitance sensor behavior where the CDC ambient level remains constant SENSOR 2 INT NOTASSERTED rshegoawrdnl eiss sf oorf at hpea eirn ovfi rdoinffmereennttaial lc bountdtiotnio snesn. sTohres, CwDhCer eo uotnpeu t CHANGING ENVIRONMENTAL CONDITIONS t 05702-023 sensor caused an increase, and the other a decrease in measured Figure 34. Typical Sensor Behavior Without Calibration Applied capacitance when activated. The positive and negative sensor CAPACITANCE SENSOR BEHAVIOR WITH threshold levels are calculated as a percentage of the CALIBRATION STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW values based on the threshold sensitivity settings and the ambient The AD7142 on-chip adaptive calibration algorithm prevents value. These values are sufficient to detect a sensor contact, sensor detection errors such as the one shown in Figure 34. This resulting with the AD7142 asserting the INT output when the is achieved by monitoring the CDC ambient levels and threshold levels are exceeded. readjusting the initial STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW values according to the amount of SENSOR 1 INT ASSERTED ambient drift measured on each sensor. The internal STAGE_HIGH_THRESHOLD STAGE_HIGH_THRESHOLD and STAGE_LOW_THRESHOLD S values described in Equation 1 and Equation 2 are automatically E D O updated based on the new STAGE_OFFSET_HIGH and C T STAGE_OFFSET_LOW values. This closed-loop routine U CDCAMBIENTVALUE P T ensures the reliability and repeatable operation of every sensor U O C connected to the AD7142 under dynamic environmental D C STAGE_LOW_THRESHOLD conditions. Figure 35 shows a simplified example of how the SENSOR 2 INT AD7142 applies the adaptive calibration process resulting in no ASSERTED interrupt errors under changing CDC ambient levels due to CHANGING ENVIRONMENTAL CONDITIONS t 05702-022 environmental conditions. Figure 33. Ideal Sensor Behavior with a Constant Ambient Level Rev. B | Page 23 of 70

AD7142 Data Sheet SENSOR 1 INT capacitance value tracks the measured capacitance value read by ASSERTED 3 STAGE_HIGH_THRESHOLD the converter. 2 (POST CALIBRATED 1 REGISTERVALUE) Slow FIFO update rate in full power mode = AVG_FP_SKIP × [(3 × Decimation Rate) × (SEQUENCE_STAGE_NUM +1) × S DE (FF_SKIP_CNT +1) × 4 × 10-7] CO CDCAMBIENT T VALUE DRIFTING Slow FIFO update rate in low power mode = (AVG_LP_SKIP +1) × U P T [(3 × Decimation Rate) × (SEQUENCE_STAGE_NUM +1) × OU 6 C 5 STAGE_LOW_THRESHOLD (FF_SKIP_CNT +1) × 4 × 10-7] / [(FF_SKIP_CNT +1) + CD 4 (POST CALIBRATED LP_CONV_DELAY] REGISTERVALUE) SENSOR 2 INT The slow FIFO is used by the on-chip logic to track the ambient ASSERTED capacitance value. The slow FIFO expects to receive samples t CHANGING ENVIRONMENTAL CONDITIONS from the converter at a rate of 33 ms to 40 ms. AVG_FP_SKIP and AVG_LP_SKIP are used to normalize the frequency of the NOTES samples going into the FIFO, regardless of how many 1. INITIAL STAGE_OFFSET_HIGH REGISTERVALUE 2. POST CALIBRATED REGISTER STAGE_HIGH_THRESHOLD conversion stages are in a sequence. 345... IPPNOOITSSITTA LCC AASTLLAIIBBGRREAA_TTLEEODDW RR_EETGGHIIRSSETTSEEHRRO SSLTTDAAGGEE__HLOIGWH__TTHHRREESSHHOOLLDD 05702-024 Determining the AVG_FP_SKIP and AVG_LP_SKIP value is 6. POST CALIBRATED REGISTER STAGE_LOW_THRESHOLD only required once during the initial setup of the capacitance Figure 35. Typical Sensor Behavior with Calibration Applied on the Data Path sensor interface. Recommended values for these settings when SLOW FIFO using all 12 conversion stages on the AD7142 are: As shown in Figure 32, there are a number of FIFOs AVG_FP_SKIP = 00 = skip 3 samples implemented on the AD7142. These FIFOs are located in AVG_LP_SKIP = 00 = skip 0 samples Bank 3 of the on-chip memory. The slow FIFOs are used by the SLOW_FILTER_UPDATE_LVL on-chip logic to monitor the ambient capacitance level from The SLOW_FILTER_UPDATE_LVL controls whether the most each sensor. recent CDC measurement goes into the Slow FIFO (slow filter) AVG_FP_SKIP and AVG_LP_SKIP or not. The slow filter is updated when the difference between In Register 0x001, Bits[13:12] are the slow FIFO skip control for the current CDC value and last value pushed into the slow FIFO full power mode, AVG_FP_SKIP. Bits[15:14] in the same > SLOW_FILTER_UPDATE_LVL. This variable is in Ambient register are the slow FIFO skip control for low power mode, Control Register 1, at Address 0x003. AVG_LP_SKIP. These values determine which CDC samples are not used (skipped) in the slow FIFO. Changing theses values slows down or speeds up the rate at which the ambient  STAGE_OFFSET_HIGH  STAGE_OFFSET_HIGH   STAGE_HIGH_THRESHOLD STAGE_SF_AMBIENT STAGE_OFFSET _HIGH  4 POS_THRESHOLD _SENSITIVITY  4   16      Equation 1. On-Chip Logic Stage High Threshold Calculation  STAGE_OFFSET _LOW  STAGE_OFFSET _LOW   STAGE_OFFSET _LOW   4  STAGE_LOW_THRESHOLD STAGE_SF_AMBIENT  4  16 NEG_THRESHOLD _SENSITIVITY     Equation 2. On-Chip Logic Stage Low Threshold Calculation Rev. B | Page 24 of 70

Data Sheet AD7142 ADAPTIVE THRESHOLD AND SENSITIVITY The AD7142 provides an on-chip self-learning adaptive a large average maximum or minimum value, and a small finger threshold and sensitivity algorithm. This algorithm continu- gives smaller values. When the average maximum or minimum ously monitors the output levels of each sensor and automatically value changes, the threshold levels are rescaled to ensure that rescales the threshold levels proportionally to the sensor area the threshold levels are appropriate for the current user. Figure 37 covered by the user. As a result, the AD7142 maintains optimal shows how the minimum and maximum sensor responses are threshold and sensitivity levels for all types of users regardless tracked by the on-chip logic. of their finger sizes. Reference A in Figure 36 shows an undersensitive threshold The threshold level is always referenced from the ambient level level for a small finger user, demonstrating the disadvantages of and is defined as the CDC converter output level that must be a fixed threshold level. exceeded for a valid sensor contact. The sensitivity level is By enabling the adaptive threshold and sensitivity algorithm, defined as how sensitive the sensor is before a valid contact the positive and negative threshold levels are determined by the is registered. POS_THRESHOLD_SENSITIVITY and NEG_THRESHOLD_ Figure 36 provides an example of how the adaptive threshold and SENSITIVITY register values and the most recent average sensitivity algorithm works. The positive and negative sensor maximum sensor output value. These registers can be used to threshold levels are calculated as a percentage of the STAGE_ select 16 different positive and negative sensitivity levels OFFSET_HIGH and STAGE_OFFSET_LOW values based on ranging between 25% and 95.32% of the most recent average the threshold sensitivity settings and the ambient value. On maximum output level referenced from the ambient value. The configuration, initial estimates are supplied for both smaller the sensitivity percentage setting, the easier it is to STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW after trigger a sensor activation. Reference B shows that the positive which the calibration engine automatically adjusts the adaptive threshold level is set at almost mid-sensitivity with a STAGE_HIGH_THRESHOLD and STAGE_LOW_ 62.51% threshold level by setting POS_THRESHOLD_ THRESHOLD values for sensor response. SENSITIVITY = 1000. Figure 36 also provides a similar example for the negative threshold level with NEG_ The AD7142 tracks the average maximum and minimum values THRESHOLD_SENSITIVITY = 0001. measured from each sensor. These values give an indication of how the user is interacting with the sensor. A large finger gives AVERAGE MAXVALUE 95.32% STAGE_OFFSET_HIGH S E IS UPDATED D O C AVERAGE MAXVALUE T 62.51% = POSADAPTIVE TPU STAGE_OFFSET_HIGH A THRESHOLD LEVEL OU 95.32% C STAGE_OFFSET_HIGH CD IS UPDATED HERE 62.51% = POS ADAPTIVE 25% THRESHOLD LEVEL 25% B AMBIENT LEVEL 25% NEGADAPTIVE THRESHOLD LEVEL = 39.08% STAGE_OFFSET_LOW 25% IS UPDATED HERE STAGE_OFFSET_LOW NEGADAPTIVE THRESHOLD LEVEL = 39.08% 95.32% STAGE_OFFSET_LOW IS UPDATED HERE 95.32% SEBNYS SOMRA CLOL NFTINAGCETRED SEBNYS LOARR GCOE NFTINAGCETRED 05702-025 Figure 36. Threshold Sensitivity Example with POS_THRESHOLD_SENSITIVITY = 1000 and NEG_THRESHOLD_SENSITIVITY = 0011 Rev. B | Page 25 of 70

AD7142 Data Sheet STAGE_MAX_WORD0 STAGE_MAX_WORD1 BANK 3 STAGE_MAX_WORD2 REGISTERS STAGE_MAX_WORD3 Σ-∆ 16 16-BIT CDC MAX LEVEL STAGE_MAX_AVG DETECTION BANK 3 REGISTERS LOGIC STAGE_MAX_TEMP BANK 3 REGISTERS STAGE_HIGH_THRESHOLD BANK 3 REGISTERS STAGE_MIN_WORD0 STAGE_MIN_WORD1 BANK 3 STAGE_MIN_WORD2 REGISTERS STAGE_MIN_WORD3 MIN LEVEL DETECTION STAGE_MIN_AVG LOGIC BANK 3 REGISTER3 STAGE_MIN_TEMP BANK 3 REGISTERS STABGAEN_KL O3 WR_ETGHISRTEESRHSOLD 05702-062 Figure 37. Tracking the Minimum and Maximum Average Sensor Values Table 14. Additional Information about Environmental Calibration and Adaptive Threshold Registers Register Register Location Description NEG_THRESHOLD_SENSITIVITY Bank 2 Used in Equation 2. This value is programmed once at start up. NEG_PEAK_DETECT Bank 2 Used by internal adaptive threshold logic only. The NEG_PEAK_DETECT is set to a percentage of the difference between the ambient CDC value, and the min average CDC value. If the output of the CDC gets within the NEG_PEAK_DETECT percentage of the min average, only then is the min average value updated. POS_THRESHOLD_SENSITIVITY Bank 2 Used in Equation 1. This value is programmed once at start up. POS_PEAK_DETECT Bank 2 Used by internal adaptive threshold logic only. The POS_PEAK_DETECT is set to a percentage of the difference between the ambient CDC value, and the max average CDC value. If the output of the CDC gets within the POS_PEAK_DETECT percentage of the min average, only then is the max average value updated. STAGE_OFFSET_LOW Bank 2 Used in Equation 2. An initial value (based on sensor characterization) is programmed into this register at start up. The AD7142 on chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. Set to 80% of the STAGE_OFFSET_LOW_CLAMP value. STAGE_OFFSET_HIGH Bank 2 Used in Equation 1. An initial value (based on sensor characterization) is programmed into this register at start up. The AD7142 on chip calibration algorithm automatically updates this register based on the amount of sensor drift due to changing ambient conditions. Set to 80% of the STAGE_OFFSET_HIGH_CLAMP value. STAGE_OFFSET_HIGH_CLAMP Bank 2 Used by internal environmental calibration and adaptive threshold algorithms only. An initial value (based on sensor characterization) is programmed into this register at start up. The value in this register prevents a user from causing a sensor’s output value to exceed the expected nominal value. Set to the maximum expected sensor response, maximum change in CDC output code. STAGE_OFFSET_LOW_CLAMP Bank 2 Used by internal environmental calibration and adaptive threshold algorithms only. An initial value (based on sensor characterization) is programmed into this register at start up. The value in this register prevents a user from causing a sensor’s output value to exceed the expected nominal value. Set to the minimum expected sensor response, minimum change in CDC output code. STAGE_SF_AMBIENT Bank 3 Used in Equation 1 and Equation 2. This is the ambient sensor output, when the sensor is not touched, as calculated using the slow FIFO. STAGE_HIGH_THRESHOLD Bank 3 Equation 1 value. STAGE_LOW_THRESHOLD Bank 3 Equation 2 value. Rev. B | Page 26 of 70

Data Sheet AD7142 INTERRUPT OUTPUT The AD7142 has an interrupt output that triggers an interrupt SENSOR TOUCH INTERRUPT service routine on the host processor. The INT signal is on Use the sensor touch interrupt mode to interrupt the host Pin 25, and is an open-drain output. There are three types of processor only when the sensor is activated. interrupt events on the AD7142: a CDC conversion complete Configuring the AD7142 into this mode results in the interrupt interrupt, a sensor threshold interrupt, and a GPIO interrupt. being asserted when the user makes contact with the sensor and Each interrupt has enable and status registers. The conversion again when the user lifts off the sensor. The second interrupt is complete and sensor threshold interrupts can be enabled on a required to alert the host processor that the user is no longer per conversion stage basis. The status registers indicate what contacting the sensor. type of interrupt triggered the INT pin. Status registers are cleared, and the INT signal is reset high, during a read The registers located at Address 0x005 and Address 0x006 are operation. The signal returns high as soon as the read address used to enable the interrupt output for each stage. The registers has been set up. located at Address 0x008 and Address 0x009 are used to read back the interrupt status for each stage. CDC CONVERSION COMPLETE INTERRUPT Figure 38 shows the interrupt output timing during contact with The AD7142 interrupt signal asserts low to indicate the one of the sensors connected to STAGE0 when operating in the completion of a conversion stage, and new conversion result sensor touch interrupt mode. For a low limit configuration, the data is available in the registers. interrupt output is asserted as soon as the sensor is contacted and The interrupt can be independently enabled for each conversion again after the user has stopped contacting the sensor. stage. Each conversion stage complete interrupt can be enabled via Note: The interrupt output remains low until the host processor the STAGE_COMPLETE_EN register (Address 0x007). This reads back the interrupt status registers located at Address 0x008 register has a bit that corresponds to each conversion stage. Setting and Address 0x009. this bit to 1 enables the interrupt for that stage. Clearing this bit to 0 The interrupt output is asserted when there is a change in the disables the conversion complete interrupt for that stage. threshold status bits. This could indicate that a user is now In normal operation, the AD7142 interrupt is enabled only for the touching the sensor(s) for the first time, the number of sensors last stage in a conversion sequence. For example, if there are five being touched has changed, or the user is no longer touching conversion stages, the conversion complete interrupt for STAGE4 is the sensor(s). Reading the status bits in the interrupt status enabled. INT only asserts when all five conversion stages are register shows the current sensor activations. complete, and the host can read new data from all five result registers. The interrupt is cleared by reading the STAGE_ CONVERSION STAGE STAGE0 STAGE1 COMPLETE_STATUS_INT register located at Address 0x00A. Register 0x00A is the conversion complete interrupt status register. 2 4 Each bit in this register corresponds to a conversion stage. If a SERIAL bit is set, it means that the conversion complete interrupt for the READBACK corresponding stage was triggered. This register is cleared on a read, provided the underlying condition that triggered the INT OUTPUT interrupt has gone away. NOTES: 1234.... UAAUSDDSEEDDRRRR EETLSSOIFSSUT 00CINXXHG00IN00 O88G FRR DFEE OOAAWDDF NSBB EAAONCCNSKK SO TTEROON SCCOLLREEAARR IINNTTEERRRRUUPPTT 05702-055 Figure 38. Example of Sensor Touch Interrupt Rev. B | Page 27 of 70

AD7142 Data Sheet CONVERSIONS STAGE0 STAGE1 STAGE2 STAGE3 STAGE4 STAGE5 STAGE6 STAGE7 STAGE8 STAGE9 STAGE10 STAGE11 INT 1 2 3 SERIAL READS NOTES THIS ISAN EXAMPLE OF A CDC CONVERSION COMPLETE INTERRUPT. THIS TIMING EXAMPLE SHOWS THAT THE INTERRUPT OUTPUT HAS BEEN ENABLEDTO BEASSERTEDAT THE END OF A CONVERSION CYCLE FOR STAGE0, STAGE5,AND STAGE9. THE INTERRUPTS FORALL OTHER STAGES HAVE BEEN DISABLED. STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE5,AND STAGE9 (x = 0, 5, 9) STAGEx_LOW_INT_EN (ADDRESS 0x005) = 0 STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0 STAGEx_COMPLETE_EN (ADDRESS 0x007) = 1 STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE1 THROUGH STAGE8, STAGE10,AND STAGE11 (x = 1, 2, 3, 4, 5, 6, 7, 8, 10,11) STAGEx_LOW_INT_EN (ADDRESS 0x005) = 0 STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0 STAGEx_COMPLETE_EN (ADDRESS 0x007) = 0 S12..E RRREEIAAALDD RTTEHHAEED SSBTTAAACGGKEE R05__ECCQOOUMMIRPPELLMEEETTEEN__TSSSTT FAAOTTUURSS S__TIINNATTG E((AA0DD, SDDTRRAEEGSSESS5 00Axx00N00DAA S)) RRTAEEGGGEIISS9TT. EETRRHIS READBACK OPERATION IS REQUIREDTO CLEAR THE INTERRUPT OUTPUT. 05702-026 3. READ THE STAGE9_COMPLETE_STATUS_INT (ADDRESS 0x00A) REGISTER Figure 39. Example of Configuring the Registers for End of Conversion Interrupt Setup CONVERSIONS STAGE0 STAGE1 STAGE2 STAGE3 STAGE4 STAGE5 STAGE6 STAGE7 STAGE8 STAGE9 STAGE10 STAGE11 INT 1 4 2 SERIAL READS NOTES THIS ISAN EXAMPLE OF A SENSOR THRESHOLD INTERRUPT FOR A CASE WHERE THE LOW THRESHOLD LEVELS WERE EXCEEDED. FOR EXAMPLE: THE SENSOR CONNECTEDTO STAGE0AND STAGE9 WERE CONTACTEDAND THE LOW THRESHOLD LEVELS WERE EXCEEDED RESULTING IN THE INTERRUPT BEINGASSERTED. THE STAGE6 INTERRUPTWAS NOTASSERTED BECAUSE THE USER DID NOT CONTACT THE SENSOR CONNECTEDTO STAGE6. STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE6,AND STAGE9 (x = 0, 6, 9) STAGEx_LOW_INT_EN (ADDRESS 0x005) = 1 STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0 STAGEx_COMPLETE_EN (ADDRESS 0x007) = 0 STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE1 THROUGH STAGE7, STAGE8, STAGE10,AND STAGE11 (x = 1, 2, 3, 4, 5, 6, 7, 8, 10,11) STAGEx_LOW_INT_EN (ADDRESS 0x005) = 0 STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0 STAGEx_COMPLETE_EN (ADDRESS 0x007) = 0 S1.E RREIAALD RTEHAED SBTAACGKE R0_ELQOUWIR_ELMIMEINT_TISN TF O(ARD SDTRAEGSES0 0AxN00D8 )S RTAEGGIES9T. ETRHIS READBACK OPERATION IS REQUIREDTO CLEAR THE INTERRUPT OUTPUT. 05702-027 2. READ THE STAGE5_LOW_LIMIT_INT (ADDRESS 0x008) REGISTER Figure 40. Example of Configuring the Registers for Sensor Interrupt Setup Rev. B | Page 28 of 70

Data Sheet AD7142 GPIO INT OUTPUT CONTROL The INT output signal can be controlled by the GPIO pin when The GPIO interrupt can be set to trigger on a rising edge, falling the GPIO is configured as an input. The GPIO is configured as edge, high level, or low level at the GPIO input pin. Table 15 an input by setting the GPIO_SETUP bits in the interrupt shows how the settings of the GPIO_INPUT_CONFIG bits in configuration register to 01. See the GPIO section for more the interrupt enable register affect the behavior of INT. information on how to configure the GPIO. Figure 41 to Figure 44 show how the interrupt output is cleared on Enable the GPIO interrupt by setting the GPIO_INT_EN bit in a read from the CDC conversion complete interrupt status register. Register 0x007 to 1, or disable the GPIO interrupt by clearing this bit to 0. The GPIO status bit in the conversion complete interrupt status register reflects the status of the GPIO interrupt. This bit is set to 1 when the GPIO has triggered INT. The bit is cleared on readback from the register, provided the condition that caused the interrupt has gone away. 1 1 SERIAL SERIAL READBACK READBACK GPIO INPUT HIGH WHEN REGISTER IS READ BACK GPIO INPUT HIGH WHEN REGISTER IS READ BACK GPIO INPUT GPIO INPUT INT INT OUTPUT OUTPUT GPIO INPUT LOW WHEN REGISTER IS READ BACK GPIO INPUT LOW WHEN REGISTER IS READ BACK GPIO INPUT GPIO INPUT INT INT OUTPUT OUTPUT N1.O RTEEASD GPIO_STATUS REGISTER TO RESET INT OUTPUT. 05702-028 N1.O RTEEASD GPIO_STATUS REGISTERTO RESET INT OUTPUT. 05702-029 Figure 41. INT Output Controlled by the GPIO Input Example, Figure 42. INT Output Controlled by the GPIO Input Example, GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 00 GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 01 Rev. B | Page 29 of 70

AD7142 Data Sheet 1 1 SERIAL SERIAL READBACK READBACK GPIO INPUT LOW WHEN REGISTER IS READ BACK GPIO INPUT LOW WHEN REGISTER IS READ BACK GPIO GPIO INPUT INPUT INT INT OUTPUT OUTPUT GPIO INPUT HIGH WHEN REGISTER IS READ BACK GPIO INPUT HIGH WHEN REGISTER IS READ BACK GPIO GPIO INPUT INPUT INT INT OUTPUT OUTPUT N1.O RTEEASD GPIO_STATUS REGISTER TO RESET INT OUTPUT. 05702-030 N1.O RTEEASD GPIO_STATUS REGISTER TO RESET INT OUTPUT. 05702-031 Figure 44. INT Output Controlled by the GPIO Input Example, Figure 43. INT Output Controlled by the GPIO Input Example, GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 11 GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 10 Table 15. GPIO Interrupt Behavior GPIO_INPUT_CONFIG GPIO Pin GPIO_STATUS INT INT Behavior 00 = Negative Level Triggered 1 0 1 Not triggered 00 = Negative Level Triggered 0 1 0 Asserted when signal on GPIO pin is low 01 = Positive Edge Triggered 1 1 0 Pulses low at low-to-high GPIO transition 01 = Positive Edge Triggered 0 0 1 Not triggered 10 = Negative Edge Triggered 1 0 1 Pulses low at high-to-low GPIO transition 10 = Negative Edge Triggered 0 1 0 Not triggered 11 = Positive Level Triggered 1 1 0 Asserted when signal on GPIO pin is high 11 = Positive Level Triggered 0 0 1 Not triggered Rev. B | Page 30 of 70

Data Sheet AD7142 OUTPUTS EXCITATION SOURCE GPIO The excitation source onboard the AD7142 is a square wave The AD7142 has one GPIO pin located at Pin 26. It can be source with a frequency of 250 kHz. This excitation source configured as an input or an output. The GPIO_SETUP forms the electric field between the transmitter and receiver in Bits[13:12] in the interrupt enable register determine how the the external capacitance sensor PCB. The source is output from GPIO pin is configured. the AD7142 on two pins, the SRC pin and the SRC pin (outputs Table 16. GPIO_SETUP Bits an inverted version of the source square wave). The SRC signal GPIO_SETUP GPIO Configuration offsets large external sensor capacitances. SRC is not used in the 00 GPIO disabled majority of applications. 01 Input The source output can be disabled from both output pins 10 Output low separately by writing to the control register bits (Address 11 Output high 0x000[13:12]). Setting Bit 12 in this register to 1 disables the When the GPIO is configured as an output, the voltage level on source output on the SRC pin. Setting Bit 13 in this register to 1 the pin is set to either a low level or a high level, as defined by disables the inverted source output on the SRC pin. the GPIO_SETUP bits shown in Table 16. C OUTPUT SHIELD When the GPIO is configured as an input, the To prevent leakage from the external capacitance sensors, the GPIO_INPUT_CONFIG bits in the interrupt enable register sensor traces can be shielded. The AD7142 has a voltage output determine the response of the AD7142 to a signal on the GPIO that can be used as the potential for any shield traces, CSHIELD. pin. The GPIO can be configured as either active high or active The CSHIELD voltage is equal to AVDD/2. low, as well as either edge-triggered or level-triggered, as listed The C potential is derived from the output of the AD7142 in Table 17. SHIELD internal amplifier, and is of equal potential to the CIN input Table 17. GPIO_INPUT_CONFIG Bits lines. Because the shield is at the same potential as the sensor GPIO_INPUT_CONFIG GPIO Configuration traces, no leakage to ground occurs. To eliminate any ringing on 00 Triggered on negative level (active low) the C output, connect a 10 nF capacitor between the SHIELD 01 Triggered on positive edge (active high) C pin and ground. This capacitor is required, whether SHIELD 10 Triggered on negative edge (active low) C is used in the application or not SHIELD . 11 Triggered on positive level (active high) For most applications, C is not used, and a ground plane is SHIELD used instead around the sensors. When GPIO is configured as an input, it triggers the interrupt output on the AD7142. Table 15 lists the interrupt output behavior for each of the GPIO configuration setups. USING THE GPIO TO TURN ON/OFF AN LED The GPIO on the AD7142 can be used to turn on and off LEDs by setting the GPIO as either output high or low. Setting the GPIO output high turns on the LED; setting the GPIO output low turns off the LED. The GPIO pin connects to a transistor that provides the drive current for the LED. Suitable transistors include the KTC3875. KTC3875 VCC OR SIMILAR AD7142 GPIO 05702-061 Figure 45. Controlling LEDs Using the GPIO Rev. B | Page 31 of 70

AD7142 Data Sheet SERIAL INTERFACE The AD7142 is available with an SPI serial interface. The Bits[15:11] of the command word must be set to 11100 to AD7142-1 is available with an I2C-compatible interface. Both successfully begin a bus transaction. parts are the same, with the exception of the serial interface. Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates a SPI INTERFACE write. The AD7142 has a 4-wire serial peripheral interface (SPI). The Bits[9:0] contain the target register address. When reading or SPI has a data input pin (SDI) for inputting data to the device, a writing to more than one register, this address indicates the data output pin (SDO) for reading data back from the device, address of the first register to be written to or read from. and a data clock pin (SCLK) for clocking data into and out of Writing Data the device. A chip select pin (CS) enables or disables the serial Data is written to the AD7142 in 16-bit words. The first word interface. CS is required for correct operation of the SPI written to the device is the command word, with the read/write interface. Data is clocked out of the AD7142 on the negative bit set to 0. The master then supplies the 16-bit input data-word edge of SCLK, and data is clocked into the device on the on the SDI line. The AD7142 clocks the data into the register positive edge of SCLK. addressed in the command word. If there is more than one SPI Command Word word of data to be clocked in, the AD7142 automatically incre- All data transactions on the SPI bus begin with the master ments the address pointer, and clocks the next data-word into taking CS from high to low and sending out the command the next register. word. This indicates to the AD7142 whether the transaction is a The AD7142 continues to clock in data on the SDI line until read or a write, and gives the address of the register from which either the master finishes the write transition by pulling CS to begin the data transfer. The following bit map shows the SPI high, or the address pointer reaches its maximum value. The command word. AD7142 address pointer does not wrap around. When it MSB LSB reaches its maximum value, any data provided by the master on the SDI line is ignored by the AD7142. 15 14 13 12 11 10 9:0 1 1 1 0 0 R/W Register address 16-BIT COMMAND WORD ENABLE WORD R/W REGISTERADDRESS 16-BIT DATA SDI CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW D15 D14 D13 D2 D1 D0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t t t 2 4 5 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 31 32 t1 t3 t8 CS NOTES 1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2.ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR CONTROL WORD AND 16 BITS FOR DATA. 3. 16-BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION: CCCWWW[[[9115:00:]1] = 1= ]0 [= A( RD1/19W1, 0)A0D (8E,N AADB7L, EA DW6O, ARDD5), AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS) 05702-033 Figure 46. Single Register Write SPI Timing Rev. B | Page 32 of 70

Data Sheet AD7142 16-BIT COMMAND WORD ENABLE WORD R/W STARTING REGISTERADDRESS DRAETGAIS FTOERR SATDADRRTEINSGS REDGAITSAT EFRORA DNDERXETSS SDI CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW D15 D14 D1 D0 D15 D14 D1 D0 D15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 31 32 33 34 47 48 49 CS NOTES 1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN). 4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. 5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION: CCCWWW[[[119:050:]1] = 1= ]0 [= A( RD1/19W1, 0)A0D (8E,N AADB7L, EA DW6O, ARDD5), AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS) 05702-034 Figure 47. Sequential Register Write SPI Timing 16-BIT COMMAND WORD ENABLE WORD R/W REGISTERADDRESS SDI CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t t t 2 4 5 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 31 32 t t t 1 3 8 CS t t 6 7 SDO XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14 D13 D2 D1 D0 XXX 16-BIT READBACK DATA NOTES 1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS. 3. THE REGISTER DATA IS READ BACK ON THE SDO PIN. 4. X DENOTES DON’T CARE. 5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT. 6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION: CCCWWW[[[11950:0:]1 ]= 1= ]1 [= A( RD1/19W1, 0)A0D (8E,N AADB7L, EA DW6O, ARDD5), AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS) 05702-035 Figure 48. Single Register Readback SPI Timing Reading Data The AD7142 continues to clock out data on the SDO line A read transaction begins when the master writes the command provided the master continues to supply the clock signal on word to the AD7142 with the read/write bit set to 1. The master SCLK. The read transaction finishes when the master takes then supplies 16 clock pulses per data-word to be read, and the CS high. If the AD7142 address pointer reaches its maximum AD7142 clocks out data from the addressed register on the SDO value, then the AD7142 repeatedly clocks out data from the line. The first data-word is clocked out on the first falling edge addressed register. The address pointer does not wrap around. of SCLK following the command word, as shown in Figure 48. Rev. B | Page 33 of 70

AD7142 Data Sheet 16-BIT COMMAND WORD ENABLE WORD R/W REGISTER ADDRESS SDI CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW X X X X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 31 32 33 34 47 48 49 CS SDO XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14 D1 D0 D15 D14 D1 D0 D15 READBACK DATA FOR READBACK DATA FOR STARTING REGISTER ADDRESS NEXT REGISTER ADDRESS NOTES 1. MULTIPLE REGISTERS CAN BE READ BACK CONTINUOUSLY. 2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE SDO PIN. 4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 5. X DENOTES DON’T CARE. 6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT. 7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION: CCCWWW[[[1190:50]:] 1= 1= ]1 [ =A( RD1/19W1, 0)A0D (8E,N AADB7L, EA DW6O, ARDD5), AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS) 05702-036 Figure 49. Sequential Register Read back SPI Timing I2C COMPATIBLE INTERFACE All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a The AD7142-1 supports the industry standard 2-wire I2C serial 7-bit address (MSB first) plus a R/W bit that determines the interface protocol. The two wires associated with the I2C timing are direction of the data transfer. The peripheral whose address the SCLK and the SDA inputs. The SDA is an I/O pin that allows corresponds to the transmitted address responds by pulling the both register write and register readback operations. The AD7142-1 is always a slave device on the I2C serial interface bus. data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices on the bus now remain idle It has a 7-bit device address, Address 0101 1XX. The lower two when the selected device waits for data to be read from, or bits are set by tying the ADD0 and ADD1 pins high or low. The written to it. If the R/W bit is a 0, the master writes to the slave AD7142-1 responds when the master device sends its device device. If the R/W bit is a 1, the master reads from the slave device. address over the bus. The AD7142-1 cannot initiate data transfers on the bus. Data is sent over the serial bus in a sequence of nine clock pulses, eight bits of data followed by an acknowledge bit from Table 18. AD7142-1 I2C Device Address the slave device. Transitions on the data line must occur during ADD1 ADD0 I2C Address the low period of the clock signal and remain stable during the 0 0 0101 100 high period, since a low-to-high transition when the clock is 0 1 0101 101 high can be interpreted as a stop signal. The number of data 1 0 0101 110 bytes transmitted over the serial bus in a single read or write 1 1 0101 111 operation is limited only by what the master and slave devices Data Transfer can handle. Data is transferred over the I2C serial interface in 8-bit bytes. When all data bytes are read or written, a stop condition is The master initiates a data transfer by establishing a start con- established. A stop condition is defined by a low-to-high dition, defined as a high-to-low transition on the serial data transition on SDA when SCLK remains high. If the AD7142 line, SDA, when the serial clock line, SCLK, remains high. This encounters a stop condition, it returns to its idle condition, and indicates that an address/data stream follows. the address pointer register resets to Address 0x00. Rev. B | Page 34 of 70

Data Sheet AD7142 START AD7142 DEVICEADDRESS REGISTERADDRESS[A15:A8] REGISTERADDRESS[A7:A0] SDA DEV DEV DEV DEV DEV DEV DEV R/W ACK A15 A14 A9 A8 ACK A7 A6 A1 A0 A6 A5 A4 A3 A2 A1 A0 t t 1 3 SCLK 1 2 3 4 5 6 7 8 9 10 11 16 17 18 19 20 25 26 t 2 STOP START REGISTER DATA[D15:D8] REGISTER DATA[D7:D0] t AD7142 DEVICEADDRESS 8 DEV DEV DEV ACK D15 D14 D9 D8 ACK D7 D6 D1 D0 ACK A6 A5 A4 t4 t5 t6 t7 27 28 29 34 35 36 37 38 43 44 45 46 1 2 3 NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE X ARE DON'T CARE BITS. 456... 1RR6EE-GGBIIITSS TTREEERRG ADISDATDTEARR E[ ADSD1S5D [:ARD1E85]S :ASAN[8AD] 1A 5RN:EADG0 ]RI S=ET G[EXIRS, XTDE,A XRT, AAX D,[ DDX7,R :XED,S0 A]S 9A [,AR AE78: ,AA A0L]7W ,A AARY6E,S AA S5LE,W PAAA4Y,R ASA 3TS, EEADP2 A,B ARY1A A,T A EL0DO], W BWY AH ACE KRLO EB WXIT .AARCEK DBOITN.’T CARE BITS. 05702-037 Figure 50. Example of I2C Timing for Single Register Write Operation Writing Data over the I2C Bus Any data written to the AD7142-1 after the address pointer has The process for writing to the AD7142-1 over the I2C bus is reached its maximum value is discarded. shown in Figure 50 and Figure 52. The device address is sent All registers on the AD7142-1 are 16-bit. Two consecutive 8-bit over the bus followed by the R/W bit set to 0. This is followed data bytes are combined and written to the 16-bit registers. To by two bytes of data that contain the 10-bit address of the avoid errors, all writes to the device must contain an even internal data register to be written. The following bit map shows number of data bytes. the upper register address bytes. Note that Bit 7 to Bit 2 in the To finish the transaction, the master generates a stop condition upper address byte are don’t care bits. The address is contained on SDO, or generates a repeat start condition if the master is to in the 10 LSBs of the register address bytes. maintain control of the bus. MSB LSB Reading Data over the I2C Bus 7 6 5 4 3 2 1 0 To read from the AD7142-1, the address pointer register must X X X X X X Register Register first be set to the address of the required internal register. The Address Address Bit 9 Bit 8 master performs a write transaction, and writes to the AD7142-1 to set the address pointer. The master then outputs a repeat start The following bit map shows the lower register address bytes. condition to keep control of the bus, or if this is not possible, ends MSB LSB the write transaction with a stop condition. A read transaction is 7 6 5 4 3 2 1 0 initiated, with the R/W bit set to 1. Reg. Reg. Reg. Reg. Reg. Reg. Reg. Reg. The AD7142-1 supplies the upper eight bits of data from the Addr. Addr. Addr. Addr. Addr. Addr. Addr. Addr. addressed register in the first readback byte, followed by the Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 lower eight bits in the next byte. This is shown in Figure 51 and The third data byte contains the 8 MSBs of the data to be Figure 52. written to the internal register. The fourth data byte contains Because the address pointer automatically increases after each the 8 LSBs of data to be written to the internal register. read, the AD7142-1 continues to output readback data until the The AD7142-1 address pointer register automatically increments master puts a no acknowledge and stop condition on the bus. If after each write. This allows the master to sequentially write to all the address pointer reaches its maximum value, and the master registers on the AD7142-1 in the same write transaction. However, continues to read from the part, the AD7142-1 repeatedly sends the address pointer register does not wrap around after the last data from the last register addressed. address. Rev. B | Page 35 of 70

AD7142 Data Sheet START AD7142-1 DEVICEADDRESS REGISTERADDRESS[A15:A8] REGISTERADDRESS[A7:A0] SDA DEV DEV DEV DEV DEV DEV DEV R/W ACK A15 A14 A9 A8 ACK A7 A6 A1 A0 ACK A6 A5 A4 A3 A2 A1 A0 t1 t3 SCLK 1 2 3 4 5 6 7 8 9 10 11 16 17 18 19 20 25 26 27 t2 P SR AD7142-1 DEVICEADDRESS REGISTER DATA[D7:D0] t8 AD7142 DEVICEADDRESS DAE6V DAE5V DAE1V DAE0V R/W ACK D7 D6 D1 D0 ACK DAE6V DAE5V DAE4V REPEATED USSTIANRGT t4 t5 t6 t7 28 29 30 34 35 36 37 38 39 44 45 46 1 2 3 P S AD7142-1 DEVICEADDRESS REGISTER DATA[D7:D0] P DEV DEV DEV DEV A6 A5 A1 A0 R/W ACK D7 D6 D1 D0 ACK WSREITPAE RTARTAEN RSEAACDTIAONNDS t4 t5 28 29 30 34 35 36 37 38 39 44 45 46 NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA. 4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB X's ARE DON'T CARE BITS. 5. 16-BIT REGISTER ADDRESS[A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE THE UPPER LSB X’s ARE DON’T CARE BITS. 678... TRRHEEEGG IIRSS/TTWEE RRB IDATA DISTD ARS EE[DST1S T5 [O:AD 1A85]1 :A ATN8OD] AI NRNDEDIGC RIASETTGEEI RSA T DREAERTA AAD DB[DDA7RC:EDKS0 O]S A P[ARE7ER: AAAT0LI]WO ANAR.YES A SLEWPAAYRSA TSEEDP ABRYA AT ELDO WBY A AC KL OBWIT .ACK BITS. 05702-038 Figure 51. Example of I2C Timing for Single Register Readback Operation WRITE 6-BIT DEVICE K REGISTERADDR K REGISTERADDR K WRITE DATA K WRITE DATA WRITE DATA K WRITE DATA K S ADDRESS W AC [15:8] AC [7:0] ACHIGH BYTE [15:8] ACLOW BYTE [7:0] HIGH BYTE [15:8] AC LOW BYTE [7:0] ACP READ (USING REPEATED START) S 6-ABDITD DREEVSISCE W ACK REGHIIGSTHE BRYATDEDR ACK REGLOISWTE BRYATDEDR ACKSR6-ABDITD DREEVSISCERACKHIGRHE ABDY TDEA [T1A5:8] ACKLORWEA BDY TDEA T[7A:0] HIGRHE ABDY TDEA [T1A5:8] ACK LORWEA BDY TDEA T[7A:0] ACK P READ (WRITE TRANSACTION SETS UP REGISTERADDRESS) S 6-ABDITD DREEVSISCE W ACK REGHIIGSTHE BRYATDEDR ACK REGLOISWTE BRYATDEDR ACK P S 6-ABDITD DREEVSISCERACKHIGRHE ABDY TDEA [T1A5:8] ACKLORWEA BDY TDEA T[7A:0] HIGRHE ABDY TDEA [T1A5:8] ACK LORWEA BDY TDEA T[7A:0] ACK P OOUUTTPPUUTT FFRROOMM AMDA7S1T4E2R SPS R== =SS TTRAOERPPT EB ABITTITED START BIT AACCKK == ANCOKANCOKWNLOEWDLGEED BGIET BIT 05702-039 Figure 52. Example of Sequential I2C Write and Readback Operation V INPUT This allows the AD7142 to be connected directly to processors DRIVE whose supply voltage is less than the minimum operating The supply voltage to all pins associated with both the I2C and voltage of the AD7142 without the need for external level- SPI serial interfaces (SDO, SDI, SCLK, SDA, and CS) is separate shifters. The V pin can be connected to voltage supplies as from the main V supplies and is connected to the V pin. DRIVE CC DRIVE low as 1.65 V and as high as DV . CC Rev. B | Page 36 of 70

Data Sheet AD7142 PCB DESIGN GUIDELINES CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS Table 19. Parameter Symbol Min Typ Max Unit Distance from Edge of Any Sensor to Edge of Grounded Metal Object D 0.1 mm 1 Distance Between Sensor Edges1 D = D = D 0 mm 2 3 4 Distance Between Bottom of Sensor Board and Controller Board or Grounded D 1.0 mm 5 Metal Casing2 1 The distance is dependent on the application and the positioning of the switches relative to each other and with respect to the user’s finger positioning and handling. Adjacent sensors, with 0 minimum space between them, are implemented differentially. 2 The 1.0 mm specification is meant to prevent direct sensor board contact with any conductive material. This specification does not guarantee no EMI coupling from the controller board to the sensors. Address potential EMI coupling issues by placing a grounded metal shield between the capacitive sensor board and the main controller board as shown in Figure 55. CAPACITIVE SENSOR BOARD METAL OBJECT D5 GROUNDED METAL SHIELD CAPACITIVE SENSOR PRINTED CIRCUIT S8W-WITACYH CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING 05702-046 Figure 55. Capacitive Sensor Board with Grounded Shield D4 CHIP SCALE PACKAGES SLIDER The lands on the chip scale package (CP-32-3) are rectangular. The printed circuit board pad for these must be 0.1 mm longer than the package land length, and 0.05 mm wider than the BUTTONS D3 package land width. Center the land on the pad to maximize the solder joint size. D2 The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board must be at least as D1 large as this exposed pad. To avoid shorting, provide a clearance 05702-045 oedf gaet sl eoafs tth 0e.2 l5an md mpa btteetrwne oenn tthhee tphreinrmtedal cpiracdu aitn bdo tahred i. n ner Figure 53. Capacitive Sensor Board Mechanicals Top View Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are CAPACITIVE SENSOR BOARD used, they must be incorporated in the thermal pad at a 1.2 mm D5 pitch grid. The via diameter must be between 0.3 mm and CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING 05702-047 0p.l3u3g mthme v, iaan. d the via barrel must be plated with 1 oz. copper to Figure 54. Capacitive Sensor Board Mechanicals Side View Connect the printed circuit board thermal pad to GND. Rev. B | Page 37 of 70

AD7142 Data Sheet POWER-UP SEQUENCE When the AD7142 is powered up, the following sequence is Address 0x003 = 0x14C8 recommended when initially developing the AD7142 and μP Address 0x004 = 0x0832 serial interface: Address 0x005 = 0x0000 Address 0x006 = 0x0000 1. Turn on the power supplies to the AD7142. Address 0x007 = 0x0001 (The AD7142 interrupt is asserted 2. Write to the Bank 2 registers at Address 0x080 through approximately every 36 ms.) Address 0x0DF. These registers are contiguous so a 6. Write to the Bank 1 register, Address 0x001 = 0x0FFF. sequential register write sequence can be applied. 7. Read back the corresponding interrupt status register at 3. Note: The Bank 2 register values are unique for each Address 0x008, Address 0x009, or Address 0x00A. This is application. Register values are provided by Analog determined by the interrupt output configuration as Devices after the sensor board has been developed. explained in the Interrupt Output section. 4. Write to the Bank 1 registers at Address 0x000 through 8. Note: The specific registers required to be read back Address 0x007 as follows. These registers are contiguous so depend on each application. Analog Devices provides this a sequential register write sequence can be applied (see information after the sensor board has been developed. Figure 47 and Figure 52). 9. Repeat Step 5 every time INT is asserted. 5. Caution: At this time, Address 0x001 must remain set to default value 0x0000 during this contiguous write operation. Register values: Address 0x000 = 0x00B2 Address 0x001 = 0x0000 Address 0x002 = 0x3230 CSTOANGVEERSION CONVERSION STAGES DISABLED 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 9 10 11 0 1 2 9 10 11 0 1 FIRST CONVERSION SEQUENCE S E C O SNEDQ CUOENNVCEERSION T H I R D S ECQOUNEVNECRESION 05702-040 Figure 56. Recommended Start-Up Sequence Rev. B | Page 38 of 70

Data Sheet AD7142 TYPICAL APPLICATION CIRCUITS VDRIVE AVCC,DVCC 2.2kΩ 32 31 30 29 28 27 26 25 HOST BUTTON BUTTON CIN2 CIN1 CIN0 VREF– VREF+ TEST GPIO ITN INT WSITPHI T 1 CIN3 CS 24 SS INTERFACE O CONNECE AROUNDGROUND 23 CCIINN45 SCSLDKI 2232 SMCOKSI DED TPLANS TO SCROLL WHEEL 4 CIN6 SDO 21 MISO ENCOMMLOODED SENSOR BUTTON BUTTON 5 CIN7 AD7142 VDRIVE 20 VHOST REF 6 CIN8 DGND2 19 1.8V SENSORPCB 7 CIN9 DGND1 18 D 8 CIN10CIN11 CIN12 CIN13 CSHIEL AVCC AGND SRC DSRCVCC 17 9 10 11 12 13 14 15 16 AVCC,DVCC2.7V TO3.6V 0.1µF 1µF TO 10µF 10nF (OPTIONAL) 05702-041 Figure 57. Typical Application Circuit with SPI Interface VDRIVE VDRIVE AVCC,DVCC 2.2kΩ VDRIVE 2.2kΩ 2.2kΩ 32 31 30 29 28 27 26 25 HOST SLIDER 1CIN3CIN2 CIN1 CIN0 VREF– VREF+ TEST GPIO ADINTD1 24 INT INTERFWAIICT2HCE BUTTON CTD 2CIN4 SCLK 23 SCK O CONNEE AROUNGROUND BUTTON 34CCIINN56 ADSDDA0 2221 SDO ENDED TED PLANORS TO BUTTON 5CIN7 AD7142-1 VDRIVE 20 MMODNS 6CIN8 DGND2 19 COLOSE EF 7CIN9 DGND1 18 R 8CIN10 D CIN11 CIN12 CIN13 CSHIEL AVCC AGND SRC DSRCVCC 17 9 10 11 12 13 14 15 16 AVCC,DVCC2.7V TO3.6V 0.1µF 1µF TO 10µF (OPTIONAL) 10nF 05702-042 Figure 58. Typical Application Circuit with I2C Interface Rev. B | Page 39 of 70

AD7142 Data Sheet REGISTER MAP The AD7142 address space is divided into three different register Bank 3 registers contain the results of each conversion stage. banks, referred to as Bank 1, Bank 2, and Bank 3. Figure 59 These registers automatically update at the end of each conversion shows the division of these three banks. sequence. Although these registers are primarily used by the AD7142 internal data processing, they are accessible by the host Bank 1 contains control registers, CDC conversion control processor for additional external data processing, if desired. registers, interrupt enable registers, interrupt status registers, CDC 16-bit conversion data registers, device ID registers, and Default values are undefined for Bank 2 registers and Bank 3 proximity status registers. registers until after power-up and configuration of the Bank 2 registers. Bank 2 contains the configuration registers used for uniquely configuring the CIN inputs for each conversion stage. Initialize the Bank 2 configuration registers immediately after power-up to obtain valid CDC conversion result data. REGISTER BANK 1 REGISTER BANK 2 REGISTER BANK 3 ADDR 0x000 SET UP CONTROL ADDR 0x080 STAGE0 CONFIGURATION ADDR 0xE0 STAGE0 RESULTS (1 REGISTER) (8 REGISTERS) (36 REGISTERS) ADDR 0x001 ADDR 0x088 STAGE1 CONFIGURATION ADDR 0x104 STAGE1 RESULTS CALIBRATION AND SET UP ADDR 0x090 (8 REGISTERS) ADDR 0x128 (36 REGISTERS) (4 REGISTERS) STAGE2 CONFIGURATION STAGE2 RESULTS (8 REGISTERS) (36 REGISTERS) ADDR 0x005 ADDR 0x098 ADDR 0x14C STAGE3 CONFIGURATION STAGE3 RESULTS INTERRUPT ENABLE (8 REGISTERS) (36 REGISTERS) (3 REGISTERS) ADDR 0x0A0 ADDR 0x170 ADDR 0x008 STAGE4 CONFIGURATION STAGE4 RESULTS INTERRUPT STATUS ADDR 0x0A8 (8 REGISTERS) ADDR 0x194 (36 REGISTERS) (3 REGISTERS) STAGE5 CONFIGURATION STAGE5 RESULTS ADDR 0x00B (8 REGISTERS) (36 REGISTERS) ADDR 0x0B0 ADDR 0x1B8 CDC 16-BIT CONVERSION DATA STAGE6 CONFIGURATION STAGE6 RESULTS (12 REGISTERS) (8 REGISTERS) (36 REGISTERS) ADDR 0x017 ADDR 0x0B8 ADDR 0x1DC DEVICE ID REGISTER STAGE7 CONFIGURATION STAGE7 RESULTS ADDR 0x018 (8 REGISTERS) (36 REGISTERS) INVALID DO NOT ACCESS ADDR 0x0C0 STAGE8 CONFIGURATION ADDR 0x200 STAGE8 RESULTS ADDR 0x042 (8 REGISTERS) (36 REGISTERS) PROXIMITY STATUS REGISTER ADDR 0x0C8 ADDR 0x224 STAGE9 CONFIGURATION STAGE9 RESULTS ADDR 0x043 (8 REGISTERS) (36 REGISTERS) ADDR 0x0D0 ADDR 0x248 STAGE10 CONFIGURATION STAGE10 RESULTS INVALID DO NOT ACCESS (8 REGISTERS) (36 REGISTERS) ADDR 0x7F0 ADDR 0x0D8 STAGE(81 1R ECGOINSFTIEGRUSR)ATION ADDR 026C ST(3A6G REE1G1 IRSETESRUSLT)S 05702-043 Figure 59. Layout of Bank 1 Registers, Bank 2 Registers, and Bank 3 Registers Rev. B | Page 40 of 70

Data Sheet AD7142 DETAILED REGISTER DESCRIPTIONS BANK 1 REGISTERS All addresses and default values are expressed in hexadecimal. Table 20. PWR_CONTROL Register Address Data Bit Default Value Type Name Description 0x000 [1:0] 0 R/W POWER_MODE Operating modes 00 = full power mode (normal operation, CDC conversions approximately every 36 ms) 01 = full shutdown mode (no CDC conversions) 10 = low power mode (automatic wake up operation) 11 = full shutdown mode (no CDC conversions) [3:2] 0 LP_CONV_DELAY Low power mode conversion delay 00 = 200 ms 01 = 400 ms 10 = 600 ms 11 = 800 ms [7:4] 0 SEQUENCE_STAGE_NUM Number of stages in sequence (N + 1) 0000 = 1 conversion stage in sequence 0001 = 2 conversion stages in sequence Maximum value = 1011 = 12 conversion stages per sequence [9:8] 0 DECIMATION ADC decimation factor 00 = decimate by 256 01 = decimate by 128 10 = do not use this setting 11 = do not use this setting 10 0 SW_RESET Software reset control (self-clearing) 1 = resets all registers to default values 11 0 INT_POL Interrupt polarity control 0 = active low 1 = active high 12 0 EXCITATION_SOURCE Excitation source control for Pin 15 0 = enable output 1 = disable output 13 0 SRC Excitation source control for Pin 16 0 = enable output 1 = disable output [15:14] 0 CDC_BIAS CDC bias current control 00 = normal operation 01 = normal operation + 20% 10 = normal operation + 35% 11 = normal operation + 50% Rev. B | Page 41 of 70

AD7142 Data Sheet Table 21. STAGE_CAL_EN Register Address Data Bit Default Value Type Name Description 0x001 0 0 R/W STAGE0_CAL_EN STAGE0 calibration enable 0 = disable 1 = enable 1 0 STAGE1_CAL_EN STAGE1 calibration enable 0 = disable 1 = enable 2 0 STAGE2_CAL_EN STAGE2 calibration enable 0 = disable 1 = enable 3 0 STAGE3_CAL_EN STAGE3 calibration enable 0 = disable 1 = enable 4 0 STAGE4_CAL_EN STAGE4 calibration enable 0 = disable 1 = enable 5 0 STAGE5_CAL_EN STAGE5 calibration enable 0 = disable 1 = enable 6 0 STAGE6_CAL_EN STAGE6 calibration enable 0 = disable 1 = enable 7 0 STAGE7_CAL_EN STAGE7 calibration enable 0 = disable 1 = enable 8 0 STAGE8_CAL_EN STAGE8 calibration enable 0 = disable 1 = enable 9 0 STAGE9_CAL_EN STAGE9 calibration enable 0 = disable 1 = enable 10 0 STAGE10_CAL_EN STAGE10 calibration enable 0 = disable 1 = enable 11 0 STAGE11_CAL_EN STAGE11 calibration enable 0 = disable 1 = enable [13:12] 0 AVG_FP_SKIP Full power mode skip control 00 = skip 3 samples 01 = skip 7 samples 10 = skip 15 samples 11 = skip 31 samples [15:14] 0 AVG_LP_SKIP Low power mode skip control 00 = use all samples 01 = skip 1 sample 10 = skip 2 samples 11 = skip 3 samples Rev. B | Page 42 of 70

Data Sheet AD7142 Table 22. AMB_COMP_CTRL0 Register Address Data Bit Default Value Type Name Description 0x002 [3:0] 0 R/W FF_SKIP_CNT Fast filter skip control (N + 1) 0000 = no sequence of results are skipped 0001 = one sequence of results is skipped for every one allowed into fast FIFO 0010 = two sequences of results are skipped for every one allowed into fast FIFO 1011 = maximum value = 12 sequences of results are skipped for every one allowed into Fast FIFO [7:4] F FP_PROXIMITY_CNT Calibration disable period in full power mode = FP_PROXIMITY_CNT × 16 × Time taken for one conversion sequence in full power mode [11:8] F LP_PROXIMITY_CNT Calibration disable period in low power mode = LP_PROXIMITY_CNT × 4 × Time taken for one conversion sequence in low power mode [13:12] 0 PWR_DOWN_TIMEOUT Full power to low power mode timeout control 00 = 1.25 × (FP_PROXIMITY_CNT) 01 = 1.50 × (FP_PROXIMITY_CNT) 10 = 1.75 × (FP_PROXIMITY_CNT) 11 = 2.00 × (FP_PROXIMITY_CNT) 14 0 FORCED_CAL Forced calibration control 0 = normal operation 1 = forces all conversion stages to recalibrate 15 0 CONV_RESET Conversion reset control (self-clearing) 0 = normal operation 1 = resets the conversion sequence back to STAGE0 Table 23. AMB_COMP_CTRL1 Register Default Address Data Bit Value Type Name Description 0x003 [7:0] 64 R/W PROXIMITY_RECAL_LVL Proximity recalibration level [13:8] 1 PROXIMITY_DETECTION_RATE Proximity detection rate [15:14] 0 SLOW_FILTER_UPDATE_LVL Slow filter update level Table 24. AMB_COMP_CTRL2 Register Default Address Data Bit Value Type Name Description 0x004 [9:0] 3FF R/W FP_PROXIMITY_RECAL Full power mode proximity recalibration time control [15:10] 3F LP_PROXIMITY_RECAL Low power mode proximity recalibration time control Rev. B | Page 43 of 70

AD7142 Data Sheet Table 25. STAGE_LOW_INT_EN Register Address Data Bit Default Value Type Name Description 0x005 0 0 R/W STAGE0_LOW_INT_EN STAGE0 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low threshold is exceeded 1 0 STAGE1_LOW_INT_EN STAGE1 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE1 low threshold is exceeded 2 0 STAGE2_LOW_INT_EN STAGE2 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE2 low threshold is exceeded 3 0 STAGE3_LOW_INT_EN STAGE3 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE3 low threshold is exceeded 4 0 STAGE4_LOW_INT_EN STAGE4 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE4 low threshold is exceeded 5 0 STAGE5_LOW_INT_EN STAGE5 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE5 low threshold is exceeded 6 0 STAGE6_LOW_INT_EN STAGE6 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE6 low threshold is exceeded 7 0 STAGE7_LOW_INT_EN STAGE7 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE7 low threshold is exceeded 8 0 STAGE8_LOW_INT_EN STAGE8 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE8 low threshold is exceeded 9 0 STAGE9_LOW_INT_EN STAGE9 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE9 low threshold is exceeded 10 0 STAGE10_LOW_INT_EN STAGE10 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE10 low threshold is exceeded 11 0 STAGE11_LOW_INT_EN STAGE11 low interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE11 low threshold is exceeded [13:12] 0 GPIO_SETUP GPIO setup 00 = disable GPIO pin 01 = configure GPIO as an input 10 = configure GPIO as an active low output 11 = configure GPIO as an active high output [15:14] 0 GPIO_INPUT_CONFIG GPIO input configuration 00 = triggered on negative level 01 = triggered on positive edge 10 = triggered on negative edge 11 = triggered on positive level Rev. B | Page 44 of 70

Data Sheet AD7142 Table 26. STAGE_HIGH_INT_EN Register Address Data Bit Default Value Type Name Description 0x006 0 0 R/W STAGE0_HIGH_INT_EN STAGE0 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high threshold is exceeded 1 0 STAGE1_HIGH_INT_EN STAGE1 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE1 high threshold is exceeded 2 0 STAGE2_HIGH_INT_EN STAGE2 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE2 high threshold is exceeded 3 0 STAGE3_HIGH_INT_EN STAGE3 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE3 high threshold is exceeded 4 0 STAGE4_HIGH_INT_EN STAGE4 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE4 high threshold is exceeded 5 0 STAGE5_HIGH_INT_EN STAGE5 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE5 high threshold is exceeded 6 0 STAGE6_HIGH_INT_EN STAGE6 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE6 high threshold is exceeded 7 0 STAGE7_HIGH_INT_EN STAGE7 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE7 high threshold is exceeded 8 0 STAGE8_HIGH_INT_EN STAGE8 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE8 high threshold is exceeded 9 0 STAGE9_HIGH_INT_EN STAGE9 sensor high interrupt enable l 0 = interrupt source disabled 1 = INT asserted if STAGE9 high threshold is exceeded 10 0 STAGE10_HIGH_INT_EN STAGE10 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE10 high threshold is exceeded 11 0 STAGE11_HIGH_INT_EN STAGE11 high interrupt enable 0 = interrupt source disabled 1 = INT asserted if STAGE11 high threshold is exceeded [15:12] Unused Set unused register bits = 0 Rev. B | Page 45 of 70

AD7142 Data Sheet Table 27. STAGE_COMPLETE_INT_EN Register Address Data Bit Default Value Type Name Description 0x007 0 0 R/W STAGE0_COMPLETE_EN STAGE0 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE0 conversion 1 0 STAGE1_COMPLETE_EN STAGE1 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE1 conversion 2 0 STAGE2_COMPLETE_EN STAGE2 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE2 conversion 3 0 STAGE3_COMPLETE_EN STAGE3 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE3 conversion 4 0 STAGE4_COMPLETE_EN STAGE4 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE4 conversion 5 0 STAGE5_COMPLETE_EN STAGE5 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE5 conversion 6 0 STAGE6_COMPLETE_EN STAGE6 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE6 conversion 7 0 STAGE7_COMPLETE_EN STAGE7 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE7 conversion 8 0 STAGE8_COMPLETE_EN STAGE8 conversion complete interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE8 conversion 9 0 STAGE9_COMPLETE_EN STAGE9 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE9 conversion 10 0 STAGE10_COMPLETE_EN STAGE10 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE10 conversion 11 0 STAGE11_COMPLETE_EN STAGE11 conversion interrupt control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE11 conversion 12 0 GPIO_INT_EN Interrupt control when GPIO input pin changes level 0 = disabled 1 = enabled [15:13] Unused Set unused register bits = 0 Rev. B | Page 46 of 70

Data Sheet AD7142 Table 28. STAGE_LOW_LIMIT_INT Register1 Address Data Bit Default Value Type Name Description 0x008 0 0 R STAGE0_LOW_LIMIT_INT STAGE0 CDC conversion low limit interrupt result 1 = indicates STAGE0_LOW_THRESHOLD value was exceeded 1 0 STAGE1_LOW_LIMIT_INT STAGE1 CDC conversion low limit interrupt result 1 = indicates STAGE1_LOW_THRESHOLD value was exceeded 2 0 STAGE2_LOW_LIMIT_INT STAGE2 CDC conversion low limit interrupt result 1 = indicates STAGE2_LOW_THRESHOLD value was exceeded 3 0 STAGE3_LOW_LIMIT_INT STAGE3 CDC conversion low limit interrupt result 1 = indicates STAGE3_LOW_THRESHOLD value was exceeded 4 0 STAGE4_LOW_LIMIT_INT STAGE4 CDC conversion low limit interrupt result 1 = indicates STAGE4_LOW_THRESHOLD value was exceeded 5 0 STAGE5_LOW_LIMIT_INT STAGE5 CDC conversion low limit interrupt result 1 = indicates STAGE5_LOW_THRESHOLD value was exceeded 6 0 STAGE6_LOW_LIMIT_INT STAGE6 CDC conversion low limit interrupt result 1 = indicates STAGE6_LOW_THRESHOLD value was exceeded 7 0 STAGE7_LOW_LIMIT_INT STAGE7 CDC conversion low limit interrupt result 1 = indicates STAGE7_LOW_THRESHOLD value was exceeded 8 0 STAGE8_LOW_LIMIT_INT STAGE8 CDC conversion low limit interrupt result 1 = indicates STAGE8_LOW_THRESHOLD value was exceeded 9 0 STAGE9_LOW_LIMIT_INT STAGE9 CDC conversion low limit interrupt result 1 = indicates STAGE9_LOW_THRESHOLD value was exceeded 10 0 STAGE10_LOW_LIMIT_INT STAGE10 CDC Conversion Low Limit Interrupt result 1 = indicates STAGE10_LOW_THRESHOLD value was exceeded 11 0 STAGE11_LOW_LIMIT_INT STAGE11 CDC conversion low limit interrupt result 1 = indicates STAGE11_LOW_THRESHOLD value was exceeded [15:12] Unused Set unused register bits = 0 1 Registers self-clear to 0 after readback, provided that the limits are not exceeded. Rev. B | Page 47 of 70

AD7142 Data Sheet Table 29. STAGE_HIGH_LIMIT_INT Register1 Address Data Bit Default Value Type Name Description 0x009 0 0 R STAGE0_HIGH_LIMIT_INT STAGE0 CDC conversion high limit interrupt result 1 = indicates STAGE0_HIGH_THRESHOLD value was exceeded 1 0 STAGE1_HIGH_LIMIT_INT STAGE1 CDC conversion high limit interrupt result 1 = indicates STAGE1_HIGH_THRESHOLD value was exceeded 2 0 STAGE2_HIGH_LIMIT_INT Stage2 CDC conversion high limit interrupt result 1 = indicates STAGE2_HIGH_THRESHOLD value was exceeded 3 0 STAGE3_HIGH_LIMIT_INT STAGE3 CDC conversion high limit interrupt result 1 = indicates STAGE3_HIGH_THRESHOLD value was exceeded 4 0 STAGE4_HIGH_LIMIT_INT STAGE4 CDC conversion high limit interrupt result 1 = indicates STAGE4_HIGH_THRESHOLD value was exceeded 5 0 STAGE5_HIGH_LIMIT_INT STAGE5 CDC conversion high limit interrupt result 1 = indicates STAGE5_HIGH_THRESHOLD value was exceeded 6 0 STAGE6_HIGH_LIMIT_INT STAGE6 CDC conversion high limit interrupt result 1 = indicates STAGE6_HIGH_THRESHOLD value was exceeded 7 0 STAGE7_HIGH_LIMIT_INT STAGE7 CDC conversion high limit interrupt result 1 = indicates STAGE7_HIGH_THRESHOLD value was exceeded 8 0 STAGE8_HIGH_LIMIT_INT STAGE8 CDC conversion high limit interrupt result 1 = indicates STAGE8_HIGH_THRESHOLD value was exceeded 9 0 STAGE9_HIGH_LIMIT_INT STAGE9 CDC conversion high limit interrupt result 1 = indicates STAGE9_HIGH_THRESHOLD value was exceeded 10 0 STAGE10_HIGH_LIMIT_INT STAGE10 CDC conversion high limit interrupt result 1 = indicates STAGE10_HIGH_THRESHOLD value was exceeded 11 0 STAGE11_HIGH_LIMIT_INT STAGE11 CDC conversion high limit interrupt result 1 = indicates STAGE11_HIGH_THRESHOLD value was exceeded [15:12] Unused Set unused register bits = 0 1 Registers self-clear to 0 after readback, provided that the limits are not exceeded. Rev. B | Page 48 of 70

Data Sheet AD7142 Table 30. STAGE_COMPLETE_LIMIT_INT Register1 Default Address Data Bit Value Type Name Description 0x00A 0 0 R STAGE0_COMPLETE_STATUS_INT STAGE0 conversion complete register interrupt status 1 = indicates STAGE0 conversion completed 1 0 STAGE1_COMPLETE_STATUS_INT STAGE1 conversion complete register interrupt status 1 = indicates STAGE1 conversion completed 2 0 STAGE2_COMPLETE_STATUS_INT STAGE2 conversion complete register interrupt status 1 = indicates STAGE2 conversion completed 3 0 STAGE3_COMPLETE_STATUS_INT STAGE3 conversion complete register interrupt status 1 = indicates STAGE3 conversion completed 4 0 STAGE4_COMPLETE_STATUS_INT STAGE4 conversion complete register interrupt status 1 = indicates STAGE4 conversion completed 5 0 STAGE5_COMPLETE_STATUS_INT STAGE5 conversion complete register interrupt status 1 = indicates STAGE5 conversion completed 6 0 STAGE6_COMPLETE_STATUS_INT STAGE6 conversion complete register interrupt status 1 = indicates STAGE6 conversion completed 7 0 STAGE7_COMPLETE_STATUS_INT STAGE7 conversion complete register interrupt status 1 = indicates STAGE7 conversion completed 8 0 STAGE8_COMPLETE_STATUS_INT STAGE8 conversion complete register interrupt status 1 = indicates STAGE8 conversion completed 9 0 STAGE9_COMPLETE_STATUS_INT STAGE9 conversion complete register interrupt status 1 = indicates STAGE9 conversion completed 10 0 STAGE10_COMPLETE_STATUS_INT STAGE10 conversion complete register interrupt status 1 = indicates STAGE10 conversion completed 11 0 STAGE11_COMPLETE_STATUS_INT STAGE11 conversion complete register interrupt status 1 = indicates STAGE11 conversion completed 12 0 GPIO_STATUS GPIO input pin status 1 = indicates level on GPIO pin has changed [15:13] Unused Set unused register bits = 0 1 Registers self-clear to 0 after readback, provided that the limits are not exceeded. Table 31. CDC 16-Bit Conversion Data Registers Default Address Data Bit Value Type Name Description 0x00B [15:0] 0 R ADC_RESULT_S0 STAGE0 CDC 16-bit conversion data 0x00C [15:0] 0 R ADC_RESULT_S1 STAGE1 CDC 16-bit conversion data 0x00D [15:0] 0 R ADC_RESULT_S2 STAGE2 CDC 16-bit conversion data 0x00E [15:0] 0 R ADC_RESULT_S3 STAGE3 CDC 16-bit conversion data 0x00F [15:0] 0 R ADC_RESULT_S4 STAGE4 CDC 16-bit conversion data 0x010 [15:0] 0 R ADC_RESULT_S5 STAGE5 CDC 16-bit conversion data 0x011 [15:0] 0 R ADC_RESULT_S6 STAGE6 CDC 16-bit conversion data 0x012 [15:0] 0 R ADC_RESULT_S7 STAGE7 CDC 16-bit conversion data 0x013 [15:0] 0 R ADC_RESULT_S8 STAGE8 CDC 16-bit conversion data 0x014 [15:0] 0 R ADC_RESULT_S9 STAGE9 CDC 16-bit conversion data 0x015 [15:0] 0 R ADC_RESULT_S10 STAGE10 CDC 16-bit conversion data 0x016 [15:0] 0 R ADC_RESULT_S11 STAGE11 CDC 16-bit conversion data Rev. B | Page 49 of 70

AD7142 Data Sheet Table 32. Device ID Register Default Address Data Bit Value Type Name Description 0x017 [3:0] 2 R REVISION_CODE AD7142 revision code [15:4] E62 DEVID AD7142 device ID = 1110 0110 0010 Table 33. Proximity Status Register Default Address Data Bit Value Type Name Description 0x042 0 0 R STAGE0_PROXIMITY_STATUS STAGE0 proximity status register 1 = indicates proximity has been detected on STAGE0 1 0 R STAGE1_PROXIMITY_STATUS STAGE1 proximity status register 1 = indicates proximity has been detected on STAGE1 2 0 R STAGE2_PROXIMITY_STATUS STAGE2 proximity status register 1 = indicates proximity has been detected on STAGE2 3 0 R STAGE3_PROXIMITY_STATUS STAGE3 proximity status register 1 = indicates proximity has been detected on STAGE3 4 0 R STAGE4_PROXIMITY_STATUS STAGE4 proximity status register 1 = indicates proximity has been detected on STAGE4 5 0 R STAGE5_PROXIMITY_STATUS STAGE5 proximity status register 1 = indicates proximity has been detected on STAGE5 6 0 R STAGE6_PROXIMITY_STATUS STAGE6 proximity status register 1 = indicates proximity has been detected on STAGE6 7 0 R STAGE7_PROXIMITY_STATUS STAGE7 proximity status register 1 = indicates proximity has been detected on STAGE7 8 0 R STAGE8_PROXIMITY_STATUS STAGE8 proximity status register 1 = indicates proximity has been detected on STAGE8 9 0 R STAGE9_PROXIMITY_STATUS STAGE9 proximity status register 1 = indicates proximity has been detected on STAGE9 10 0 R STAGE10_PROXIMITY_STATUS STAGE10 proximity status register 1 = indicates proximity has been detected on STAGE10 11 0 R STAGE11_PROXIMITY_STATUS STAGE11 proximity status register 1 = indicates proximity has been detected on STAGE11 [15:0] Unused Set unused register bits = 0 Rev. B | Page 50 of 70

Data Sheet AD7142 BANK 2 REGISTERS All address values are expressed in hexadecimal. Table 34. STAGE0 Configuration Registers Default Address Data Bit Value Type Name Description 0x080 [15:0] X R/W STAGE0_CONNECTION[6:0] STAGE0 CIN(6:0) connection setup (see Table 46) 0x081 [15:0] X R/W STAGE0_CONNECTION[13:7] STAGE0 CIN(13:7) connection setup (see Table 47) 0x082 [15:0] X R/W STAGE0_AFE_OFFSET STAGE0 AFE offset control (see Table 48) 0x083 [15:0] X R/W STAGE0_SENSITIVITY STAGE0 sensitivity control (see Table 49) 0x084 [15:0] X R/W STAGE0_OFFSET_LOW STAGE0 initial offset low value 0x085 [15:0] X R/W STAGE0_OFFSET_HIGH STAGE0 initial offset high value 0x086 [15:0] X R/W STAGE0_OFFSET_HIGH_CLAMP STAGE0 offset high clamp value 0x087 [15:0] X R/W STAGE0_ OFFSET_LOW_CLAMP STAGE0 offset low clamp value Table 35. STAGE1 Configuration Registers Default Address Data Bit Value Type Name Description 0x088 [15:0] X R/W STAGE1_CONNECTION[6:0] STAGE1 CIN(6:0) connection setup (see Table 46) 0x089 [15:0] X R/W STAGE1_CONNECTION[13:7] STAGE1 CIN(13:7) connection setup (see Table 47) 0x08A [15:0] X R/W STAGE1_AFE_OFFSET STAGE1 AFE offset control (see Table 48) 0x08B [15:0] X R/W STAGE1_SENSITIVITY STAGE1 sensitivity control (see Table 49) 0x08C [15:0] X R/W STAGE1_OFFSET_LOW STAGE1 initial offset low value 0x08D [15:0] X R/W STAGE1_OFFSET_HIGH STAGE1 initial offset high value 0x08E [15:0] X R/W STAGE1_OFFSET_HIGH_CLAMP STAGE1 offset high clamp value 0x08F [15:0] X R/W STAGE1_OFFSET_LOW_CLAMP STAGE1 offset low clamp value Table 36. STAGE2 Configuration Registers Default Address Data Bit Value Type Name Description 0x090 [15:0] X R/W STAGE2_CONNECTION[6:0] STAGE2 CIN(6:0) connection setup (see Table 46) 0x091 [15:0] X R/W STAGE2_CONNECTION[13:7] STAGE2 CIN(13:7) connection setup (see Table 47) 0x092 [15:0] X R/W STAGE2_AFE_OFFSET STAGE2 AFE offset control (see Table 48) 0x093 [15:0] X R/W STAGE2_SENSITIVITY STAGE2 sensitivity control (see Table 49) 0x094 [15:0] X R/W STAGE2_OFFSET_LOW STAGE2 initial offset low value 0x095 [15:0] X R/W STAGE2_OFFSET_HIGH STAGE2 initial offset high value 0x096 [15:0] X R/W STAGE2_OFFSET_HIGH_CLAMP STAGE2 offset high clamp value 0x097 [15:0] X R/W STAGE2_OFFSET_LOW_CLAMP STAGE2 offset low clamp value Rev. B | Page 51 of 70

AD7142 Data Sheet Table 37. STAGE3 Configuration Registers Default Address Data Bit Value Type Name Description 0x098 [15:0] X R/W STAGE3_CONNECTION[6:0] STAGE3 CIN(6:0) connection setup (see Table 46) 0x099 [15:0] X R/W STAGE3_CONNECTION[13:7] STAGE3 CIN(13:7) connection setup (see Table 47) 0x09A [15:0] X R/W STAGE3_AFE_OFFSET STAGE3 AFE offset control (see Table 48) 0x09B [15:0] X R/W STAGE3_SENSITIVITY STAGE3 sensitivity control (see Table 49) 0x09C [15:0] X R/W STAGE3_OFFSET_LOW STAGE3 initial offset low value 0x09D [15:0] X R/W STAGE3_OFFSET_HIGH STAGE3 initial offset high value 0x09E [15:0] X R/W STAGE3_OFFSET_HIGH_CLAMP STAGE3 offset high clamp value 0x09F [15:0] X R/W STAGE3_OFFSET_LOW_CLAMP STAGE3 offset low clamp value Table 38. STAGE4 Configuration Registers Default Address Data Bit Value Type Name Description 0x0A0 [15:0] X R/W STAGE4_CONNECTION[6:0] STAGE4 CIN(6:0) connection setup (see Table 46) 0x0A1 [15:0] X R/W STAGE4_CONNECTION[13:7] STAGE4 CIN(13:7) connection setup (see Table 47) 0x0A2 [15:0] X R/W STAGE4_AFE_OFFSET STAGE4 AFE offset control (see Table 48) 0x0A3 [15:0] X R/W STAGE4_SENSITIVITY STAGE4 sensitivity control (see Table 49) 0x0A4 [15:0] X R/W STAGE4_OFFSET_LOW STAGE4 initial offset low value 0x0A5 [15:0] X R/W STAGE4_OFFSET_HIGH STAGE4 initial offset high value 0x0A6 [15:0] X R/W STAGE4_OFFSET_HIGH_CLAMP STAGE4 offset high clamp value 0x0A7 [15:0] X R/W STAGE4_OFFSET_LOW_CLAMP STAGE4 offset low clamp value Table 39. STAGE5 Configuration Registers Default Address Data Bit Value Type Name Description 0x0A8 [15:0] X R/W STAGE5_CONNECTION[6:0] STAGE5 CIN(6:0) connection setup (see Table 46) 0x0A9 [15:0] X R/W STAGE5_CONNECTION[13:7] STAGE5 CIN(13:7) connection setup (see Table 47) 0x0AA [15:0] X R/W STAGE5_AFE_OFFSET STAGE5 AFE offset control (see Table 48) 0x0AB [15:0] X R/W STAGE5_SENSITIVITY STAGE5 sensitivity control (see Table 49) 0x0AC [15:0] X R/W STAGE5_OFFSET_LOW STAGE5 initial offset low value 0x0AD [15:0] X R/W STAGE5_OFFSET_HIGH STAGE5 initial offset high value 0x0AE [15:0] X R/W STAGE5_OFFSET_HIGH_CLAMP STAGE5 offset high clamp value 0x0AF [15:0] X R/W STAGE5_OFFSET_LOW_CLAMP STAGE5 offset low clamp value Rev. B | Page 52 of 70

Data Sheet AD7142 Table 40. STAGE6 Configuration Registers Default Address Data Bit Value Type Name Description 0x0B0 [15:0] X R/W STAGE6_CONNECTION[6:0] STAGE6 CIN(6:0) connection setup (see Table 46) 0x0B1 [15:0] X R/W STAGE6_CONNECTION[13:7] STAGE6 CIN(13:7) connection setup (see Table 47) 0x0B2 [15:0] X R/W STAGE6_AFE_OFFSET STAGE6 AFE offset control (see Table 48) 0x0B3 [15:0] X R/W STAGE6_SENSITIVITY STAGE6 sensitivity control (see Table 49) 0x0B4 [15:0] X R/W STAGE6_OFFSET_LOW STAGE6 initial offset low value 0x0B5 [15:0] X R/W STAGE6_OFFSET_HIGH STAGE6 initial offset high value 0x0B6 [15:0] X R/W STAGE6_OFFSET_HIGH_CLAMP STAGE6 offset high clamp value 0x0B7 [15:0] X R/W STAGE6_OFFSET_LOW_CLAMP STAGE6 offset low clamp value Table 41. STAGE7 Configuration Registers Default Address Data Bit Value Type Name Description 0x0B8 [15:0] X R/W STAGE7_CONNECTION[6:0] STAGE7 CIN(6:0) connection setup (see Table 46) 0x0B9 [15:0] X R/W STAGE7_CONNECTION[13:7] STAGE7 CIN(13:7) connection setup (see Table 47) 0x0BA [15:0] X R/W STAGE7_AFE_OFFSET STAGE7 AFE offset control (see Table 48) 0x0BB [15:0] X R/W STAGE7_SENSITIVITY STAGE7 sensitivity control (see Table 49) 0x0BC [15:0] X R/W STAGE7_OFFSET_LOW STAGE7 initial offset low value 0x0BD [15:0] X R/W STAGE7_OFFSET_HIGH STAGE7 initial offset high value 0x0BE [15:0] X R/W STAGE7_OFFSET_HIGH_CLAMP STAGE7 offset high clamp value 0x0BF [15:0] X R/W STAGE7_OFFSET_LOW_CLAMP STAGE7 offset low clamp value Table 42. STAGE8 Configuration Registers Default Address Data Bit Value Type Name Description 0x0C0 [15:0] X R/W STAGE8_CONNECTION[6:0] STAGE8 CIN(6:0) connection setup (see Table 46) 0x0C1 [15:0] X R/W STAGE8_CONNECTION[13:7] STAGE8 CIN(13:7) connection setup (see Table 47) 0x0C2 [15:0] X R/W STAGE8_AFE_OFFSET STAGE8 AFE offset control (see Table 48) 0x0C3 [15:0] X R/W STAGE8_SENSITIVITY STAGE8 sensitivity control (see Table 49) 0x0C4 [15:0] X R/W STAGE8_OFFSET_LOW STAGE8 initial offset low value 0x0C5 [15:0] X R/W STAGE8_OFFSET_HIGH STAGE8 initial offset high value 0x0C6 [15:0] X R/W STAGE8_OFFSET_HIGH_CLAMP STAGE8 offset high clamp value 0x0C7 [15:0] X R/W STAGE8_OFFSET_LOW_CLAMP STAGE8 offset low clamp value Rev. B | Page 53 of 70

AD7142 Data Sheet Table 43. STAGE9 Configuration Registers Default Address Data Bit Value Type Name Description 0x0C8 [15:0] X R/W STAGE9_CONNECTION[6:0] STAGE9 CIN(6:0) connection setup (see Table 46) 0x0C9 [15:0] X R/W STAGE9_CONNECTION[13:7] STAGE9 CIN(13:7) connection setup (see Table 47) 0x0CA [15:0] X R/W STAGE9_AFE_OFFSET STAGE9 AFE offset control (see Table 48) 0x0CB [15:0] X R/W STAGE9_SENSITIVITY STAGE9 sensitivity control (see Table 49) 0x0CC [15:0] X R/W STAGE9_OFFSET_LOW STAGE9 initial offset low value 0x0CD [15:0] X R/W STAGE9_OFFSET_HIGH STAGE9 initial offset high value 0x0CE [15:0] X R/W STAGE9_OFFSET_HIGH_CLAMP STAGE9 offset high clamp value 0x0CF [15:0] X R/W STAGE9_OFFSET_LOW_CLAMP STAGE9 offset low clamp value Table 44. STAGE10 Configuration Registers Default Address Data Bit Value Type Name Description 0x0D0 [15:0] X R/W STAGE10_CONNECTION[6:0] STAGE10 CIN(6:0) connection setup (see Table 46) 0x0D1 [15:0] X R/W STAGE10_CONNECTION[13:7] STAGE10 CIN(13:7) connection setup (see Table 47) 0x0D2 [15:0] X R/W STAGE10_AFE_OFFSET STAGE10 AFE offset control (see Table 48) 0x0D3 [15:0] X R/W STAGE10_SENSITIVITY STAGE10 sensitivity control (see Table 49) 0x0D4 [15:0] X R/W STAGE10_OFFSET_LOW STAGE10 initial offset low value 0x0D5 [15:0] X R/W STAGE10_OFFSET_HIGH STAGE10 initial offset high value 0x0D6 [15:0] X R/W STAGE10_OFFSET_HIGH_CLAMP STAGE10 offset high clamp value 0x0D7 [15:0] X R/W STAGE10_OFFSET_LOW_CLAMP STAGE10 offset low clamp value Table 45. STAGE11 Configuration Registers Default Address Data Bit Value Type Name Description 0x0D8 [15:0] X R/W STAGE11_CONNECTION[6:0] STAGE11 CIN(6:0) connection setup (see Table 46) 0x0D9 [15:0] X R/W STAGE11_CONNECTION[13:7] STAGE11 CIN(13:7) connection setup (see Table 47) 0x0DA [15:0] X R/W STAGE11_AFE_OFFSET STAGE11 AFE offset control (see Table 48) 0x0DB [15:0] X R/W STAGE11_SENSITIVITY STAGE11 sensitivity control (see Table 49) 0x0DC [15:0] X R/W STAGE11_OFFSET_LOW STAGE11 initial offset low value 0x0DD [15:0] X R/W STAGE11_OFFSET_HIGH STAGE11 initial offset high value 0x0DE [15:0] X R/W STAGE11_OFFSET_HIGH_CLAMP STAGE11 offset high clamp value 0x0DF [15:0] X R/W STAGE11_OFFSET_LOW_CLAMP STAGE11 offset low clamp value Rev. B | Page 54 of 70

Data Sheet AD7142 Table 46. STAGEX Detailed CIN (0:6) Connection Setup Description (X = 0 to 11) Default Data Bit Value Type Name Description [1:0] X R/W CIN0_CONNECTION_SETUP CIN0 connection setup 00 = CIN0 not connected to CDC inputs 01 = CIN0 connected to CDC negative input 10 = CIN0 connected to CDC positive input 11 = CIN0 connected to BIAS (connect unused CIN inputs) [3:2] X R/W CIN1_CONNECTION_SETUP CIN1 connection setup 00 = CIN1 not connected to CDC inputs 01 = CIN1 connected to CDC negative input 10 = CIN1 connected to CDC positive input 11 = CIN1 connected to BIAS (connect unused CIN inputs) [5:4] X R/W CIN2_CONNECTION_SETUP CIN2 connection setup 00 = CIN2 not connected to CDC inputs 01 = CIN2 connected to CDC negative input 10 = CIN2 connected to CDC positive input 11 = CIN2 connected to BIAS (connect unused CIN inputs) [7:6] X R/W CIN3_CONNECTION_SETUP CIN3 connection setup 00 = CIN3 not connected to CDC inputs 01 = CIN3 connected to CDC negative input 10 = CIN3 connected to CDC positive input 11 = CIN3 connected to BIAS (connect unused CIN inputs) [9:8] X R/W CIN4_CONNECTION_SETUP CIN4 connection setup 00 = CIN4 not connected to CDC inputs 01 = CIN4 connected to CDC negative input 10 = CIN4 connected to CDC positive input 11 = CIN4 connected to BIAS (connect unused CIN inputs) [11:10] X R/W CIN5_CONNECTION_SETUP CIN5 connection setup 00 = CIN5 not connected to CDC inputs 01 = CIN5 connected to CDC negative input 10 = CIN5 connected to CDC positive input 11 = CIN5 connected to BIAS (connect unused CIN inputs) [13:12] X R/W CIN6_CONNECTION_SETUP CIN6 connection setup 00 = CIN6 not connected to CDC inputs 01 = CIN6 connected to CDC negative input 10 = CIN6 connected to CDC positive input 11 = CIN6 connected to BIAS (connect unused CIN inputs) [15:14] X Unused Set unused register bits = 0 Rev. B | Page 55 of 70

AD7142 Data Sheet Table 47. STAGEX Detailed CIN (7:13) Connection Setup Description (X = 0 to 11) Data Bit Default Value Type Name Description [1:0] X R/W CIN7_CONNECTION_SETUP CIN7 connection setup 00 = CIN7 not connected to CDC inputs 01 = CIN7 connected to CDC negative input 10 = CIN7 connected to CDC positive input 11 = CIN7 connected to BIAS (connect unused CIN inputs) [3:2] X R/W CIN8_CONNECTION_SETUP CIN8 connection setup 00 = CIN8 not connected to CDC inputs 01 = CIN8 connected to CDC negative input 10 = CIN8 connected to CDC positive input 11 = CIN8 connected to BIAS (connect unused CIN inputs) [5:4] X R/W CIN9_CONNECTION_SETUP CIN9 connection setup 00 = CIN9 not connected to CDC inputs 01 = CIN9 connected to CDC negative input 10 = CIN9 connected to CDC positive input 11 = CIN9 connected to BIAS (connect unused CIN inputs) [7:6] X R/W CIN10_CONNECTION_SETUP CIN10 connection setup 00 = CIN10 not connected to CDC inputs 01 = CIN10 connected to CDC negative input 10 = CIN10 connected to CDC positive input 11 = CIN10 connected to BIAS (connect unused CIN inputs) [9:8] X R/W CIN11_CONNECTION_SETUP CIN11 connection setup 00 = CIN11 not connected to CDC inputs 01 = CIN11 connected to CDC negative input 10 = CIN11 connected to CDC positive input 11 = CIN11 connected to BIAS (connect unused CIN inputs) [11:10] X R/W CIN12_CONNECTION_SETUP CIN12 connection setup 00 = CIN12 not connected to CDC inputs 01 = CIN12 connected to CDC negative input 10 = CIN12 connected to CDC positive input 11 = CIN12 connected to BIAS (connect unused CIN inputs) [13:12] X R/W CIN13_CONNECTION_SETUP CIN13 connection setup 00 = CIN13 not connected to CDC inputs 01 = CIN13 connected to CDC negative input 10 = CIN13 connected to CDC positive input 11 = CIN13 connected to BIAS (connect unused CIN inputs) 14 X NEG_AFE_OFFSET_DISABLE Negative AFE offset enable control 0 = enable 1 = disable 15 X POS_AFE_OFFSET_DISABLE Positive AFE offset enable control 0 = enable 1 = disable Rev. B | Page 56 of 70

Data Sheet AD7142 Table 48. STAGEX Detailed Offset Control Description (X = 0 to 11) Default Data Bit Value Type Name Description [6:0] X R/W NEG_AFE_OFFSET Negative AFE offset setting (20 pF range) 1 LSB value = 0.16 pF of offset 7 X R/W NEG_AFE_OFFSET_SWAP Negative AFE offset swap control 0 = NEG_AFE_OFFSET applied to CDC negative input 1 = NEG_AFE_OFFSET applied to CDC positive input [14:8] X R/W POS_AFE_OFFSET Positive AFE offset setting (20 pF range) 1 LSB value = 0.16 pF of offset 15 X R/W POS_AFE_OFFSET_SWAP Positive AFE offset swap control 0 = POS_AFE_OFFSET applied to CDC positive input 1 = POS_AFE_OFFSET applied to CDC negative input Table 49. STAGEX Detailed Sensitivity Control Description (X = 0 to 11) Default Data Bit Value Type Name Description [3:0] X R/W NEG_THRESHOLD_SENSITIVITY Negative threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% [6:4] X R/W NEG_PEAK_DETECT Negative peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level 7 X R/W Unused Set unused register bits = 0 [11:8] X R/W POS_THRESHOLD_SENSITIVITY Positive threshold sensitivity control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% [14:12] X R/W POS_PEAK_DETECT Positive peak detect setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level 15 X R/W Unused Set unused register bits = 0 Rev. B | Page 57 of 70

AD7142 Data Sheet BANK 3 REGISTERS All address values are expressed in hexadecimal. Table 50. STAGE0 Results Registers Address Data Bit Default Value Type Name Description 0x0E0 [15:0] X R/W STAGE0_CONV_DATA STAGE0 CDC 16-bit conversion data (copy of data in STAGE0_CONV_DATA register) 0x0E1 [15:0] X R/W STAGE0_FF_WORD0 STAGE0 fast FIFO WORD0 0x0E2 [15:0] X R/W STAGE0_FF_WORD1 STAGE0 fast FIFO WORD1 0x0E3 [15:0] X R/W STAGE0_FF_WORD2 STAGE0 fast FIFO WORD2 0x0E4 [15:0] X R/W STAGE0_FF_WORD3 STAGE0 fast FIFO WORD3 0x0E5 [15:0] X R/W STAGE0_FF_WORD4 STAGE0 fast FIFO WORD4 0x0E6 [15:0] X R/W STAGE0_FF_WORD5 STAGE0 fast FIFO WORD5 0x0E7 [15:0] X R/W STAGE0_FF_WORD6 STAGE0 fast FIFO WORD6 0x0E8 [15:0] X R/W STAGE0_FF_WORD7 STAGE0 fast FIFO WORD7 0x0E9 [15:0] X R/W STAGE0_SF_WORD0 STAGE0 slow FIFO WORD0 0x0EA [15:0] X R/W STAGE0_SF_WORD1 STAGE0 slow FIFO WORD1 0x0EB [15:0] X R/W STAGE0_SF_WORD2 STAGE0 slow FIFO WORD2 0x0EC [15:0] X R/W STAGE0_SF_WORD3 STAGE0 slow FIFO WORD3 0x0ED [15:0] X R/W STAGE0_SF_WORD4 STAGE0 slow FIFO WORD4 0x0EE [15:0] X R/W STAGE0_SF_WORD5 STAGE0 slow FIFO WORD5 0x0EF [15:0] X R/W STAGE0_SF_WORD6 STAGE0 slow FIFO WORD6 0x0F0 [15:0] X R/W STAGE0_SF_WORD7 STAGE0 slow FIFO WORD7 0x0F1 [15:0] X R/W STAGE0_SF_AMBIENT STAGE0 slow FIFO ambient value 0x0F2 [15:0] X R/W STAGE0_FF_AVG STAGE0 fast FIFO average value 0x0F3 [15:0] X R/W STAGE0_PEAK_DETECT_WORD0 STAGE0 peak FIFO WORD0 value 0x0F4 [15:0] X R/W STAGE0_PEAK_DETECT_WORD1 STAGE0 peak FIFO WORD1 value 0x0F5 [15:0] X R/W STAGE0_MAX_WORD0 STAGE0 maximum value FIFO WORD0 0x0F6 [15:0] X R/W STAGE0_MAX_WORD1 STAGE0 maximum value FIFO WORD1 0x0F7 [15:0] X R/W STAGE0_MAX_WORD2 STAGE0 maximum value FIFO WORD2 0x0F8 [15:0] X R/W STAGE0_MAX_WORD3 STAGE0 maximum value FIFO WORD3 0x0F9 [15:0] X R/W STAGE0_MAX_AVG STAGE0 average maximum FIFO value 0x0FA [15:0] X R/W STAGE0_HIGH_THRESHOLD STAGE0 high threshold value 0x0FB [15:0] X R/W STAGE0_MAX_TEMP STAGE0 temporary maximum value 0x0FC [15:0] X R/W STAGE0_MIN_WORD0 STAGE0 minimum value FIFO WORD0 0x0FD [15:0] X R/W STAGE0_MIN_WORD1 STAGE0 minimum value FIFO WORD1 0x0FE [15:0] X R/W STAGE0_MIN_WORD2 STAGE0 minimum value FIFO WORD2 0x0FF [15:0] X R/W STAGE0_MIN_WORD3 STAGE0 minimum value FIFO WORD3 0x100 [15:0] X R/W STAGE0_MIN_AVG STAGE0 average minimum FIFO value 0x101 [15:0] X R/W STAGE0_LOW_THRESHOLD STAGE0 low threshold value 0x102 [15:0] X R/W STAGE0_MIN_TEMP STAGE0 temporary minimum value 0x103 [15:0] X R/W Unused Set unused register bits = 0 Rev. B | Page 58 of 70

Data Sheet AD7142 Table 51. STAGE1 Results Registers Address Data Bit Default Value Type Name Description 0x104 [15:0] X R/W STAGE1_CONV_DATA STAGE1 CDC 16-bit conversion data (copy of data in STAGE1_CONV_DATA register) 0x105 [15:0] X R/W STAGE1_FF_WORD0 STAGE1 fast FIFO WORD0 0x106 [15:0] X R/W STAGE1_FF_WORD1 STAGE1 fast FIFO WORD1 0x107 [15:0] X R/W STAGE1_FF_WORD2 STAGE1 fast FIFO WORD2 0x108 [15:0] X R/W STAGE1_FF_WORD3 STAGE1 fast FIFO WORD3 0x109 [15:0] X R/W STAGE1_FF_WORD4 STAGE1 fast FIFO WORD4 0x10A [15:0] X R/W STAGE1_FF_WORD5 STAGE1 fast FIFO WORD5 0x10B [15:0] X R/W STAGE1_FF_WORD6 STAGE1 fast FIFO WORD6 0x10C [15:0] X R/W STAGE1_FF_WORD7 STAGE1 fast FIFO WORD7 0x10D [15:0] X R/W STAGE1_SF_WORD0 STAGE1 slow FIFO WORD0 0x10E [15:0] X R/W STAGE1_SF_WORD1 STAGE1 slow FIFO WORD1 0x10F [15:0] X R/W STAGE1_SF_WORD2 STAGE1 slow FIFO WORD2 0x110 [15:0] X R/W STAGE1_SF_WORD3 STAGE1 slow FIFO WORD3 0x111 [15:0] X R/W STAGE1_SF_WORD4 STAGE1 slow FIFO WORD4 0x112 [15:0] X R/W STAGE1_SF_WORD5 STAGE1 slow FIFO WORD5 0x113 [15:0] X R/W STAGE1_SF_WORD6 STAGE1 slow FIFO WORD6 0x114 [15:0] X R/W STAGE1_SF_WORD7 STAGE1 slow FIFO WORD7 0x115 [15:0] X R/W STAGE1_SF_AMBIENT STAGE1 slow FIFO ambient value 0x116 [15:0] X R/W STAGE1_FF_AVG STAGE1 fast FIFO average value 0x117 [15:0] X R/W STAGE1_CDC_WORD0 STAGE1 CDC FIFO WORD0 0x118 [15:0] X R/W STAGE1_CDC_WORD1 STAGE1 CDC FIFO WORD1 0x119 [15:0] X R/W STAGE1_MAX_WORD0 STAGE1 maximum value FIFO WORD0 0x11A [15:0] X R/W STAGE1_MAX_WORD1 STAGE1 maximum value FIFO WORD1 0x11B [15:0] X R/W STAGE1_MAX_WORD2 STAGE1 maximum value FIFO WORD2 0x11C [15:0] X R/W STAGE1_MAX_WORD3 STAGE1 maximum value FIFO WORD3 0x11D [15:0] X R/W STAGE1_MAX_AVG STAGE1 average maximum FIFO value 0x11E [15:0] X R/W STAGE1_HIGH_THRESHOLD STAGE1 high threshold value 0x11F [15:0] X R/W STAGE1_MAX_TEMP STAGE1 temporary maximum value 0x120 [15:0] X R/W STAGE1_MIN_WORD0 STAGE1 minimum value FIFO WORD0 0x121 [15:0] X R/W STAGE1_MIN_WORD1 STAGE1 minimum value FIFO WORD1 0x122 [15:0] X R/W STAGE1_MIN_WORD2 STAGE1 minimum value FIFO WORD2 0x123 [15:0] X R/W STAGE1_MIN_WORD3 STAGE1 minimum value FIFO WORD3 0x124 [15:0] X R/W STAGE1_MIN_AVG STAGE1 average minimum FIFO value 0x125 [15:0] X R/W STAGE1_LOW_THRESHOLD STAGE1 low threshold value 0x126 [15:0] X R/W STAGE1_MIN_TEMP STAGE1 temporary minimum value 0x127 [15:0] X R/W Unused Set unused register bits = 0 Rev. B | Page 59 of 70

AD7142 Data Sheet Table 52. STAGE2 Results Registers Address Data Bit Default Value Type Name Description 0x128 [15:0] X R/W STAGE2_CONV_DATA STAGE2 CDC 16-bit conversion data (copy of data in STAGE2_CONV_DATA register) 0x129 [15:0] X R/W STAGE2_FF_WORD0 STAGE2 fast FIFO WORD0 0x12A [15:0] X R/W STAGE2_FF_WORD1 STAGE2 fast FIFO WORD1 0x12B [15:0] X R/W STAGE2_FF_WORD2 STAGE2 fast FIFO WORD2 0x12C [15:0] X R/W STAGE2_FF_WORD3 STAGE2 fast FIFO WORD3 0x12D [15:0] X R/W STAGE2_FF_WORD4 STAGE2 fast FIFO WORD4 0x12E [15:0] X R/W STAGE2_FF_WORD5 STAGE2 fast FIFO WORD5 0x12F [15:0] X R/W STAGE2_FF_WORD6 STAGE2 fast FIFO WORD6 0x130 [15:0] X R/W STAGE2_FF_WORD7 STAGE2 fast FIFO WORD7 0x131 [15:0] X R/W STAGE2_SF_WORD0 STAGE2 slow FIFO WORD0 0x132 [15:0] X R/W STAGE2_SF_WORD1 STAGE2 slow FIFO WORD1 0x133 [15:0] X R/W STAGE2_SF_WORD2 STAGE2 slow FIFO WORD2 0x134 [15:0] X R/W STAGE2_SF_WORD3 STAGE2 slow FIFO WORD3 0x135 [15:0] X R/W STAGE2_SF_WORD4 STAGE2 slow FIFO WORD4 0x136 [15:0] X R/W STAGE2_SF_WORD5 STAGE2 slow FIFO WORD5 0x137 [15:0] X R/W STAGE2_SF_WORD6 STAGE2 slow FIFO WORD6 0x138 [15:0] X R/W STAGE2_SF_WORD7 STAGE2 slow FIFO WORD7 0x139 [15:0] X R/W STAGE2_SF_AMBIENT STAGE2 slow FIFO ambient value 0x13A [15:0] X R/W STAGE2_FF_AVG STAGE2 fast FIFO average value 0x13B [15:0] X R/W STAGE2_CDC_WORD0 STAGE2 CDC FIFO WORD0 0x13C [15:0] X R/W STAGE2_CDC_WORD1 STAGE2 CDC FIFO WORD1 0x13D [15:0] X R/W STAGE2_MAX_WORD0 STAGE2 maximum value FIFO WORD0 0x13E [15:0] X R/W STAGE2_MAX_WORD1 STAGE2 maximum value FIFO WORD1 0x13F [15:0] X R/W STAGE2_MAX_WORD2 STAGE2 maximum value FIFO WORD2 0x140 [15:0] X R/W STAGE2_MAX_WORD3 STAGE2 maximum value FIFO WORD3 0x141 [15:0] X R/W STAGE2_MAX_AVG STAGE2 average maximum FIFO value 0x142 [15:0] X R/W STAGE2_HIGH_THRESHOLD STAGE2 high threshold value 0x143 [15:0] X R/W STAGE2_MAX_TEMP STAGE2 temporary maximum value 0x144 [15:0] X R/W STAGE2_MIN_WORD0 STAGE2 minimum value FIFO WORD0 0x145 [15:0] X R/W STAGE2_MIN_WORD1 STAGE2 minimum value FIFO WORD1 0x146 [15:0] X R/W STAGE2_MIN_WORD2 STAGE2 minimum value FIFO WORD2 0x147 [15:0] X R/W STAGE2_MIN_WORD3 STAGE2 minimum value FIFO WORD3 0x148 [15:0] X R/W STAGE2_MIN_AVG STAGE2 average minimum FIFO value 0x149 [15:0] X R/W STAGE2_LOW_THRESHOLD STAGE2 low threshold value 0x14A [15:0] X R/W STAGE2_MIN_TEMP STAGE2 temporary minimum value 0x14B [15:0] X R/W Unused Set unused register bits = 0 Rev. B | Page 60 of 70

Data Sheet AD7142 Table 53. STAGE3 Results Registers Address Data Bit Default Value Type Name Description 0x14C [15:0] X R/W STAGE3_CONV_DATA STAGE3 CDC 16-bit conversion data (copy of data in STAGE3_CONV_DATA register) 0x14D [15:0] X R/W STAGE3_FF_WORD0 STAGE3 fast FIFO WORD0 0x14E [15:0] X R/W STAGE3_FF_WORD1 STAGE3 fast FIFO WORD1 0x14F [15:0] X R/W STAGE3_FF_WORD2 STAGE3 fast FIFO WORD2 0x150 [15:0] X R/W STAGE3_FF_WORD3 STAGE3 fast FIFO WORD3 0x151 [15:0] X R/W STAGE3_FF_WORD4 STAGE3 fast FIFO WORD4 0x152 [15:0] X R/W STAGE3_FF_WORD5 STAGE3 fast FIFO WORD5 0x153 [15:0] X R/W STAGE3_FF_WORD6 STAGE3 fast FIFO WORD6 0x154 [15:0] X R/W STAGE3_FF_WORD7 STAGE3 fast FIFO WORD7 0x155 [15:0] X R/W STAGE3_SF_WORD0 STAGE3 slow FIFO WORD0 0x156 [15:0] X R/W STAGE3_SF_WORD1 STAGE3 slow FIFO WORD1 0x157 [15:0] X R/W STAGE3_SF_WORD2 STAGE3 slow FIFO WORD2 0x158 [15:0] X R/W STAGE3_SF_WORD3 STAGE3 slow FIFO WORD3 0x159 [15:0] X R/W STAGE3_SF_WORD4 STAGE3 slow FIFO WORD4 0x15A [15:0] X R/W STAGE3_SF_WORD5 STAGE3 slow FIFO WORD5 0x15B [15:0] X R/W STAGE3_SF_WORD6 STAGE3 slow FIFO WORD6 0x15C [15:0] X R/W STAGE3_SF_WORD7 STAGE3 slow FIFO WORD7 0x15D [15:0] X R/W STAGE3_SF_AMBIENT STAGE3 slow FIFO ambient value 0x15E [15:0] X R/W STAGE3_FF_AVG STAGE3 fast FIFO average value 0x15F [15:0] X R/W STAGE3_CDC_WORD0 STAGE3 CDC FIFO WORD0 0x160 [15:0] X R/W STAGE3_CDC_WORD1 STAGE3 CDC FIFO WORD1 0x161 [15:0] X R/W STAGE3_MAX_WORD0 STAGE3 maximum value FIFO WORD0 0x162 [15:0] X R/W STAGE3_MAX_WORD1 STAGE3 maximum value FIFO WORD1 0x163 [15:0] X R/W STAGE3_MAX_WORD2 STAGE3 maximum value FIFO WORD2 0x164 [15:0] X R/W STAGE3_MAX_WORD3 STAGE3 maximum value FIFO WORD3 0x165 [15:0] X R/W STAGE3_MAX_AVG STAGE3 average maximum FIFO value 0x166 [15:0] X R/W STAGE3_HIGH_THRESHOLD STAGE3 high threshold value 0x167 [15:0] X R/W STAGE3_MAX_TEMP STAGE3 temporary maximum value 0x168 [15:0] X R/W STAGE3_MIN_WORD0 STAGE3 minimum value FIFO WORD0 0x169 [15:0] X R/W STAGE3_MIN_WORD1 STAGE3 minimum value FIFO WORD1 0x16A [15:0] X R/W STAGE3_MIN_WORD2 STAGE3 minimum value FIFO WORD2 0x16B [15:0] X R/W STAGE3_MIN_WORD3 STAGE3 minimum value FIFO WORD3 0x16C [15:0] X R/W STAGE3_MIN_AVG STAGE3 average minimum FIFO value 0x16D [15:0] X R/W STAGE3_LOW_THRESHOLD STAGE3 low threshold value 0x16E [15:0] X R/W STAGE3_MIN_TEMP STAGE3 temporary minimum value 0x16F [15:0] X R/W Unused Set unused register bits = 0 Rev. B | Page 61 of 70

AD7142 Data Sheet Table 54. STAGE4 Results Registers Address Data Bit Default Value Type Name Description 0x170 [15:0] X R/W STAGE4_CONV_DATA STAGE4 CDC 16-bit conversion data (copy of data in STAGE4_CONV_DATA register) 0x171 [15:0] X R/W STAGE4_FF_WORD0 STAGE4 fast FIFO WORD0 0x172 [15:0] X R/W STAGE4_FF_WORD1 STAGE4 fast FIFO WORD1 0x173 [15:0] X R/W STAGE4_FF_WORD2 STAGE4 fast FIFO WORD2 0x174 [15:0] X R/W STAGE4_FF_WORD3 STAGE4 fast FIFO WORD3 0x175 [15:0] X R/W STAGE4_FF_WORD4 STAGE4 fast FIFO WORD4 0x176 [15:0] X R/W STAGE4_FF_WORD5 STAGE4 fast FIFO WORD5 0x177 [15:0] X R/W STAGE4_FF_WORD6 STAGE4 fast FIFO WORD6 0x178 [15:0] X R/W STAGE4_FF_WORD7 STAGE4 fast FIFO WORD7 0x179 [15:0] X R/W STAGE4_SF_WORD0 STAGE4 slow FIFO WORD0 0x17A [15:0] X R/W STAGE4_SF_WORD1 STAGE4 slow FIFO WORD1 0x17B [15:0] X R/W STAGE4_SF_WORD2 STAGE4 slow FIFO WORD2 0x17C [15:0] X R/W STAGE4_SF_WORD3 STAGE4 slow FIFO WORD3 0x17D [15:0] X R/W STAGE4_SF_WORD4 STAGE4 slow FIFO WORD4 0x17E [15:0] X R/W STAGE4_SF_WORD5 STAGE4 slow FIFO WORD5 0x17F [15:0] X R/W STAGE4_SF_WORD6 STAGE4 slow FIFO WORD6 0x180 [15:0] X R/W STAGE4_SF_WORD7 STAGE4 slow FIFO WORD7 0x181 [15:0] X R/W STAGE4_SF_AMBIENT STAGE4 slow FIFO ambient value 0x182 [15:0] X R/W STAGE4_FF_AVG STAGE4 fast FIFO average value 0x183 [15:0] X R/W STAGE4_CDC_WORD0 STAGE4 CDC FIFO WORD0 0x184 [15:0] X R/W STAGE4_CDC_WORD1 STAGE4 CDC FIFO WORD1 0x185 [15:0] X R/W STAGE4_MAX_WORD0 STAGE4 maximum value FIFO WORD0 0x186 [15:0] X R/W STAGE4_MAX_WORD1 STAGE4 maximum value FIFO WORD1 0x187 [15:0] X R/W STAGE4_MAX_WORD2 STAGE4 maximum value FIFO WORD2 0x188 [15:0] X R/W STAGE4_MAX_WORD3 STAGE4 maximum value FIFO WORD3 0x189 [15:0] X R/W STAGE4_MAX_AVG STAGE4 average maximum FIFO value 0x18A [15:0] X R/W STAGE4_HIGH_THRESHOLD STAGE4 high threshold value 0x18B [15:0] X R/W STAGE4_MAX_TEMP STAGE4 temporary maximum value 0x18C [15:0] X R/W STAGE4_MIN_WORD0 STAGE4 minimum value FIFO WORD0 0x18D [15:0] X R/W STAGE4_MIN_WORD1 STAGE4 minimum value FIFO WORD1 0x18E [15:0] X R/W STAGE4_MIN_WORD2 STAGE4 minimum value FIFO WORD2 0x18F [15:0] X R/W STAGE4_MIN_WORD3 STAGE4 minimum value FIFO WORD3 0x190 [15:0] X R/W STAGE4_MIN_AVG STAGE4 average minimum FIFO value 0x191 [15:0] X R/W STAGE4_LOW_THRESHOLD STAGE4 low threshold value 0x192 [15:0] X R/W STAGE4_MIN_TEMP STAGE4 temporary minimum value 0x193 [15:0] X R/W Unused Set unused register bits = 0 Rev. B | Page 62 of 70

Data Sheet AD7142 Table 55. STAGE5 Results Registers Address Data Bit Default Value Type Name Description 0x194 [15:0] X R/W STAGE5_CONV_DATA STAGE5 CDC 16-bit conversion data (copy of data in STAGE5_CONV_DATA register) 0x195 [15:0] X R/W STAGE5_FF_WORD0 STAGE5 fast FIFO WORD0 0x196 [15:0] X R/W STAGE5_FF_WORD1 STAGE5 fast FIFO WORD1 0x197 [15:0] X R/W STAGE5_FF_WORD2 STAGE5 fast FIFO WORD2 0x198 [15:0] X R/W STAGE5_FF_WORD3 STAGE5 fast FIFO WORD3 0x199 [15:0] X R/W STAGE5_FF_WORD4 STAGE5 fast FIFO WORD4 0x19A [15:0] X R/W STAGE5_FF_WORD5 STAGE5 fast FIFO WORD5 0x19B [15:0] X R/W STAGE5_FF_WORD6 STAGE5 fast FIFO WORD6 0x19C [15:0] X R/W STAGE5_FF_WORD7 STAGE5 fast FIFO WORD7 0x19D [15:0] X R/W STAGE5_SF_WORD0 STAGE5 slow FIFO WORD0 0x19E [15:0] X R/W STAGE5_SF_WORD1 STAGE5 slow FIFO WORD1 0x19F [15:0] X R/W STAGE5_SF_WORD2 STAGE5 slow FIFO WORD2 0x1A0 [15:0] X R/W STAGE5_SF_WORD3 STAGE5 slow FIFO WORD3 0x1A1 [15:0] X R/W STAGE5_SF_WORD4 STAGE5 slow FIFO WORD4 0x1A2 [15:0] X R/W STAGE5_SF_WORD5 STAGE5 slow FIFO WORD5 0x1A3 [15:0] X R/W STAGE5_SF_WORD6 STAGE5 slow FIFO WORD6 0x1A4 [15:0] X R/W STAGE5_SF_WORD7 STAGE5 slow FIFO WORD7 0x1A5 [15:0] X R/W STAGE5_SF_AMBIENT STAGE5 slow FIFO ambient value 0x1A6 [15:0] X R/W STAGE5_FF_AVG STAGE5 fast FIFO average value 0x1A7 [15:0] X R/W STAGE5_CDC_WORD0 STAGE5 CDC FIFO WORD0 0x1A8 [15:0] X R/W STAGE5_CDC_WORD1 STAGE5 CDC FIFO WORD1 0x1A9 [15:0] X R/W STAGE5_MAX_WORD0 STAGE5 maximum value FIFO WORD0 0x1AA [15:0] X R/W STAGE5_MAX_WORD1 STAGE5 maximum value FIFO WORD1 0x1AB [15:0] X R/W STAGE5_MAX_WORD2 STAGE5 maximum value FIFO WORD2 0x1AC [15:0] X R/W STAGE5_MAX_WORD3 STAGE5 maximum value FIFO WORD3 0x1AD [15:0] X R/W STAGE5_MAX_AVG STAGE5 average maximum FIFO value 0x1AE [15:0] X R/W STAGE5_HIGH_THRESHOLD STAGE5 high threshold value 0x1AF [15:0] X R/W STAGE5_MAX_TEMP STAGE5 temporary maximum value 0x1B0 [15:0] X R/W STAGE5_MIN_WORD0 STAGE5 minimum value FIFO WORD0 0x1B1 [15:0] X R/W STAGE5_MIN_WORD1 STAGE5 minimum value FIFO WORD1 0x1B2 [15:0] X R/W STAGE5_MIN_WORD2 STAGE5 minimum value FIFO WORD2 0x1B3 [15:0] X R/W STAGE5_MIN_WORD3 STAGE5 minimum value FIFO WORD3 0x1B4 [15:0] X R/W STAGE5_MIN_AVG STAGE5 average minimum FIFO value 0x1B5 [15:0] X R/W STAGE5_LOW_THRESHOLD STAGE5 low threshold value 0x1B6 [15:0] X R/W STAGE5_MIN_TEMP STAGE5 temporary minimum value 0x1B7 [15:0] X R/W Unused Set unused register bits = 0 Rev. B | Page 63 of 70

AD7142 Data Sheet Table 56. STAGE6 Results Registers Address Data Bit Default Value Type Name Description 0x1B8 [15:0] X R/W STAGE6_CONV_DATA STAGE6 CDC 16-bit conversion data (copy of data in STAGE6_CONV_DATA register) 0x1B9 [15:0] X R/W STAGE6_FF_WORD0 STAGE6 fast FIFO WORD0 0x1BA [15:0] X R/W STAGE6_FF_WORD1 STAGE6 fast FIFO WORD1 0x1BB [15:0] X R/W STAGE6_FF_WORD2 STAGE6 fast FIFO WORD2 0x1BC [15:0] X R/W STAGE6_FF_WORD3 STAGE6 fast FIFO WORD3 0x1BD [15:0] X R/W STAGE6_FF_WORD4 STAGE6 fast FIFO WORD4 0x1BE [15:0] X R/W STAGE6_FF_WORD5 STAGE6 fast FIFO WORD5 0x1BF [15:0] X R/W STAGE6_FF_WORD6 STAGE6 fast FIFO WORD6 0x1C0 [15:0] X R/W STAGE6_FF_WORD7 STAGE6 fast FIFO WORD7 0x1C1 [15:0] X R/W STAGE6_SF_WORD0 STAGE6 slow FIFO WORD0 0x1C2 [15:0] X R/W STAGE6_SF_WORD1 STAGE6 slow FIFO WORD1 0x1C3 [15:0] X R/W STAGE6_SF_WORD2 STAGE6 slow FIFO WORD2 0x1C4 [15:0] X R/W STAGE6_SF_WORD3 STAGE6 slow FIFO WORD3 0x1C5 [15:0] X R/W STAGE6_SF_WORD4 STAGE6 slow FIFO WORD4 0x1C6 [15:0] X R/W STAGE6_SF_WORD5 STAGE6 slow FIFO WORD5 0x1C7 [15:0] X R/W STAGE6_SF_WORD6 STAGE6 slow FIFO WORD6 0x1C8 [15:0] X R/W STAGE6_SF_WORD7 STAGE6 slow FIFO WORD7 0x1C9 [15:0] X R/W STAGE6_SF_AMBIENT STAGE6 slow FIFO ambient value 0x1CA [15:0] X R/W STAGE6_FF_AVG STAGE6 fast FIFO average value 0x1CB [15:0] X R/W STAGE6_CDC_WORD0 STAGE0 CDC FIFO WORD0 0x1CC [15:0] X R/W STAGE6_CDC_WORD1 STAGE6 CDC FIFO WORD1 0x1CD [15:0] X R/W STAGE6_MAX_WORD0 STAGE6 maximum value FIFO WORD0 0x1CE [15:0] X R/W STAGE6_MAX_WORD1 STAGE6 maximum value FIFO WORD1 0x1CF [15:0] X R/W STAGE6_MAX_WORD2 STAGE6 maximum value FIFO WORD2 0x1D0 [15:0] X R/W STAGE6_MAX_WORD3 STAGE6 maximum value FIFO WORD3 0x1D1 [15:0] X R/W STAGE6_MAX_AVG STAGE6 average maximum FIFO value 0x1D2 [15:0] X R/W STAGE6_HIGH_THRESHOLD STAGE6 high threshold value 0x1D3 [15:0] X R/W STAGE6_MAX_TEMP STAGE6 temporary maximum value 0x1D4 [15:0] X R/W STAGE6_MIN_WORD0 STAGE6 minimum value FIFO WORD0 0x1D5 [15:0] X R/W STAGE6_MIN_WORD1 STAGE6 minimum value FIFO WORD1 0x1D6 [15:0] X R/W STAGE6_MIN_WORD2 STAGE6 minimum value FIFO WORD2 0x1D7 [15:0] X R/W STAGE6_MIN_WORD3 STAGE6 minimum value FIFO WORD3 0x1D8 [15:0] X R/W STAGE6_MIN_AVG STAGE6 average minimum FIFO value 0x1D9 [15:0] X R/W STAGE6_LOW_THRESHOLD STAGE6 low threshold value 0x1DA [15:0] X R/W STAGE6_MIN_TEMP STAGE6 temporary minimum value 0x1DB [15:0] X R/W Unused Set unused register bits = 0 Rev. B | Page 64 of 70

Data Sheet AD7142 Table 57. STAGE7 Results Registers Address Data Bit Default Value Type Name Description 0x1DC [15:0] X R/W STAGE7_CONV_DATA STAGE7 CDC 16-bit conversion data (copy of data in STAGE7_CONV_DATA register) 0x1DD [15:0] X R/W STAGE7_FF_WORD0 STAGE7 fast FIFO WORD0 0x1DE [15:0] X R/W STAGE7_FF_WORD1 STAGE7 fast FIFO WORD1 0x1DF [15:0] X R/W STAGE7_FF_WORD2 STAGE7 fast FIFO WORD2 0x1E0 [15:0] X R/W STAGE7_FF_WORD3 STAGE7 fast FIFO WORD3 0x1E1 [15:0] X R/W STAGE7_FF_WORD4 STAGE7 fast FIFO WORD4 0x1E2 [15:0] X R/W STAGE7_FF_WORD5 STAGE7 fast FIFO WORD5 0x1E3 [15:0] X R/W STAGE7_FF_WORD6 STAGE7 fast FIFO WORD6 0x1E4 [15:0] X R/W STAGE7_FF_WORD7 STAGE7 fast FIFO WORD7 0x1E5 [15:0] X R/W STAGE7_SF_WORD0 STAGE7 slow FIFO WORD0 0x1E6 [15:0] X R/W STAGE7_SF_WORD1 STAGE7 slow FIFO WORD1 0x1E7 [15:0] X R/W STAGE7_SF_WORD2 STAGE7 slow FIFO WORD2 0x1E8 [15:0] X R/W STAGE7_SF_WORD3 STAGE7 slow FIFO WORD3 0x1E9 [15:0] X R/W STAGE7_SF_WORD4 STAGE7 slow FIFO WORD4 0x1EA [15:0] X R/W STAGE7_SF_WORD5 STAGE7 slow FIFO WORD5 0x1EB [15:0] X R/W STAGE7_SF_WORD6 STAGE7 slow FIFO WORD6 0x1EC [15:0] X R/W STAGE7_SF_WORD7 STAGE7 slow FIFO WORD7 0x1ED [15:0] X R/W STAGE7_SF_AMBIENT STAGE7 slow FIFO ambient value 0x1EE [15:0] X R/W STAGE7_FF_AVG STAGE7 fast FIFO average value 0x1EF [15:0] X R/W STAGE7_CDC_WORD0 STAGE7 CDC FIFO WORD0 0x1F0 [15:0] X R/W STAGE7_CDC_WORD1 STAGE7 CDC FIFO WORD1 0x1F1 [15:0] X R/W STAGE7_MAX_WORD0 STAGE7 maximum value FIFO WORD0 0x1F2 [15:0] X R/W STAGE7_MAX_WORD1 STAGE7 maximum value FIFO WORD1 0x1F3 [15:0] X R/W STAGE7_MAX_WORD2 STAGE7 maximum value FIFO WORD2 0x1F4 [15:0] X R/W STAGE7_MAX_WORD3 STAGE7 maximum value FIFO WORD3 0x1F5 [15:0] X R/W STAGE7_MAX_AVG STAGE7 average maximum FIFO value 0x1F6 [15:0] X R/W STAGE7_HIGH_THRESHOLD STAGE7 high threshold value 0x1F7 [15:0] X R/W STAGE7_MAX_TEMP STAGE7 temporary maximum value 0x1F8 [15:0] X R/W STAGE7_MIN_WORD0 STAGE7 minimum value FIFO WORD0 0x1F9 [15:0] X R/W STAGE7_MIN_WORD1 STAGE7 minimum value FIFO WORD1 0x1FA [15:0] X R/W STAGE7_MIN_WORD2 STAGE7 minimum value FIFO WORD2 0x1FB [15:0] X R/W STAGE7_MIN_WORD3 STAGE7 minimum value FIFO WORD3 0x1FC [15:0] X R/W STAGE7_MIN_AVG STAGE7 average minimum FIFO value 0x1FD [15:0] X R/W STAGE7_LOW_THRESHOLD STAGE7 low threshold value 0x1FE [15:0] X R/W STAGE7_MIN_TEMP STAGE7 temporary minimum value 0x1FF [15:0] X R/W Unused Set unused register bits = 0 Rev. B | Page 65 of 70

AD7142 Data Sheet Table 58. STAGE8 Results Registers Address Data Bit Default Value Type Name Description 0x200 [15:0] X R/W STAGE8_CONV_DATA STAGE8 CDC 16-bit conversion data (copy of data in STAGE8_CONV_DATA register) 0x201 [15:0] X R/W STAGE8_FF_WORD0 STAGE8 fast FIFO WORD0 0x202 [15:0] X R/W STAGE8_FF_WORD1 STAGE8 fast FIFO WORD1 0x203 [15:0] X R/W STAGE8_FF_WORD2 STAGE8 fast FIFO WORD2 0x204 [15:0] X R/W STAGE8_FF_WORD3 STAGE8 fast FIFO WORD3 0x205 [15:0] X R/W STAGE8_FF_WORD4 STAGE8 fast FIFO WORD4 0x206 [15:0] X R/W STAGE8_FF_WORD5 STAGE8 fast FIFO WORD5 0x207 [15:0] X R/W STAGE8_FF_WORD6 STAGE8 fast FIFO WORD6 0x208 [15:0] X R/W STAGE8_FF_WORD7 STAGE8 fast FIFO WORD7 0x209 [15:0] X R/W STAGE8_SF_WORD0 STAGE8 slow FIFO WORD0 0x20A [15:0] X R/W STAGE8_SF_WORD1 STAGE8 slow FIFO WORD1 0x20B [15:0] X R/W STAGE8_SF_WORD2 STAGE8 slow FIFO WORD2 0x20C [15:0] X R/W STAGE8_SF_WORD3 STAGE8 slow FIFO WORD3 0x20D [15:0] X R/W STAGE8_SF_WORD4 STAGE8 slow FIFO WORD4 0x20E [15:0] X R/W STAGE8_SF_WORD5 STAGE8 slow FIFO WORD5 0x20F [15:0] X R/W STAGE8_SF_WORD6 STAGE8 slow FIFO WORD6 0x210 [15:0] X R/W STAGE8_SF_WORD7 STAGE8 slow FIFO WORD7 0x211 [15:0] X R/W STAGE8_SF_AMBIENT STAGE8 slow FIFO ambient value 0x212 [15:0] X R/W STAGE8_FF_AVG STAGE8 fast FIFO average value 0x213 [15:0] X R/W STAGE8_CDC_WORD0 STAGE8 CDC FIFO WORD0 0x214 [15:0] X R/W STAGE8_CDC_WORD1 STAGE8 CDC FIFO WORD1 0x215 [15:0] X R/W STAGE8_MAX_WORD0 STAGE8 maximum value FIFO WORD0 0x216 [15:0] X R/W STAGE8_MAX_WORD1 STAGE8 maximum value FIFO WORD1 0x217 [15:0] X R/W STAGE8_MAX_WORD2 STAGE8 maximum value FIFO WORD2 0x218 [15:0] X R/W STAGE8_MAX_WORD3 STAGE8 maximum value FIFO WORD3 0x219 [15:0] X R/W STAGE8_MAX_AVG STAGE8 average maximum FIFO value 0x21A [15:0] X R/W STAGE8_HIGH_THRESHOLD STAGE8 high threshold value 0x21B [15:0] X R/W STAGE8_MAX_TEMP STAGE8 temporary maximum value 0x21C [15:0] X R/W STAGE8_MIN_WORD0 STAGE8 minimum value FIFO WORD0 0x21D [15:0] X R/W STAGE8_MIN_WORD1 STAGE8 minimum value FIFO WORD1 0x21E [15:0] X R/W STAGE8_MIN_WORD2 STAGE8 minimum value FIFO WORD2 0x21F [15:0] X R/W STAGE8_MIN_WORD3 STAGE8 minimum value FIFO WORD3 0x220 [15:0] X R/W STAGE8_MIN_AVG STAGE8 average minimum FIFO value 0x221 [15:0] X R/W STAGE8_LOW_THRESHOLD STAGE8 low threshold value 0x222 [15:0] X R/W STAGE8_MIN_TEMP STAGE7 temporary minimum value 0x223 [15:0] X R/W Unused Set unused register bits = 0 Rev. B | Page 66 of 70

Data Sheet AD7142 Table 59. STAGE9 Results Registers Address Data Bit Default Value Type Name Description 0x224 [15:0] X R/W STAGE9_CONV_DATA STAGE9 CDC 16-bit conversion data (copy of data in STAGE9_CONV_DATA register) 0x225 [15:0] X R/W STAGE9_FF_WORD0 STAGE9 fast FIFO WORD0 0x226 [15:0] X R/W STAGE9_FF_WORD1 STAGE9 fast FIFO WORD1 0x227 [15:0] X R/W STAGE9_FF_WORD2 STAGE9 fast FIFO WORD2 0x228 [15:0] X R/W STAGE9_FF_WORD3 STAGE9 fast FIFO WORD3 0x229 [15:0] X R/W STAGE9_FF_WORD4 STAGE9 fast FIFO WORD4 0x22A [15:0] X R/W STAGE9_FF_WORD5 STAGE9 fast FIFO WORD5 0x22B [15:0] X R/W STAGE9_FF_WORD6 STAGE9 fast FIFO WORD6 0x22C [15:0] X R/W STAGE9_FF_WORD7 STAGE9 fast FIFO WORD7 0x22D [15:0] X R/W STAGE9_SF_WORD0 STAGE9 slow FIFO WORD0 0x22E [15:0] X R/W STAGE9_SF_WORD1 STAGE9 slow FIFO WORD1 0x22F [15:0] X R/W STAGE9_SF_WORD2 STAGE9 slow FIFO WORD2 0x230 [15:0] X R/W STAGE9_SF_WORD3 STAGE9 slow FIFO WORD3 0x231 [15:0] X R/W STAGE9_SF_WORD4 STAGE9 slow FIFO WORD4 0x232 [15:0] X R/W STAGE9_SF_WORD5 STAGE9 slow FIFO WORD5 0x233 [15:0] X R/W STAGE9_SF_WORD6 STAGE9 slow FIFO WORD6 0x234 [15:0] X R/W STAGE9_SF_WORD7 STAGE9 slow FIFO WORD7 0x235 [15:0] X R/W STAGE9_SF_AMBIENT STAGE9 slow FIFO ambient value 0x236 [15:0] X R/W STAGE9_FF_AVG STAGE9 fast FIFO average value 0x237 [15:0] X R/W STAGE9_CDC_WORD0 STAGE9 CDC FIFO WORD0 0x238 [15:0] X R/W STAGE9_CDC_WORD1 STAGE9 CDC FIFO WORD1 0x239 [15:0] X R/W STAGE9_MAX_WORD0 STAGE9 maximum value FIFO WORD0 0x23A [15:0] X R/W STAGE9_MAX_WORD1 STAGE9 maximum value FIFO WORD1 0x23B [15:0] X R/W STAGE9_MAX_WORD2 STAGE9 maximum value FIFO WORD2 0x23C [15:0] X R/W STAGE9_MAX_WORD3 STAGE9 maximum value FIFO WORD3 0x23D [15:0] X R/W STAGE9_MAX_AVG STAGE9 average maximum FIFO value 0x23E [15:0] X R/W STAGE9_HIGH_THRESHOLD STAGE9 high threshold value 0x23F [15:0] X R/W STAGE9_MAX_TEMP STAGE9 temporary maximum value 0x240 [15:0] X R/W STAGE9_MIN_WORD0 STAGE9 minimum value FIFO WORD0 0x241 [15:0] X R/W STAGE9_MIN_WORD1 STAGE9 minimum value FIFO WORD1 0x242 [15:0] X R/W STAGE9_MIN_WORD2 STAGE9 minimum value FIFO WORD2 0x243 [15:0] X R/W STAGE9_MIN_WORD3 STAGE9 minimum value FIFO WORD3 0x244 [15:0] X R/W STAGE9_MIN_AVG STAGE9 average minimum FIFO value 0x245 [15:0] X R/W STAGE9_LOW_THRESHOLD STAGE9 low threshold value 0x246 [15:0] X R/W STAGE9_MIN_TEMP STAGE9 temporary minimum value 0x247 [15:0] X R/W Unused Set unused register bits = 0 Rev. B | Page 67 of 70

AD7142 Data Sheet Table 60. STAGE10 Results Registers Address Data Bit Default Value Type Name Description 0x248 [15:0] X R/W STAGE10_CONV_DATA STAGE10 CDC 16-bit conversion data (copy of data in STAGE10_CONV_DATA register) 0x249 [15:0] X R/W STAGE10_FF_WORD0 STAGE10 fast FIFO WORD0 0x24A [15:0] X R/W STAGE10_FF_WORD1 STAGE10 fast FIFO WORD1 0x24B [15:0] X R/W STAGE10_FF_WORD2 STAGE10 fast FIFO WORD2 0x24C [15:0] X R/W STAGE10_FF_WORD3 STAGE10 fast FIFO WORD3 0x24D [15:0] X R/W STAGE10_FF_WORD4 STAGE10 fast FIFO WORD4 0x24E [15:0] X R/W STAGE10_FF_WORD5 STAGE10 fast FIFO WORD5 0x24F [15:0] X R/W STAGE10_FF_WORD6 STAGE10 fast FIFO WORD6 0x250 [15:0] X R/W STAGE10_FF_WORD7 STAGE10 fast FIFO WORD7 0x251 [15:0] X R/W STAGE10_SF_WORD0 STAGE10 slow FIFO WORD0 0x252 [15:0] X R/W STAGE10_SF_WORD1 STAGE10 slow FIFO WORD1 0x253 [15:0] X R/W STAGE10_SF_WORD2 STAGE10 slow FIFO WORD2 0x254 [15:0] X R/W STAGE10_SF_WORD3 STAGE10 slow FIFO WORD3 0x255 [15:0] X R/W STAGE10_SF_WORD4 STAGE10 slow FIFO WORD4 0x256 [15:0] X R/W STAGE10_SF_WORD5 STAGE10 slow FIFO WORD5 0x257 [15:0] X R/W STAGE10_SF_WORD6 STAGE10 slow FIFO WORD6 0x258 [15:0] X R/W STAGE10_SF_WORD7 STAGE10 slow FIFO WORD7 0x259 [15:0] X R/W STAGE10_SF_AMBIENT STAGE10 slow FIFO ambient value 0x25A [15:0] X R/W STAGE10_FF_AVG STAGE10 fast FIFO average value 0x25B [15:0] X R/W STAGE10_CDC_WORD0 STAGE10 CDC FIFO WORD0 0x25C [15:0] X R/W STAGE10_CDC_WORD1 STAGE10 CDC FIFO WORD1 0x25D [15:0] X R/W STAGE10_MAX_WORD0 STAGE10 maximum value FIFO WORD0 0x25E [15:0] X R/W STAGE10_MAX_WORD1 STAGE10 maximum value FIFO WORD1 0x25F [15:0] X R/W STAGE10_MAX_WORD2 STAGE10 maximum value FIFO WORD2 0x260 [15:0] X R/W STAGE10_MAX_WORD3 STAGE10 maximum value FIFO WORD3 0x261 [15:0] X R/W STAGE10_MAX_AVG STAGE10 average maximum FIFO value 0x262 [15:0] X R/W STAGE10_HIGH_THRESHOLD STAGE10 high threshold value 0x263 [15:0] X R/W STAGE10_MAX_TEMP STAGE10 temporary maximum value 0x264 [15:0] X R/W STAGE10_MIN_WORD0 STAGE10 minimum value FIFO WORD0 0x265 [15:0] X R/W STAGE10_MIN_WORD1 STAGE10 minimum value FIFO WORD1 0x266 [15:0] X R/W STAGE10_MIN_WORD2 STAGE10 minimum value FIFO WORD2 0x267 [15:0] X R/W STAGE10_MIN_WORD3 STAGE10 minimum value FIFO WORD3 0x268 [15:0] X R/W STAGE10_MIN_AVG STAGE10 average minimum FIFO value 0x269 [15:0] X R/W STAGE10_LOW_THRESHOLD STAGE10 low threshold value 0x26A [15:0] X R/W STAGE10_MIN_TEMP STAGE10 temporary minimum value 0x26B [15:0] X R/W Unused Set unused register bits = 0 Rev. B | Page 68 of 70

Data Sheet AD7142 Table 61. STAGE11 Results Registers Address Data Bit Default Value Type Name Description 0x26C [15:0] X R/W STAGE11_CONV_DATA STAGE11 CDC 16-bit conversion data (copy of data in STAGE11_CONV_DATA register) 0x26D [15:0] X R/W STAGE11_FF_WORD0 STAGE11 fast FIFO WORD0 0x26E [15:0] X R/W STAGE11_FF_WORD1 STAGE11 fast FIFO WORD1 0x26F [15:0] X R/W STAGE11_FF_WORD2 STAGE11 fast FIFO WORD2 0x270 [15:0] X R/W STAGE11_FF_WORD3 STAGE11 fast FIFO WORD3 0x271 [15:0] X R/W STAGE11_FF_WORD4 STAGE11 fast FIFO WORD4 0x272 [15:0] X R/W STAGE11_FF_WORD5 STAGE11 fast FIFO WORD5 0x273 [15:0] X R/W STAGE11_FF_WORD6 STAGE11 fast FIFO WORD6 0x274 [15:0] X R/W STAGE11_FF_WORD7 STAGE11 fast FIFO WORD7 0x275 [15:0] X R/W STAGE11_SF_WORD0 STAGE11 slow FIFO WORD0 0x276 [15:0] X R/W STAGE11_SF_WORD1 STAGE11 slow FIFO WORD1 0x277 [15:0] X R/W STAGE11_SF_WORD2 STAGE11 slow FIFO WORD2 0x278 [15:0] X R/W STAGE11_SF_WORD3 STAGE11 slow FIFO WORD3 0x279 [15:0] X R/W STAGE11_SF_WORD4 STAGE11 slow FIFO WORD4 0x27A [15:0] X R/W STAGE11_SF_WORD5 STAGE11 slow FIFO WORD5 0x27B [15:0] X R/W STAGE11_SF_WORD6 STAGE11 slow FIFO WORD6 0x27C [15:0] X R/W STAGE11_SF_WORD7 STAGE11 slow FIFO WORD7 0x27D [15:0] X R/W STAGE11_SF_AMBIENT STAGE11 slow FIFO ambient value 0x27E [15:0] X R/W STAGE11_FF_AVG STAGE11 fast FIFO average value 0x27F [15:0] X R/W STAGE11_CDC_WORD0 STAGE11 CDC FIFO WORD0 0x280 [15:0] X R/W STAGE11_CDC_WORD1 STAGE11 CDC FIFO WORD1 0x281 [15:0] X R/W STAGE11_MAX_WORD0 STAGE11 maximum value FIFO WORD0 0x282 [15:0] X R/W STAGE11_MAX_WORD1 STAGE11 maximum value FIFO WORD1 0x283 [15:0] X R/W STAGE11_MAX_WORD2 STAGE11 maximum value FIFO WORD2 0x284 [15:0] X R/W STAGE11_MAX_WORD3 STAGE11 maximum value FIFO WORD3 0x285 [15:0] X R/W STAGE11_MAX_AVG STAGE11 average maximum FIFO value 0x286 [15:0] X R/W STAGE11_HIGH_THRESHOLD STAGE11 high threshold value 0x287 [15:0] X R/W STAGE11_MAX_TEMP STAGE11 temporary maximum value 0x288 [15:0] X R/W STAGE11_MIN_WORD0 STAGE11 minimum value FIFO WORD0 0x289 [15:0] X R/W STAGE11_MIN_WORD1 STAGE11 minimum value FIFO WORD1 0x28A [15:0] X R/W STAGE11_MIN_WORD2 STAGE11 minimum value FIFO WORD2 0x28B [15:0] X R/W STAGE11_MIN_WORD3 STAGE11 minimum value FIFO WORD3 0x28C [15:0] X R/W STAGE11_MIN_AVG STAGE11 average minimum FIFO value 0x28D [15:0] X R/W STAGE11_LOW_THRESHOLD STAGE11 low threshold value 0x28E [15:0] X R/W STAGE11_MIN_TEMP STAGE11 temporary minimum value 0x28F [15:0] X R/W Unused Set unused register bits = 0 Rev. B | Page 69 of 70

AD7142 Data Sheet OUTLINE DIMENSIONS DETAIL A 5.10 0.30 (JEDEC 95) 5.00 SQ 0.25 PIN 1 4.90 0.18 INDICATOR 25 32 IPNIND I1CATOR AREA OPTIONS 24 1 (SEE DETAIL A) 0.50 BSC 3.25 EXPOSED 3.10 SQ PAD 2.95 17 8 0.50 16 9 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 0.80 FOR PROPER CONNECTION OF 00..7750 SIDE VIEW 0.05 MAX TTHHEE EPXINP COOSENDFI GPAUDR,A RTEIOFNE RA NTOD 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF PKG-003898 COMPLIANT TO JEDEC STANDARDS MO-220-WHHD 02-22-2017-A Figure 60. 32-Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm and 0.75 mm Package Height (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Serial Interface Description Package Description Package Option AD7142ACPZ-REEL –40°C to +85°C SPI Interface 32-Lead LFCSP CP-32-7 AD7142ACPZ-500RL7 –40°C to +85°C SPI Interface 32-Lead LFCSP CP-32-7 AD7142ACPZ-1REEL –40°C to +85°C I2C Interface 32-Lead LFCSP CP-32-7 AD7142ACPZ-1500RL7 –40°C to +85°C I2C Interface 32-Lead LFCSP CP-32-7 1 Z = RoHS Compliant Part I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors. ©2006–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05702-0-9/17(B) Rev. B | Page 70 of 70

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD7142ACPZ-1500RL7 AD7142ACPZ-1REEL AD7142ACPZ-REEL AD7142ACPZ-500RL7