Precision, Low Cost, High Speed BiFET Dual Op Amp Data Sheet AD712 FEATURES CONNECTION DIAGRAM Enhanced replacement for LF412 and TL082 AMPLIFIERNO.1 AMPLIFIERNO.2 AC performance OUTPUT 1 8 V+ Settles to ±0.01% in 1.0 μs INVERINTPINUGT 2 7 OUTPUT 16 V/μs minimum slew rate (AD712J) 3 MHz minimum unity-gain bandwidth (AD712J) NONINVERINTPINUGT 3 6 IINNVPEURTTING DC2 p0e0r Vfo/mrmVa mncine imum open-loop gain (AD712K) V– 4 AD712 5 NINOPNUITNVERTING 00823-001 Figure 1. 8-Lead PDIP (N-Suffix), Surface mount available in tape and reel in SOIC_N (R-Suffix), and CERDIP (Q-Suffix) accordance with the EIA-481A standard MIL-STD-883B parts available Single version available: AD711 Quad version: AD713 Available in PDIP, SOIC_N, and CERDIP packages GENERAL DESCRIPTION The AD712 is a high speed, precision, monolithic operational Extended reliability PLUS screening is available, specified amplifier offering high performance at very modest prices. The over the commercial and industrial temperature ranges. PLUS very low offset voltage and offset voltage drift are the results of screening includes 168-hour burn-in, in addition to other advanced laser wafer trimming technology. These performance environmental and physical tests. benefits allow the user to easily upgrade existing designs that The AD712 is available in 8-lead PDIP, SOIC_N, and CERDIP use older precision BiFETs and, in many cases, bipolar op amps. packages. The superior ac and dc performance of this op amp makes it PRODUCT HIGHLIGHTS suitable for active filter applications. With a slew rate of 16 V/μs and a settling time of 1 μs to ±0.01%, the AD712 is ideal as a 1. The AD712 offers excellent overall performance at very buffer for 12-bit digital-to-analog converters (DACs) and analog- competitive prices. to-digital converters (ADCs) and as a high speed integrator. 2. The Analog Devices, Inc., advanced processing technology The settling time is unmatched by any similar IC amplifier. and 100% testing guarantee a low input offset voltage (3 mV maximum, J grade). Input offset voltage is specified in the The combination of excellent noise performance and low input warmed-up condition. current also make the AD712 useful for photo diode preamps. 3. Together with precision dc performance, the AD712 offers Common-mode rejection of 88 dB and open-loop gain of excellent dynamic response. It settles to ±0.01% in 1 μs and 400 V/mV ensure 12-bit performance even in high speed has a minimum slew rate of 16 V/μs. Thus, this device is unity-gain buffer circuits. ideal for applications such as DAC and ADC buffers that require a combination of superior ac and dc performance. The AD712 is pinned out in a standard op amp configuration and is available in seven performance grades. The AD712J and AD712K are rated over the commercial temperature range of 0°C to 70°C. The AD712A is rated over the industrial tempera- ture range of −40°C to +85°C. The AD712S is rated over the military temperature range of −55°C to +125°C and is available processed to MIL-STD-883B, Rev. C. Rev. I Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©1986–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD712 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 14 Connection Diagram ....................................................................... 1 Guarding ...................................................................................... 14 General Description ......................................................................... 1 DAC Converter Applications .................................................... 14 Product Highlights ........................................................................... 1 Noise Characteristics ................................................................. 15 Revision History ............................................................................... 2 Driving the Analog Input of an ADC ...................................... 15 Specifications ..................................................................................... 3 Driving a Large Capacitive Load .............................................. 16 Absolute Maximum Ratings ............................................................ 5 Filters ................................................................................................ 17 Thermal Resistance ...................................................................... 5 Active Filter Applications .......................................................... 17 ESD Caution .................................................................................. 5 Second-Order Low-Pass Filter.................................................. 17 Typical Performance Characteristics ............................................. 6 9-Pole Chebychev Filter ............................................................. 18 Settling Time ................................................................................... 11 Outline Dimensions ....................................................................... 19 Optimizing Settling Time .......................................................... 11 Ordering Guide .......................................................................... 20 Op Amp Settling Time—A Mathematical Model .................. 12 REVISION HISTORY 7/2002—Rev. D to Rev. E 11/2018—Rev. H to Rev. I Edits to Features ................................................................................. 1 Added Thermal Resistance Section and Table 3 .......................... 5 Changes to Table 2 ............................................................................ 5 9/2001—Rev. C to Rev. D Changes to Ordering Guide .......................................................... 20 Edits to Features ................................................................................. 1 Edits to General Description ........................................................... 1 7/2010—Rev. G to Rev. H Edits to Connection Diagram .......................................................... 1 Changes to Product Title ................................................................. 1 Edits to Ordering Guide ................................................................... 3 Added Input Voltage Noise Parameter, Input Current Noise Deleted Metallization Photograph .................................................. 3 Parameter, and Open-Loop Gain Parameter, Table 1 .................. 4 Edits to Absolute Maximum Ratings ............................................. 3 Moved Figure 29 and Figure 30 .................................................... 11 Edits to Figure 7 ................................................................................. 9 Moved Figure 34 ............................................................................. 12 Edits to Outline Dimensions ......................................................... 15 Moved Figure 44 and Figure 45 .................................................... 15 Changes to Ordering Guide .......................................................... 20 8/2006—Rev. F to Rev. G Edits to Figure 1 ................................................................................ 1 Change to 9-Pole Chebychev Filter Section ................................ 18 6/2006—Rev. E to Rev. F Updated Format .................................................................. Universal Deleted B, C, and T Models............................................... Universal Changes to General Description .................................................... 1 Changes to Product Highlights ....................................................... 1 Changes to Specifications Section .................................................. 3 Changes to Figure 43 ...................................................................... 15 Rev. I | Page 2 of 20

Data Sheet AD712 SPECIFICATIONS V = ±15 V at T = 25°C, unless otherwise noted. Specifications in boldface are tested on all production units at final electrical test. S A Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed, although only those shown in boldface are tested on all production units. Table 1. AD712J/AD712A/AD712S AD712K Parameter Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE1 Initial Offset 0.3 3/1/1 0.2 1.0 mV TMIN to TMAX 4/2/2 2.0 mV vs. Temperature 7 20/20/20 7 10 μV/°C vs. Supply 76 95 80 100 dB TMIN to TMAX 76/76/76 80 dB Long-Term Offset Stability 15 15 µV/month INPUT BIAS CURRENT2 VCM = 0 V 25 75 20 75 pA V = 0 V at T 0.6/1.6/26 1.7/4.8/77 0.5 1.7 nA CM MAX VCM = ±10 V 100 100 pA INPUT OFFSET CURRENT VCM = 0 V 10 25 5 25 pA V = 0 V at T 0.3/0.7/11 0.6/1.6/26 0.1 0.6 nA CM MAX MATCHING CHARACTERISTICS Input Offset Voltage 3/1/1 1.0 mV TMIN to TMAX 4/2/2 2.0 mV Input Offset Voltage Drift 20/20/20 10 µV/°C Input Bias Current 25 25 pA Crosstalk At f = 1 kHz 120 120 dB At f = 100 kHz 90 90 dB FREQUENCY RESPONSE Small Signal Bandwidth 3.0 4.0 3.4 4.0 MHz Full Power Response 200 200 kHz Slew Rate 16 20 18 20 V/µs Settling Time to 0.01% 1.0 1.2 1.0 1.2 µs Total Harmonic Distortion 0.0003 0.0003 % INPUT IMPEDANCE Differential 3×1012||5.5 3×1012||5.5 Ω||pF Common Mode 3×1012||5.5 3×1012||5.5 Ω||pF INPUT VOLTAGE RANGE Differential3 ±20 ±20 V Common-Mode Voltage4 +14.5, −11.5 +14.5, −11.5 V TMIN to TMAX −VS + 4 +VS − 2 −VS + 4 +VS − 2 V Common-Mode Rejection Ratio VCM = ±10 V 76 88 80 88 dB TMIN to TMAX 76/76/76 84 80 84 dB VCM = ±11 V 70 84 76 84 dB TMIN to TMAX 70/70/70 80 74 80 dB Rev. I | Page 3 of 20

AD712 Data Sheet AD712J/AD712A/AD712S AD712K Parameter Min Typ Max Min Typ Max Unit INPUT VOLTAGE NOISE f = 0.1 Hz to 10 Hz 2 2 µV p-p f = 10 Hz 45 45 nV/√Hz f = 100 Hz 22 22 nV/√Hz f = 1 kHz 18 18 nV/√Hz f = 10 kHz 16 16 nV/√Hz INPUT CURRENT NOISE f = 1 kHz 0.01 0.01 pA/√Hz OPEN-LOOP GAIN VOUT = −10 V to +10 V 150 400 200 400 V/mV TMIN to TMAX 100/100/100 100 V/mV OUTPUT CHARACTERISTICS Voltage +13, −12.5 +13.9, −13.3 +13, −12.5 +13.9, −13.3 V ±12/±12/±12 +13.8, −13.1 ±12 +13.8, −13.1 V Current +25 +25 mA POWER SUPPLY Rated Performance ±15 ±15 V Operating Range ±4.5 ±18 ±4.5 ±18 V Quiescent Current +5.0 +6.8 +5.0 +6.0 mA 1 Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = 25°C. 2 Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = 25°C. For higher temperatures, the current doubles every 10°C. 3 Defined as voltage between inputs, such that neither exceeds ±10 V from ground. 4 Typically exceeding −14.1 V negative common-mode voltage on either input results in an output phase reversal. Rev. I | Page 4 of 20

Data Sheet AD712 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Rating Thermal performance is directly linked to printed circuit board Supply Voltage ±18 V (PCB) design and operating environment. Careful attention to Internal Power Dissipation1 PCB thermal design is required. Input Voltage2 ±18 V Output Short-Circuit Duration Indefinite Table 3. Differential Input Voltage +VS and −VS Package Type θJA θJC Unit Storage Temperature Range 8-Lead PDIP 165 °C/W Q-Suffix −65°C to +150°C 8-Lead CERDIP 110 22 °C/W N-Suffix and R-Suffix −65°C to +125°C 8-Lead SOIC 120 °C/W Operating Temperature Range ESD CAUTION AD712J/K 0°C to 70°C AD712A −40°C to +85°C AD712S −55°C to +125°C Lead Temperature Range (Soldering 60 sec) 300°C 1 See Table 3. 2 For supply voltages less than ±18 V, the absolute maximum voltage is equal to the supply voltage. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. I | Page 5 of 20

AD712 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 20 6 WING (V)15 NT (mA) 5 E S RRE AG10 CU 4 T VOLT R25L°=C 2kΩ SCENT U E INP 5 QUI 3 00 5 SUPPLY VO10LTAGE ± V 15 20 00823-002 20 5 SUPPLY VO10LTAGE ± V 15 20 00823-005 Figure 2. Input Voltage Swing vs. Supply Voltage Figure 5. Quiescent Current vs. Supply Voltage 20 106 s) E SWING (V)15 +VOUT –VOUT V = 0) (AmpCM110078 TPUT VOLTAG10 R25L°=C 2kΩ AS CURRENT (1100109 U 5 BI O T PU1011 N I 00 5 SUPPLY V1O0LTAGE ± V 15 20 00823-003 1012–60 –40 –20 0 TEM20PERA4T0URE6 (0°C) 80 100 120 140 00823-006 Figure 3. Output Voltage Swing vs. Supply Voltage Figure 6. Input Bias Current vs. Temperature 30 100 p) 25 p- WING (V 20 NCE (Ω) 10 S ±15V SUPPLIES A GE 15 PED1.0 A M OLT UT I UT V 10 UTP P O0.1 T U O 5 010 1L0O0AD RESISTANCE (1Ωk) 10k 00823-004 0.011k 10k FREQU1E0N0kCY (Hz) 1M 10M 00823-007 Figure 4. Output Voltage Swing vs. Load Resistance Figure 7. Output Impedance vs. Frequency Rev. I | Page 6 of 20

Data Sheet AD712 100 100 100 MAX J GRADE LIMIT 80 80 RRENT (pA) 75 V25S° C= 15V GAIN (dB) 60 60 N (Degrees) S CU 50 OOP 40 GAIN 40 ARGI PUT BIA OPEN-L 20 P21k0H0ΩApSFE 20 HASE M N 25 LOAD P I 0 0 0–10 –5COMMON MOD0E VOLTAGE (V)5 10 00823-008 –2010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M–20 00823-011 Figure 8. Input Bias Current vs. Common-Mode Voltage Figure 11. Open-Loop Gain and Phase Margin vs. Frequency 26 125 A) 24 m 120 T ( 22 + OUTPUT CURRENT ENT LIMI 20 AIN (dB)115 RL= 2kΩ CURR 18 OP G110 25°C CIRCUIT 16 – OUTPUT CURRENT OPEN-LO105 T- 14 R HO 100 S 12 10–60 –40 –20 AM0BIEN2T0 TEM4P0ERA6T0URE (8°0C) 100 120 140 00823-009 950 5 SUPPLY VO10LTAGE ± V 15 20 00823-012 Figure 9. Short-Circuit Current Limit vs. Temperature Figure 12. Open-Loop Gain vs. Supply Voltage 5.0 110 100 B) d H (MHz)4.5 CTION ( 80 + SUPPLY WIDT REJE D Y 60 AN4.0 PL GAIN B ER SUP 40 – SUPPLY Y- W NIT3.5 PO U 20 VS = ±15V SUPPLIES WITH 1V p-p SINEWAVE 25°C 3.0–60 –40 –20 0 TE2M0PERA40TURE6 0(°C) 80 100 120 140 00823-010 010 S10U0PPLY MOD1UkLATION F1R0EkQUENCY 1(H00zk) 1M 00823-013 Figure 10. Unity-Gain Bandwidth vs. Temperature Figure 13. Power Supply Rejection vs. Frequency Rev. I | Page 7 of 20

AD712 Data Sheet 100 –70 VS = ±15V VCM = 1V p-p –80 80 25°C 3V rms RL = 2kΩ –90 CL = 100pF 60 B) B) d d R ( D ( –100 M H C40 T –110 20 –120 010 100 FR1kEQUENCY 1(0Hkz) 100k 1M 00823-014 –130100 1kFREQUENCY (Hz)10k 100k 00823-017 Figure 14. Common-Mode Rejection vs. Frequency Figure 17. Total Harmonic Distortion vs. Frequency 30 1k RL= 2kΩ 25°C p-p) 25 VS = ±15V Hz) WING (V 20 GE (nV/√100 S A LTAGE 15 E VOLT O S T V 10 NOI 10 OUTPU 5 INPUT 1000k FREQU1EMNCY (Hz) 10M 00823-015 11 10 FR10E0QUENCY (H1kz) 10k 100k 00823-018 Figure 15. Large Signal Frequency Response Figure 18. Input Noise Voltage Spectral Density 10 25 8 S T OL 6 20 V ± O 4 V T µs) NG FROM 0 –202 ERROR1%1%0.1%0.1%0.010%.01% W RATE (V/1105 WI LE T S –4 S U TP –6 5 U O –8 –100.5 0.6 SE0T.T7LING TIME0. 8(µs) 0.9 1.0 00823-016 00 100 200 IN(A3P0TU0 TS UEMR4MR00OINRG S 5JI0UG0NNCATL6I O(0m0NV)) 700 800 900 00823-019 Figure 16. Output Swing and Error vs. Settling Time Figure 19. Slew Rate vs. Input Error Signal Rev. I | Page 8 of 20

Data Sheet AD712 25 +VS 0.1µF µs) – 8 TE (V/ AD17/212 VOUT W RA20 VIN + 4 0.1µF R2kLΩ C10L0pF E L S SWINQAPUVUAETRE –VS 00823-023 15–60 –40 –20 0 TEM20PERA4T0URE6 (0°C) 80 100 120 140 00823-020 Figure 20. Slew Rate vs. Temperature Figure 23. Unity-Gain Follower +VS 0.1µF + 8 100 1/2 90 INPUT AD712 OUTPUT – 2kΩ 100pF 4 0.1µF –VS 00823-021 10 0% 5V 1µs 00823-024 Figure 21. THD Test Circuit Figure 24. Unity-Gain Follower Pulse Response (Large Signal) VOUT 100 +VS 20kΩ 2.2kΩ 90 2 – 8 – 6 1/2 1 7 1/2 20V p-p AD712 AD712 3 + + 5 5kΩ 5kΩ VIN 4 CROSSTALK = 20 log1V0OVUITN –VS 00823-022 01%0 50mV 100ns 00823-025 Figure 22. Crosstalk Test Circuit Figure 25. Unity-Gain Follower Pulse Response (Small Signal) Rev. I | Page 9 of 20

AD712 Data Sheet 5kΩ +VS 0.1µF 100 90 VIN 5kΩ – 8 1/2 VOUT AD712 SQUARE + RL CL WAVE 4 0.1µF 2kΩ 100pF INPUT –VS 00823-026 01%0 50mV 200ns 00823-028 Figure 26. Unity-Gain Inverter Figure 28. Unity-Gain Inverter Pulse Response (Small Signal) 100 90 10 0% 5V 1µs 00823-027 Figure 27. Unity-Gain Inverter Pulse Response (Large Signal) Rev. I | Page 10 of 20

Data Sheet AD712 SETTLING TIME OPTIMIZING SETTLING TIME Therefore, with an ideal op amp, settling to ±1/2 LSB (±0.01%) requires that 375 µV or less appears at the summing junction. Most bipolar high speed DACs have current outputs; therefore, This means that the error between the input and output (that for most applications, an external op amp is required for a current- voltage which appears at the AD712 summing junction) must to-voltage conversion. The settling time of the converter/op amp be less than 375 µV. As shown in Figure 29, the total settling combination depends on the settling time of the DAC and output time for the AD712/AD565A combination is 1.2 microseconds. amplifier. A good approximation is ( ) ( ) t Total= t DAC2+ t AMP 2 S S S 1mV 5V The settling time of an op amp DAC buffer varies with the noise 100 gain of the circuit, the DAC output capacitance, and the amount 90 of external compensation capacitance across the DAC output SUMMING scaling resistor. JUNCTION Settling time for a bipolar DAC is typically 100 ns to 500 ns. 0V Previously, conventional op amps have required much longer settling times than have typical state-of-the-art DACs; therefore, 10 OUTPUT the amplifier settling time has been the major limitation to a high 0% –10V ospf etehde, AvoDlt7a1gex ofaumtpiulyt, odfi goitpa la-mtop-asn waliothg ftuhneicrt i1o nμ.s T (htoe ±in0t.r0o1d%uc otifo n 500ns 00823-030 final value) settling time permits the full high speed capabilities Figure 29. Settling Characteristics for AD712 with AD565A, Full-Scale Negative Transition of most modern DACs to be realized. In addition to a significant improvement in settling time, the 1mV 5V low offset voltage, low offset voltage drift, and high open-loop gain of the AD71x family assure 12-bit accuracy over the full 100 90 operating temperature range. SUMMING The excellent high speed performance of the AD712 is shown in JUNCTION the oscilloscope photos in Figure 29 and Figure 30. Measurements were taken using a low input capacitance amplifier connected 0V directly to the summing junction of the AD712, and both figures OUTPUT 10 show a worst-case situation: full-scale input transition. The 4 kΩ 0% [10 kΩ||8 kΩ = 4.4 kΩ] output impedance of the DAC, together –10V w3.i2t5h. aT 1h0e kcuΩr rfeenedt boauctkp urte sfirsotmor ,t phreo DduAcCe panro odpu caems pa n1o0i Vse sgtaeipn aot f 500ns 00823-031 Figure 30. Settling Characteristics for AD712 with AD565A, the op amp output (0 to −10 V shown in Figure 29, and −10 V to Full-Scale Positive Transition 0 V shown in Figure 30). 0.1µF BIPOLAR OFFSET ADJUST R1 R2 ROEUFT VCC 100Ω BIPOLOAFRF GAIN 100Ω 20V SPAN ADJUST + – 10V AD565A 9.95kΩ 5kΩ 10V 10pF +15V REINF 19.95kΩ 0.5mA SPAN 0.1µF 5kΩ DAC IREF OUT – 8 DAC GRNEDF 20kΩ IOUT = 4 × IO 8kΩ AD17/212 O–1U0TVP TUOT +10V IREF × CODE + 4 0.1µF POWER –VEE GND MSB LSB –15V 0.1µF 00823-029 Figure 31. ±10 V Voltage Output Bipolar DAC Rev. I | Page 11 of 20

AD712 Data Sheet OP AMP SETTLING TIME—A MATHEMATICAL When R and I are replaced with their Thevenin V and R O O IN IN MODEL equivalents, the general-purpose inverting amplifier shown in Figure 33 is created. Note that when using this general model, The design of the AD712 gives careful attention to optimizing Capacitance C is either the input capacitance of the op amp, if individual circuit components; in addition, a careful trade-off X a simple inverting op amp is being simulated or the combined was made: the gain bandwidth product (4 MHz) and slew rate capacitance of the DAC output and the op amp input if the (20 V/µs) were chosen to be high enough to provide very fast DAC buffer is being modeled. settling time but not too high to cause a significant reduction in phase margin (and therefore, stability). Thus designed, the + AD712 settles to ±0.01%, with a 10 V output step, in under 1 µs, 1/2 AD712 VOUT while retaining the ability to drive a 250 pF load capacitance – CF RL CL when operating as a unity-gain follower. RIN R If an op amp is modeled as an ideal integrator with a unity-gain cdreosscsroibveesr tfhreeq sumenalcly s iogfn ωalO /b2eπh,a tvhieonr oEfq tuhaet icoinrc 1u iatc ocfu Fraigteulrye 32, VIN CX 00823-033 consisting of an op amp connected as an I-to-V converter at the Figure 33. Simplified Model of the AD712 Used as an Inverter output of a bipolar or CMOS DAC. This equation would com- In either case, Capacitance C causes the system to go from a X pletely describe the output of the system if not for the finite slew one-pole to a two-pole response; this additional pole increases rate and other nonlinear effects of the op amp. settling time by introducing peaking or ringing in the op amp VO = −R (1) output. Because the value of CX can be estimated with reasonable I R(C ) G  accuracy, Equation 2 can be used to choose a small capacitor IN X s2+ N +RC s+1 ω ω f (CF) to cancel the input pole and optimize amplifier response. O O Figure 34 is a graphical solution of Equation 2 for the AD712 Where with R = 4 kΩ. ω 60 O = unity-gain frequency of the op amp. 2π  R  50 GN = noise gain of circuit 1+ .  R  O 40 GN= 4.0 This equation can then be solved for C f CX30 2−G RC ω +(1−G ) GN= 3.0 CX = Rω N +2 X ORω N (2) 20 GN= 2.0 O O GN= 1.5 In these equations, Capacitance CX is the total capacitance 10 GN= 1.0 appearing at the inverting terminal of the op amp. When mcirocdueitli snhgo aw DnA inC F biuguffreer 3a2p pclainca btieo uns, etdh ed Nireocrttloyn; Ceqaupiavcailteanntc e CX 00 10 20 C30F 40 50 60 00823-034 is the total capacitance of the output of the DAC plus the input Figure 34. Value of Capacitor CF vs. Value of CX capacitance of the op amp (because the two are in parallel). + 1/2 AD712 VOUT – CF RL CL R IO RO CX 00823-032 Figure 32. Simplified Model of the AD712 Used as a Current-Out DAC Buffer Rev. I | Page 12 of 20

Data Sheet AD712 The photos of Figure 35 and Figure 36 show the dynamic response of the AD712 in the settling test circuit of Figure 37. 5V 100 5V 90 100 90 10 0% 01%0 5mV 500ns 00823-036 Figure 36. Settling Characteristics 0 V to −10 V Step 5mV 500ns 00823-035 ULpopweer rT Traraccee: :O Aumtppulitf ioefd A EDrr7o1r2 V Uonltdaegre T (e0s.0t 1(5% V/D/Diviv) ) Figure 35. Settling Characteristics 0 V to +10 V Step Upper Trace: Output of AD712 Under Test (5 V/Div) The input of the settling time fixture is driven by a flat top pulse Lower Trace: Amplified Error Voltage (0.01%/Div) generator. The error signal output from the false summing node of A1 is clamped, amplified by A2, and then clamped again. The error signal is thus clamped twice: once to prevent overloading Amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. The Tektronix oscilloscope preamp type 7A26 was carefully chosen because it does not overload with these input levels. Amplifier A2 needs to be a very high speed FET-input op amp; it provides a gain of 10, amplifying the error signal output of A1. 5pF TEKTRONIX 7A26 OSCILLOSCOPE PREAMP + 1/2 205Ω VERROR × 5 INPUT SECTION AD712 HP2835 – 1MΩ 20pF HP2835 0.47µF 0.47µF 4.99kΩ 4.99kΩ 200Ω –15V +15V 5 TO 18pF DATA 10kΩ DYNAMICS 5109 10kΩ 1.1kΩ VIN 10kΩ 0.2 TO 0.6pF – 1/2 AD712 VOUT + 5kΩ 10pF (OR EQUIVALENT FLAT TOP PULSE GENERATION) 0.1µF 0.1µF –15V +15V 00823-037 Figure 37. Settling Time Test Circuit Rev. I | Page 13 of 20

AD712 Data Sheet APPLICATIONS INFORMATION GUARDING Figure 39 and Figure 40 show the AD712 and AD7545 (12-bit CMOS DAC) configured for unipolar binary (2-quadrant multi- The low input bias current (15 pA) and low noise characteristics plication) or bipolar (4-quadrant multiplication) operation. of the AD712 BiFET op amp make it suitable for electrometer Capacitor C1 provides phase compensation to reduce overshoot applications such as photo diode preamplifiers and picoampere and ringing. current-to-voltage converters. The use of a guarding technique, such as that shown in Figure 38, in printed circuit board (PCB) VDD R2A* layout and construction is critical to minimize leakage currents. C1A +15V The guard ring is connected to a low impedance potential at the 33pF 0.1µF same level as the inputs. High impedance signal lines should GAIN VDD RFB ADJUST OUT1 – not be extended for any unnecessary length on the PCB. VIN VREF AD7545 AD17/212 VOUTA R1A* AGND + PDIP(N),CERDIP(Q), DGND ANDSOIC(R)PACKAGES. *REFERTO ANALOG 4 5 TABLE3 COMMON DB11TODB0 6 3 VDD R2B* 2 7 1 8 00823-038 GAIN VDD RFB C331pBF Figure 38. Board Layout for Guarding Inputs ADJUST OUT1 – VIN VREF AD7545 AD17/212 VOUTB DAC CONVERTER APPLICATIONS R1B* AGND + DGND 0.1µF The AD712 is an excellent output amplifier for CMOS DACs. It can ANALOG bTeh ue soeudt tpou pt eimrfopremd abnocteh o2f- qau DadArCan ut sainndg 4a-nq uinavderratnetd o Rp-e2raRt iloandsd. er *TRAEBFLEER3TO DB11TODB0 COMMON –15V 00823-039 Figure 39. Unipolar Binary Operation approaches R for codes containing many 1s, and 3R for codes containing a single 1. For codes containing all 0s, the output R1 and R2 calibrate the zero offset and gain error of the DAC. impedance is infinite. Specific values for these resistors depend upon the grade of AD7545 and are listed in Table 4. For example, the output resistance of the AD7545 modulates between 11 kΩ and 33 kΩ. Therefore, with an 11 kΩ DAC Table 4. Recommended Trim Resistor Values vs. Grades of internal feedback resistance, the noise gain varies from 2 to 4/3. the AD7545 for V = 5 V DD This changing noise gain modulates the effect of the input offset Trim voltage of the amplifier, resulting in nonlinear DAC amplifier Resistor JN/AQ KN/BQ LN GLN performance. R1 500 Ω 200 Ω 100 Ω 20 Ω The AD712K with guaranteed 700 μV offset voltage minimizes R2 150 Ω 68 Ω 33 Ω 6.8 Ω this effect to achieve 12-bit performance. VDD R2* R4 20kΩ1% C1 +15V 33pF 0.1µF R5 GAIN VDD RFB 20kΩ1% ADJUST OUT1 – VIN R1* VREF AD7545 AGND +AD17/212 10kRΩ31% –AD17/212 VOUT DB11TODB0DGND + 0.1µF 12 DATA INPUT *RF1OARNVDARL2UESESE OTFABLE3 ACNOAMLMOOGN –15V 00823-040 Figure 40. Bipolar Operation Rev. I | Page 14 of 20

Data Sheet AD712 Figure 41 and Figure 42 show the settling time characteristics of 12/8 STS the AD712 when used as a DAC output buffer for the AD7545. CS HIGH AO BITS 1mV GAIN R/C AD574A ADJUST CE MIDDLE BITS 100 REF IN R2 90 100Ω REF OUT LOW +15V 10R01Ω BITS 0.1µF BIP OFF +5V – AODFFJSUESTT 10VIN +15V 1/2 AD712 20VIN –15V ±10V 10 ANALOG + AC DC 0% INPUT 0.1µF 5V 500ns 00823-041 Fi–g1u5rVe 43. AD712A aNsA aLnO GA DCCO MUnity-Gain Buffer 00823-043 Figure 41. Positive Settling Characteristics for AD712 with AD7545 A few hundred microamps reflected from the change in converter loading can introduce errors in instantaneous input voltage. If 1mV the analog-to-digital conversion speed is not excessive and the 100 bandwidth of the amplifier is sufficient, the amplifier output 90 returns to the nominal value before the converter makes its comparison. However, many amplifiers have relatively narrow bandwidth yielding slow recovery from output transients. The AD712 is ideally suited to drive high speed ADCs because it offers both wide bandwidth and high open-loop gain. 10 0% 5V 500ns 00823-042 100 1mV PD711 BUFF Figure 42. Negative Settling Characteristics for AD712 with AD7545 90 NOISE CHARACTERISTICS The random nature of noise, particularly in the flicker noise region, makes it difficult to specify in practical terms. At the same time, designers of precision instrumentation require 10 certain guaranteed maximum noise levels to realize the full 0% atecsctuedra ocny oafn t AheQirL e bqausiipsm toe na tl.i mAlilt gorfa d6 eμsV o fp t-hpe, A0.D1 7H12z taore 1 s0a mHpzl. e 500mV –10V ADC IN 200ns 00823-044 Figure 44. ADC Input Unity Gain Buffer Recovery Times, −10 V ADC IN DRIVING THE ANALOG INPUT OF AN ADC An op amp driving the analog input of an ADC, such as that 1mV PD711 BUFF shown in Figure 43, must be capable of maintaining a constant output voltage under dynamically changing load conditions. In 100 90 successive approximation converters, the input current is compared to a series of switched trial currents. The comparison point is diode clamped, but can deviate several hundred millivolts resulting in high frequency modulation of analog-to-digital input current. The output impedance of a feedback amplifier is made artificially low by the loop gain. At high frequencies, where the loop gain is 10 low, the amplifier output impedance can approach its open-loop 0% vimalpueed. Manocset oIfC 2 a5m Ωp ldifuiee rtso e cxuhrirbeint ta- lmiminitiimngu mre soispteonr-sl. oop output 500mV –5V ADC IN 200ns 00823-045 Figure 45. ADC Input Unity Gain Buffer Recovery Times, −5 V ADC IN Rev. I | Page 15 of 20

AD712 Data Sheet DRIVING A LARGE CAPACITIVE LOAD 5V 1µs The circuit in Figure 46 uses a 100 Ω isolation resistor that enables the amplifier to drive capacitive loads exceeding 1500 pF; the 100 90 resistor effectively isolates the high frequency feedback from the load and stabilizes the circuit. Low frequency feedback is returned to the amplifier summing junction via the low-pass filter formed by the 100 Ω series resistor and the Load Capacitance C. L Figure 47 shows a typical transient response for this connection. 10 4.99kΩ 0% 30pF+VIN 00823-047 0.1µF + – Figure 47. Transient Response RL = 2 kΩ, CL = 500 pF 4.99kΩ – INPUT 1/2 100Ω AD712 OUTPUT TYPICAL CAPACITANCE + C1 R1 LIMIT FOR VARIOUS LOAD RESISTORS 0.1µF – + R1 C1 UP TO 221k00ΩΩkΩ 111505000000pppFFF –VIN 00823-046 Figure 46. Circuit for Driving a Large Capacitive Load Rev. I | Page 16 of 20

Data Sheet AD712 FILTERS ACTIVE FILTER APPLICATIONS C1 560pF In active filter applications using op amps, the dc accuracy of +15V 0.1µF the amplifier is critical to optimal filter performance. The R1 R2 amplifier offset voltage and bias current contribute to output 20kΩ 20kΩ + error. Offset voltage is passed by the filter and can be amplified 1/2 C2 AD712 VOUT to produce excessive output offset. For low frequency applications VIN 280pF – requiring large value input resistors, bias currents flowing 0.1µF tIhnr aodudgihti othne, saet rheisgihsteorr sfr aelqsuoe gnecnieesr,a tteh ea no po fafmsept vdoylntaagme.i cs must –15V 00823-048 Figure 48. Second-Order Low-Pass Filter be carefully considered. Here, slew rate, bandwidth, and open- loop gain play a major role in op amp selection. The slew rate An important property of filters is their out-of-band rejection. must be fast as well as symmetrical to minimize distortion. The The simple 20 kHz low-pass filter shown in Figure 48 can be amplifier bandwidth in conjunction with the filter gain dictates used to condition a signal contaminated with clock pulses or the frequency response of the filter. sampling glitches that have considerable energy content at high frequencies. The use of a high performance amplifier such as the AD712 minimizes both dc and ac errors in all active filter applications. The low output impedance and high bandwidth of the AD712 minimize high frequency feedthrough as shown in Figure 49. SECOND-ORDER LOW-PASS FILTER The upper trace is that of another low cost BiFET op amp Figure 48 depicts the AD712 configured as a second-order, showing 17 dB more feedthrough at 5 MHz. Butterworth low-pass filter. With the values as shown, the REF 20.0 dBm OFFSET .0 Hz corner frequency is 20 kHz; however, the wide bandwidth of the 10dB/DIV RANGE 15.0dBm 0dB AD712 permits a corner frequency as high as several hundred kilohertz. Equations for component selection are as follows: R1 = R2 = A user selected value (10 kΩ to 100 kΩ, typical) TYPICAL BIFET 1.414 C1 (in farads) = ( ) (2π) f (R1) cutoff 0.707 AD712 C2= ( ) (2π) f (R1) cutoff CREBNWT 3E0Rk H5 z000 000.0Hz VBW 30kHz SPASNT 1 .08 0S0E0C 000.0Hz 00823-049 Figure 49. High Frequency Feedthrough Rev. I | Page 17 of 20

AD712 Data Sheet +15V 0.1µF +15V 0.1µF VIN + A1 0.001µF 2800Ω 6190Ω 6490Ω 6190Ω 2800Ω + AD711 A2 – 4.9395E–15 5.9276E–15 5.9276E–15 4.9395E–15 AD711 VOUT 0.1µF A + B + C + D + – 0.1µF 4.99kΩ –15V * * * * 100kΩ 0.001µF 124kΩ –15V *SEE TEXT 4.99kΩ 00823-050 Figure 50. 9-Pole Chebychev Filter 9-POLE CHEBYCHEV FILTER REF 5.0dBm MARKER 96 800.0Hz 10dB/DIV RANGE –5.0dBm –90dBm Figure 50 and Figure 51 show the AD712 and its dual counterpart, the AD711, as a 9-pole Chebychev filter using active frequency dependent negative resistors (FDNRs). With a cutoff frequency of 50 kHz and better than 90 dB rejection, it can be used as an antialiasing filter for a 12-bit data acquisition system with 100 kHz throughput. As shown in Figure 50, the filter is comprised of four FDNRs (A, B, C, D) having values of 4.9395 × 10−15 and 5.9276 × 10–15 farad-seconds. Each FDNR active network provides a two-pole response for eight poles. The ninth pole consists of a 0.001 μF capacitor and a 124 kΩ resistor at Pin 3 of Amplifier A2. Figure 51 dRe. pTioc tasc thhiee vceir ocuptitism faolr p eearcfho rFmDaNnRce ,w tihthe 0th.0e0 p1r μoFp ecra psealceicttoirosn of SRTBAWR 3T0.00HHzz VBW 30Hz STOSPT 6290.06 0S0E0C.0Hz 00823-052 Figure 52. High Frequency Response for 9-Pole Chebychev Filter must be selected for 1% or better matching and all resistors should have 1% or better tolerance. +15V + 0.1µF 0.001µF + 1/2 AD712 R – 0.1µF – 1/2 AD712 0.001µF + –15V 1.0kΩ 4.99kΩ R: 2249..94kkΩΩ FFOORR 45..99329756EE––1155 00823-051 Figure 51. FDNR for 9-Pole Chebychev Filter Rev. I | Page 18 of 20

Data Sheet AD712 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 0.280 (7.11) 0.250 (6.35) 1 4 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINEOFRPEANRREERENN LCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 070606-A Figure 53. 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 0.005 (0.13) 0.055 (1.40) MIN MAX 8 5 0.310 (7.87) 0.220 (5.59) 1 4 0.100 (2.54) BSC 0.405 (10.29) MAX 0.320 (8.13) 0.290 (7.37) 0.200 (5.08) 0.060 (1.52) MAX 0.015 (0.38) 0.200 (5.08) 0.150 (3.81) MIN 0.125 (3.18) 0.015 (0.38) 00..002134 ((00..5386)) 0.070 (1.78) SPELAANTIENG 1 05°° 0.008 (0.20) 0.030 (0.76) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 54. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) Rev. I | Page 19 of 20

AD712 Data Sheet 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 55. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD712AQ −40°C to +85°C 8-Lead CERDIP Q-8 AD712JNZ 0°C to 70°C 8-Lead PDIP N-8 AD712JRZ 0°C to 70°C 8-Lead SOIC_N R-8 AD712JRZ-REEL 0°C to 70°C 8-Lead SOIC_N R-8 AD712JRZ-REEL7 0°C to 70°C 8-Lead SOIC_N R-8 AD712KNZ 0°C to 70°C 8-Lead PDIP N-8 AD712KRZ 0°C to 70°C 8-Lead SOIC_N R-8 AD712KRZ-REEL 0°C to 70°C 8-Lead SOIC_N R-8 AD712KRZ-REEL7 0°C to 70°C 8-Lead SOIC_N R-8 AD712SQ/883B −55°C to +125°C 8-Lead CERDIP Q-8 1 Z = RoHS Compliant Part. ©1986–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00823-0-11/18(I) Rev. I | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD712AQ AD712JNZ AD712JR AD712JRZ AD712JRZ-REEL7 AD712KNZ AD712KRZ AD712JRZ-REEL AD712KRZ-REEL AD712KRZ-REEL7 AD712SQ/883B AD712TRZ-EP AD712TRZ-EP-R7