Monolithic 16-Bit Serial/Byte DACPORT AD660 FEATURES FUNCTIONAL BLOCK DIAGRAM Complete 16-bit digital-to-analog function DB0/ LBE/ DB8/ DB1/DB9/ DB7/ On-chip output amplifier CLEAR SELECT CS SIN DATADIR DB15 On-chip buried Zener voltage reference 15 14 12 11 5 AD660 ±1 LSB integral linearity HBE 16 16-BIT LATCH 13 SOUT 15-bit monotonic over temperature CONTROL Microprocessor compatible SER 17 LOGIC 10kΩ SPAN/ Serial or byte input CLR 18 16-BIT LATCH 22 BOIFPFOSLEATR 10.05kΩ Double-buffered latches LDAC 19 10kΩ Fast (40 ns) write pulse REF IN 23 16-BIT DAC Asynchronous clear (to 0 V) function 21 VOUT Serial output pin facilitates daisy-chaining 10V REF Unipolar or bipolar output 20 AGND LLooww TgHlitDc h+: N15: 0 n.0V0-s9 % REF2 4OUT –V1EE +V2CC +V3LL DG4ND 01813-001 Figure 1. GENERAL DESCRIPTION The AD660 DACPORT® is a complete 16-bit monolithic digital- is also available compliant to MIL-STD-883. Refer to the to-analog converter with an on-board voltage reference, double- AD660SQ/883B military data sheet for specifications and test buffered latches, and an output amplifier. It is manufactured on conditions. the Analog Devices, Inc., BiMOS II process. This process allows PRODUCT HIGHLIGHTS the fabrication of low power CMOS logic functions on the same 1. The AD660 is a complete 16-bit DAC, with a voltage chip as high precision bipolar linear circuitry. reference, double-buffered latches, and an output amplifier The AD660 architecture ensures 15-bit monotonicity over time on a single chip. and temperature. Integral and differential nonlinearity is main- 2. The internal buried Zener reference is laser trimmed to tained at ±0.003% maximum. The on-chip output amplifier 10.000 V with a ±0.1% maximum error and a temperature provides a voltage output settling time of 10 μs to within ½ LSB for drift performance of ±15 ppm/°C. The reference is available a full-scale step. for external applications. The AD660 has an extremely flexible digital interface. Data can 3. The output range of the AD660 is pin programmable and be loaded into the AD660 in serial mode or as two 8-bit bytes. can be set to provide a unipolar output range of 0 V to 10 V This is made possible by two digital input pins that have dual or a bipolar output range of −10 V to +10 V. No external functions. The serial mode input format is pin selectable to be components are required. MSB or LSB first. The serial output pin allows the user to daisy- 4. The AD660 is both dc and ac specified. DC specifications chain several AD660 devices by shifting the data through the include ±1 LSB INL and ±1 LSB DNL errors. AC specifica- input latch into the next DAC, thus minimizing the number of tions include 0.009% THD + N and 83 dB SNR. control lines required to SIN, CS and LDAC. The byte mode input 5. The double-buffered latches on the AD660 eliminate data format is also flexible in that the high byte or low byte data can skew errors and allow simultaneous updating of DACs in be loaded first. The double buffered latch structure eliminates multiDAC applications. data skew errors and provides for simultaneous updating of DACs 6. The clear function can asynchronously set the output in a multiDAC system. to 0 V regardless of whether the DAC is in unipolar or bipolar mode. The AD660 is available in five grades. AN and BN versions are 7. The output amplifier settles within 10 μs to ±½ LSB for a specified from −40°C to +85°C and are packaged in a 24-lead full-scale step and within 2.5 μs for a 1 LSB step over tempera- 300 mil plastic DIP. AR and BR versions are also specified from ture. The output glitch is typically 15 nV-s when a full-scale −40°C to +85°C and are packaged in a 24-lead SOIC. The SQ step is loaded. version is packaged in a 24-lead 300 mil CERDIP package and Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1993–2008 Analog Devices, Inc. All rights reserved.

AD660 TABLE OF CONTENTS Features .............................................................................................. 1  Bipolar Configuration ................................................................ 11  Functional Block Diagram .............................................................. 1  Internal/External Reference Use .............................................. 11  General Description ......................................................................... 1  Output Settling and Glitch ........................................................ 13  Product Highlights ........................................................................... 1  Digital Circuit Details ................................................................ 14  Revision History ............................................................................... 2  Microprocessor Interface ............................................................... 15  Specifications ..................................................................................... 3  AD660 to MC68HC11 (SPI Bus) Interface ............................. 15  AC Performance Characteristics ................................................ 4  AD660 to MICROWIRE Interface ........................................... 15  Timing Characteristics ................................................................ 5  AD660 to ADSP-210x Family Interface .................................. 15  Absolute Maximum Ratings ............................................................ 7  AD660 to Z80 Interface ............................................................. 16  ESD Caution .................................................................................. 7  Noise ............................................................................................ 16  Pin Configuration and Function Descriptions ............................. 8  Board Layout ................................................................................... 17  Terminology ...................................................................................... 9  Supply Decoupling ..................................................................... 17  Theory of Operation ...................................................................... 10  Grounding ................................................................................... 17  Analog Circuit Connections ..................................................... 10  Outline Dimensions ....................................................................... 18  Unipolar Configuration ............................................................. 10  Ordering Guide .......................................................................... 19  REVISION HISTORY 6/08—Rev. A to Rev. B Changes to Table 4 ............................................................................. 7 Updated Format .................................................................. Universal Added Pin Configuration and Function Descriptions Section ... 8 Updated Pin Name MSB/LSB to DATADIR Throughout ........... 1 Changes to Internal/External Reference Use Section ................ 11 Updated Pin Name UNI/BIP CLEAR to CLEAR SELECT Changes to Figure 12 ...................................................................... 12 Throughout ....................................................................................... 1 Changes to Figure 13, Figure 14, Figure 15, and Figure 16....... 13 Changes to Table 1 ............................................................................ 3 Changes to Figure 17 and Figure 18............................................. 15 Changes to Endnote 3 in Table 1 .................................................... 4 Changes to Figure 19 ...................................................................... 16 Changes to Figure 2 .......................................................................... 5 Updated Outline Dimensions ....................................................... 18 Changes to Figure 3 and Figure 5 ................................................... 6 Changes to Ordering Guide .......................................................... 19 Rev. B | Page 2 of 20

AD660 SPECIFICATIONS T = 25°C, +V = 15 V, −V = −15 V, +V = 5 V unless otherwise noted. A CC EE LL Table 1. AD660AN/AR/SQ AD660BN/BR Parameter Min Typ Max Min Typ Max Unit RESOLUTION 16 16 Bits DIGITAL INPUTS (T to T ) MIN MAX V (Logic 1) 2.0 5.5 2.0 5.5 V IH V (Logic 0) 0 0.8 0 0.8 V IL I (V = 5.5 V) −10 +10 −10 +10 μA IH IH I (V = 0 V) −10 +10 −10 +10 μA IL IL TRANSFER FUNCTION CHARACTERISTICS1 Integral Nonlinearity Bipolar Operation −2 +2 −1 +1 LSB T to T −4 +4 −2 +2 LSB MIN MAX Unipolar Operation −2 +2 −1 +1.5 LSB T to T −4 +4 −2 +2 LSB MIN MAX Differential Nonlinearity −2 +2 −1 +1 LSB T to T −4 +4 −2 +2 LSB MIN MAX Monotonicity Over Temperature 14 15 Bits Gain Error2, 3 −0.1 +0.1 −0.1 +0.1 % of FSR Gain Drift (T to T ) 25 15 ppm/°C MIN MAX DAC Gain Error4 −0.05 +0.05 −0.05 +0.05 % of FSR DAC Gain Drift4 10 10 ppm/°C Unipolar Offset −2.5 +2.5 −2.5 +2.5 mV Unipolar Offset Drift (T to T ) 3 3 ppm/°C MIN MAX Bipolar Zero Error −7.5 +7.5 −7.5 +7.5 mV Bipolar Zero Error Drift (T to T ) 5 5 ppm/°C MIN MAX REFERENCE INPUT Input Resistance 7 10 13 7 10 13 kΩ Bipolar Offset Input Resistance 7 10 13 7 10 13 kΩ REFERENCE OUTPUT Voltage 9.99 10.00 10.01 9.99 10.00 10.01 V Drift 25 15 ppm/°C External Current5 2 4 2 4 mA Capacitive Load 1000 1000 pF Short-Circuit Current 25 25 mA OUTPUT CHARACTERISTICS Output Voltage Range Unipolar Configuration 0 +10 0 +10 V Bipolar Configuration −10 +10 −10 +10 V Output Current 5 5 mA Capacitive Load 1000 1000 pF Short-Circuit Current 25 25 mA Rev. B | Page 3 of 20

AD660 AD660AN/AR/SQ AD660BN/BR Parameter Min Typ Max Min Typ Max Unit POWER SUPPLIES Voltage +V 6 +13.5 +16.5 +13.5 +16.5 V CC −V 6 −13.5 −16.5 −13.5 −16.5 V EE +V +4.5 +5.5 +4.5 +5.5 V LL Current (No Load) I +12 +18 +12 +18 mA CC I −12 −18 −12 −18 mA EE I LL @ V = 5 V, V = 0 V 0.3 2 0.3 2 mA IH IL @ V = 2.4 V, V = 0.4 V 3 7.5 3 7.5 mA IH IL Power Supply Sensitivity 1 2 1 2 ppm/% Power Dissipation (Static, No Load) 365 625 365 625 mW TEMPERATURE RANGE Specified Performance (A, B) −40 +85 −40 +85 °C Specified Performance (S) −55 +125 °C 1 For 16-bit resolution, 1 LSB = 0.0015% of FSR. For 15-bit resolution, 1 LSB = 0.003% of FSR. For 14-bit resolution, 1 LSB = 0.006% of FSR. FSR stands for full-scale range and is 10 V in a unipolar mode and 20 V in bipolar mode. 2 Gain error and gain drift are measured using the internal reference. The internal reference is the main contributor to gain drift. If lower gain drift is required, the AD660 can be used with a precision external reference such as the AD587, AD586, or AD688. 3 Gain error is measured with fixed 50 Ω resistors as shown in the Theory of Operation section. Eliminating these resistors increases the gain error by 0.25% of FSR (unipolar mode) or 0.50% of FSR (bipolar mode). 4 DAC gain error and drift are measured with an external voltage reference. They represent the error contributed by the DAC alone, for use with an external reference. 5 External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD660. 6 Operation on ±12 V supplies is possible using an external reference such as the AD586 and reducing the output range. Refer to the Internal/External Reference Use section. AC PERFORMANCE CHARACTERISTICS With the exception of total harmonic distortion + noise (THD + N) and signal-to-noise (SNR) ratio, these characteristics are included for design guidance only and are not subject to test. THD + N and SNR are 100% tested. T ≤ T ≤ T , +V = 15 V, −V = −15 V, +V = 5 V except where noted. MIN A MAX CC EE LL Table 2. Parameter Limit Unit Test Conditions/Comments OUTPUT SETTLING TIME 13 μs max 20 V step, T = 25°C A (Time to ±0.0008% FS 8 μs typ 20 V step, T = 25°C A with 2 kΩ, 1000 pF Load) 10 μs typ 20 V step, T ≤ T ≤ T MIN A MAX 6 μs typ 10 V step, T = 25°C A 8 μs typ 10 V step, T ≤ T ≤ T MIN A MAX 2.5 μs typ 1 LSB step, T ≤ T ≤ T MIN A MAX TOTAL HARMONIC DISTORTION + NOISE A, B, S Grade 0.009 % max 0 dB, 990.5 Hz, sample rate = 96 kHz, T = 25°C A A, B, S Grade 0.056 % max −20 dB, 990.5 Hz, sample rate = 96 kHz, T = 25°C A A, B, S Grade 5.6 % max −60 dB, 990.5 Hz, sample rate = 96 kHz, T = 25°C A SIGNAL-TO-NOISE RATIO 83 dB min T = 25°C A DIGITAL-TO-ANALOG GLITCH IMPULSE 15 nV-s typ DAC alternately loaded with 0x8000 and 0x7FFF DIGITAL FEEDTHROUGH 2 nV-s typ DAC alternately loaded with 0x0000 and 0xFFFF, CS high OUTPUT NOISE VOLTAGE Density (1 kHz to 1 MHz) 120 nV/√Hz typ Measured at V , 20 V span, excludes reference OUT REFERENCE NOISE 125 nV/√Hz typ Measured at REF OUT Rev. B | Page 4 of 20

AD660 TIMING CHARACTERISTICS +V = 15 V, −V = −15 V, +V = 5 V, V = 2.4 V, V = 0.4 V. CC EE LL HIGH LOW Table 3. Parameter Limit at T = 25°C Limit at T = −55°C to +125°C Unit A A BYTE LOAD (see Figure 2) t 40 50 ns min CS t 40 50 ns min DS t 0 10 ns min DH t 40 50 ns min BES t 0 10 ns min BEH t 80 100 ns min LH t 40 50 ns min LW SERIAL LOAD (see Figure 3) t 80 100 ns min CLK t 30 50 ns min LOW t 30 50 ns min HIGH t 0 10 ns min SS t 40 50 ns min DS t 0 10 ns min DH t 0 10 ns min SH t 80 100 ns min LH t 40 50 ns min LW ASYNCHRONOUS CLEAR TO BIPOLAR OR UNIPOLAR ZERO (see Figure 4) t 80 110 ns min CLR t 80 110 ns min SET t 0 10 ns min HOLD SERIAL OUT (see Figure 5) t 50 100 ns min PROP t 50 80 ns min DS DB0TO DB7 t DS t DH HBE OR LBE t t BES BEH t CS CS t t LH LW LDAC 01813-002 Figure 2. AD660 Byte Load Timing Rev. B | Page 5 of 20

AD660 DB0 VALID 1 VALID 16 t DS t SH t t SS DH SER DB1 1 = MSB FIRST, 0 = LSB FIRST (DATADIR) t t LOW HIGH CS t t t LH LW CLK LDAC 01813-003 Figure 3. AD660 Serial Load Timing t CLR CLR t HOLD t SET LBE 1 = BIPOLAR 0, 0 = UNIPOLAR 0 01813-004 Figure 4. Asynchronous Clear to Bipolar or Unipolar Zero DB0 VALID 16 VALID 17 t DS SER DB1 (DATADIR) CS t PROP SOUT VALID SOUT 1 01813-005 Figure 5. Serial Out Timing Rev. B | Page 6 of 20

AD660 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 4. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any +V to AGND −0.3 V to +17.0 V CC other conditions above those indicated in the operational −V to AGND +0.3 V to −17.0 V EE section of this specification is not implied. Exposure to absolute +V to DGND −0.3 V to +7 V LL maximum rating conditions for extended periods may affect AGND to DGND ±1 V device reliability. Digital Inputs (Pin 5 through Pin 23) −1.0 V to +7.0 V to DGND REF IN to AGND ±10.5 V ESD CAUTION SPAN/BIPOLAR OFFSET to AGND ±10.5 V REF OUT, V Indefinite short to AGND, OUT DGND, +V , −V , and +V CC EE LL Power Dissipation (Any Package) To +60°C 1000 mW Derates Above +60°C 8.7 mW/°C Storage Temperature −65°C to +150°C Lead Temperature JEDEC industry standard Soldering J-STD-020 Rev. B | Page 7 of 20

AD660 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –VEE 1 24 REF OUT +VCC 2 23 REF IN +VLL 3 22 SPAN/BIPOLAR OFFSET DGND 4 21 VOUT DB7/DB15 5 AD660 20 AGND DB6/DB14 6 TOP VIEW 19 LDAC (Not to Scale) DB5/DB13 7 18 CLR DB4/DB12 8 17 SER DB3/DB11 9 16 HBE DB2/DB10 10 15 LBE/CLEAR SELECT DB1/DDBB90/D/DABT8A/DSIINR 1112 1134 CSOSUT 01813-006 Figure 6. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 −V Negative Analog Supply Pin EE 2 +V Positive Analog Supply Pin CC 3 +V Digital Supply Pin LL 4 DGND Digital Ground Reference Pin 5 DB7/DB15 DB7 and DB15 Byte Load Data Input Pin 6 DB6/DB14 DB6 and DB14 Byte Load Data Input Pin 7 DB5/DB13 DB5 and DB13 Byte Load Data Input Pin 8 DB4/DB12 DB4 and DB12 Byte Load Data Input Pin 9 DB3/DB11 DB3 and DB11 Byte Load Data Input Pin 10 DB2/DB10 DB2 and DB10 Byte Load Data Input Pin 11 DB1/DB9/DATADIR DB1 and DB9 Byte Load Data Input Pin/MSB or LSB First Data Direction Serial Input Select Pin 12 DB0/DB8/SIN DB0 and DB8 Byte Load Data Input Pin/Serial Data Input Pin 13 S Serial Data Output Pin OUT 14 CS Chip Select Pin 15 LBE/CLEAR SELECT Low Byte Enable Pin/Unipolar or Bipolar Clear Select Pin 16 HBE High Byte Enable Pin 17 SER Serial Input Enable Pin 18 CLR Output Clear Pin 19 LDAC Load DAC Pin 20 AGND Analog Ground Reference Pin 21 V Voltage Output Pin OUT 22 SPAN/BIPOLAR OFFSET Output Span Configuration Pin 23 REF IN External Reference Voltage Input Pin 24 REF OUT Internal Reference Voltage Output Pin Rev. B | Page 8 of 20

AD660 TERMINOLOGY coefficient, specified in ppm/°C, is calculated by measuring the Integral Nonlinearity parameter at T , 25°C, and T , and dividing the change in Integral nonlinearity is the maximum deviation of the actual, MIN MAX the parameter by the corresponding temperature change. adjusted DAC output from the ideal analog output (a straight line drawn from 0 to FS − 1 LSB) for any bit combination. This Total Harmonic Distortion + Noise is also referred to as relative accuracy. Total harmonic distortion + noise (THD + N) is defined as the ratio of the square root of the sum of the squares of the values of Differential Nonlinearity the harmonics and noise to the value of the fundamental input Differential nonlinearity is the measure of the change in the frequency. It is usually expressed in percent (%). analog output, normalized to full scale, associated with a 1 LSB change in the digital input code. Monotonic behavior requires THD + N is a measure of the magnitude and distribution of that the differential linearity error be greater than or equal to linearity error, differential linearity error, quantization error, −1 LSB over the temperature range of interest. and noise. The distribution of these errors may be different, depending upon the amplitude of the output signal. Therefore, Monotonicity to be the most useful, THD + N should be specified for both A DAC is monotonic if the output either increases or remains large and small signal amplitudes. constant for increasing digital inputs with the result that the output is always a single-valued function of the input. Signal-To-Noise Ratio The signal-to-noise ratio is the ratio of the amplitude of the output Gain Error when a full-scale signal is present to the output with no signal Gain error is a measure of the output error between an ideal present. The signal-to-noise ratio is measured in decibels (dB). DAC and the actual device output with all 1s loaded after offset error has been adjusted out. Digital-To-Analog Glitch Impulse Digital-to-analog glitch impulse is the amount of charge Offset Error injected from the digital inputs to the analog output when the Offset error is a combination of the offset errors of the voltage- inputs change state. This is measured at half scale when the DAC mode DAC and the output amplifier and is measured with all 0s switches around the MSB and as many as possible switches loaded in the DAC. change state, that is, from 011…111 to 100…000. Bipolar Zero Error Digital Feedthrough When the AD660 is connected for bipolar output and 10…000 When the DAC is not selected (that is, CS is held high), high is loaded in the DAC, the deviation of the analog output from the ideal midscale value of 0 V is called the bipolar zero error. frequency logic activity on the digital inputs is capacitively coupled through the device to show up as noise on the V pin. OUT Drift This noise is digital feedthrough. Drift is the change in a parameter (such as gain, offset, and bipolar zero) over a specified temperature range. The drift temperature Rev. B | Page 9 of 20

AD660 THEORY OF OPERATION The AD660 uses an array of bipolar current sources with MOS DB0/ LBE/ DB8/ DB1/DB9/ DB7/ current steering switches to develop a current proportional to the CLEAR SELECT CS SIN DATADIR DB15 applied digital word, ranging from 0 mA to 2 mA. A segmented 15 14 12 11 5 AD660 architecture is used, where the most significant four data bits HBE 16 16-BIT LATCH SOUT13 are thermometer decoded to drive 15 equal current sources. CONTROL SPAN/ The lesser bits are scaled using a R-2R ladder, then applied SER 17 LOGIC 10kΩ BIPOLAR OFFSET CLR 18 16-BIT LATCH 22 together with the segmented sources to the summing node of the output amplifier. The internal span/bipolar offset resistor LDAC 19 10.05kΩ 50RΩ2 REF IN 10kΩ can be connected to the DAC output to provide a 0 V to 10 V 23 16-BIT DAC VOUT span, or it can be connected to the reference input to provide a 21 OUTPUT −10 V to +10 V span. 10V REF 20 AGND DB0/ LBE/ DB8/ DB1/DB9/ DB7/ REF OUT CLEAR1 S5ELECTC14S S1I2N DAT1A1DIR DB515 AD660 5R01Ω 24 –V1EE +V2CC +V3LL DGND4 01813-008 HBE 16 16-BIT LATCH 13 SOUT Figure 8. 0 V to 10 V Unipolar Voltage Output CONTROL SER 17 LOGIC 10kΩ SPAN/ If it is desired to adjust the gain and offset errors to zero, this CLR 18 16-BIT LATCH 22 BOIFPFOSLEATR can be accomplished using the circuit shown in Figure 9. The LDAC 19 10.05kΩ adjustment procedure is as follows: REF IN 23 10kΩ 16-BIT DAC 1. Zero adjust. 21 VOUT Turn all bits off and adjust the zero trimmer, R4, until the 10V REF output reads 0.000000 V (1 LSB = 153 μV). 20 AGND 2. Gain adjust. REF2 4OUT –V1EE +V2CC +V3LL DG4ND 01813-007 Touutrpnu atl ils b 9it.s9 9o9n8 a4n7d V a. d(Fjuusltl tshcea lgea iisn a tdrjiumstmede rt,o R 11 ,L uSnBt ille sths e Figure 7. Functional Block Diagram than the nominal full scale of 10.000000 V.) ANALOG CIRCUIT CONNECTIONS DB0/ LBE/ DB8/ DB1/DB9/ DB7/ Internal scaling resistors provided in the AD660 can be connected CLEAR SELECTCS SIN DATADIR DB15 to produce a unipolar output range of 0 V to 10 V or a bipolar 15 14 12 11 5 AD660 output range of −10 V to +10 V. Gain and offset drift are mini- HBE 16 16-BIT LATCH SOUT13 +VCC mized in the AD660 because of the thermal tracking of the CONTROL SPAN/ R3 SER 17 LOGIC BIPOLAR 16k R4 scaling resistors with other device components. 10kΩOFFSET 10k CLR 18 16-BIT LATCH 22 UNIPOLAR CONFIGURATION LDAC 19 10.05kΩ R2 –VEE 50Ω The configuration shown in Figure 8 provides a unipolar 0 V to REF IN 10kΩ 23 16-BIT DAC VOUT 10 V output range. In this mode, 50 Ω resistors are tied between 21 OUTPUT the SPAN/BIPOLAR OFFSET terminal (Pin 22) and V (Pin 21), OUT 10V REF and between REF OUT (Pin 24) and REF IN (Pin 23). It is possible 20 AGND to use the AD660 without any external components by tying Pin 24 REF OUT 24 1 2 3 4 dthireescet rlye stiost Poirns i2n3c raenads ePsi nth 2e2 g daiinre ecrtrlyo rt ob yP i0n.2 251%. E olfi mFSinRa.t ing –VEE +VCC +VLL DGND 01813-009 R1 100Ω Figure 9. 0 V to 10 V Unipolar Voltage Output with Gain and Offset Adjustment Rev. B | Page 10 of 20

AD660 BIPOLAR CONFIGURATION R2 100Ω The circuit shown in Figure 10 provides a bipolar output voltage DB0/ from −10.000000 V to +9.999694 V with positive full scale occur- LBE/ DB8/ DB1/DB9/ DB7/ CLEAR SELECT CS SIN DATADIR DB15 ring with all bits on. As in the unipolar mode, Resistor R1 and 15 14 12 11 5 Resistor R2 can be eliminated altogether to provide AD660 bipolar AD660 operation without any external components. Eliminating these HBE 16 16-BIT LATCH 13SOUT CONTROL resistors increases the gain error by 0.50% of FSR in bipolar mode. SER 17 LOGIC 10kΩ R2 CLR 18 16-BIT LATCH 22SPAN/ 50Ω 10.05kΩ BIPOLAR LDAC 19 OFFSET DB0/ CLEALRB SEE/LECT CS DSBIN8/ DDBA1T/ADDBI9R/ DDBB175/ R1 23REF IN10kΩ 16-BIT DAC 21VOUT 15 14 12 11 5 50Ω OUTPUT AD660 10V REF HBE 16 16-BIT LATCH 13SOUT 20 AGND CONTROL SER 17 LOGIC 10kΩ REF OUT24 1 2 3 4 CLR 18 16-BIT LATCH 22SPAN/ –VEE +VCC +VLL LDAC 19REF IN 10.05kΩ BOIFPFOSLEATR DGND 01813-011 R1 23 10kΩ 16-BIT DAC 21VOUT Figure 11. ±10 V Bipolar Voltage Output with Gain and Offset Adjustment 50Ω OUTPUT Note that using external resistors introduces a small temperature 10V REF drift component beyond that inherent in the AD660. The inter- 20 AGND nal resistors are trimmed to ratio-match and temperature-track 24 1 2 3 4 other resistors on-chip, even though their absolute tolerances are REF OUT –VEE +VCC +VLL DGND 01813-010 ±−2500% pp amnd/° aCb. sIonl uthtee tceamsep ethraattu erxet ecroneaffli rceiesnisttso arsr ea raep pursoexdi,m thaet ely Figure 10. ±10 V Bipolar Voltage Output temperature coefficient mismatch between internal and external resistors, multiplied by the sensitivity of the circuit to variations Gain offset and bipolar zero errors can be adjusted to zero using in the external resistor value, is the resultant additional tempera- the circuit shown in Figure 11 as follows: ture drift. 1. Offset adjust. INTERNAL/EXTERNAL REFERENCE USE Turn off all bits. Adjust the trimmer, R2, to give 10.000000 V output. The AD660 has an internal low noise buried Zener diode 2. Gain adjust. reference that is trimmed for absolute accuracy and temperature Turn all bits on and adjust R1 to give a reading of 9.999694 V. coefficient. This reference is buffered and optimized for use in a 3. Bipolar zero adjust (optional). high speed DAC and gives long-term stability equal or superior to In applications where an accurate zero output is required, set the best discrete Zener diode references. The performance of the MSB on, all other bits off, and readjust R2 for 0 V output. the AD660 is specified with the internal reference driving the DAC and with the DAC alone (for use with a precision external reference). The internal reference has sufficient buffering to drive external circuitry in addition to the reference currents required for the DAC (typically 1 mA to REF IN and 1 mA to SPAN/BIPOLAR OFFSET). A minimum of 2 mA is available for driving external loads. The AD660 reference output should be buffered with an external op amp if it is required to supply more than 4 mA total current. The reference is tested and guaranteed to ±0.2% maximum error. Rev. B | Page 11 of 20

AD660 It is also possible to use external references other than 10 V with zero errors in a manner similar to that described in the Bipolar slightly degraded linearity specifications. The recommended Configuration section. Use −5.000000 V and +4.999847, as the range of reference voltages is 5 V to 10.24 V, which allows 5 V, output values. 8.192 V, and 10.24 V ranges to be used. For example, by using The AD660 can also be used with the AD587 10 V reference, the AD586 5 V reference, outputs of 0 V to 5 V unipolar or ±5 V using the same configuration shown in Figure 12 to produce a bipolar can be realized. Using the AD586 voltage reference ±10 V output. The highest grade AD587UQ is specified at makes it possible to operate the AD660 with ±12 V supplies 5 ppm/°C, which is a 3× improvement over the AD660 internal with 10% tolerances. reference. Figure 12 shows the AD660 using the AD586 precision 5 V Figure 13 shows the AD660 using the AD688 precision reference in the bipolar configuration. The highest grade ±10 V reference, in the unipolar configuration. The highest AD586MN is specified with a drift of 2 ppm/°C, which is a grade AD688BQ is specified with a temperature coefficient of 7.5× improvement over the AD660 internal reference. This 1.5 ppm/°C. The ±10 V output is also ideal for providing precise circuit includes two optional potentiometers and one optional biasing for the offset trim resistor, R4. resistor that can be used to adjust the gain, offset, and bipolar R2 50Ω DB0/ LBE/ DB8/ DB1/DB9/ DB7/ CLEAR SELECT CS SIN DATADIR DB15 15 14 12 11 5 AD660 HBE 16 16-BIT LATCH 13SOUT CONTROL SER 17 LOGIC 10kΩ 2VIN LDCALCR 1189 16-BIT LATCH 10.05kΩ 22SBOPIFPAFONSL/EATR VOUT6 R1 23REF IN10kΩ 16-BIT DAC 21VOUT AD586 50Ω OUTPUT 10V REF GTNRDIM5 R102kΩ 20 AGND 4 24 1 2 3 4 REF OUT –VEE +VCC +VLL DGND 01813-012 Figure 12. Using the AD660 with the AD586 5 V Reference Rev. B | Page 12 of 20

AD660 R2 50Ω DB0/ LBE/ DB8/ DB1/DB9/ DB7/ CLEAR SELECT CS SIN DATADIR DB15 15 14 12 11 5 AD660 HBE 16 16-BIT LATCH 13SOUT CONTROL SER 17 LOGIC R3 10kΩ 10kΩ R4 CLR 18 16-BIT LATCH 22SPAN/ 10kΩ 10.05kΩ BIPOLAR LDAC 19 OFFSET R2 100Ω REF IN R1 23 10kΩ 16-BIT DAC 21VOUT 50Ω OUTPUT 7 6 4 3 10V REF 0VTO 10V 20 AGND AD688 RS A1 A3 1 REF2 O4UT –V1EE +V2CC +V3LL 4 R4 R2 R1 R5 14 DGND A4 15 A2 R6 2 +VS R3 5 9 10 8 12 11 13 16 –VS 01813-013 Figure 13. Using the AD660 with the AD688 High Precision ±10 V Reference OUTPUT SETTLING AND GLITCH The AD660 output buffer amplifier typically settles to within 600 0.0008% FS (1/2 LSB) of its final value in 8 μs for a full-scale 400 V) step. Figure 14 and Figure 15 show settling for a full-scale and µ an LSB step, respectively, with a 2 kΩ, 1000 pF load applied. GE ( 200 A T The guaranteed maximum settling time at 25°C for a full-scale OL 0 V step is 13 μs with this load. The typical settling time for a 1 LSB T step is 2.5 μs. TPU –200 U O The digital-to-analog glitch impulse is specified as 15 nV-s –400 typical. Figure 16 shows the typical glitch impulse characteristic aset ctohne d0 1ra1n…k1 r1e1g itsote 1r0 f0ro…m0 0th0e c foirdset trraannks irteiognis twerh. en loading the –6000 1 2 3 4 5 01813-015 TIME (µs) Figure 15. LSB Step Settling 600 +10 400 OUTPUT VOLTAGE (V)–100 20––02400000 OUTPUT VOLTAGE (µV) T VOLTAGE (mV)+100 U P T –600 01813-014 OU–10 0 Figure 14. −10 V toT +IM11E00 (Vµ sF)ull-Scale Step Settling2 0 0 1 2 3 4 5 01813-016 TIME (µs) Figure 16. Output Characteristics Rev. B | Page 13 of 20

AD660 DIGITAL CIRCUIT DETAILS CLR to be strobed has ended. Alternatively, new data can be loaded into the first rank latch if desired. The AD660 has several dual-use pins that allow flexible opera- tion while maintaining the lowest possible pin count and The serial out pin (S ) can be used to daisy-chain several DACs OUT consequently the smallest package size. The user should, together in multiDAC applications to minimize the number of therefore, pay careful attention to the following information isolators being used to cross an intrinsic safety barrier. The first when applying the AD660. rank latch acts like a 16-bit shift register, and repeated strobing Data can be loaded into the AD660 in serial or byte mode, of CS shifts the data out through SOUT and into the next DAC. described as follows. Each DAC in the chain requires its own LDAC signal unless all of the DACs are to be updated simultaneously. Serial mode operation is enabled by bringing SER (Pin 17) low. This changes the function of DB0 (Pin 12) to that of the serial Byte mode operation is enabled simply by keeping SER high, input pin, SIN. It also changes the function of DB1 (Pin 11) to which configures DB0 to DB7 as data inputs. In this mode, HBE a control input that tells the AD660 whether the serial data is and LBE are used to identify the data as either the high byte or going to be loaded MSB or LSB first. the low byte of the 16-bit input word. (The user can load the data, in any order, into the first rank latch.) As in the serial mode In serial mode, HBE and LBE are effectively disabled except case, the status of LBE, when CLR is strobed, determines whether for the dual function of LBE, which is to control whether the the AD660 clears to unipolar or bipolar zero. Therefore, when in asynchronous clear function goes to unipolar or bipolar zero. byte mode, the user must take care to set LBE to the desired (A low on LBE, when CLR is strobed, sends the DAC output status before strobing CLR. (In serial mode the user can simply to unipolar zero, a high to bipolar zero.) The AD660 does not hardware LBE to the desired state.) recognize the status of HBE when in serial mode. Note that CS is edge triggered. HBE, LBE, and LDAC are level Data is clocked into the input register on the rising edge of CS, triggered. as shown in Figure 3. The data then resides in the first rank latch and can be loaded into the DAC latch by taking LDAC high. This causes the DAC to change to the appropriate output value. It should be noted that the CLR function clears the DAC latch but does not clear the first rank latch. Therefore, the data that was previously residing in the first rank latch can be reloaded simply by bringing LDAC high after the event that necessitated Rev. B | Page 14 of 20

AD660 MICROPROCESSOR INTERFACE AD660 TO MC68HC11 (SPI BUS) INTERFACE 68HC11 The AD660 interface to the Motorola SPI (serial peripheral MDSI DB0/DB8/SIN SCK CS interface) is shown in Figure 17. The MOSI, SCK, and SS pins AD660 SS LDAC oCfS t,h aen 6d8 LHDCA1C1 aprien sr eosfp tehcet iAveDly6 c6o0n. Tnehcet eSdE Rto p tihne o Df Bth0e/ DABD86/6S0IN is, SER 01813-017 tied low causing the first rank latch to be transparent. The Figure 17. AD660 to 68HC11 (SPI) Interface majority of the interfacing issues are taken care of in the AD660 TO MICROWIRE INTERFACE software initialization. A typical routine such as the one shown The flexible serial interface of the AD660 is also compatible in the Software Initialization Example begins by initializing the with the National Semiconductor MICROWIRE™ interface. state of the various SPI data and control registers. The MICROWIRE interface is used on microcontrollers, such The most significant data byte (MSBY) is then retrieved from as the COP400 and COP800 series of processors. A generic memory and processed by the SENDAT subroutine. The SS pin interface to the MICROWIRE interface is shown in Figure 18. is driven low by indexing into the PORTD data register and The G1, SK, and SO pins of the MICROWIRE interface are respec- clearing Bit 5. This causes the 2nd rank latch of the AD660 to tively connected to the LDAC, CS and DB0/DB8/SIN pins of become transparent. The MSBY is then set to the SPI data the AD660. register where it is automatically transferred to the AD660. MICROWIRE™ The HC11 generates the requisite eight clock pulses with data SO DB0/DB8/SIN valid on the rising edges. After the most significant byte is SK CS AD660 transmitted, the least significant byte (LSBY) is loaded from G1 LDAC mtraenmsfoerry, tahned L tDraAnCsm piitnte ids dinr iav esnim hiilgahr ,f alasthcihoinn.g T toh ec ocmomplpelteet eth e SER 01813-018 Figure 18. AD660 to MICROWIRE Interface 16-bit word into the AD660. AD660 TO ADSP-210x FAMILY INTERFACE Software Initialization Example The serial mode of the AD660 minimizes the number of control INIT LDAA #$2F ; SS = I; SCK = 0; MOSI = I and data lines required to interface to digital signal processors STAA PORTD ;SEND TO SPI OUTPUTS (DSPs) such as the ADSP-210x family. The application in LDAA #$38 ; SS, SCK,MOSI = OUTPUTS Figure 19 shows the interface between an ADSP-210x and the ;SEND DATA DIRECTION AD660. Both the TFS pin and the DT pins of the ADSP-210x STAA DDRD INFO should be connected to the SER and DB0 pins of the AD660, ;DABL INTRPTS,SPI IS LDAA #$50 respectively. An inverter is required between the SCLK output MASTER & ON and the CS input of the AD660 to ensure that data transmitted STAA SPCR ;CPOL = 0, CPHA = 0,1MHZ BAUD RATE to the DB0 pin is valid on the rising edge of CS. ;LOAD ACCUM WITH UPPER 8 NEXTPT LDAA MSBY BITS The serial port (SPORT) of the DSP should be configured for BSR SENDAT ;JUMP TO DAC OUTPUT alternate framing mode so that TFS complies with the word ROUTINE length framing requirement of SER. Note that the INVTFS bit JMP NEXTPT ;INFINITE LOOP in the SPORT control register should be set to invert the TFS ;POINT AT ON-CHIP SENDAT LDY #$1000 signal so that SER is the correct polarity. The LDAC signal, REGISTERS BCLR $08,Y,$20 ;DRIVE SS (LDAC) LOW which must meet the minimum hold specification of tHIGH, is STAA SPDR ;SEND MS-BYTE TO SPI easily generated by delaying the rising edge of SER with a DATA REG 74HC74 flip-flop. The CS signal clocks the flip-flop, resulting WAIT1 LDAA SPSR ;CHECK STATUS OF SPIE in a delay of approximately one CS clock cycle. ;POLL FOR END OF X- BPL WAIT1 MISSION ;GET LOW 8 BITS FROM LDAA LSBY MEMORY ;SEND LS-BYTE TO SPI STAA SPDR DATA REG WAIT2 LDAA SPSR ;CHECK STATUS OF SPIE ;POLL FOR END OF X- BPL WAIT2 MISSION ;DRIV SS HIGH TO LATCH BSET $08,Y,$20 DATA RTS Rev. B | Page 15 of 20

AD660 In applications such as waveform generation, accurate timing of NOISE the output samples is important to avoid noise that is induced In high resolution systems, noise is often the limiting factor. A by jitter on the LDAC signal. In this example, the ADSP-210x 16-bit DAC with a 10 V span has an LSB size of 153 μV (−96 dB). is set up to use the internal timer to interrupt the processor at Therefore, the noise floor must remain below this level in the the precise and desired sample rate. When the timer interrupt frequency range of interest. The noise spectral density of the occurs, the 16-bit data word of the processor is written to the AD660 is shown in Figure 21 and Figure 22. Figure 21 shows transmit register (TXn). This causes the DSP to automatically the DAC output noise voltage spectral density for a 20 V span generate the TFS signal and begin transmission of the data. excluding the reference. This figure shows the 1/f corner frequency ADSP-210x 74HC04 at 100 Hz and the wideband noise to be below 120 nV/√Hz. SCLK CS AD660 Figure 22 shows the reference noise voltage spectral density and DT DB0/DB8/SIN shows the reference wideband noise to be below 125 nV/√Hz. TFS SER 1k D Q 74HC74 LDAC 01813-019 Figure 19. AD660 to ADSP-210x Interface Hz) AD660 TO Z80 INTERFACE nV/ 100 E ( G Figure 20 shows a Zilog Z80 8-bit microprocessor connected to A T L the AD660 using the byte mode interface. The double-buffered O V capability of the AD660 allows the microprocessor to indepen- SE 10 OI dently write to the low and high byte registers, and update the N DAC output. Processor speeds up to 6 MHz on the Z80 require no extra wait states to interface with the AD660 when using a 7T4hAe LadSd13re8s sa sd ethcoed aedrd arneaslsy zdeesc tohdee irn. put-output address produced 11 10 100 FREQ1kUENCY1 (0Hkz) 100k 1M 10M01813-021 Figure 21. DAC Output Noise Voltage Spectral Density by the processor to select the function to be performed by the 1k AD660, qualified by the coincidence of the input/output request (IORQ) and write (WR) pins. The least significant address bit (A0) determines if the low or high byte register of the AD660 is active. More significant address bits select between input register Hz) loading, DAC output update, and unipolar or bipolar clear. V/ 100 n E ( A typical Z80 software routine begins by writing the low byte of G A T the desired 16-bit DAC data to Address 0, followed by the high L O V byte to Address 1. The DAC output is then updated by activating E 10 S LDAC with a write to Address 2 (or Address 3). A clear to unipolar OI N zero occurs on a write to Address 4, and a clear to bipolar zero is performed by a write to Address 5. The actual data written to Abed dexrepsasn 2d tehdr otoug cho nAtdrdorl easss m5 iasn iyrr AeleDv6a6n0t. dTehvei cdeesc oasd erre qcaunir eedas. ily 11 10 100 FREQ1kUENCY1 (0Hkz) 100k 1M 10M01813-022 Figure 22. Reference Noise Voltage Spectral Density D0TO D7 Z80 ADDRESS DECODE DB0TO DB7 SER +VLL IORQ E2 Y2 CLR WR E1 Y1 LDAC AD660 Y0 CS A1TOA15 HBE LBE DGND A0TOA15 A0 01813-020 Figure 20. Connections for 8-Bit Bus Interface Rev. B | Page 16 of 20

AD660 BOARD LAYOUT Designing with high resolution data converters requires careful tantalum capacitor in parallel with a 0.1 μF ceramic capacitor attention to board layout. Trace impedance is the first issue. A provides adequate decoupling. V and V should be bypassed CC EE 306 μA current through a 0.5 Ω trace develops a voltage drop of to analog ground, while V should be decoupled to digital ground. LL 153 μV, which is 1 LSB at the 16-bit level for a 10 V full-scale An effort should be made to minimize the trace length between span. In addition to ground drops, inductive and capacitive the capacitor leads and the respective converter power supply coupling need to be considered, especially when high accuracy and common pins. The circuit layout should attempt to locate analog signals share the same board with digital signals. Finally, the AD660, associated analog circuitry, and interconnections as power supplies need to be decoupled to filter out ac noise. far as possible from logic circuitry. A solid analog ground plane Analog and digital signals should not share a common path. around the AD660 will isolate large switching ground currents. Each signal should have an appropriate analog or digital return For these reasons, the use of wire wrap circuit construction is routed close to it. Using this approach, signal loops enclose a not recommended; careful printed circuit construction is small area, minimizing the inductive coupling of noise. Wide preferred. PC tracks, large gauge wire, and ground planes are highly GROUNDING recommended to provide low impedance signal paths. Separate The AD660 has two ground pins, designated analog ground analog and digital ground planes should also be used, with a (AGND) and digital ground (DGND.) The analog ground pin is single interconnection point to minimize ground loops. Analog the high quality ground reference point for the device. Any signals should be routed as far as possible from digital signals external loads on the output of the AD660 should be returned and should cross them at right angles. to analog ground. If an external reference is used, this should One feature that the AD660 incorporates to help the user layout also be returned to the analog ground. is that the analog pins (+V , −V , REF OUT, REF IN, SPAN/ CC EE If a single AD660 is used with separate analog and digital ground BIPOLAR OFFSET, V and AGND) are adjacent to help OUT planes, connect the analog ground plane to AGND and the digital isolate analog signals from digital signals. ground plane to DGND keeping lead lengths as short as possible. SUPPLY DECOUPLING Then connect AGND and DGND together at the AD660. If The AD660 power supplies should be well filtered, well regulated, multiple AD660 devices are used or the AD660 shares analog and free from high frequency noise. Switching power supplies supplies with other components, connect the analog and digital are not recommended due to their tendency to generate spikes, returns together once at the power supplies rather than at each which can induce noise in the analog system. chip. This single interconnection of grounds prevents large ground loops and consequently prevents digital currents from Decoupling capacitors should be used in very close layout flowing through the analog ground. proximity between all power supply pins and ground. A 10 μF Rev. B | Page 17 of 20

AD660 OUTLINE DIMENSIONS 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 24 13 0.280 (7.11) 0.250 (6.35) 1 12 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 00..001140 ((00..3265)) PLANE 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINOEFRPEANRREEREN NLCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 071006-A Figure 23. 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) 0.005 (0.13) 0.098 (2.49) MIN MAX 0.310 (7.87) 24 13 0.220 (5.59) 1 12 PIN 1 0.060 (1.52) 0.200 (5.08) 1.280 (32.51) MAX 0.015 (0.38) 0.320 (8.13) MAX 0.290 (7.37) 0.150 (3.81) MIN 0.015 (0.38) 0.200 (5.08) 15° 0.008 (0.20) 0.125 (3.18) 0.100 0.070 (1.78) SEATING 0° 0.023 (0.58) (B2.S5C4) 0.030 (0.76) PLANE 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 24. 24-Lead Ceramic Dual In-Line Package [CERDIP] (Q-24) Dimensions shown in inches and (millimeters) Rev. B | Page 18 of 20

AD660 15.60 (0.6142) 15.20 (0.5984) 24 13 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 12 10.00 (0.3937) 0.75 (0.0295) 45° 2.65 (0.1043) 0.25 (0.0098) 0.30 (0.0118) 2.35 (0.0925) 8° 0.10 (0.0039) 0° COPLANARITY 0.10 1.27 B(0S.C0500) 00..5311 ((00..00210212)) SPELAATNIENG 00..3230 ((00..00103709)) 10..2470 ((00..00510507)) COMPLIANTTO JEDEC STANDARDS MS-013-AD C(RINOEFNPETARRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060706-A Figure 25. 24-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-24) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Gain TC Max ppm/°C Package Description Package Option AD660AN −40°C to +85°C 25 24-Lead PDIP N-24-1 AD660ANZ1 −40°C to +85°C 25 24-Lead PDIP N-24-1 AD660AR −40°C to +85°C 25 24-Lead SOIC_W RW-24 AD660AR-REEL −40°C to +85°C 25 24-Lead SOIC_W RW-24 AD660ARZ1 −40°C to +85°C 25 24-Lead SOIC_W RW-24 AD660ARZ-REEL1 −40°C to +85°C 25 24-Lead SOIC_W RW-24 AD660BN −40°C to +85°C 15 24-Lead PDIP N-24-1 AD660BNZ1 −40°C to +85°C 15 24-Lead PDIP N-24-1 AD660BR −40°C to +85°C 15 24-Lead SOIC_W RW-24 AD660BR-REEL −40°C to +85°C 15 24-Lead SOIC_W RW-24 AD660BRZ1 −40°C to +85°C 15 24-Lead SOIC_W RW-24 AD660BRZ-REEL1 −40°C to +85°C 15 24-Lead SOIC_W RW-24 AD660SQ −55°C to +125°C 25 24-Lead CERDIP Q-24 AD660SQ/883B2 −55°C to +125°C 1 Z = RoHS Compliant Part. 2 For further details, refer to the AD660SQ/883B military data sheet. Rev. B | Page 19 of 20

AD660 NOTES ©1993–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01813-0-6/08(B) Rev. B | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD660BRZ-REEL AD660AR AD660BN AD660ARZ AD660AN AD660SQ/883B 5962-9463301MLA AD660BR AD660ARZ-REEL AD660BNZ AD660BRZ AD660ANZ AD660BR-REEL AD660SQ