High Common-Mode Voltage, Difference Amplifier AD629 FEATURES FUNCTIONAL BLOCK DIAGRAM Improved replacement for: INA117P and INA117KU 21.1kΩ 380kΩ ±270 V common-mode voltage range REF(–) 1 8 NC 380kΩ Input protection to –IN 2 7 +VS ±500 V common mode 380kΩ +IN 3 6 OUTPUT ±500 V differential mode 20kΩ W±1id0 eV p oouwtpeur ts uswppinlyg roann g±e1 2(± V2 s.5u pVp tloy ±18 V) –VS 4 ANDC 6=2 N9O CONNECT 5 REF(+)00783-001 1 mA maximum power supply current Figure 1. GENERAL DESCRIPTION HIGH ACCURACY DC PERFORMANCE 3 ppm maximum gain nonlinearity (AD629B) The AD629 is a difference amplifier with a very high input, 20 μV/°C maximum offset drift (AD629A) common-mode voltage range. It is a precision device that allows 10 μV/°C maximum offset drift (AD629B) the user to accurately measure differential signals in the 10 ppm/°C maximum gain drift presence of high common-mode voltages up to ±270 V. The AD629 can replace costly isolation amplifiers in EXCELLENT AC SPECIFICATIONS applications that do not require galvanic isolation. The device 77 dB minimum CMRR @ 500 Hz (AD629A) operates over a ±270 V common-mode voltage range and has 86 dB minimum CMRR @ 500 Hz (AD629B) inputs that are protected from common-mode or differential 500 kHz bandwidth mode transients up to ±500 V. The AD629 has low offset, low offset drift, low gain error drift, APPLICATIONS low common-mode rejection drift, and excellent CMRR over a High voltage current sensing wide frequency range. Battery cell voltage monitors The AD629 is available in die and packaged form featuring Power supply current monitors 8-lead PDIP and 8-lead SOIC packages. For all packages Motor controls (including die) and grades, performance is guaranteed over Isolation the industrial temperature range of −40°C to +85°C. 100 2mV/DIV B) 95 d O ( 90 TI V) CTION RA 8805 R (2mV/DI E O J 75 R DE RE 70 UT ER O P N-M 65 OUT O M 60 M CO 550520 100 1k 10k 20k00783-002 –240 –120 0 12060V/DIV240 00783-003 FREQUENCY (Hz) COMMON-MODE VOLTAGE (V) Figure 2. Common-Mode Rejection Ratio vs. Frequency Figure 3. Error Voltage vs. Input Common-Mode Voltage Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1999-2011 Analog Devices, Inc. All rights reserved.

AD629 TABLE OF CONTENTS Features..............................................................................................1  Basic Connections......................................................................11  Applications.......................................................................................1  Single-Supply Operation...........................................................11  Functional Block Diagram..............................................................1  System-Level Decoupling and Grounding..............................11  General Description.........................................................................1  Using a Large Sense Resistor.....................................................12  Revision History...............................................................................2  Output Filtering..........................................................................12  Specifications.....................................................................................3  Output Current and Buffering..................................................13  Absolute Maximum Ratings............................................................4  A Gain of 19 Differential Amplifier.........................................13  ESD Caution..................................................................................4  Error Budget Analysis Example 1............................................13  Pin Configuration and Function Descriptions.............................5  Error Budget Analysis Example 2............................................14  Typical Performance Characteristics.............................................6  Outline Dimensions.......................................................................15  Theory of Operation......................................................................10  Ordering Guide..........................................................................16  Applications.....................................................................................11  REVISION HISTORY 4/11—Rev. B to Rev. C 3/07—Rev. A to Rev. B Changes to General Description Section......................................1 Updated Format and Layout.............................................Universal Added Endnote 1 in Table 1............................................................3 Changes to Ordering Guide..........................................................15 Added Figure 5; Renumbered Sequentially..................................4 Added Table 3; Renumbered Sequentially....................................4 3/00—Rev. 0 to Rev. A Added Pin Configuration and Function Descriptions Section, Figure 6, and Table 4........................................................................5 10/99—Revision 0: Initial Version Changes to Ordering Guide..........................................................16 Rev. C | Page 2 of 16

AD629 SPECIFICATIONS T = 25°C, V = ±15 V, unless otherwise noted. A S Table 1. AD629A1 AD629B Parameter Condition Min Typ Max Min Typ Max Unit GAIN V = ±10 V, R = 2 kΩ OUT L Nominal Gain 1 1 V/V Gain Error 0.01 0.05 0.01 0.03 % Gain Nonlinearity 4 10 4 10 ppm R = 10 kΩ 1 1 3 ppm L Gain vs. Temperature T = T to T 3 10 3 10 ppm/°C A MIN MAX OFFSET VOLTAGE Offset Voltage 0.2 1 0.1 0.5 mV V = ±5 V 1 mV S vs. Temperature T = T to T 6 20 3 10 μV/°C A MIN MAX vs. Supply (PSRR) V = ±5 V to ± 15 V 84 100 90 110 dB S INPUT Common-Mode Rejection Ratio V = ±250 V dc 77 88 86 96 dB CM T = T to T 73 82 dB A MIN MAX V = 500 V p-p, dc to 500 Hz 77 86 dB CM V = 500 V p-p, dc to 1 kHz 88 90 dB CM Operating Voltage Range Common mode ±270 ±270 V Differential ±13 ±13 V Input Operating Impedance Common mode 200 200 kΩ Differential 800 800 kΩ OUTPUT Operating Voltage Range R = 10 kΩ ±13 ±13 V L R = 2 kΩ ±12.5 ±12.5 V L V = ±12 V, R = 2 kΩ ±10 ±10 V S L Output Short-Circuit Current ±25 ±25 mA Capacitive Load Stable operation 1000 1000 pF DYNAMIC RESPONSE Small Signal –3 dB Bandwidth 500 500 kHz Slew Rate 1.7 2.1 1.7 2.1 V/μs Full Power Bandwidth V = 20 V p-p 28 28 kHz OUT Settling Time 0.01%, V = 10 V step 15 15 μs OUT 0.1%, V = 10 V step 12 12 μs OUT 0.01%, V = 10 V step, V = 0 V 5 5 μs CM DIFF OUTPUT NOISE VOLTAGE 0.01 Hz to 10 Hz 15 15 μV p-p Spectral Density, ≥100 Hz2 550 550 nV/√Hz POWER SUPPLY Operating Voltage Range ±2.5 ±18 ±2.5 ±18 V Quiescent Current V = 0 V 0.9 1 0.9 1 mA OUT T to T 1.2 1.2 mA MIN MAX TEMPERATURE RANGE For Specified Performance T = T to T −40 +85 −40 +85 °C A MIN MAX 1 Specifications for the AD629 A grade are also valid for the die model (listed in the Ordering Guide as AD629AC-WP). 2 See Figure 21. Rev. C | Page 3 of 16

AD629 ABSOLUTE MAXIMUM RATINGS Table 2. 1a 1b Parameter Rating 2 Supply Voltage, V ±18 V S Internal Power Dissipation1 7 8-Lead PDIP (N) See Figure 4 8-Lead SOIC (R) See Figure 4 Input Voltage Range, Continuous ±300 V Y Common-Mode and Differential, 10 sec ±500 V Output Short-Circuit Duration Indefinite Pin 1 and Pin 5 –V − 0.3 V to +V + 0.3 V S S 3 Maximum Junction Temperature 150°C Operating Temperature Range −55°C to +125°C 4 6b Storage Temperature Range −65°C to +150°C 6a Lead Temperature (Soldering 60 sec) 300°C 5a 5b 1 S88p--LLeeecaaifddic PSaODtiIoICPn,, θθisJJ AAf o==r 11d05e05v°°iCCce//WW in;. free air: FiDgIuEr SeI Z5E. M: 1e65ta5µllmizX a(Xt)i obny 2P4h6o5tµomg (rYa)ph 00783-041 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 3. Pin Pad Coordinates rating only; functional operation of the device at these or any Coordinates1 other conditions above those indicated in the operational Pad Pin X Y Description section of this specification is not implied. Exposure to absolute 1a REF(−) −677 +1082 For the die model, either maximum rating conditions for extended periods may affect 1b −534 +1084 pad can be bonded because 1a and 1b are internally device reliability. shorted. 2.0 2 −IN −661 +939 TJ = 150°C 3 +IN −661 −658 W) 8-LEAD PDIP ON ( 1.5 4 −VS +680 −800 TI 5a REF(+) +396 −1084 For the die model, either A SIP 5b +538 −1084 pad can be bonded because S 5a and 5b are internally DI R 1.0 shorted. E W O 6a OUTPUT +681 −950 For the die model, both P M 8-LEAD SOIC 6b +681 −807 pads must be bonded U M 0.5 because 6a and 6b are not AXI internally shorted. M 0 00783-004 7 +VS +680 +612 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 1 All coordinates are with respect to the center of the die. AMBIENT TEMPERATURE (°C) ESD CAUTION Figure 4. Maximum Power Dissipation vs. Temperature for SOIC and PDIP Rev. C | Page 4 of 16

AD629 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF(–) 1 8 NC –IN 2 AD629 7 +VS +IN 3 TOP VIEW 6 OUTPUT (Not to Scale) –VS N4C = NO CONNECT5 REF(+) 00783-040 Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 REF(−) Negative Reference Voltage Input. 2 −IN Inverting Input. 3 +IN Noninverting Input. 4 −VS Negative Supply Voltage. 5 REF(+) Positive Reference Voltage Input. 6 OUTPUT Output. 7 +VS Positive Supply Voltage. 8 NC No Connect. Do not connect to this pin. Rev. C | Page 5 of 16

AD629 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = ±15 V, unless otherwise noted. A S 100 400 dB) 90 360 TA = +25°C JECTION RATIO ( 87650000 E VOLTAGE (±V) 322228400000 TA = +85°C TA = –40°C E D R O E 40 M 160 N-MOD 30 MMON- 120 O O M 20 C 80 M O C 100 00783-006 400 00783-009 100 1k 10k 100k 1M 10M 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (Hz) POWER SUPPLY VOLTAGE (±V) Figure 7. Common-Mode Rejection Ratio vs. Frequency Figure 10. Common-Mode Operating Range vs. Power Supply Voltage 2mV/DIV RL = 10kΩ RL = 2kΩ V) VS = ±18V V) VS = ±18V DI DI V/ V/ m m R (2 VS = ±15V R (2 VS = ±15V O O R R R R E E UTPUT VS = ±12V UTPUT VS = ±12V O O VS = ±10V 4V/DIV 00783-007 VS = ±10V 4V/DIV 00783-010 –20 –16 –12 –8 –4 0 4 8 12 16 20 –20 –16 –12 –8 –4 0 4 8 12 16 20 VOUT (V) VOUT (V) Figure 8. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Figure 11. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Operating Range vs. Supply Voltage, RL = 10 kΩ (Curves Offset for Clarity) Operating Range vs. Supply Voltage, RL = 2 kΩ (Curves Offset for Clarity) RL = 1kΩ VS =±5V, RL = 10kΩ V) VS = ±18V V) DI DI V/ V/ m m R (2 VS = ±15V R (2 VS = ±5V, RL = 2kΩ O O R R R R E E UTPUT VS = ±12V UTPUT VS = ±5V, RL = 1kΩ O O VS = ±10V 4V/DIV 00783-008 VS = ±2.5V, RL = 1kΩ 1V/DIV 00783-011 –20 –16 –12 –8 –4 0 4 8 12 16 20 –20 –16 –12 –8 –4 0 4 8 12 16 20 VOUT (V) VOUT (V) Figure 9. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Figure 12. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Operating Range vs. Supply Voltage, RL = 1 kΩ (Curves Offset for Clarity) Operating Range vs. Supply Voltage (Curves Offset for Clarity) Rev. C | Page 6 of 16

AD629 20µV/DIV 40µV/DIV VS = ±15V VS = ±15V RL = 10kΩ RL = 2kΩ ERROR (0.8ppm/DIV) ERROR (2ppm/DIV) 2.5V/DIV 00783-012 2V/DIV 00783-015 –10 –5 0 5 10 –10 –8 –6 –4 –2 0 2 4 6 8 10 VOUT (V) VOUT (V) Figure 13. Gain Nonlinearity; VS = ±15 V, RL = 10 kΩ Figure 16. Gain Nonlinearity; VS = ±15 V, RL = 2kΩ 14.0 20µV/DIV –40°C VS = ±12V 13.0 –40°C RL = 10kΩ 12.0 V) V) 11.0 VS= ±15V +85°C +25°C DI E ( m/ G 10.0 R (1pp VOLTA 9.0 O T R U –11.5 R P E T OU –12.0 –12.5 –40°C –10 –8 –6 –4 –2 0 2 4 6 2V8/DIV 10 00783-013 ––1133..05 +85°C +25°C 00783-016 0 2 4 6 8 10 12 14 16 18 20 VOUT (V) OUTPUT CURRENT (mA) Figure 14. Gain Nonlinearity; VS = ±12 V, RL =10 kΩ Figure 17. Output Voltage Operating Range vs. Output Current; VS = ±15 V 11.5 +85°C 40µV/DIV VS = ±5V 10.5 –40°C RL = 1kΩ –40°C 9.5 R (6.67ppm/DIV) T VOLTAGE (V) 876...555 VS= ±12V +25°C +85°C O U –9.0 R P ER OUT –9.5 –40°C –10.0 +25°C –3.0 –2.4 –1.8 –1.2 –0.6 0 0.6 1.2 1.80.62V.4/DIV3.000783-014 ––1101..50 +85°C 00783-017 0 2 4 6 8 10 12 14 16 18 20 VOUT (V) OUTPUT CURRENT (mA) Figure 15. Gain Nonlinearity; VS = ±5 V, RL = 1 kΩ Figure 18. Output Voltage Operating Range vs. Output Current; VS = ±12 V Rev. C | Page 7 of 16

AD629 4.5 +85°C 3.5 –40°C –40°C G = +1 2.5 RL = 2kΩ +85°C CL = 1000pF V) 1.5 E ( AG 0.5 VS= ±5V +25°C T L O V T +85°C U –2.0 P T OU –2.5 –40°C –3.0 +25°C ––34..500 +252°C 4 +856°C 8 10 12 14 16 18 2000783-018 25mV/DIV 4µs/DIV 00783-021 OUTPUT CURRENT (mA) Figure 19. Output Voltage Operating Range vs. Output Current; VS = ±5 V Figure 22. Small Signal Pulse Response 120 +VS B) 110 ATIO (d 100 –VS GRCLL = == + 1210k0Ω0pF R 90 N O TI 80 C E J 70 E R Y 60 L P P U 50 S R E 40 W O P 300.1 1.0 FR10EQUENCY 1(0H0z) 1k 10k00783-019 25mV/DIV 4µs/DIV 00783-022 Figure 20. Power Supply Rejection Ratio vs. Frequency Figure 23. Small Signal Pulse Response 5.0 Hz) SITY (µV/ 443...505 GRCLL = == + 1210k0Ω0pF N E L D 3.0 A TR 2.5 C E P 2.0 S E OIS 1.5 N E 1.0 G A VOLT 0.50.01 0.1 1.0 FRE1Q0UENC1Y0 0(Hz) 1k 10k 10000783-020k 5V/DIV 5µs/DIV 00783-023 Figure 21. Voltage Noise Spectral Density vs. Frequency Figure 24. Large Signal Pulse Response Rev. C | Page 8 of 16

AD629 5V/DIV 5V/DIV +10V 0V VOUT VOUT 0V –10V OERURTOPURT 1mV = 0.01% OERURTOPURT 1mV = 0.01% 1mV/DIV 10µs/DIV 00783-024 1mV/DIV 10µs/DIV 00783-027 Figure 25. Settling Time to 0.01%, for 0 V to 10 V Output Step; G = −1, RL = 2 kΩ Figure 28. Settling Time to 0.01% for 0 V to −10 V Output Step; G = −1, RL = 2kΩ 350 300 N = 2180 N = 2180 300 n ≈ 200 PCS. FROM 250 n ≈ 200 PCS. FROM 10ASSEMBLY LOTS 10ASSEMBLY LOTS 250 S S 200 T T NI NI F U 200 F U O O 150 R R BE 150 BE M M NU NU 100 100 50 50 0 00783-025 0 00783-028 –150 –100 –50 0 50 100 150 –900 –600 –300 0 300 600 900 COMMON-MODE REJECTION RATIO (ppm) OFFSET VOLTAGE (µV) Figure 26. Typical Distribution of Common-Mode Rejection; Package Option N-8 Figure 29. Typical Distribution of Offset Voltage; Package Option N-8 400 400 N = 2180 N = 2180 350 n ≈ 200 PCS. FROM 350 n ≈ 200 PCS. FROM 10ASSEMBLY LOTS 10ASSEMBLY LOTS 300 300 S S NIT 250 NIT 250 U U F F R O 200 R O 200 E E B B M 150 M 150 U U N N 100 100 500 00783-026 500 00783-029 –600 –400 –200 0 200 400 600 –600 –400 –200 0 200 400 600 –1 GAIN ERROR (ppm) +1 GAIN ERROR (ppm) Figure 27. Typical Distribution of −1 Gain Error; Package Option N-8 Figure 30. Typical Distribution of +1 Gain Error; Package Option N-8 Rev. C | Page 9 of 16

AD629 THEORY OF OPERATION The AD629 is a unity gain, differential-to-single-ended To reduce output drift, the op amp uses super beta transistors amplifier (diff amp) that can reject extremely high common- in its input stage. The input offset current and its associated mode signals (in excess of 270 V with 15 V supplies). It consists temperature coefficient contribute no appreciable output of an operational amplifier (op amp) and a resistor network. voltage offset or drift, which has the added benefit of reducing voltage noise because the corner where 1/f noise becomes To achieve high common-mode voltage range, an internal dominant is below 5 Hz. To reduce the dependence of gain resistor divider (Pin 3 or Pin 5) attenuates the noninverting accuracy on the op amp, the open-loop voltage gain of the op signal by a factor of 20. Other internal resistors (Pin 1, Pin 2, amp exceeds 20 million, and the PSRR exceeds 140 dB. and the feedback resistor) restore the gain to provide a differential gain of unity. The complete transfer function equals 21.1kΩ 380kΩ REF(–) 1 8 NC V = V (+IN) − V (−IN) OUT 380kΩ –IN 2 7 +VS Laser wafer trimming provides resistor matching so that 380kΩ common-mode signals are rejected while differential input +IN 3 6 OUTPUT 20kΩ signals are amplified. –VS 4 5 REF(+) ANDC 6=2 N9O CONNECT 00783-001 Figure 31. Functional Block Diagram Rev. C | Page 10 of 16

AD629 APPLICATIONS BASIC CONNECTIONS REF (–) 21.1kΩ AD629 +VS 1 8 NC Figure 32 shows the basic connections for operating the AD629 –IN 380kΩ 380kΩ with a dual supply. A supply voltage of between ±3 V and ±18 V 2 7 is applied between Pin 7 and Pin 4. Both supplies should be ISHUNT RSHUNT +IN 380kΩ VX +VS 0.1µF 3 6 decoupled close to the pins using 0.1 μF capacitors. Electrolytic VY capacitors of 10 μF, also located close to the supply pins, may be –VS 4 20kΩ 5 REF (+) OUTPUT = VOUT – VREF required if low frequency noise is present on the power supply. NC = NO CONNECT While multiple amplifiers can be decoupled by a single set of 10 μF capacitors, each in amp should have its own set of 0.1 μF cthaep aIcCit’so prso wsoe rth paitn tsh. e decoupling point can be located right at VREF 00783-031 Figure 33. Operation with a Single Supply +VS Applying a reference voltage to REF(+) and REF(–) and REF (–) 21.1kΩ AD629 +3VTO +18V 1 8 NC operating on a single supply reduces the input common-mode range of the AD629. The new input common-mode range –IN 380kΩ 380kΩ ISHUNT RSHUNT +IN 2 380kΩ 7 +VS 0.1µF (TSEEXET) dineppuetnsd osf uthpeo nin ttheern vaoll toapgeer aatti tohnea iln avmerptliinfige ra, nladb neolendi nVvXe ratnindg V Y 3 6 VOUT = ISHUNT × RSHUNT in Figure 33. These nodes can swing to within 1 V of either rail. –VS 4 20kΩ 5 REF (+) Therefore, for a (single) supply voltage of 10 V, VX and VY can (SEE TEXT) 0.1µF range between 1 V and 9 V. If VREF is set to 5 V, the permissible –3VT–OVS –18VNC = NO CONNECT 00783-030 cvoomltamgeo rna-nmgoesd ec arnan bgee c iasl +cu8l5a tVed t ob y– 75 V. The common-mode Figure 32. Basic Connections V (±) = 20 V /V (±) − 19 V CM X Y REF The differential input signal, which typically results from a load SYSTEM-LEVEL DECOUPLING AND GROUNDING current flowing through a small shunt resistor, is applied to The use of ground planes is recommended to minimize the Pin 2 and Pin 3 with the polarity shown to obtain a positive impedance of ground returns (and therefore the size of dc gain. The common-mode range on the differential input signal errors). Figure 34 shows how to work with grounding in a can range from −270 V to +270 V, and the maximum differential mixed-signal environment, that is, with digital and analog range is ±13 V. When configured as shown in Figure 32, the signals present. To isolate low level analog signals from a noisy device operates as a simple gain-of-1, differential-to-single- digital environment, many data acquisition components have ended amplifier; the output voltage being the shunt resistance separate analog and digital ground returns. All ground pins times the shunt current. The output is measured with respect to from mixed-signal components, such as ADCs, should return Pin 1 and Pin 5. through a low impedance analog ground plane. Digital ground Pin 1 and Pin 5 (REF(–) and REF(+)) should be grounded for a lines of mixed-signal converters should also be connected to the gain of unity and should be connected to the same low impedance analog ground plane. Typically, analog and digital grounds ground plane. Failure to do this results in degraded common- should be separated; however, it is also a requirement to mode rejection. Pin 8 is a no connect pin and should be left open. minimize the voltage difference between digital and analog SINGLE-SUPPLY OPERATION grounds on a converter, to keep them as small as possible (typically <0.3 V). The increased noise, caused by the Figure 33 shows the connections for operating the AD629 with converter’s digital return currents flowing through the analog a single supply. Because the output can swing to within only ground plane, is typically negligible. Maximum isolation about 2 V of either rail, it is necessary to apply an offset to the between analog and digital is achieved by connecting the ground output. This can be conveniently done by connecting REF(+) planes back at the supplies. Note that Figure 34 suggests a “star” and REF(–) to a low impedance reference voltage (some ADCs ground system for the analog circuitry, with all ground lines provide this voltage as an output), which is capable of sinking being connected, in this case, to the ADC’s analog ground. current. Therefore, for a single supply of 10 V, V may be set REF However, when ground planes are used, it is sufficient to to 5 V for a bipolar input signal. This allows the output to swing connect ground pins to the nearest point on the low impedance ±3 V around the central 5 V reference voltage. Alternatively, for ground plane. unipolar input signals, V can be set to about 2 V, allowing the REF output to swing from 2 V (for a 0 V input) to within 2 V of the positive rail. Rev. C | Page 11 of 16

AD629 ANALOG POWER DIGITAL Table 5 shows some sample error voltages generated by a SUPPLY POWER SUPPLY common-mode voltage of 200 V dc with shunt resistors from –5V +5V GND GND +5V 20 Ω to 2000 Ω. Assuming that the shunt resistor is selected to 0.1µF use the full ±10 V output swing of the AD629, the error voltage 0.1µF 0.1µF 0.1µF becomes quite significant as RSHUNT increases. 1 6 14 Table 5. Error Resulting from Large Values of R 4–VS +VS7 VDD AGND DGND 12 GND VDD (Uncompensated Circuit) SHUNT +IN 3 AD629OUTPUT 6 4 VIN1 AD7892-2 MICROPROCESSOR R (Ω) Error V (V) Error Indicated (mA) –IN 2 S OUT REF1(–) RE5F(+) 3 VIN2 00783-032 2100 0 0 00..40918 00..459 8 Figure 34. Optimal Grounding Practice for a Bipolar Supply Environment 2000 1 0.5 with Separate Analog and Digital Supplies POWER SUPPLY To measure low current or current near zero in a high common- +5V GND mode environment, an external resistor equal to the shunt 0.1µF resistor value can be added to the low impedance side of the 0.1µF shunt resistor, as shown in Figure 36. 0.1µF +IN 3 +V7S –4VS VDD AGNDDGND VDD GND REF (–) 1 21.1kΩ AD629 8 NC +VS –IN 2 AD629 OUTPUT 6 VIN1 ADC MICROPROCESSOR RCOMP –IN 380kΩ 380kΩ FigurRe E3F15(.– O)pRtEi5mF(a+)l Ground PVrINa2ctice in a Single-Supply Environment 00783-033 ISHUNT RSHUNT +IN 23 380kΩ 76 +VSVOUT0.1µF If there is only a single power supply available, it must be shared –VS 4 20kΩ 5 REF (+) bmyi nbiomthiz dei ginittaelr faenrden acnea bloegtw ceirecnu tithrey .d Figigituarle a 3n5d sahnoawlosg h coiwrc utoit ry. –VS 0.1µF NC = NO CONNECT 00783-034 In this example, the ADC’s reference is used to drive Pin REF(+) Figure 36. Compensating for Large Sense Resistors and Pin REF(–). This means that the reference must be capable OUTPUT FILTERING of sourcing and sinking a current equal to V /200 kΩ. As in CM A simple 2-pole, low-pass Butterworth filter can be implemented the previous case, separate analog and digital ground planes using the OP177 after the AD629 to limit noise at the output, as should be used (reasonably thick traces can be used as an shown in Figure 37. Table 6 gives recommended component alternative to a digital ground plane). These ground planes values for various corner frequencies, along with the peak-to- should connect at the power supply’s ground pin. Separate peak output noise for each case. traces (or power planes) should run from the power supply to the supply pins of the digital and analog circuits. Ideally, each REF (–) 21.1kΩ AD629 +VS device should have its own power supply trace, but these can be 1 8 NC +VS shared by a number of devices, as long as a single trace is not 380kΩ 380kΩ 0.1µF C1 0.1µF –IN 2 7 used to route current to both digital and analog circuitry. +VS 380kΩ R1 R2 OP177 VOUT USING A LARGE SENSE RESISTOR +IN 3 6 0.1µF C2 20kΩ REF (+) Insertion of a large value shunt resistance across the input pins, –VS 4 5 –VS Pinitnr o2d auncdin Pgi na c3o, mwimll iomnb-malaondcee etrhreo irn. pTuhte r emsiasgtonri tnuedtwe oorfk t,h e error 0.1µF NC = NO CONNECT 00783-035 will depend on the common-mode voltage and the magnitude Figure 37. Filtering of Output Noise Using a 2-Pole Butterworth Filter of R . SHUNT Table 6. Recommended Values for 2-Pole Butterworth Filter Corner Frequency R1 R2 C1 C2 Output Noise (p-p) No Filter 3.2 mV 50 kHz 2.94 kΩ ± 1% 1.58 kΩ ± 1% 2.2 nF ± 10% 1 nF ± 10% 1 mV 5 kHz 2.94 kΩ ± 1% 1.58 kΩ ± 1% 22 nF ± 10% 10 nF ± 10% 0.32 mV 500 Hz 2.94 kΩ ± 1% 1.58 kΩ ± 1% 220 nF ± 10% 0.1 μF ± 10% 100 μV 50 Hz 2.7 kΩ ± 10% 1.5 kΩ ± 10% 2.2 μF ± 20% 1 μF ± 20% 32 μV Rev. C | Page 12 of 16

AD629 OUTPUT CURRENT AND BUFFERING ERROR BUDGET ANALYSIS EXAMPLE 1 The AD629 is designed to drive loads of 2 kΩ to within 2 V of In the dc application that follows, the 10 A output current from the rails but can deliver higher output currents at lower output a device with a high common-mode voltage (such as a power voltages (see Figure 17). If higher output current is required, the supply or current-mode amplifier) is sensed across a 1 Ω shunt output of the AD629 should be buffered with a precision op amp, resistor (see Figure 40). The common-mode voltage is 200 V, such as the OP113, as shown in Figure 38. This op amp can swing and the resistor terminals are connected through a long pair of to within 1 V of either rail while driving a load as small as 600 Ω. lead wires located in a high noise environment, for example, 50 Hz/60 Hz, 440 V ac power lines. The calculations in Table 7 REF (–) 21.1kΩ AD629 +VS 1 8 NC assume an induced noise level of 1 V at 60 Hz on the leads, in 380kΩ 380kΩ 0.1µF addition to a full-scale dc differential voltage of 10 V. The error –IN 2 7 budget table quantifies the contribution of each error source. 0.1µF 380kΩ Note that the dominant error source in this example is due to +IN 3 6 OP113 VOUT the dc common-mode voltage. 20kΩ REF (+) 0.1µF –VS 4 5 OUTPUT 0.1µF NFCig =u NreO 3C8O. NONuEtCpTut Buffering Appli–cVaStion 00783-036 CURRET12N00OT0A VGMCRPMOSDUCND REF– (I–N) 12 2318.01kkΩΩ A38D06kΩ29 87 NC +VS 1Ω 0.1µF A GAIN OF 19 DIFFERENTIAL AMPLIFIER SHUNT +IN 380kΩ 3 6 VOUT While low level signals can be connected directly to the –IN and 20kΩ REF (+) +IN inputs of the AD629, differential input signals can also be –VS 4 5 cHoonwneevcetre, dla, ragse s choomwmn oinn -Fmigoudree v 3o9lt,a tgoe sg iavree an op rloecnigseer g paeirnm oifs s1i9b.l e. POW6E0RHz LINE 0.1µF NC = NO CONNECT 00783-038 Figure 40. Error Budget Analysis Example 1: VIN = 10 V Full-Scale, Cold junction compensation can be implemented using a VCM = 200 V DC, RSHUNT = 1 Ω, 1 V p-p, 60 Hz Power-Line Interference temperature sensor, such as the AD590. REF (–) 21.1kΩ AD629 +VS 1 8 NC THERMOCOUPLE –IN 380kΩ 380kΩ 2 7 +VS 0.1µF +IN 380kΩ 3 6 VOUT VREF 20kΩ REF (+) 4 5 NC = NO CONNECT 00783-037 Figure 39. A Gain of 19 Thermocouple Amplifier Table 7. AD629 vs. INA117 Error Budget Analysis Example 1 (V = 200 V dc) CM Error, ppm of FS Error Source AD629 INA117 AD629 INA117 ACCURACY, T = 25°C A Initial Gain Error (0.0005 × 10)/10 V × 106 (0.0005 × 10)/10 V × 106 500 500 Offset Voltage (0.001 V/10 V) × 106 (0.002 V/10 V) × 106 100 200 DC CMR (Over Temperature) (224 × 10-6 × 200 V)/10 V × 106 (500 × 10-6 × 200 V)/10 V × 106 4480 10,000 Total Accuracy Error 5080 10,700 TEMPERATURE DRIFT (85°C) Gain 10 ppm/°C × 60°C 10 ppm/°C × 60°C 600 600 Offset Voltage (20 μV/°C × 60°C) × 106/10 V (40 μV/°C × 60°C) × 106/10 V 120 240 Total Drift Error 720 840 RESOLUTION Noise, Typical, 0.01 Hz to 10 Hz, μV p-p 15 μV/10 V × 106 25 μV/10 V × 106 2 3 CMR, 60 Hz (141 × 10-6 × 1 V)/10 V × 106 (500 × 10-6 × 1 V)/10 V × 106 14 50 Nonlinearity (10-5 × 10 V)/10 V × 106 (10-5 × 10 V)/10 V × 106 10 10 Total Resolution Error 26 63 Total Error 5826 11,603 Rev. C | Page 13 of 16

AD629 ERROR BUDGET ANALYSIS EXAMPLE 2 This application is similar to the previous example except OUTPUT that the sensed load current is from an amplifier with an ac CURRE1N0TAMPS REF (–) 1 21.1kΩ AD629 8 NC common-mode component of ±100 V (frequency = 500 Hz) ±100VAC CM present on the shunt (see Figure 41). All other conditions are TO GROUND –IN 2 380kΩ 380kΩ 7 +VS 1Ω 0.1µF the same as before. Note that the same kind of power-line SHUNT +IN 380kΩ interference can happen as detailed in Example 1. However, 3 6 VOUT the ac common-mode component of 200 V p-p coming from –VS 4 20kΩ 5 REF (+) tthheer sehfournet, itsh mis uincthe rlaferrgeenr cteh acno mthpeo innetnertf cearenn bcee noef g1l eVc tpe-dp. ; POW6E0HRz LINE 0.1µF NC = NO CONNECT 00783-039 Figure 41. Error Budget Analysis Example 2: VIN = 10 V Full-Scale, VCM = ±100 V at 500 Hz, RSHUNT =1 Ω Table 8. AD629 vs. INA117 AC Error Budget Example 2 (V = ±100 V @ 500 Hz) CM Error, ppm of FS Error Source AD629 INA117 AD629 INA117 ACCURACY, T = 25°C A Initial Gain Error (0.0005 × 10)/10 V × 106 (0.0005 × 10)/10 V × 106 500 500 Offset Voltage (0.001 V/10 V) × 106 (0.002 V/10 V) × 106 100 200 Total Accuracy Error 600 700 TEMPERATURE DRIFT (85°C) Gain 10 ppm/°C × 60°C 10 ppm/°C × 60°C 600 600 Offset Voltage (20 μV/°C × 60°C) × 106/10 V (40 μV/°C × 60°C) × 106/10 V 120 240 Total Drift Error 720 840 RESOLUTION Noise, Typical, 0.01 Hz to 10 Hz, μV p-p 15 μV/10 V × 106 25 μV/10 V × 106 2 3 CMR, 60 Hz (141 × 10-6 × 1 V)/10 V × 106 (500 × 10-6 × 1 V)/10 V × 106 14 50 Nonlinearity (10-5 × 10 V)/10 V × 106 (10-5 × 10 V)/10 V × 106 10 10 AC CMR @ 500 Hz (141 × 10-6 × 200 V)/10 V × 106 (500 × 10-6 × 200 V)/10 V × 106 2820 10,000 Total Resolution Error 2846 10,063 Total Error 4166 11,603 Rev. C | Page 14 of 16

AD629 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 0.280 (7.11) 0.250 (6.35) 1 4 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINEOFRPEANRERERENN LCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 070606-A Figure 42. 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINEOFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 43. 8-Lead Standard Small Outline Package [SOIC_N] (R-8) Dimensions shown in millimeters and (inches) Rev. C | Page 15 of 16

AD629 ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD629AN −40°C to +85°C 8-Lead PDIP N-8 AD629ANZ −40°C to +85°C 8-Lead PDIP N-8 AD629AR −40°C to +85°C 8-Lead SOIC_N R-8 AD629AR-REEL −40°C to +85°C 8-Lead SOIC_N R-8 AD629AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 AD629ARZ −40°C to +85°C 8-Lead SOIC_N R-8 AD629ARZ-RL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces R-8 AD629ARZ-R7 −40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces R-8 AD629BNZ −40°C to +85°C 8-Lead PDIP N-8 AD629BR −40°C to +85°C 8-Lead SOIC_N R-8 AD629BR-REEL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces R-8 AD629BR-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces R-8 AD629BRZ −40°C to +85°C 8-Lead SOIC_N R-8 AD629BRZ-RL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel, 2,500 pieces R-8 AD629BRZ-R7 −40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel, 1,000 pieces R-8 AD629AC-WP −40°C to +85°C Die 1 Z = RoHS Compliant Part. ©1999-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00783-0-4/11(C) Rev. C | Page 16 of 16