Micropower, Single- and Dual-Supply, Rail-to-Rail Instrumentation Amplifier Data Sheet AD627 FEATURES FUNCTIONAL BLOCK DIAGRAM Micropower, 85 μA maximum supply current AD627 Wide power supply range (+2.2 V to ±18 V) RG 1 8 RG Easy to use –IN 2 7 +VS Gain set with one external resistor +IN 3 6 OUTPUT Gain range 5 (no resistor) to 1000 HRaigilh-teor- praeirl foourmtpaunt csew tihnagn discrete designs –VS 4 5 REF 00782-001 Figure 1. 8-Lead PDIP (N) and SOIC_N (R) High accuracy dc performance 0.03% typical gain accuracy (G = +5) (AD627A) 100 10 ppm/°C typical gain drift (G = +5) 90 125 μV maximum input offset voltage (AD627B dual supply) 80 AD627 200 μV maximum input offset voltage (AD627A dual supply) 70 1 μV/°C maximum input offset voltage drift (AD627B) 3 μV/°C maximum input offset voltage drift (AD627A) B)60 d 10 nA maximum input bias current R (50 R Noise: 38 nV/√Hz RTI noise at 1 kHz (G = +100) CM40 TLROAWD IPTOIOWNEARL Excellent ac specifications DISCRETE DESIGN 30 AD627A: 77 dB minimum CMRR (G = +5) 20 AD627B: 83 dB minimum CMRR (G = +5) 80 kHz bandwidth (G = +5) 10 135 μs settling time to 0.01% (G = +5, 5 V step) 01 10 FREQU1E0N0CY (Hz) 1k 10k 00782-002 APPLICATIONS Figure 2. CMRR vs. Frequency, ±5 VS, Gain = +5 4 mA to 20 mA loop-powered applications Low power medical instrumentation—ECG, EEG Transducer interfacing Thermocouple amplifiers Industrial process controls Low power data acquisition Portable battery-powered instruments GENERAL DESCRIPTION ideal for battery-powered applications. Its rail-to-rail output stage maximizes dynamic range when operating from low The AD627 is an integrated, micropower instrumentation supply voltages. Dual-supply operation (±15 V) and low power amplifier that delivers rail-to-rail output swing on single and consumption make the AD627 ideal for industrial applications, dual (+2.2 V to ±18 V) supplies. The AD627 provides excellent including 4 mA to 20 mA loop-powered systems. ac and dc specifications while operating at only 85 μA maximum. The AD627 does not compromise performance, unlike other The AD627 offers superior flexibility by allowing the user to set micropower instrumentation amplifiers. Low voltage offset, the gain of the device with a single external resistor while con- offset drift, gain error, and gain drift minimize errors in the forming to the 8-lead industry-standard pinout configuration. system. The AD627 also minimizes errors over frequency by With no external resistor, the AD627 is configured for a gain of 5. providing excellent CMRR over frequency. Because the CMRR With an external resistor, it can be set to a gain of up to 1000. remains high up to 200 Hz, line noise and line harmonics are A wide supply voltage range (+2.2 V to ±18 V) and micropower rejected. current consumption make the AD627 a perfect fit for a wide The AD627 provides superior performance, uses less circuit range of applications. Single-supply operation, low power board area, and costs less than micropower discrete designs. consumption, and rail-to-rail output swing make the AD627 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2007−2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD627 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Reference Terminal .................................................................... 16 Applications ....................................................................................... 1 Input Range Limitations in Single-Supply Applications ....... 16 Functional Block Diagram .............................................................. 1 Output Buffering ........................................................................ 17 General Description ......................................................................... 1 Input and Output Offset Errors ................................................ 17 Revision History ............................................................................... 2 Make vs. Buy: A Typical Application Error Budget ............... 18 Specifications ..................................................................................... 3 Errors Due to AC CMRR .......................................................... 19 Single Supply ................................................................................. 3 Ground Returns for Input Bias Currents ................................ 19 Dual Supply ................................................................................... 5 Layout and Grounding .............................................................. 20 Dual and Single Supplies ............................................................. 6 Input Protection ......................................................................... 21 Absolute Maximum Ratings ............................................................ 7 RF Interference ........................................................................... 21 ESD Caution .................................................................................. 7 Applications Circuits ...................................................................... 22 Pin Configurations and Function Descriptions ........................... 8 Classic Bridge Circuit ................................................................ 22 Typical Performance Characteristics ............................................. 9 4 mA to 20 mA Single-Supply Receiver .................................. 22 Theory of Operation ...................................................................... 14 Thermocouple Amplifier .......................................................... 22 Using the AD627 ............................................................................ 15 Outline Dimensions ....................................................................... 24 Basic Connections ...................................................................... 15 Ordering Guide .......................................................................... 24 Setting the Gain .......................................................................... 15 REVISION HISTORY 12/13—Rev. D to Rev. E 11/05—Rev. B to Rev. C Updated Format .................................................................. Universal Change to Voltage Noise, 1 kHz Parameter, Table 3 .................... 6 Added Pin Configurations and Function Changes to Figure 35 ...................................................................... 14 Descriptions Section ......................................................................... 8 Change to Equation 3, Input Range Limitations in Single- Change to Figure 33 ....................................................................... 13 Supply Applications Section .......................................................... 16 Updated Outline Dimensions ....................................................... 24 Changes to Table 8 .......................................................................... 17 Changes to Ordering Guide .......................................................... 24 Changes to Figure 40 ...................................................................... 17 Change to Table 9 ........................................................................... 18 Rev. A to Rev. B Change to 4 mA to 20 mA Single-Supply Receiver Section ..... 22 Changes to Figure 4 and Table I, Resulting Gain column ......... 11 Change to Figure 9 ......................................................................... 13 11/07—Rev. C to Rev. D Changes to Features .......................................................................... 1 Changes to Figure 29 to Figure 34 Captions ............................... 13 Changes to Setting the Gain Section ............................................ 15 Changes to Input Range Limitations in Single-Supply Applications Section ....................................................................... 16 Changes to Table 7 .......................................................................... 17 Changes to Figure 41 ...................................................................... 18 Rev. E | Page 2 of 24

Data Sheet AD627 SPECIFICATIONS SINGLE SUPPLY Typical at 25°C single supply, V = 3 V and 5 V, and R = 20 kΩ, unless otherwise noted. S L Table 1. AD627A AD627B Parameter Conditions Min Typ Max Min Typ Max Unit GAIN G = +5 + (200 kΩ/R ) G Gain Range 5 1000 5 1000 V/V Gain Error1 V = (−V) + 0.1 to (+V) − 0.15 OUT S S G = +5 0.03 0.10 0.01 0.06 % G = +10 0.15 0.35 0.10 0.25 % G = +100 0.15 0.35 0.10 0.25 % G = +1000 0.50 0.70 0.25 0.35 % Nonlinearity G = +5 10 100 10 100 ppm G = +100 20 100 20 100 ppm Gain vs. Temperature1 G = +5 10 20 10 20 ppm/°C G > +5 −75 −75 ppm/°C VOLTAGE OFFSET Input Offset, V 2 50 250 25 150 µV OSI Over Temperature V = V = +V/2 445 215 µV CM REF S Average TC 0.1 3 0.1 1 µV/°C Output Offset, V 1000 500 µV OSO Over Temperature 1650 1150 µV Average TC 2.5 10 2.5 10 µV/°C Offset Referred to the Input vs. Supply (PSRR) G = +5 86 100 86 100 dB G = +10 100 120 100 120 dB G = +100 110 125 110 125 dB G = +1000 110 125 110 125 dB INPUT CURRENT Input Bias Current 3 10 3 10 nA Over Temperature 15 15 nA Average TC 20 20 pA/°C Input Offset Current 0.3 1 0.3 1 nA Over Temperature 2 2 nA Average TC 1 1 pA/°C INPUT Input Impedance Differential 20||2 20||2 GΩ||pF Common-Mode 20||2 20||2 GΩ||pF Input Voltage Range3 V = 2.2 V to 36 V (−V) − 0.1 (+V) − 1 (−V) − 0.1 (+V) – 1 V S S S S S Common-Mode Rejection V = V/2 REF S Ratio3 DC to 60 Hz with 1 kΩ Source Imbalance G = +5 V = 3 V, V = 0 V to 1.9 V 77 90 83 96 dB S CM G = +5 V = 5 V, V = 0 V to 3.7 V 77 90 83 96 dB S CM OUTPUT Output Swing R = 20 kΩ (−V) + 25 (+V) − 70 (−V) + 25 (+V) − 70 mV L S S S S R = 100 kΩ (−V) + 7 (+V) − 25 (−V) + 7 (+V) − 25 mV L S S S S Short-Circuit Current Short circuit to ground ±25 ±25 mA Rev. E | Page 3 of 24

AD627 Data Sheet AD627A AD627B Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = +5 80 80 kHz G = +100 3 3 kHz G = +1000 0.4 0.4 kHz Slew Rate +0.05/−0.07 +0.05/−0.07 V/µs Settling Time to 0.01% V = 3 V, 1.5 V output step S G = +5 65 65 µs G = +100 290 290 µs Settling Time to 0.01% V = 5 V, 2.5 V output step S G = +5 85 85 µs G = +100 330 330 µs Overload Recovery 50% input overload 3 3 µs 1 Does not include effects of External Resistor RG. 2 See Table 8 for total RTI errors. 3 See the Using the AD627 section for more information on the input range, gain range, and common-mode range. Rev. E | Page 4 of 24

Data Sheet AD627 DUAL SUPPLY Typical at 25°C dual supply, V = ±5 V and ±15 V, and R = 20 kΩ, unless otherwise noted. S L Table 2. AD627A AD627B Parameter Conditions Min Typ Max Min Typ Max Unit GAIN G = +5 + (200 kΩ/R ) G Gain Range 5 1000 5 1000 V/V Gain Error1 V = (−V) + 0.1 to OUT S (+V) − 0.15 S G = +5 0.03 0.10 0.01 0.06 % G = +10 0.15 0.35 0.10 0.25 % G = +100 0.15 0.35 0.10 0.25 % G = +1000 0.50 0.70 0.25 0.35 % Nonlinearity G = +5 V = ±5 V/±15 V 10/25 100 10/25 100 ppm S G = +100 V = ±5 V/±15 V 10/15 100 10/15 100 ppm S Gain vs. Temperature1 G = +5 10 20 10 20 ppm/°C G > +5 –75 −75 ppm/°C VOLTAGE OFFSET Total RTI error = V + V /G OSI OSO Input Offset, V 2 25 200 25 125 µV OSI Over Temperature V = V = 0 V 395 190 µV CM REF Average TC 0.1 3 0.1 1 µV/°C Output Offset, V 1000 500 µV OSO Over Temperature 1700 1100 µV Average TC 2.5 10 2.5 10 µV/°C Offset Referred to the Input vs. Supply (PSRR) G = +5 86 100 86 100 dB G = +10 100 120 100 120 dB G = +100 110 125 110 125 dB G = +1000 110 125 110 125 dB INPUT CURRENT Input Bias Current 2 10 2 10 nA Over Temperature 15 15 nA Average TC 20 20 pA/°C Input Offset Current 0.3 1 0.3 1 nA Over Temperature 5 5 nA Average TC 5 5 pA/°C INPUT Input Impedance Differential 20||2 20||2 GΩ||pF Common Mode 20||2 20||2 GΩ||pF Input Voltage Range3 V = ±1.1 V to ±18 V (−V) − 0.1 (+V) − 1 (−V) − 0.1 (+V) − 1 V S S S S S Common-Mode Rejection Ratio3 DC to 60 Hz with 1 kΩ Source Imbalance G = +5 to +1000 V = ±5 V, V = 77 90 83 96 dB S CM −4 V to +3.0 V G = +5 to +1000 V = ±15 V, V = 77 90 83 96 dB S CM −12 V to +10.9 V OUTPUT Output Swing R = 20 kΩ (−V) + 25 (+V) − 70 (−V) + 25 (+V) − 70 mV L S S S S R = 100 kΩ (−V) + 7 (+V) − 25 (−V) + 7 (+V) − 25 mV L S S S S Short-Circuit Current Short circuit to ground ±25 ±25 mA Rev. E | Page 5 of 24

AD627 Data Sheet AD627A AD627B Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = +5 80 80 kHz G = +100 3 3 kHz G = +1000 0.4 0.4 kHz Slew Rate +0.05/−0.06 +0.05/−0.06 V/µs Settling Time to 0.01% V = ±5 V, S +5 V output step G = +5 135 135 µs G = +100 350 350 µs Settling Time to 0.01% V = ±15 V, S +15 V output step G = +5 330 330 µs G = +100 560 560 µs Overload Recovery 50% input overload 3 3 µs 1 Does not include effects of External Resistor RG. 2 See Table 8 for total RTI errors. 3 See the Using the AD627 section for more information on the input range, gain range, and common-mode range. DUAL AND SINGLE SUPPLIES Table 3. AD627A AD627B Parameter Conditions Min Typ Max Min Typ Max Unit NOISE Voltage Noise, 1 kHz TotalRTINoise= (e )2+(e /G)2 ni no Input, Voltage Noise, e 38 38 nV/√Hz ni Output, Voltage Noise, e 177 177 nV/√Hz no RTI, 0.1 Hz to 10 Hz G = +5 1.2 1.2 µV p-p G = +1000 0.56 0.56 µV p-p Current Noise f = 1 kHz 50 50 fA/√Hz 0.1 Hz to 10 Hz 1.0 1.0 pA p-p REFERENCE INPUT R R = ∞ 125 125 kΩ IN G Gain to Output 1 1 Voltage Range1 POWER SUPPLY Operating Range Dual supply ±1.1 ±18 ±1.1 ±18 V Single supply 2.2 36 2.2 36 V Quiescent Current 60 85 60 85 µA Over Temperature 200 200 nA/°C TEMPERATURE RANGE For Specified Performance −40 +85 −40 +85 °C 1 See Using the AD627 section for more information on the reference terminal, input range, gain range, and common-mode range. Rev. E | Page 6 of 24

Data Sheet AD627 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 4. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Supply Voltage ±18 V other conditions above those indicated in the operational Internal Power Dissipation1 section of this specification is not implied. Exposure to absolute PDIP (N-8) 1.3 W maximum rating conditions for extended periods may affect SOIC_N (R-8) 0.8 W device reliability. −IN, +IN −V − 20 V to +V + 20 V S S Common-Mode Input Voltage −V − 20 V to +V + 20 V S S Differential Input Voltage (+IN − (−IN)) +VS − (−VS) ESD CAUTION Output Short-Circuit Duration Indefinite Storage Temperature Range (N, R) −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C 1 Specification is for device in free air: 8-lead PDIP package: θJA = 90°C/W. 8-lead SOIC_N package: θJA = 155°C/W. Rev. E | Page 7 of 24

AD627 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS RG 1 8 RG RG 1 8 RG –+–VIINNS 234 (NTAoOtD Pto 6V S2IEc7aWle) 765 +ORVEUSFTPUT 00782-051 –+–VIINNS 234 (NToAOt DPto 6V S2IEc7aWle) 765 +ORVEUSFTPUT 00782-052 Figure 3. 8-Lead PDIP Pin Configuration Figure 4. 8-Lead SOIC_N Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 R External Gain Setting Resistor. Place gain setting resistor across R pins to set the gain. G G 2 −IN Negative Input. 3 +IN Positive Input. 4 −V Negative Voltage Supply Pin. S 5 REF Reference Pin. Drive with low impedance voltage source to level shift the output voltage. 6 OUTPUT Output Voltage. 7 +V Positive Supply Voltage. S 8 R External Gain Setting Resistor. Place gain setting resistor across R pins to set the gain. G G Rev. E | Page 8 of 24

Data Sheet AD627 TYPICAL PERFORMANCE CHARACTERISTICS At 25°C, V = ±5 V, R = 20 kΩ, unless otherwise noted. S L 100 –5.5 90 –5.0 80 E (nV/ Hz, RTI)765000 GAIN = +5 S CURRENT (nA)–––344...550 VS = +5VVS= ±5V S A OI40 BI–3.0 N T 30 PU GAIN = +100 N–2.5 I 20 VS = ±15V GAIN = +1000 –2.0 10 01 10 F1R00EQUENCY 1(Hkz) 10k 100k 00782-003 –1.–560 –40 –20 0TEMP2E0RAT4U0RE (°6C0) 80 100 120 140 00782-006 Figure 5. Voltage Noise Spectral Density vs. Frequency Figure 8. Input Bias Current vs. Temperature 100 65.5 90 80 A) 64.5 µ E (fA/ Hz)7600 URRENT ( 63.5 S C NT NOI5400 UPPLY 62.5 E S CURR30 WER 61.5 20 PO 60.5 10 01 10 FREQU1E0N0CY (Hz) 1k 10k 00782-004 59.50 5 TO1T0AL PO1W5ER SU20PPLY V2O5LTAG3E0 (V) 35 40 00782-007 Figure 6. Current Noise Spectral Density vs. Frequency Figure 9. Supply Current vs. Supply Voltage –3.2 V+ VS = ±15V –3.0 (V+) –1 S CURRENT (nA) ––22..86 LTAGE SWING (V)((VV++)) ––23 VS = ±S1O.5UVVRSC I=N ±G2.5V VS = ±5V A O INPUT BI –2.4 OUTPUT V(V–) +2 SINKING –2.2 (V–) +1 VS = ±2.5V VS = ±5V VS = ±1.5V VS = ±15V –2.0–15 –10 COM–5MON-MOD0E INPUT (V5) 10 15 00782-005 V–0 5 OUTP1U0T CURREN1T5 (mA) 20 25 00782-008 Figure 7. Input Bias Current vs. CMV, VS = ±15 V Figure 10. Output Voltage Swing vs. Output Current Rev. E | Page 9 of 24

AD627 Data Sheet 120 500mV 1s 110 100 100 G = +1000 B)90 R (d80 G = +100 R S P70 E V TI60 G = +5 SI O 10 P50 40 00782-009 320010 100 FREQUEN1kCY (Hz) 10k 100k 00782-012 Figure 11. 0.1 Hz to 10 Hz Current Noise (0.71 pA/DIV) Figure 14. Positive PSRR vs. Frequency, ±5 V 100 20mV 11ss 90 100 80 B)70 d RR (60 G = +1000 S P E 50 ATIV40 G = +100 G E 10 N30 G = +5 20 00782-010 10010 100 FREQUE1NkCY (Hz) 10k 100k 00782-013 Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise (400 nV/DIV), G = +5 Figure 15. Negative PSRR vs. Frequency, ±5 V 120 2V 1s 110 100 100 G = +1000 B)90 d R (80 G = +100 R S E P70 V SITI60 G = +5 O 10 P50 40 00782-011 320010 100 FREQUE1NkCY (Hz) 10k 100k 00782-014 Figure 13. 0.1 Hz to 10 Hz RTI Voltage Noise (200 nV/DIV), G = +1000 Figure 16. Positive PSRR vs. Frequency (VS = 5 V, 0 V) Rev. E | Page 10 of 24

Data Sheet AD627 10 400 300 ms) µs) E ( E ( M M TI TI G 1 G 200 N N LI LI T T T T E E S S 100 0.15 10 GAIN (V1/V0)0 1k 00782-015 00 ±2 OUT±P4UT PULSE ±(V6) ±8 ±10 00782-018 Figure 17. Settling Time to 0.01% vs. Gain for a 5 V Step at Output, RL = 20 kΩ, Figure 20. Settling Time to 0.01% vs. Output Swing, G = +5, RL = 20 kΩ, CL = 100 pF, VS = ±5 V CL = 100 pF 200µV 1V 100µs 1mV 1V 50µs 00782-016 00782-019 Figure 18. Large Signal Pulse Response and Settling Time, G = –5, RL = 20 kΩ, Figure 21. Large Signal Pulse Response and Settling Time, G = –100, CL = 100 pF (1.5 mV = 0.01%) RL = 20 kΩ, CL = 100 pF (100 µV = 0.01%) 1mV 1V 50µs 200µV 1V 500µs 00782-017 00782-020 Figure 19. Large Signal Pulse Response and Settling Time, G = −10, Figure 22. Large Signal Pulse Response and Settling Time, G = –1000, RL = 20 kΩ, CL = 100 pF (1.0 mV = 0.01%) RL = 20 kΩ, CL = 100 pF (10 µV = 0.01%) Rev. E | Page 11 of 24

AD627 Data Sheet 120 A 20µs 286mV EXT1 110 CH2 20mV 100 90 G = +1000 80 B) 70 R (d 60 G = +100 R M C 50 G = +5 40 30 20 1001 10 F1R0E0QUENCY (1Hkz) 10k 100k 00782-021 00782-024 Figure 23. CMRR vs. Frequency, ±5 VS (CMV = 200 mV p-p) Figure 26. Small Signal Pulse Response, G = +10, RL = 20 kΩ, CL = 50 pF 70 A 100µs 286mV EXT1 G = +1000 CH2 20mV 60 50 G = +100 40 30 dB) G = +10 N (20 AI G10 G = +5 0 –10 ––2300100 1k FREQUENCY (1H0zk) 100k 00782-022 00782-025 Figure 24. Gain vs. Frequency (VS = 5 V, 0 V), VREF = 2.5 V Figure 27. Small Signal Pulse Response, G = +100, RL = 20 kΩ, CL = 50 pF A 20µs 288mV EXT1 A 1ms 286mV EXT1 CH2 20mV CH2 50mV 00782-023 00782-026 Figure 25. Small Signal Pulse Response, G = +5, RL = 20 kΩ, CL = 50 pF Figure 28. Small Signal Pulse Response, G = +1000, RL = 20 kΩ, CL = 50 pF Rev. E | Page 12 of 24

Data Sheet AD627 20µV/DIV 200µV/DIV V0.O5UVT/DIV 00782-027 V3VO/UDTIV 00782-030 Figure 29. Gain Nonlinearity, Negative Input, Figure 32. Gain Nonlinearity, Negative Input, VS = ±2.5 V, G = +5 (4 ppm/DIV) VS = ±15 V, G = +100 (7 ppm/DIV) 40µV/DIV 200µV/DIV V0.O5UVT/DIV 00782-028 V3VO/UDTIV 00782-031 Figure 30. Gain Nonlinearity, Negative Input, Figure 33. Gain Nonlinearity, Negative Input, VS = ±2.5 V, G = +100 (8 ppm/DIV) VS = ±15 V, G = +5 (7 ppm/DIV) 40µV/DIV 200µV/DIV V3VO/UDTIV 00782-029 V3VO/UDTIV 00782-032 Figure 31. Gain Nonlinearity, Negative Input, Figure 34. Gain Nonlinearity, Negative Input, VS = ±15 V, G = +5 (1.5 ppm/DIV) VS = ±15 V, G = +100 (7 ppm/DIV) Rev. E | Page 13 of 24

AD627 Data Sheet THEORY OF OPERATION The AD627 is a true instrumentation amplifier, built using two The inverting terminal gain of A1 (1.25) times the gain of A2 feedback loops. Its general properties are similar to those of the (−4) makes the gain from the inverting and noninverting classic two-op-amp instrumentation amplifier configuration but terminals equal. internally the details are somewhat different. The AD627 uses a The differential mode gain is equal to 1 + R4/R3, nominally 5, modified current feedback scheme, which, coupled with interstage and is factory trimmed to 0.01% final accuracy. Adding an feedforward frequency compensation, results in a much better external gain setting resistor (R ) increases the gain by an G common-mode rejection ratio (CMRR) at frequencies above amount equal to (R4 + R1)/R . The output voltage of the G dc (notably the line frequency of 50 Hz to 60 Hz) than might AD627 is given by otherwise be expected of a low power instrumentation amplifier. V = [V (+) – V (−)] × (5 + 200 kΩ/R ) + V (1) OUT IN IN G REF In Figure 35, A1 completes a feedback loop that, in conjunction Laser trims are performed on R1 through R4 to ensure that with V1 and R5, forces a constant collector current in Q1. Assume their values are as close as possible to the absolute values in the that the gain-setting resistor (R ) is not present. Resistors R2 G gain equation. This ensures low gain error and high common- and R1 complete the loop and force the output of A1 to be equal mode rejection at all practical gains. to the voltage on the inverting terminal with a gain of nearly 1.25. A2 completes a nearly identical feedback loop that forces a current in Q2 that is nearly identical to that in Q1; A2 also provides the output voltage. When both loops are balanced, the gain from the noninverting terminal to V is equal to 5, OUT whereas the gain from the output of A1 to V is equal to −4. OUT EXTERNAL GAIN RESISTOR R1 RG R4 100kΩ 100kΩ REF R2 R3 25kΩ 25kΩ +VS +VS 2kΩ 2kΩ –IN Q1 Q2 +IN –VS –VS A1 A2 OUTPUT R2050kΩ V1 0.1V R2060kΩ –VS 00782-033 Figure 35. Simplified Schematic Rev. E | Page 14 of 24

Data Sheet AD627 USING THE AD627 BASIC CONNECTIONS SETTING THE GAIN Figure 36 shows the basic connection circuit for the AD627. The gain of the AD627 is resistor programmed by RG, or, more precisely, by whatever impedance appears between Pin 1 and Pin 8. The +V and −V terminals connect to the power supply. The S S supply can be either bipolar (VS = ±1.1 V to ±18 V) or single The gain is set according to supply (−V = 0 V, +V = 2.2 V to 36 V). Capacitively decouple S S Gain = 5 + (200 kΩ/R ) or R = 200 kΩ/(Gain − 5) (2) G G the power supplies close to the power pins of the device. For Therefore, the minimum achievable gain is 5 (for 200 kΩ/ best results, use surface-mount 0.1 µF ceramic chip capacitors. (Gain − 5)). With an internal gain accuracy of between 0.05% The input voltage can be single-ended (tie either −IN or +IN to and 0.7%, depending on gain and grade, a 0.1% external gain ground) or differential. The difference between the voltage on the resistor is appropriate to prevent significant degradation of the inverting and noninverting pins is amplified by the programmed overall gain error. However, 0.1% resistors are not available in a gain. The gain resistor programs the gain as described in the wide range of values and are quite expensive. Table 6 shows Setting the Gain and Reference Terminal sections. Basic recommended gain resistor values using 1% resistors. For all connections are shown in Figure 36. The output signal appears gains, the size of the gain resistor is conservatively chosen as the as the voltage difference between the output pin and the closest value from the standard resistor table that is higher than externally applied voltage on the REF pin, as shown in Figure 37. the ideal value. This results in a gain that is always slightly less than the desired gain, thereby preventing clipping of the signal at the output due to resistor tolerance. The internal resistors on the AD627 have a negative temperature coefficient of −75 ppm/°C maximum for gains > 5. Using a gain resistor that also has a negative temperature coefficient of −75 ppm/°C or less tends to reduce the overall gain drift of the circuit. +VS +VS +1.1V TO +18V +2.2V TO +36V 0.1µF 0.1µF +IN +IN RG RG VIN RG OUTPUT VOUT VIN RG OUTPUT VOUT –IN RG REF –IN RG REF REF (INPUT) REF (INPUT) 0.1µF –VS –1.1V TO –18V GAIN = 5 + (200kΩ/RG) 00782-034 Figure 36. Basic Connections for Single and Dual Supplies V+ VDIFF +IN EXTERNAL GAIN RESISTOR 2 RG 100kΩ 25kΩ 25kΩ 100kΩ REF VCM VDIFF +VS +VS 2 –IN –IN 2kΩ 2kΩ +IN Q1 Q2 V– –VS –VS A1 A2 OUTPUT 200kΩ 0.1V VA 200kΩ –VS 00782-035 Figure 37. Amplifying Differential Signals with a Common-Mode Component Rev. E | Page 15 of 24

AD627 Data Sheet Table 6. Recommended Values of Gain Resistors The voltage on A1 can also be expressed as a function of the 1% Standard Table actual voltages on the –IN and +IN pins (V− and V+) such that Desired Gain Value of R Resulting Gain G V = 1.25 ((V−) + 0.5 V) − 0.25 V − ((V+) − (V−)) 25 kΩ/R (4) A1 REF G 5 ∞ 5.00 6 200 kΩ 6.00 The output of A1 is capable of swinging to within 50 mV of the negative rail and to within 200 mV of the positive rail. It is clear, 7 100 kΩ 7.00 from either Equation 3 or Equation 4, that an increasing V 8 68.1 kΩ 7.94 REF (while it acts as a positive offset at the output of the AD627) 9 51.1 kΩ 8.91 tends to decrease the voltage on A1. Figure 38 and Figure 39 10 40.2 kΩ 9.98 show the maximum voltages that can be applied to the REF pin 15 20 kΩ 15.00 for a gain of 5 for both the single-supply and dual-supply cases. 20 13.7 kΩ 19.60 25 10 kΩ 25.00 5 30 8.06 kΩ 29.81 4 40 5.76 kΩ 39.72 3 50 4.53 kΩ 49.15 2 60 3.65 kΩ 59.79 MAXIMUM VREF 1 70 3.09 kΩ 69.72 V) 80 2.67 kΩ 79.91 (REF 0 V 90 2.37 kΩ 89.39 –1 MINIMUM VREF 100 2.1 kΩ 100.24 –2 200 1.05 kΩ 195.48 –3 500 412 Ω 490.44 –4 1000 205 Ω 980.61 –5–6 –5 –4 –3 –2 V–I1N(–) (V0) 1 2 3 4 00782-036 REFERENCE TERMINAL Figure 38. Reference Input Voltage vs. Negative Input Voltage, The reference terminal potential defines the zero output voltage VS = ±5 V, G = +5 5 and is especially useful when the load does not share a precise ground with the rest of the system. It provides a direct means of MAXIMUM VREF injecting a precise offset to the output. The reference terminal is 4 also useful when amplifying bipolar signals, because it provides a virtual ground voltage. V) 3 The AD627 output voltage is developed with respect to the poten- (EF R tial on the reference terminal; therefore, tying the REF pin to the V 2 appropriate local ground solves many grounding problems. For optimal CMR, tie the REF pin to a low impedance point. MINIMUM VREF 1 INPUT RANGE LIMITATIONS IN SINGLE-SUPPLY APPLICATIONS Ianv agielanbelrea ol,u tthpeu mt saigxnimalu rman agceh. iHevoawbelev egra, iinn issi ndgetlee-rsmuipnpeldy abpyp tlhicea - –00.5 0 0.5 1.0 1.5 VI2N.(0–) (V2).5 3.0 3.5 4.0 4.5 00782-037 Figure 39. Reference Input Voltage vs. Negative Input Voltage, tions where the input common-mode voltage is nearly or equal VS = 5 V, G = +5 to 0, some limitations on the gain can be set. Although the Specifications section nominally defines the input, output, and Raising the input common-mode voltage increases the voltage reference pin ranges, the voltage ranges on these pins are on the output of A1. However, in single-supply applications mutually interdependent. Figure 37 shows the simplified where the common-mode voltage is low, a differential input schematic of the AD627, driven by a differential voltage (V ) voltage or a voltage on REF that is too high can drive the output DIFF that has a common-mode component, V . The voltage on the of A1 into the ground rail. Some low-side headroom is added CM A1 op amp output is a function of V , V , the voltage on the because both inputs are shifted upwards by about 0.5 V (that is, DIFF CM REF pin, and the programmed gain. This voltage is given by by the VBE of Q1 and Q2). Use Equation 3 and Equation 4 to check whether the voltage on Amplifier A1 is within its V = 1.25 (V + 0.5 V) − 0.25 V − V (25 kΩ/R + 0.625) (3) A1 CM REF DIFF G operating range. Rev. E | Page 16 of 24

Data Sheet AD627 Table 7. Maximum Gain for Low Common-Mode, Single-Supply Applications V REF Pin Supply Voltage R (1% Tolerance) Resulting Maximum Gain Output Swing WRT 0 V IN G ±100 mV, V = 0 V 2 V 5 V to 15 V 28.7 kΩ 12.0 0.8 V to 3.2 V CM ±50 mV, V = 0 V 2 V 5 V to 15 V 10.7 kΩ 23.7 0.8 V to 3.2 V CM ±10 mV, V = 0 V 2 V 5 V to 15 V 1.74 kΩ 119.9 0.8 V to 3.2 V CM V− = 0 V, V+ = 0 V to 1 V 1 V 10 V to 15 V 78.7 kΩ 7.5 1 V to 8.5 V V− = 0 V, V+ = 0 mV to 100 mV 1 V 5 V to 15 V 7.87 kΩ 31 1 V to 4.1 V V− = 0 V, V+ = 0 mV to 10 mV 1 V 5 V to 15 V 787 Ω 259.1 1 V to 3.6 V Table 8. RTI Error Sources Maximum Total RTI Offset Error (μV) Maximum Total RTI Offset Drift (μV/°C) Total RTI Noise (nV/√Hz) Gain AD627A AD627B AD627A AD627B AD627A/AD627B +5 450 250 5 3 52 +10 350 200 4 2 42 +20 300 175 3.5 1.5 39 +50 270 160 3.2 1.2 38 +100 270 155 3.1 1.1 38 +500 252 151 3 1 38 +1000 251 151 3 1 38 Table 7 gives values for the maximum gain for various single- INPUT AND OUTPUT OFFSET ERRORS supply input conditions. The resulting output swings refer to The low errors of the AD627 are attributed to two sources, 0 V. To maximize the available gain and output swing, set the input and output errors. The output error is divided by G when voltages on the REF pins to either 2 V or 1 V. In most cases, referred to the input. In practice, input errors dominate at high there is no advantage to increasing the single supply to greater gains and output errors dominate at low gains. The total offset than 5 V (the exception is an input range of 0 V to 1 V). error for a given gain is calculated as OUTPUT BUFFERING Total Error RTI = Input Error + (Output Error/Gain) (5) The AD627 is designed to drive loads of 20 kΩ or greater but Total Error RTO = (Input Error × G) + Output Error (6) can deliver up to 20 mA to heavier loads at lower output voltage RTI offset errors and noise voltages for different gains are listed swings (see Figure 10). If more than 20 mA of output current is in Table 8. required at the output, buffer the AD627 output with a precision op amp, such as the OP113. Figure 40 shows this for a single supply. This op amp can swing from 0 V to 4 V on its output while driving a load as small as 600 Ω. +VS 0.1µF 0.1µF VIN RG AD627 REF OP113 VOUT 0.1µF 0.1µF –VS –VS 00782-038 Figure 40. Output Buffering Rev. E | Page 17 of 24

AD627 Data Sheet MAKE vs. BUY: A TYPICAL APPLICATION ERROR The errors associated with each implementation (see Table 9) BUDGET show the integrated in-amp to be more precise at both ambient and overtemperature. Note that the discrete implementation is The example in Figure 41 serves as a good comparison between more expensive, primarily due to the relatively high cost of the the errors associated with an integrated and a discrete in-amp low drift precision resistor network. implementation. A ±100 mV signal from a resistive bridge (common-mode voltage = 2.5 V) is amplified. This example The input offset current of the discrete instrumentation amplifier compares the resulting errors from a discrete two-op-amp implementation is the difference in the bias currents of the two- instrumentation amplifier and the AD627. The discrete op amplifiers, not the offset currents of the individual op amps. implementation uses a four-resistor precision network In addition, although the values of the resistor network are chosen (1% match, 50 ppm/°C tracking). so that the inverting and noninverting inputs of each op amp see the same impedance (about 350 Ω), the offset current of each op amp adds another error that must be characterized. +5V +5V +5V 350Ω 350Ω LT10781SB 350Ω 350Ω 40.21Rk%ΩG AD627A VOUT LT10781SB 1/2 VOUT ±100mV +10ppm/°C 1/2 +2.5V 3.15kΩ* 350Ω* 350Ω* 3.15kΩ* AD627A GAIN = 9.98 (5+(200kΩ/RG)) +2.5V *1% RESHISOTMOERB MREAWTC IHN,- A50MpPp,m G/ °=C +T1R0ACKING 00782-039 Figure 41. Make vs. Buy Table 9. Make vs. Buy Error Budget Total Error Total Error AD627 Homebrew Error Source AD627 Circuit Calculation Homebrew Circuit Calculation (ppm) (ppm) ABSOLUTE ACCURACY at T = 25°C A Total RTI Offset Voltage, mV (250 μV + (1000 μV/10))/100 mV (180 μV × 2)/100 mV 3,500 3,600 Input Offset Current, nA 1 nA × 350 Ω/100 mV 20 nA × 350 Ω/100 mV 3.5 70 Internal Offset Current Not applicable 0.7 nA × 350 Ω/100 mV 2.45 (Homebrew Only) CMRR, dB 77 dB→141 ppm × 2.5 V/100 mV (1% match × 2.5 V)/10/100 mV 3,531 25,000 Gain 0.35% + 1% 1% match 13,500 10,000 Total Absolute Error 20,535 38,672 DRIFT TO 85°C Gain Drift, ppm/°C (−75 + 10) ppm/°C × 60°C 50 ppm/°C × 60°C 3,900 3,000 Total RTI Offset Voltage, mV/°C (3.0 μV/°C + (10 μV/°C/10)) × (2 × 3.5 μV/°C × 60°C)/100 mV 2,600 4,200 60°C/100 mV Input Offset Current, pA/°C (16 pA/°C × 350 Ω × 60°C)/100 mV (33 pA/°C × 350 Ω × 60°C)/100 mV 3.5 7 Total Drift Error 6,504 7,207 Grand Total Error 27,039 45,879 Rev. E | Page 18 of 24

Data Sheet AD627 ERRORS DUE TO AC CMRR GROUND RETURNS FOR INPUT BIAS CURRENTS In Table 9, the error due to common-mode rejection results Input bias currents are dc currents that must flow to bias the from the common-mode voltage from the bridge 2.5 V. The input transistors of an amplifier. They are usually transistor base ac error due to less than ideal common-mode rejection cannot currents. When amplifying floating input sources, such as be calculated without knowing the size of the ac common-mode transformers or ac-coupled sources, there must be a direct dc voltage (usually interference from 50 Hz/60 Hz mains frequencies). path into each input so that the bias current can flow. Figure 44, Figure 45, and Figure 46 show how to provide a bias current A mismatch of 0.1% between the four gain setting resistors path for the cases of, respectively, transformer coupling, a determines the low frequency CMRR of a two-op-amp thermocouple application, and capacitive ac-coupling. instrumentation amplifier. The plot in Figure 43 shows the practical results of resistor mismatch at ambient temperature. In dc-coupled resistive bridge applications, providing this path is generally not necessary because the bias current simply flows The CMRR of the circuit in Figure 42 (Gain = +11) was from the bridge supply through the bridge and into the amplifier. measured using four resistors with a mismatch of nearly 0.1% However, if the impedance that the two inputs see are large, and (R1 = 9999.5 Ω, R2 = 999.76 Ω, R3 = 1000.2 Ω, R4 = 9997.7 Ω). differ by a large amount (>10 kΩ), the offset current of the input As expected, the CMRR at dc was measured at about 84 dB stage causes dc errors compatible with the input offset voltage of (calculated value is 85 dB). However, as frequency increases, the amplifier. CMRR quickly degrades. For example, a 200 mV p-p harmonic of the mains frequency at 180 Hz would result in an output +VS –INPUT 2 voltage of about 800 µV. To put this in context, a 12-bit data 7 1 acquisition system, with an input range of 0 V to 2.5 V, has an RG AD627 6 VOUT LSB weighting of 610 µV. 8 5 By contrast, the AD627 uses precision laser trimming of internal +INPUT 3 4 REFERENCE LOAD rdecs iCstMorRs,R a alonndg a w witihd epra bteanntdewd iCdMth Ro vterirm wmhiicnhg ,t htoe yCieMldR aR h iisg fhlaetr –VS TSGOURP OPPUOLNWYDER 00782-042 (see Figure 23). Figure 44. Ground Returns for Bias Currents with Transformer Coupled Inputs +5V +VS –INPUT 2 A2 1 7 VIN– OP1/2296 VOUT RG AD627 6 VOUT VIN+ A1 8 5 OP1/2296 +INPUT 3 4 REFERENCE LOAD R1 R–52V R3 R4 –VS TSGOURP OPPUOLNWYDER 00782-043 9999.5Ω 999.76Ω 1000.2Ω 9997.7Ω 00782-040 Figure 45. Ground Returns for +BViaSs Currents with Thermocouple Inputs Figure 42. 0.1% Resistor Mismatch Example –INPUT 2 7 120 1 110 RG AD627 6 VOUT 8 5 100 +INPUT 3 4 REFERENCE LOAD RR (dB) 9800 100kΩ –VS TSGOURP OPPUOLNWYDER 00782-044 CM 70 Figure 46. Ground Returns for Bias Currents with AC-Coupled Inputs 60 50 40 30 201 10 F1R0E0QUENCY 1(Hkz) 10k 100k 00782-041 Figure 43. CMRR over Frequency of Discrete In-Amp in Figure 42 Rev. E | Page 19 of 24

AD627 Data Sheet LAYOUT AND GROUNDING If there is only one power supply available, it must be shared by both digital and analog circuitry. Figure 48 shows how to minimize The use of ground planes is recommended to minimize the interference between the digital and analog circuitry. As in the impedance of ground returns (and hence, the size of dc errors). previous case, use separate analog and digital ground planes or To isolate low level analog signals from a noisy digital environment, use reasonably thick traces as an alternative to a digital ground many data acquisition components have separate analog and plane. Connect the ground planes at the ground pin of the power digital ground returns (see Figure 47). Return all ground pins supply. Run separate traces (or power planes) from the power from mixed-signal components, such as analog-to-digital supply to the supply pins of the digital and analog circuits. Ideally, converters, through the high quality analog ground plane. each device should have its own power supply trace, but they Digital ground lines of mixed-signal components should also can be shared by multiple devices if a single trace is not used to be returned through the analog ground plane. This may seem route current to both digital and analog circuitry. to break the rule of separating analog and digital grounds; however, in general, there is also a requirement to keep the voltage difference between digital and analog grounds on a converter as small as possible (typically, <0.3 V). The increased noise, caused by the digital return currents of the converter flowing through the analog ground plane, is generally negligible. To maximize isolation between analog and digital, connect the ground planes back at the supplies. ANALOG POWER SUPPLY DIGITAL POWER SUPPLY +5V –5V GND GND +5V 0.1µF 0.1µF 0.1µF 0.1µF 7 2 4 1 6 14 AADD662277 6 4 VIN1 VDD AGND DGND 12 AGND VDD 3 5 3 VIN2 ADC AD7892-2 PRMOCICERSOS-OR 00782-045 Figure 47. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies POWER SUPPLY 5V GND 0.1µF 0.1µF 0.1µF 7 1 2 4 VDD AGND DGND 12 VDD DGND AD627 6 4 VIN MICRO- 3 5 ADC AD7892-2 PROCESSOR 00782-046 Figure 48. Optimal Ground Practice in a Single-Supply Environment Rev. E | Page 20 of 24

Data Sheet AD627 INPUT PROTECTION Capacitor C3 is needed to maintain common-mode rejection at low frequencies. R1/R2 and C1/C2 form a bridge circuit whose As shown in the simplified schematic (see Figure 35), both the output appears across the input pins of the in-amp. Any mismatch inverting and noninverting inputs are clamped to the positive between C1 and C2 unbalances the bridge and reduces common- and negative supplies by ESD diodes. In addition, a 2 kΩ series mode rejection. C3 ensures that any RF signals are common resistor on each input provides current limiting in the event of mode (the same on both in-amp inputs) and are not applied an overvoltage. These ESD diodes can tolerate a maximum differentially. This second low-pass network, R1 + R2 and C3, continuous current of 10 mA. So an overvoltage (that is, the has a −3 dB frequency equal to amount by which the input voltage exceeds the supply voltage) of ±20 V can be tolerated. This is true for all gains, and for 1/(2π((R1 + R2) × C3)) (8) power on and off. This last case is particularly important +VS because the signal source and amplifier can be powered 0.33µF 0.01µF separately. C1 R1 1000pF If the overvoltage is expected to exceed 20 V, use additional 20kΩ 5% 1% external series current-limiting resistors to keep the diode +IN current below 10 mA. 20Rk2Ω 0.022CµF3 RG AD627 VOUT 1% RF INTERFERENCE –IN REFERENCE C2 1000pF All instrumentation amplifiers can rectify high frequency out- 5% 0.33µF 0.01µF oerf-rboarsn adt stihgen aolust. pOunt.c Te hreec ctiirfcieudit, tihne Fsieg suirgen 4al9s parpopveiadre sa sg dooc do fRfsFeIt –VS 00782-047 suppression without reducing performance within the pass Figure 49. Circuit to Attenuate RF Interference band of the instrumentation amplifier. Resistor R1 and Using a C3 value of 0.022 μF, as shown in Figure 49, the −3 dB Capacitor C1 (and likewise, R2 and C2) form a low-pass RC signal bandwidth of this circuit is approximately 200 Hz. The filter that has a –3 dB BW equal to typical dc offset shift over frequency is less than 1 mV and the f = 1/(2π(R1 × C1)) (7) RF signal rejection of the circuit is better than 57 dB. To increase the 3 dB signal bandwidth of this circuit, reduce the value of Using the component values shown in Figure 49, this filter has Resistor R1 and Resistor R2. The performance is similar to that a –3 dB bandwidth of approximately 8 kHz. Resistor R1 and when using 20 kΩ resistors, except that the circuitry preceding Resistor R2 were selected to be large enough to isolate the circuit the in-amp must drive a lower impedance load. input from the capacitors but not large enough to significantly increase circuit noise. To preserve common-mode rejection in When building a circuit like that shown in Figure 49, use a PC the amplifier pass band, Capacitor C1 and Capacitor C2 must board with a ground plane on both sides. Make all component be 5% mica units, or low cost 20% units can be tested and binned leads as short as possible. Resistor R1 and Resistor R2 can be to provide closely matched devices. common 1% metal film units, but Capacitor C1 and Capacitor C2 must be ±5% tolerance devices to avoid degrading the common- mode rejection of the circuit. Either the traditional 5% silver mica units or Panasonic ±2% PPS film capacitors are recommended. Rev. E | Page 21 of 24

AD627 Data Sheet APPLICATIONS CIRCUITS CLASSIC BRIDGE CIRCUIT 4 mA TO 20 mA SINGLE-SUPPLY RECEIVER Figure 50 shows the AD627 configured to amplify the signal Figure 51 shows how a signal from a 4 mA to 20 mA transducer from a classic resistive bridge. This circuit works in dual-supply can be interfaced to the ADuC812, a 12-bit ADC with an mode or single-supply mode. Typically, the same voltage that embedded microcontroller. The signal from a 4 mA to 20 mA powers the instrumentation amplifiers excites the bridge. transducer is single-ended, which initially suggests the need for Connecting the bottom of the bridge to the negative supply of a simple shunt resistor to convert the current to a voltage at the the instrumentation amplifiers (usually 0 V, −5 V, −12 V, or high impedance analog input of the converter. However, any −15 V), sets up an input common-mode voltage that is line resistance in the return path (to the transducer) adds a optimally located midway between the supply voltages. It is current dependent offset error; therefore, the current must be sensed differentially. also appropriate to set the voltage on the REF pin to midway between the supplies, especially if the input signal is bipolar. In this example, a 24.9 Ω shunt resistor generates a maximum However, the voltage on the REF pin can be varied to suit the differential input voltage to the AD627 of between 100 mV application. For example, the REF pin is tied to the VREF pin of (for 4 mA in) and 500 mV (for 20 mA in). With no gain resistor an analog-to-digital converter (ADC) whose input range is present, the AD627 amplifies the 500 mV input voltage by a (VREF ± VIN). With an available output swing on the AD627 of factor of 5, to 2.5 V, the full-scale input voltage of the ADC. The (−VS + 100 mV) to (+VS − 150 mV), the maximum programmable zero current of 4 mA corresponds to a code of 819 and the LSB gain is simply this output range divided by the input range. size is 4.88 μA. +VS THERMOCOUPLE AMPLIFIER 0.1µF Because the common-mode input range of the AD627 extends 0.1 V below ground, it is possible to measure small differential signals that have a low, or no, common-mode component. VDIFF RG =G2A00INkΩ–5 AD627 VOUT Figure 51 shows a thermocouple application where one side of the J-type thermocouple is grounded. 0.1µF VREF Over a temperature range from −200°C to +200°C, the J-type –VS 00782-048 t+h1e0r.m77o7c omuVp.l eA d perliovgerrasm a mvoeldta ggaei nra onng itnhge fAroDm6 2−77 .o8f9 100 m0 (VR to = Figure 50. Classic Bridge Circuit G 2.1 kΩ) and a voltage on the AD627 REF pin of 2 V result in the output voltage of the AD627 ranging from 1.110 V to 3.077 V relative to ground. For a different input range or different voltage on the REF pin, it is important to verify that the voltage on Internal Node A1 (see Figure 37) is not driven below ground. This can be checked using the equations in the Input Range Limitations in Single-Supply Applications section. 5V 0.1µF THERMOCJO-UTYPPLEE 2.1RkΩG AD627 VOUT REF VREF 00782-050 Figure 51. Amplifying Bipolar Signals with Low Common-Mode Voltage Rev. E | Page 22 of 24

Data Sheet AD627 5V 5V 5V 0.1µF 0.1µF 0.1µF VREF AVDD DVDD ADuC812 TRA4N–2S0DmUACER IMPELDINAENCE 4–20mA 24.9Ω G = +5 AADD662277 AtoI NA I0N 7 MICROCONVERTER® REF AGND DGND 00782-049 Figure 52. 4 mA to 20 mA Receiver Circuit Rev. E | Page 23 of 24

AD627 Data Sheet OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 0.280 (7.11) 0.250 (6.35) 5.00(0.1968) 1 4 0.240 (6.10) 0.325 (8.26) 4.80(0.1890) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 8 5 0.210 (5.33) MAX 0.130 (3.30) 4.00(0.1574) 6.20(0.2441) MAX 0.115 (2.92) 3.80(0.1497) 1 4 5.80(0.2284) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.11500 (..200.219282 )((00..5466)) 0M.0IN05SP LE(0AA.TN13IEN)G PLANE 0.43M0 A(1X0.92) 000...000110408 (((000...322650))) 0.25(0.0098) 1.27B(0S.C0500) 11..7355((00..00658382)) 8° 00..5205((00..00109969)) 45° 0.014 (0.36) 0.10(0.0040) 0° 0.070 (1.78) COPLANARITY 0.51(0.0201) 00..006405 ((11..5124)) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS COMPLIANTTOJEDECSTANDARDSMS-012-AA (RCINEOFRPEFANRiREgERENuN LCrTEeEHA EO5DSN3SEL .MS Y8)AA-AYLNR BeDEEa AR dCROOE UP NNNlFaODIGsETtUDAiR-cPOE PDFDRFuOA INaSPC RlW HIIAnH ETO-EQLL UiFEnIO VOeRAR LPU EHaSNAEcTL kISFNa FLDgOEEAeRSD I[GSPN.D.IP] 070606-A C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Narrow Body (N-8) Figure 54. 8-Lead Small Standard Outline Package [SOIC_N] Dimensions shown in inches (and millimeters) Narrow Body (R-8) Dimensions shown in millimeters (and inches) ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD627ANZ −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8 AD627AR −40°C to +85°C 8-Lead Small Standard Outline [SOIC_N] R-8 AD627AR-REEL −40°C to +85°C 8-Lead Small Standard Outline [SOIC_N] R-8 AD627AR-REEL7 −40°C to +85°C 8-Lead Small Standard Outline [SOIC_N] R-8 AD627ARZ −40°C to +85°C 8-Lead Small Standard Outline [SOIC_N] R-8 AD627ARZ-R7 −40°C to +85°C 8-Lead Small Standard Outline [SOIC_N] R-8 AD627ARZ-RL −40°C to +85°C 8-Lead Small Standard Outline [SOIC_N] R-8 AD627BNZ −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8 AD627BR −40°C to +85°C 8-Lead Small Standard Outline [SOIC_N] R-8 AD627BR-REEL −40°C to +85°C 8-Lead Small Standard Outline [SOIC_N] R-8 AD627BR-REEL7 −40°C to +85°C 8-Lead Small Standard Outline [SOIC_N] R-8 AD627BRZ −40°C to +85°C 8-Lead Small Standard Outline [SOIC_N] R-8 AD627BRZ-RL −40°C to +85°C 8-Lead Small Standard Outline [SOIC_N] R-8 AD627BRZ-R7 −40°C to +85°C 8-Lead Small Standard Outline [SOIC_N] R-8 1 Z = RoHS Compliant part. ©2007−2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00782-0-12/13(E) Rev. E | Page 24 of 24

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD627ANZ AD627ARZ AD627BNZ AD627BRZ AD627AR AD627AR-REEL AD627AR-REEL7 AD627ARZ-R7 AD627ARZ-RL AD627BRZ-R7 AD627BRZ-RL