a Low Power Mixer 3 V Receiver IF Subsystem AD607 FEATURES PIN CONFIGURATION Complete Receiver-on-a-Chip: Monoceiver® Mixer –15 dBm 1 dB Compression Point 20-Lead SSOP –8 dBm Input Third Order Intercept (RS Suffix) 500 MHz RF and LO Bandwidths Linear IF Amplifier Linear-in-dB Gain Control FDIN 1 20 VPS1 Manual Gain Control COM1 2 19 FLTR Quadrature Demodulator PRUP 3 18 IOUT On-Board Phase-Locked Quadrature Oscillator LOIP 4 17 QOUT Demodulates IFs from 400 kHz to 12 MHz RFLO 5 AD607 16 VPS2 Can Also Demodulate AM, CW, SSB Low Power RFHI 6 (NToOt Pto V SIEcaWle)15 DMIP 25 mW at 3 V GREF 7 14 IFOP CMOS Compatible Power-Down MXOP 8 13 COM2 Interfaces to AD7013 and AD7015 Baseband Converters VMID 9 12 GAIN IFHI 10 11 IFLO APPLICATIONS GSM, CDMA, TDMA, and TETRA Receivers Satellite Terminals Battery-Powered Communications Receivers GENERAL DESCRIPTION The I and Q demodulators provide in-phase and quadrature The AD607 is a 3 V low power receiver IF subsystem for opera- baseband outputs to interface with Analog Devices’ AD7013 tion at input frequencies as high as 500 MHz and IFs from (IS54, TETRA, MSAT) and AD7015 (GSM) baseband con- 400 kHz to 12 MHz. It consists of a mixer, IF amplifiers, I and verters. A quadrature VCO phase-locked to the IF drives the I Q demodulators, a phase-locked quadrature oscillator, and a and Q demodulators. The I and Q demodulators can also biasing system with external power-down. demodulate AM; when the AD607’s quadrature VCO is phase- locked to the received signal, the in-phase demodulator becomes The AD607’s low noise, high intercept mixer is a doubly a synchronous product detector for AM. The VCO can also be balanced Gilbert cell type. It has a nominal –15 dBm input phase-locked to an external beat-frequency oscillator (BFO), referred 1 dB compression point and a –8 dBm input referred and the demodulator serves as a product detector for CW or third order intercept. The mixer section of the AD607 also SSB reception. Finally, the AD607 can be used to demodulate includes a local oscillator (LO) preamplifier, which lowers the BPSK using an external Costas Loop for carrier recovery. required LO drive to –16 dBm. In MGC operation, the AD607 accepts an external gain-control voltage input from an external AGC detector or a DAC. Monoceiver is a registered trademark of Analog Devices, Inc. REV.C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002

AD607–SPECIFICATIONS (@ T = 25(cid:1)C, Supply = 3.0 V, IF = 10.7 MHz, unless otherwise noted.) A AD607ARS Model Conditions Min Typ Max Unit DYNAMIC PERFORMANCE MIXER Maximum RF and LO Frequency Range For Conversion Gain > 20 dB 500 MHz Maximum Mixer Input Voltage For Linear Operation; Between RFHI and RFLO ±54 mV Input 1 dB Compression Point RF Input Terminated in 50 Ω –15 dBm Input Third-Order Intercept RF Input Terminated in 50 Ω –5 dBm Noise Figure Matched Input, Max Gain, f = 83 MHz, IF = 10.7 MHz 14 dB Matched Input, Max Gain, f = 144 MHz, IF = 10.7 MHz 12 dB Maximum Output Voltage at MXOP Z = 165 Ω, at Input Compression ±1.3 V IF Mixer Output Bandwidth at MXOP –3 dB, Z = 165 Ω 45 MHz IF LO Drive Level Mixer LO Input Terminated in 50 Ω –16 dBm LO Input Impedance LOIP to VMID 1 kΩ Isolation, RF to IF RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz 30 dB Isolation, LO to IF RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz 20 dB Isolation, LO to RF RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz 40 dB Isolation, IF to RF RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz 70 dB IF AMPLIFIERS Noise Figure Max Gain, f = 10.7 MHz 17 dB Input 1 dB Compression Point IF = 10.7 MHz –15 dBm Output Third-Order Intercept IF = 10.7 MHz 18 dBm Maximum IF Output Voltage at IFOP Z = 600 Ω ±560 mV IF Output Resistance at IFOP From IFOP to VMID 15 Ω Bandwidth –3 dB at IFOP, Max Gain 45 MHz GAIN CONTROL (See Figures 23 and 24) Gain Control Range Mixer + IF Section, GREF to 1.5 V 90 dB Gain Scaling GREF to 1.5 V 20 mV/dB GREF to General Reference Voltage V 75/V dB/V R R Gain Scaling Accuracy GREF to 1.5 V, 80 dB Span ±1 dB Bias Current at GAIN 5 µA Bias Current at GREF 1 µA Input Resistance at GAIN, GREF 1 MΩ I AND Q DEMODULATORS Required DC Bias at DMIP VPOS/2 V dc Input Resistance at DMIP From DMIP to VMID 50 kΩ Input Bias Current at DMIP 2 µA Maximum Input Voltage IF > 3 MHz ±150 mV IF ≤ 3 MHz ±75 mV Amplitude Balance IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz ±0.2 dB Quadrature Error IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz –1.2 Degrees Phase Noise in Degrees IF = 10.7 MHz, F = 10 kHz –100 dBc/Hz Demodulation Gain Sine Wave Input, Baseband Output 18 dB Maximum Output Voltage R ≥ 20 kΩ ±1.23 V L Output Offset Voltage Measured from I , Q to VMID –150 +10 +150 mV OUT OUT Output Bandwidth Sine Wave Input, Baseband Output 1.5 MHz PLL Required DC Bias at FDIN VPOS/2 V dc Input Resistance at FDIN From FDIN to VMID 50 kΩ Input Bias Current at FDIN 200 nA Frequency Range 0.4 to 12 MHz Required Input Drive Level Sine Wave Input at Pin 1 400 mV Acquisition Time to ±3° IF = 10.7 MHz 16.5 µs POWER-DOWN INTERFACE Logical Threshold For Power Up on Logical High 2 V dc Input Current for Logical High 75 µA Turn-On Response Time To PLL Locked 16.5 µs Standby Current 550 µA POWER SUPPLY Supply Range 2.92 5.5 V Supply Current Midgain, IF = 10.7 MHz 8.5 mA OPERATING TEMPERATURE T to T Operation to 2.92 V Minimum Supply Voltage –25 +85 °C MIN MAX Operation to 4.5 V Minimum Supply Voltage –40 +85 °C Specifications subject to change without notice. –2– REV. C

AD607 ABSOLUTE MAXIMUM RATINGS1 ORDERING GUIDE SupplyVoltage VPS1, VPS2 to COM1, COM2 . . . . . . . 5.5V Temperature Package Package InternalPowerDissipation2 . . . . . . . . . . . . . . . . . . . . 600 mW Model Range Description Option 2.92V to 5.5VOperatingTemperatureRange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°Cto+85°C AD607ARS –25°C to +85°C 20-Lead Plastic RS-20 4.5V to 5.5V Operating Temperature Range for 2.92 V to 5.5 V SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Operation; –40°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C to +85°C for 4.5 V Lead Temperature Range (Soldering60sec) . . . . . . . . . 300°C to 5.5 V Operation NOTES 1Stresses above those listed under Absolute Maximum Rating may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Thermal Characteristics: 20-lead SSOP Package: θ = 126°C/W. JA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD607 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. C –3–

AD607 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Reads Function 1 FDIN Frequency Detector Input PLL Input for I/Q Demodulator Quadrature Oscillator, ±400 mV Drive Required from External Oscillator. Must be biased at V /2. P 2 COM1 Common #1 Supply Common for RF Front End and Main Bias 3 PRUP Power-Up Input 3 V/5 V CMOS compatible power-up control; logical high = powered-up; max input level = VPS1 = VPS2. 4 LOIP Local Oscillator Input LO input, ac-coupled ±54 mV LO input is required (–16 dBm for 50 Ω input termination). 5 RFLO RF “Low” Input Usually Connected to AC Ground 6 RFHI RF “High” Input AC-Coupled, ±56 mV, Max RF Input for Linear Operation 7 GREF Gain Reference Input High Impedance Input, typically 1.5 V, sets gain scaling. 8 MXOP Mixer Output High Impedance, Single-Sided Current Output, ±1.3 V Max Voltage Output (±6 mA Max Current Output) 9 VMID Midsupply Bias Voltage Output of the Midsupply Bias Generator (VMID = VPOS/2) 10 IFHI IF “High” Input AC-Coupled IF Input, ±56 mV Max Input for Linear Operation 11 IFLO IF “Low” Input Reference Node for IF Input; Auto-Offset Null 12 GAIN Gain Control Input High Impedance Input, 0 V–2 V Using 3 V Supply, Max Gain at V = 0 13 COM2 Common #2 Supply Common for IF Stages and Demodulator 14 IFOP IF Output Low Impedance, Single-Sided Voltage Output, 5 dBm (±560 mV) Max 15 DMIP Demodulator Input Signal input to I and Q demodulators has a ±150 mV max input at IF > 3 MHz for linear operation; ±75 mV max input at IF < 3 MHz for linear operation. Must be biased at V /2. P 16 VPS2 VPOS Supply #2 Supply to High Level IF, PLL, and Demodulators 17 QOUT Quadrature Output Low Impedance Q Baseband Output; ±1.23 V Full Scale in 20 kΩ Min Load; AC-Coupled 18 IOUT In-Phase Output Low Impedance I Baseband Output; ±1.23 V Full Scale in 20 kΩ Min Load; AC-Coupled 19 FLTR PLL Loop Filter Series RC PLL Loop Filter, Connected to Ground 20 VPS1 VPOS Supply #1 Supply to Mixer, Low Level IF, PLL, and Gain Control PIN CONNECTION 20-Lead SSOP (RS-20) FDIN 1 20 VPS1 COM1 2 19 FLTR PRUP 3 18 IOUT LOIP 4 17 QOUT RFLO 5 AD607 16 VPS2 RFHI 6 TOP VIEW 15 DMIP (Not to Scale) GREF 7 14 IFOP MXOP 8 13 COM2 VMID 9 12 GAIN IFHI 10 11 IFLO –4– REV. C

AD607 50(cid:2) HP8764B HP8656B 0 IEEE RF_OUT SYNTHESIZER 1 HP8656B 0 S0 50(cid:2) HP8764B IEESEYNTHESRIZFE_ROUT 50(cid:2) 1 SV1 CHARABCOTAERRDIZATION 0 1 0 S0 RFHI MXOP R X S1 HP8656B LOIP L 50(cid:2) 1 V IEEE RF_OUT SYNTHESIZER HP6633A IFHI IFOP P6205 TEK1105 VPOS X1F0ET PROBOEUT IN1 OUT1 0 HP8765B IEEE VNEG 1 C HP8594E SPOS IN2 OUT2 RF_IN IEEE SNEG DMIP IOUT PROBE S0 V S1 SPEC AN DCPS SUPPLY FDIN HP34401A PLL QOUT HI CPIB LO VPOS DMM I BIAS DP8200 R5 PRUP VPOS 1k(cid:2) GAIN IEEE VSNPOEGS 0 HP8765B SNEG 1 C VREF S0 V S1 Figure 1.Mixer/Amplifier Test Set HP8720C PORT_1 IEEE_488 PORT_2 NETWORK AN CHARACTERIZATION BOARD 0 HP8765B HP8765B 0 50(cid:2) HP346B HP8970A 28V NOISE 1 C RFHI R X MXOP C 1 RF_IN 28V_OUT NOISE SOURCE S0 V S1 L S1 VS0 NOISE FIGURE METER HP8656B IEEE RF_OUT SYNTHESIZER LOIP IFHI IFOP DMIP IOUT FDIN PLL QOUT HP6633A VPOS VPOS BIAS VNEG PRUP IEEE SPOS GAIN SNEG DCPS DP8200 VPOS VNEG IEEE SPOS SNEG VREF Figure 2.Mixer Noise Figure Test Set REV. C –5–

AD607 CHARACTERIZATION BOARD RFHI MXOP R X L LOIP HP346B P6205 TEK1103 HP8970A 28V NOISE IFHI IFOP X10 OUT IN1 OUT1 RF_IN 28V_OUT FET PROBE NOISE SOURCE NOISE FIGURE METER IN2 OUT2 PROBE SUPPLY DMIP IOUT FDIN PLL QOUT HP6633A VPOS VPOS BIAS VNEG PRUP IEEE SPOS GAIN SNEG DCPS DP8200 VPOS IEEE VNEG SPOS SNEG VREF Figure 3.IF Amp Noise Figure Test Set CHARACTERIZATION BOARD 50(cid:2) HP8764B 0 RFHI R X MXOP HP8656B L IEEE RF_OUT 1 LOIP 0 S0 SYNTHESIZER S1 50(cid:2) 1 IFHI IFOP V HP3326A DCFM OUTPUT_1 P6205 1103 IEEE OUTPUT_2 DMIP IOUT X10 OUT IN1 OUT1 DUAL SYNTHESIZER FDIN PLL FET PROBE 0 HP8765B HP8765B 0 HP8694E QOUT P6205 RF_IN IEEE HP6633A X10 OUT IN2 OUT2 1 C C 1 SPEC AN VPOS VPOS BIAS FET PROBE SPURPOPBLEY S0V S1 S1V S0 VNEG PRUP IEEE SPOS GAIN CH1HP54120 SNEG DCPS CH2 CH3 DP8200 CH4 VPOS TRIG IEEE_488 IEEE VNEG OSCDILIGLOITSACLOPE SPOS SNEG VREF Figure 4.PLL/Demodulator Test Set –6– REV. C

AD607 CHARACTERIZATION BOARD RFHI MXOP R X L LOIP HP6633A VPOS IFHI IFOP VNEG IEEE SPOS SNEG DCPS DP8200 DMIP IOUT VPOS FDIN VNEG PLL IEEE QOUT SPOS VREF SNEG R1 VPOS BIAS HP34401A 499k(cid:2) PRUP HI GAIN GPIB LO I DMM Figure 5.GAIN Pin Bias Test Set CHARACTERIZATION BOARD RFHI MXOP R X L LOIP HP6633A VPOS IFHI IFOP VNEG IEEE SPOS SNEG DCPS DP8200 DMIP IOUT VPOS FDIN VNEG PLL IEEE QOUT SPOS VREF SNEG R1 VPOS BIAS HP34401A 499k(cid:2) PRUP HI GAIN GPIB LO I DMM Figure 6.Demodulator Bias Test Set CHARACTERIZATION BOARD HP3325B IEEE RF_OUT RFHI R X MXOP SYNTHESIZER L HP6633A LOIP VPOS HP8594E IEEE VNEG IFHI IFOP RF_IN IEEE SPOS SPEC AN SNEG DCPS HP6633A DMIP IOUT VPOS FDIN IEEE VNEG PLL SPOS QOUT SNEG DCPS R1 VPOS BIAS HP34401A 10k(cid:2) PRUP HI LO GAIN GPIB I DMM Figure 7.Power-Up Threshold Test Set REV. C –7–

AD607 CHARACTERIZATION BOARD RFHI MXOP R X L LOIP IFHI IFOP P6205 1103 HP54120 X10 OUT IN1 OUT1 CH1 50(cid:2) FET PROBE CH2 P6205 CH3 X10 OUT IN2 OUT2 CH4 FET PROBE PROBE SUPPLY FL6082A DMIP IOUT TRIG IEEE_488 IEEE RF_OUT FDIN DIGITAL MOD_OUT PLL OSCILLOSCOPE QOUT HP6633A VPOS NOTE: MUST BE 3 RESISTOR POWER DIVIDER VPOS BIAS VNEG PRUP IEEE SPOS GAIN SNEG DCPS DP8200 VPOS VNEG IEEE SPOS SNEG VREF HP8112 IEEE PULSE_OUT PULSE GENERATOR Figure 8.Power-Up Test Set CHARACTERIZATION BOARD RFHI MXOP R X L LOIP IEEE HP8656RBF_OUT IFHI IFOP X10 P6205 OUT IN1 1103OUT1 RF_INHP8594EIEEE SYNTHESIZER R1k1(cid:2) FET PROBE SPEC AN IN2 OUT2 PROBE SUPPLY DMIP IOUT FDIN PLL QOUT HP6633A VPOS VPOS BIAS VNEG PRUP IEEE SPOS GAIN SNEG DCPS Figure 9.IF Output Impedance Test Set –8– REV. C

AD607 CHARACTERIZATION BOARD RFHI MXOP R X L LOIP IFHI IFOP 20(cid:2) dB HP54120 P6205 1103 FL6082A DMIP IOUT X10 OUT IN1 OUT1 CH1 IEEE MORDF__OOUUTT FDIN PLL QOUT FETP 6P2R0O5BE CCHH23 HP6633A X10 OUT IN2 OUT2 CH4 VPOS VPOS BIAS FET PROBE PROBE SUPPLY TRIG IEEE_488 IEEE VNEG PRUP OSCDILIGLOITSACLOPE SPOS GAIN SNEG DCPS DP8200 VPOS IEEE VNEG SPOS SNEG VREF Figure 10.PLL Settling Time Test Set CHARACTERIZATION BOARD RFHI MXOP R X HP3325B LOIP L IEEE RF_OUT SYNTHESIZER IFHI IFOP HP3326 DCFM OUTPUT_1 P6205 1103 IEEE OUTPUT_2 DMIP IOUT X10 OUT IN1 OUT1 DUAL SYNTHESIZER FDIN PLL FET PROBE 0 HP8765B QOUT P6205 HP8694E 1 C HP6633A X10 OUT IN2 OUT2 RF_IN IEEE VPOS VPOS BIAS FET PROBE PROBE SUPPLY S0 V S1 SPEC AN VNEG PRUP IEEE SPOS GAIN SNEG DCPS DP8200 VPOS VNEG IEEE SPOS SNEG VREF Figure 11.Quadrature Accuracy Test Set REV. C –9–

AD607 VPOS C15 GND 0.1(cid:3)F 4.99k(cid:2) C11 R10 10nF 0.1(cid:3)F 0.1(cid:3)F C13 C1 FDIN R518.1(cid:2) 1 FDIN VPS120 0(cid:2) 2 COM1 FLTR19 R12 R1 C3 PRUP C10 3 PRUP IOUT18 1k(cid:2) 10nF 1nF LOIP R517.1(cid:2) C1n1F6 45 LROFLIPOAD607QVOPUST21167 0C.21(cid:3)F I O *UT QOUT C9 6 RFHI DMIP15 * 1nF R2 7 GREF IFOP14 316(cid:2) RFHI R6 51.1(cid:2) 8 MXOP COM213 IFOP * R13 9 VMID GAIN12 301(cid:2) 10 IFHI IFLO 11 C5 GAIN MXOP R14 R5 R9 C7 C6 1nF * * 54.9(cid:2) 332(cid:2) 51.1(cid:2) 1nF 0.1(cid:3)F DMIP C8 * IFHI 0.1(cid:3)F 0.1(cid:3)F *CONNECTIONS ARE DC-COUPLED. Figure 12.Characterization Board –10– REV. C

Typical Performance Characteristics–AD607 20 30 19 25 VGAIN = 0.3V 18 B 20 17 – d VGAIN = 0.6V SSB NF – dB 111645 VPOS =V P3VO,S I F= =5 V20, MIFH =z 20MHz VERSION GAIN 11055 VVGGAAIINN == 11..28VV N 13 O C 0 12 VGAIN = 2.4V –5 11 VPOS = 5V, IF = 10MHz VPOS = 3V, IF = 10MHz 10 –10 50 70 90 110 130 150 170 190 210 230 250 0.1 1 10 100 RF FREQUENCY – MHz INTERMEDIATE FREQUENCY – MHz TPC 1.Mixer Noise Figure vs. Frequency TPC 4.Mixer Conversion Gain vs. IF, T = 25°C, VPOS = 3 V, VREF = 1.5 V 4500 4.0 80 4000 3.5 70 CUBIC FIT OF IF_GAIN (TEMP) 3500 60 3.0 IF AMP GAIN C SHUNT COMPONENT (cid:2)ANCE – 32050000 22..50 ANCE – pF N – dB 453000 ESIST 21050000 1.5 PACIT GAI 20 CUBIC FIT OF CONV_GAIN (TEMP) R A R SHUNT COMPONENT 1.0 C 10 MIXER CG 1000 0 0.5 500 –10 0 0 –20 0 50 100 150 200 250 300 350 400 450 500 –50–40–30–20–10 0 10 20 30 40 50 60 70 80 90100110120130 FREQUENCY – MHz TEMPERATURE – (cid:1)C TPC 2.Mixer Input Impedance vs. Frequency, TPC 5.Mixer Conversion Gain and IF Amplifier Gain vs. VPOS = 3 V, V GAIN = 0.8 V Temperature, VPOS = 3 V, VGAIN = 0.3 V, VREF = 1.5 V, IF = 10.7 MHz, RF = 250 MHz 30 80 25 VGAIN = 0.00V 70 20 VGAIN = 0.54V CUBIC FIT OF IF_GAIN (VPOS) B IF AMP GAIN – d 15 60 N AI 10 B ON G 5 VGAIN = 1.62V VGAIN = 1.08V N – d 50 RSI 0 GAI 40 E V ON –5 30 CUBIC FIT OF CONV_GAIN (VPOS) C –10 VGAIN = 2.16V 20 –15 MIXER CG –20 10 0 50 100 150 200 250 300 350 400 450 500 550 600 2.4 2.62.8 3 3.2 3.43.63.8 4 4.24.44.64.8 5 5.25.45.65.8 6 RADIO FREQUENCY – MHz SUPPLY – V TPC 3.Mixer Conversion Gain vs. Frequency, TPC 6.Mixer Conversion Gain and IF Amplifier Gain vs. T = 25°C, VPOS = 2.92 V, VREF = 1.35 V, IF = 10.7 MHz Supply Voltage, T = 25°C, VGAIN = 0.3 V, VREF = 1.5 V, IF = 10.7 MHz, RF = 250 MHz REV. C –11–

AD607 80 –90.00 70 VGAIN = 0.3V –100.00 60 N – dB 50 VGAIN = 0.6V dBc–110.00 ER GAI 40 VGAIN = 1.2V OISE – –120.00 F AMPLIFI 3200 VGAIN = 1.8V PHASE N–130.00 I 10 VGAIN = 2.4V –140.00 0 –10 –150.00 0.1 1 10 100 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 INTERMEDIATE FREQUENCY – MHz CARRIER FREQUENCY OFFSET, f(fm) – Hz TPC 7.IF Amplifier Gain vs. Frequency, TPC 10.PLL Phase Noise L (F) vs. Frequency, T = 25°C, VPOS = 3 V, VREF = 1.5 V VPOS = 3 V, C3 = 0.1 µF, IF = 10.7 MHz 10 2.5 8 6 IF AMP 4 E G – dB 2 OLTA OR 0 N V 2 ERR –2 MIXER R PI T L –4 F –6 –8 –10 1.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 0.1 1 10 100 GAIN VOLTAGE – V PLL FREQUENCY – MHz TPC 8.Gain Error vs. Gain Control Voltage, TPC 11.PLL Loop Voltage at FLTR (K ) vs. Frequency VCO Representative Part 8 7 6 5 T N U 4 O C 3 2 996.200(cid:3)s 1.00870ms 1.02120ms TIMEBASE = 2.5(cid:3)s/DIV DELAY = 1.00870ms 1 MEMORY 1 = 100.0mV/DIV OFFSET= 127.3mV TIMEBASE = 2.50(cid:3)s/DIV DELAY = 1.00870ms 0 MEMORY 2 = 20.00mV/DIV OFFSET= 155.2mV 85 86 87 88 89 90 91 92 93 94 95 TIMEBASE = 2.50(cid:3)s/DIV DELAY = 1.00870ms QUADRATURE ANGLE – Degrees DELTA T = 16.5199(cid:3)s START = 1.00048ms STOP = 1.01700ms TRIGGER ON EXTERNAL AT POS. EDGE AT 134.0mV TPC 12.Demodulator Quadrature Angle, Histogram, TPC 9.PLL Acquisition Time T = 25°C, VPOS = 3 V, IF = 10.7 MHz –12– REV. C

AD607 30 20 I_GAIN_CORR 19 25 18 20 17 CUBIC FIT OF I_GAIN_CORR (TEMP) B16 T d COUN15 AIN – 15 IG14 10 13 5 12 11 0 10 –2 –1 0 1 2 2.5 3 3.5 4 4.5 5 5.5 6 IQ GAIN BALANCE – dB SUPPLY – V TPC 13.Demodulator Gain Balance, Histogram, TPC 16.Demodulator Gain vs. Supply Voltage T = 25°C, VPOS = 3 V, IF = 10.7 MHz 20 40 19 35 18 30 17 I_GAIN_CORR B16 25 – d NT N 15 U20 IGAI14 QUADRATIC FIT OF I_GAIN_CORR (IFF) CO15 13 10 12 5 11 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 17 17.2 17.4 17.6 17.8 18 18.2 18.4 18.6 18.8 BASEBAND FREQUENCY – MHz DEMODULATOR GAIN – dB TPC 14.Demodulator Gain vs. Frequency TPC 17.Demodulator Gain Histogram, T = 25°C, VPOS = 3 V, IF = 10.7 MHz 20 19 I_GAIN_CORR 18 17 CUBIC FIT OF I_GAIN_CORR (TEMP) B16 d – N 15 AI IG14 13 12 11 10 –50–40–30–20–10 0 10 20 30 40 50 60 70 80 90 100110120130 TEMPERATURE – (cid:1)C TPC 15.Demodulator Gain vs. Temperature REV. C –13–

AD607 PRODUCT OVERVIEW The AD607 provides most of the active circuitry required to realize a complete low power, single-conversion superhetero- dyne receiver, or most of a double-conversion receiver, at input frequencies up to 500 MHz, and an IF from 400 kHz to 12 MHz. The internal I/Q demodulators and their associated phase- locked loop, which can provide carrier recovery from the IF, support a wide variety of modulation modes, including n-PSK, n-QAM, and AM. A single positive supply voltage of 3 V is required (2.92 V minimum, 5.5 V maximum) at a typical supply current of 8.5 mA at midgain. In the following discus- 40.2127ms 40.2377ms 40.2627ms TIMEBASE = 500(cid:3)s/DIV DELAY = 40.2377ms sion, VP will be used to denote the power supply voltage, which MEMORY 1 = 100.0mV/DIV OFFSET= 154.0mV will be assumed to be 3 V. TIMEBASE = 5.00(cid:3)s/DIV DELAY = 40.2377ms MEMORY 2 = 60.00mV/DIV OFFSET= 209.0mV Figure 13 shows the main sections of the AD607. It consists of a TIMEBASE = 5.00(cid:3)s/DIV DELAY = 40.2377ms variable gain UHF mixer and linear four-stage IF strip, which DELTA T = 15.7990(cid:3)s together provide a voltage controlled gain range of more than START = 40.2327ms STOP = 40.2485ms 90 dB; dual demodulators, each comprising a multiplier fol- TRIGGER ON EXTERNAL AT POS. EDGE AT 40.0mV lowed by a two-pole, 2 MHz low-pass filter; and a phase-locked TPC 18.Power-Up Response Time to PLL Stable loop providing the inphase and quadrature clocks. A biasing system with CMOS compatible power-down completes the 15 AD607. Mixer The UHF mixer is an improved Gilbert cell design, and can A m – operate from low frequencies (it is internally dc-coupled) up to NT an RF input of 500 MHz. The dynamic range at the input of the E CURR 10 msigixnearl liesv deel toefr m±5in6e md Vat btehtew uepenp eRr FeHndI bany dt hReF mLaOx iumpu tmo winhpicuht the Y L mixer remains linear, and at the lower end by the noise level. It is P P U customary to define the linearity of a mixer in terms of the 1 dB S gain-compression point and third order intercept, which for the AD607 are –15 dBm and –8 dBm, respectively, in a 50 Ω system. 5 0 0.5 1 1.5 2 2.5 GAIN VOLTAGE – V TPC 19.Power Supply Current vs. Gain Control Voltage, GREF = 1.5 V LOIP RFHI VMID IOUT MXOP IFHI BPF IFOP BPF OR DMIP VQFO FDIN RFLO LPF FLTR VMID IFLO QOUT MIDPOINT BIAS GENERATOR GAIN VPS1 BIAS PTAT GREF VPS2 GENERATOR VOLTAGE AD607 PRUP COM1 COM2 Figure 13.Functional Block Diagram –14– REV. C

AD607 The mixer’s RF input port is differential, that is, pin RFLO is Table I. Filter Termination Resistor Values for functionally identical to RFHI, and these nodes are internally Common IFs biased; we will generally assume that RFLO is decoupled to ac ground. The RF port can be modeled as a parallel RC circuit as Filter Filter Termination Resistor shown in Figure 14. IF Impedance Values* for 24 dB of Mixer Gain R1 R2 R3 450 kHz 1500 Ω 174 Ω 1330 Ω 1500 Ω AD607 455 kHz 1500 Ω 174 Ω 1330 Ω 1500 Ω C1 C2 RFHI 6.5 MHz 1000 Ω 215 Ω 787 Ω 1000 Ω 10.7 MHz 330 Ω 330 Ω 0 Ω 330 Ω L1 RFLO CIN RIN *Resistor values were calculated such that R1+ R2 = Z and FILTER R1(cid:1) (R2 + Z ) = 165 Ω. FILTER C3 The maximum permissible signal level at MXOP is determined by both voltage and current limitations. Using a 3 V supply and C1, C2, L1: OPTIONAL MATCHING CIRCUIT VMID at 1.5 V, the maximum swing is about ±1.3 V. To attain C3: COUPLES RFLO TO AC GROUND a voltage swing of ±1 V in the standard IF filter load of 165 Ω Figure 14.Mixer Port Modeled as a Parallel RC Network; requires a peak drive current of about ±6 mA, which is well an Optional Matching Network Is also Shown within the linear capability of the mixer. However, these upper The local oscillator (LO) input is internally biased at VP/2 via a limits for voltage and current should not be confused with issues nominal 1000 Ω resistor internally connected from pin LOIP to related to the mixer gain, already discussed. In an operational VMID. The LO interface includes a preamplifier that minimizes system, the AGC voltage will determine the mixer gain, and the drive requirements, thus simplifying the oscillator design hence the signal level at the IF input Pin IFHI; it will always be and reducing LO leakage from the RF port. Internally, this less than ±56 mV (–15 dBm into 50 Ω), which is the limit of the single-sided input is actually differential; the noninverting input IF amplifier’s linear range. is referenced to Pin VMID. The LO requires a single-sided IF Amplifier drive of ±50 mV, or –16 dBm in a 50 Ω system. Most of the gain in the AD607 arises in the IF amplifier strip, The mixer’s output passes through both a low-pass filter and a which comprises four stages. The first three are fully differential buffer, which provides an internal differential to single-ended and each has a gain span of 25 dB for the nominal AGC voltage signal conversion with a bandwidth of approximately 45 MHz. range. Thus, in conjunction with the mixer’s variable gain, the Its output at Pin MXOP is in the form of a single-ended cur- total gain exceeds 90 dB. The final IF stage has a fixed gain of rent. This approach eliminates the 6 dB voltage loss of the usual 20 dB, and it also provides differential to single-ended conversion. series termination by replacing it with shunt terminations at The IF input is differential, at IFHI (noninverting relative to the both the input and the output of the filter. The nominal conver- output IFOP) and IFLO (inverting). Figure 16 shows a simpli- sion gain is specified for operation into a total IF band-pass fied schematic of the IF interface. The offset voltage of this filter (BPF) load of 165 Ω, that is, a 330 Ω filter doubly-termi- stage would cause a large dc output error at high gain, so it is nated as shown in Figure 14. Note that these loads are con- nulled by a low pass feedback path from the IF output, also nected to bias point VMID, which is always at the midpoint of shown in TPC 13. Unlike the mixer output, the signal at IFOP the supply (that is, V /2). P is a low-impedance single-sided voltage, centered at V /2 by the P The conversion gain is measured between the mixer input and dc feedback loop. It may be loaded by a resistance as low as the input of this filter, and varies between 1.5 dB and 26.5 dB 50 Ω, which will normally be connected to VMID. for a 165 Ω load impedance. Using filters of higher impedance, the conversion gain can always be maintained at its specified AD607 value or made even higher; for filters of lower impedance, of say IFHI 10k(cid:2) Z , the conversion gain will be lowered by 10 log (165/Z ). VMID O 10 O Thus, the use of a 50 Ω filter will result in a conversion gain that is 5.2 dB lower. Figure 15 shows filter matching networks and IFOP Table I lists resistor values. IFLO 10k(cid:2) OFFSET FEEDBACK LOOP R2 1nF MXOP 8 BPF 10 IFHI Figure 16.Simplified Schematic of the IF Interface R1 R3 VMID 9 11 IFLO 100nF 100nF Figure 15.Suggested IF Filter Matching Network. The Values of R1 and R2 Are Selected to Keep the Impedance at Pin MXOP at 165 Ω REV. C –15–

AD607 The IF’s small-signal bandwidth is approximately 45 MHz from Table II lists gain control voltages and scale factors for power IFHI and IFLO through IFOP. The peak output at IFOP is supply voltages from 2.92 V to 5.5 V ±560 mV at V = 3 V and ±400 mV at the minimum V of P P Alternatively, Pin GREF can be tied to an external voltage 2.92 V. This allows some headroom at the demodulator inputs reference (V ) from, for example, an AD1582 (2.5 V) or (Pin DMIP), which accept a maximum input of ±150 mV for R AD1580 (1.21 V) voltage reference, to provide supply- IFs > 3 MHz and ±75 mV for IFs ≤ 3 MHz (at IFs ≤ 3 MHz, independent gain scaling of V /75 (volts per dB). When using the drive to the demodulators must be reduced to avoid saturat- R the Analog Devices’ AD7013 and AD7015 baseband converters, ing the output amplifiers with higher order mixing products that the external reference may also be provided by the reference are no longer removed by the on-board low pass filters). output of the baseband converter (Figure 18). For example, the Since there is no band-limiting in the IF strip, the output- AD7015 baseband converter provides a V of 1.23 V; when R referred noise can be quite high; in a typical application and connected to GREF, the gain scaling is 16.4 mV/dB (60 dB/V). at a gain of 75 dB, it is about 100 mV rms, making post-IF filtering An auxiliary DAC in the AD7015 can be used to generate the desirable. IFOP may be also used as an IF output for driving MGC voltage. Since it uses the same reference voltage, the an A/D converter, external demodulator, or external AGC numerical input to this DAC provides an accurate RSSI value detector. Figure 17 shows methods of matching the optional in digital form, no longer requiring the reference voltage to have second IF filter. high absolute accuracy. VPOS AD607 AD7013 OR AD607 R AD7015 2RT IOUT IADC IFOP RT BPF QOUT R C QADC 2RT C VMID IADC QADC DMIP GREF REFOUT(AD7015) 10nF BYPASS(AD7013) a. Biasing DMIP from Power Supply (Assumes BPF GAIN AUX DAC 1nF AC-Coupled Internally) Figure 18. Interfacing the AD607 to the AD7013 or AD7015 AD607 Baseband Converters RT IFOP BPF I/Q Demodulators Both demodulators (I and Q) receive their inputs at Pin DMIP. DMIP Internally, this single-sided input is actually differential; the noninverting input is referenced to Pin VMID. Each demodula- RT tor comprises a full-wave synchronous detector followed by a VMID CBYPASS 2 MHz, two-pole low-pass filter, producing single-sided outputs at pins IOUT and QOUT. Using the I and Q demodulators for IFs above 12 MHz is precluded by the 400 kHz to 12 MHz b. Biasing DMIP from VMID (Assumes BPF AC-Coupled response of the PLL used in the demodulator section. Pin DMIP Internally) requires an external bias source at V /2; Figure 19 shows P Figure 17.Input and Output Matching of the Optional suggested methods. Second IF Filter Outputs IOUT and QOUT are centered at V /2 and can swing P Gain Scaling and RSSI up to ±1.23 V even at the low supply voltage of 2.92 V. They can The AD607’s overall gain, expressed in decibels, is linear-in-dB therefore directly drive the RX ADCs in the AD7015 baseband with respect to the AGC voltage V at Pin GAIN. The gain of G converter, which require an amplitude of 1.23 V to fully load all sections is maximum when V is zero, and reduces progres- G them when driven by a single-sided signal. The conversion gain of sively up to V = 2.2 V (for V = 3 V; in general, up to a limit G P the I and Q demodulators is 18 dB (X8), requiring a maxi- VP – 0.8 V). The gain of all stages changes in parallel. The AD607 mum input amplitude at DMIP of ±150 mV for IFs > 3 MHz. features temperature compensation of the gain scaling. The gain control scaling is proportional to the reference voltage applied to the Pin GREF. When this pin is tied to the midpoint of the supply (VMID), the scale is nominally 20 mV/dB (50 dB/V) for V = 3 V. Under these conditions, the lower 80 dB of gain range P (mixer plus IF) corresponds to a control voltage of 0.4 V ≤ V ≤ 2.0 V. The final centering of this 1.6 V range depends on G the insertion losses of the IF filters used. More generally, the gain scaling using these connections is V /150 (volts per dB), so scale P becomes 33.3 mV/dB (30 dB/V) using a 5 V supply, with a proportional change in the AGC range, to 0.33 V ≤ V ≤ 3 V. G –16– REV. C

AD607 VPOS are generated at IOUT and QOUT, respectively. The quadra- AD607 ture accuracy of this VFQO is typically –1.2°C at 10.7 MHz. The RT 2RT PLL uses a sequential-phase detector that comprises low power IFOP BPF emitter-coupled logic and a charge pump (Figure 20). 2RT DMIP IU~ 40(cid:3)A a. Biasing DMIP from Power Supply (Assumes BPF VF I-CLOCK AC-Coupled Internally) F SEQUENTIAL U FVRAERQIUAEBNLEC-Y R DEPTHEACSTEOR D QOUSACDILRLAATTUORRE 90(cid:1) C AD607 IFOP RT BPF ID~ R (ECQL- OCLUOTPCUKTS) 40(cid:3)A REFERENCE CARRIER DMIP (FDIN AFTER LIMITING) RT Figure 20.Simplified Schematic of the PLL and VMID Quadrature VCO CBYPASS The reference signal may be provided from an external source b. Biasing DMIP from VMID (Assumes BPF in the form of a high level clock, typically a low level signal AC-Coupled Internally) (±400 mV) since there is an input amplifier between FDIN and the loop’s phase detector. For example, the IF output itself can Figure 19. Suggested Methods for Biasing Pin DMIP be used by connecting DMIP to FDIN, which will then provide at V/2 P automatic carrier recover for synchronous AM detection and For IFs < 3 MHz, the on-chip low-pass filters (2 MHz cutoff) take advantage of any post-IF filtering. Pin FDIN must be do not attenuate the IF or feedthrough products. Thus, the biased at V /2; Figure 22 shows suggested methods. P maximum input voltage at DMIP must be limited to ±75 mV The VFQO operates from 400 kHz to 12 MHz and is controlled to allow sufficient headroom at the I and Q outputs for not only by the voltage between VPOS and FLTR. In normal operation, the desired baseband signal, but also the unattenuated higher- a series RC network forming the PLL loop filter is connected order demodulation products. These products can be removed from FLTR to ground. The use of an integral sample-hold by an external low-pass filter. In the case of IS54 applications system ensures that the frequency-control voltage on Pin FLTR using a 455 kHz IF and the AD7013 baseband converter, a simple remains held during power-down, so reacquisition of the carrier one-pole RC filter with its corner above the modulation band- typically occurs in 16.5 µs. width is sufficient to attenuate undesired outputs. In practice, the probability of a phase mismatch at power-up is Phase-Locked Loop high, so the worst-case linear settling period to full lock needs The demodulators are driven by quadrature signals that are to be considered in making filter choices. This is typically 16.5 µs provided by a variable frequency quadrature oscillator (VFQO), at an IF of 10.7 MHz for a ±100 mV signal at DMIP and FDIN. phase-locked to a reference signal applied to Pin FDIN. When this signal is at the IF, in-phase and quadrature baseband outputs Table II. AD607 Gain and Manual Gain Control Voltage vs. Power Supply Voltage Power Supply GREF Gain Control Voltage (= VMID) Scale Factor Scale Factor Voltage Input Range (V) (V) (dB/V) (mV/dB) (V) 3.0 1.5 50.00 20.00 0.400–2.000 3.5 1.75 42.86 23.33 0.467–2.333 4.0 2.0 37.50 26.67 0.533–2.667 4.5 2.25 33.33 30.00 0.600–3.000 5.0 2.5 30.00 33.33 0.667–3.333 5.5 2.75 27.27 36.67 0.733–3.667 Maximum gain occurs for gain control voltage = 0 V. REV. C –17–

AD607 Bias System USING THE AD607 The AD607 operates from a single supply, V , usually of 3 V, at In this section, we will focus on a few areas of special impor- P a typical supply current of 8.5 mA at midgain and T = 27°C, tance and include a few general application tips. As is true of corresponding to a power consumption of 25 mW. Any voltage any wideband high gain component, great care is needed in PC from 2.92 V to 5.5 V may be used. board layout. The location of the particular grounding points The bias system includes a fast-acting active-high CMOS- must be considered with due regard to the possibility of unwanted compatible power-up switch, allowing the part to idle at 550 µA signal coupling, particularly from IFOP to RFHI or IFHI or both. when disabled. Biasing is proportional-to-absolute temperature The high sensitivity of the AD607 leads to the possibility that (PTAT) to ensure stable gain with temperature. unwanted local EM signals may have an effect on the perfor- An independent regulator generates a voltage at the midpoint mance. During system development, carefully-shielded test of the supply (V /2) that appears at the VMID pin at a low assemblies should be used. The best solution is to use a fully- P impedance. This voltage does not shut down, ensuring that the enclosed box enclosing all components, with the minimum major signal interfaces (e.g., mixer-to-IF and IF-to-demodulators) number of needed signal connectors (RF, LO, I, and Q outputs) remain biased at all times, thus minimizing transient disturbances in miniature coax form. at power-up and allowing the use of substantial decoupling The I and Q output leads can include small series resistors capacitors on this node. The quiescent consumption of this (about 100 Ω) inside the shielded box without significant loss regulator is included in the idling current. of performance, provided the external loading during testing is light (that is, a resistive load of more than 20 kΩ and capaci- VPOS tances of a few picofarads). These help to keep unwanted RF AD607 emanations out of the interior. 50k(cid:2) The power supply should be connected via a through-hole FDIN EXTERNAL capacitor with a ferrite bead on both inside and outside leads. FREQUENCY 50k(cid:2) REFERENCE Close to the IC pins, two capacitors of different value should be used to decouple the main supply (V ) and the midpoint supply P pin, VMID. Guidance on these matters is also generally included a. Biasing FDIN from Supply when Using in applications schematics. External Frequency Reference Gain Distribution As in all receivers, the most critical decisions in effectively using AD607 the AD607 relate to the partitioning of gain between the various FDIN subsections (Mixer, IF Amplifier, Demodulators) and the place- EXTERNAL ment of filters so as to achieve the highest overall signal-to-noise FREQUENCY 50k(cid:2) REFERENCE ratio and lowest intermodulation distortion. VMID Figure 22 shows the main RF/IF signal path at maximum and CBYPASS minimum signal levels. b. Biasing FDIN from VMID when Using External Frequency Reference Figure 21.Suggested Methods for Biasing Pin FDIN at V/2 P I (cid:4)1.23V MAX OUTPUT (cid:4)54mV (cid:4)1.3V (cid:4)54mV (cid:4)560mV (cid:4)154mV MAX INPUT MAX OUTPUT MAX INPUT MAX OUTPUT MAX INPUT IOUT RFHI MXOP IFHI IFOP DMIP IF BPF IF BPF QOUT LOIP 330(cid:2) 330(cid:2) (VMID) Q CONSTANT –16dBm ((cid:4)50mV) (TYPICAL (LOCATION OF OPTIONAL IMPEDANCE) SECOND IF FILTER) Figure 22.Signal Levels for Minimum and Maximum Gain –18– REV. C

AD607 As noted earlier, the gain in dB is reduced linearly with the voltage Fortunately, there is a very simple solution to the fast PRUP V on the GAIN pin. Figure 23 shows how the mixer and IF strip problem. If the PRUP signal (Pin 3) is slowed down so that G gains vary with V when GREF is connected to VMID (1.5 V) and the rise time of the signal edge is greater than 35 µs, the G a supply voltage of 3 V is used. Figure 24 shows how these vary anomalous behavior will not occur. This can be realized by a when GREF is connected to a 1.23 V reference. simple RC circuit connected to the PRUP pin, where R = 4.7 kΩ and C = 1.5 nF. This circuit is shown in Figure 25. 90dB 80dB FROM PRUP 70dB (67.5dB) CONTROL SIGNAL AD607 60dB 4.7k(cid:2) 50dB IF GAIN PRUP 1.5nF 40dB 30dB 20dB (21.5dB) Figure 25.Proper Configuration of AD607 PRUP Signal MIXER GAIN 10dB All designs incorporating the AD607 should include this circuitry. (7.5dB) (1.5dB) Note that connecting the PRUP pin to the supply voltage will 0dB 0 0.4V 1V 1.8V 2V 2.2V not eliminate the problem, since the supply voltage may have a NORMAL OPERATING RANGE VG rise time faster than 35 µs. With this configuration, the 4.7 kΩ series R and 1.5 nF shunt C should be placed between the Figure 23. Gain Distribution for GREF = 1.5 V supply and the PRUP pin as shown in Figure 25. 90dB AD607 EVALUATION BOARD 80dB The AD607 evaluation board (Figures 26 and 27) consists of an AD607, ground plane, I/O connectors, and a 10.7 MHz band- 70dB (67.5dB) pass filter. The RF and LO ports are terminated in 50 Ω to 60dB provide a broadband match to external signal generators to 50dB allow a choice of RF and LO input frequencies. The IF filter is IF GAIN at 10.7 MHz and has 330 Ω input and output terminations; the 40dB board is laid out to allow the user to substitute other filters for 30dB other IFs. 20dB (21.5dB)MIXER GAIN The board provides SMA connectors for the RF and LO port inputs, the demodulated I and Q outputs, the manual gain con- 10dB (7.5dB) trol (MGC) input, the PLL input, and the power-up input. In (1.5dB) 0dB addition, the IF output is also available at an SMA connector; 0 0.328V 1V 1.64V 2V this may be connected to the PLL input for carrier recovery to NORMAL OPERATING RANGE VG realize synchronous AM and FM detection via the I and Q demodulators, respectively. Table III lists the AD607 Evalua- Figure 24.Gain Distribution for GREF = 1.23 V tion Board’s I/O Connectors and their functions. Using the AD607 with a Fast PRUP Control Signal If the AD607 is used in a system in which the PRUP signal (Pin 3) is applied with a rise time less than 35 µs, anomalous behavior occasionally occurs. The problem is intermittent, so it will not occur every time the part is powered up under these conditions. It does not occur for any other normal operating condi- tions when the PRUP signal has a rise time slower than 35 µs. Symptoms of operation with too fast a PRUP signal include low gain, oscillations at the I or Q outputs of the device, or no valid data occurring at the output of the AD607. The problem causes no permanent damage to the AD607, so it will often operate normally when reset. REV. C –19–

AD607 VPOS C15 0.1(cid:3)F JUMPER GND R10 R11 C11 4.99k(cid:2) OPEN 10nF FDIN R8 0.1C(cid:3)1F2 0.C1(cid:3)1F 51.1(cid:2) FDIN VPS1 R12 COM1 R1 C310nF PRUP 4.7k(cid:2) PRUP FLTR 1k(cid:2) C10 C17 IOUT C13 0 1nF 1.5nF I LO R517.1(cid:2) C9 C16 1nF LROFLIPO AD607 QVOPUST2 C20.1(cid:3)F 4C7p4F Q C14 0 1nF RF R516.1(cid:2) RGFRHEIF DIFMOIPP R3126(cid:2) R5 JUMPER MXOP COM2 IF 332(cid:2) R4 R3 OPEN VMID GAIN C5 GAIN IFHI IFLO 1nF 332(cid:2) 1Cn7F C0.61(cid:3)F C8 0.1(cid:3)F AD607 EVALUATION BOARD (AS RECEIVED) VPOS VPOS R15 R13 R17 R18 50k(cid:2) 50k(cid:2) OPEN OPEN C18 C19 SHORT ANYTHING FDIN R511.41(cid:2) 1C01n7F RO1P2EN FDIN FDIN RSOURRC1E9 SHCO20RT RO1P6EN FDIN VMID VMID MOD FOR LARGE MAGNITUDE MOD FOR DC-COUPLED INPUT AC-COUPLED INPUT Figure 26. Evaluation Board Figure 27a.Evaluation Board Layout, Topside –20– REV. C

AD607 Figure 27b.Evaluation Board Layout, Bottom Side Table III. AD607 Evaluation Board Input and Output Connections Reference Connector Approximate Designation Type Description Coupling Signal Level Comments J1 SMA Frequency DC ±400 mV This pin needs to be biased at VMID Detector Input and ac-coupled when driven by an external signal generator. J2 SMA Power-Up DC CMOS Logic Tied to Positive Supply by Jumper J10 Level Input J3 SMA LO Input AC –16 dBm Input is terminated in 50 Ω. (±50 mV) J4 SMA RF Input AC –15 dBm max Input is terminated in 50 Ω. (±54 mV) J5 SMA MGC Input DC 0.4 V to 2.0 V Jumper is set for manual gain control (3 V Supply) input; see Table I for control voltage (GREF = VMID) values. J6 SMA IF Output AC NA This signal level depends on the AD607’s gain setting. J7 SMA Q Output AC NA This signal level depends on the AD607’s gain setting. J8 SMA I Output AC NA This signal level depends on the AD607’s gain setting. J9 Jumper Ties GREF NA NA Sets gain-control scale factor (SF); to VMID SF = 75/VMID in dB/V, where VMID = VPOS/2. J10 Jumper Ties Power-Up NA NA Remove to test power-up/-down. to Positive Supply T1 Terminal Pin Power Supply DC DC 2.92 V to 5.5 V Positive Input Draws 8.5 mA at midgain connection. (VPS1, VPS2) T2 Terminal Pin Power Supply DC 0 V Return (GND) REV. C –21–

AD607 In operation (Figure 28), the AD607 evaluation board draws above this will overload the I and Q demodulators. The insertion about 8.5 mA at midgain (59 dB). Use high impedance probes loss between IFOP and DMIP is typically 3 dB if a simple low-pass to monitor signals from the demodulated I and Q outputs and filter (R8 and C2) is used, and higher if a reverse-terminated the IF output. The MGC voltage should be set such that the band-pass filter is used. signal level at DMIP does not exceed ±150 mV; signal levels HP 6632A HP 3326 PROGRAMMABLE SYNTHESIZED POWER SUPPLY SIGNAL GENERATOR 2.92V–6V 10.710MHz FLUKE 6082A SYNTHESIZED SIGNAL GENERATOR 240MHz VPOS FDIN I OUTPUT TEKTRONIX MCL RF AD607 11402A ZFSC–2–1 EVALUATION OSCILLOSCOPE COMBINER BOARD WITH 11A32 Q OUTPUT PLUGIN HP 8656A SYNTHESIZED LO MGC SIGNAL GENERATOR 240.02MHz HP 9920 HP 8656A DATA PRECISION IEEE CONTROLLER SYNTHESIZED DVC8200 HP9121 SIGNAL GENERATOR PROGRAMMABLE DISK DRIVE 229.3MHz VOLTAGE SOURCE IEEE–488 BUS Figure 28.Evaluation Board Test Setup –22– REV. C

AD607 OUTLINE DIMENSIONS 20-Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters 7.50 7.20 6.90 20 11 8.20 5.60 7.80 5.30 7.40 5.00 1 10 1.85 1.75 2.00 MAX 1.65 0.25 0.09 8(cid:1) 0.05 MIN B0.S6C5 00..3282 SEATING 40(cid:1)(cid:1) 00..9755 COPLANARITY PLANE 0.55 0.10 COMPLIANT TO JEDEC STANDARDS MO-150AE REV. C –23–

AD607 Revision History Location Page 11/02—Data Sheet changed from REV. B to REV. C. Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 C) 2( Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1/0 1 Changes to TPC 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 0– – 3 Edits to PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4 5 0 Edits to IF Amplifier section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 C0 Edits to Gain Scaling and RSSI section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Edits to I/Q Demodulators section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Edits to Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Edits to Bias System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Edits to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Edits to Figure 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 OUTLINE DIMENSIONS Updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 A. S. U. N D I E T N RI P –24– REV. C

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD607ARSZ AD607ARS AD607ARSZ-REEL EVAL-AD607EBZ AD607ARS-REEL