a 50 MHz, 80 dB Demodulating Logarithmic Amplifier with Limiter Output AD606 FEATURES a loadable output voltage of +0.1 V dc to +4 V dc. The logarith- Logarithmic Amplifier Performance mic scaling is such that the output is +0.5 V for a sinusoidal –75 dBm to +5 dBm Dynamic Range input of –75 dBm and +3.5 V at an input of +5 dBm; over this £ 1.5 nV/(cid:214) Hz Input Noise range the logarithmic linearity is typically within – 0.4 dB. All Usable to >50 MHz scaling parameters are proportional to the supply voltage. 37.5 mV/dB Voltage Output The AD606 can operate above and below these limits, with On-Chip Low-Pass Output Filter reduced linearity, to provide as much as 90 dB of conversion Limiter Performance range. A second low-pass filter automatically nulls the input 61 dB Output Flatness over 80 dB Range offset of the first stage down to the submicrovolt level. Adding 638 Phase Stability at 10.7 MHz over 80 dB Range external capacitors to both filters allows operation at input fre- Adjustable Output Amplitude quencies as low as a few hertz. Low Power The AD606’s limiter output provides a hard-limited signal +5 V Single Supply Operation output as a differential current of – 1.2 mA from open-collector 65 mW Typical Power Consumption outputs. In a typical application, both of these outputs are CMOS-Compatible Power-Down to 325 mW typ loaded by 200 W resistors to provide a voltage gain of more than <5 ms Enable/Disable Time 90 dB from the input. Transition times are 1.5 ns, and the APPLICATIONS phase is stable to within – 3(cid:176) at 10.7 MHz for signals from Ultrasound and Sonar Processing –75 dBm to +5 dBm. Phase-Stable Limiting Amplifier to 100 MHz The logarithmic amplifier operates from a single +5 V supply Received Signal Strength Indicator (RSSI) and typically consumes 65 mW. It is enabled by a CMOS logic Wide Range Signal and Power Measurement level voltage input, with a response time of <5 m s. When dis- abled, the standby power is reduced to <1 mW within 5 m s. PRODUCT DESCRIPTION The AD606 is a complete, monolithic logarithmic amplifier The AD606J is specified for the commercial temperature range using a 9-stage “successive-detection” technique. It provides of 0(cid:176) C to +70(cid:176) C and is available in 16-lead plastic DIPs or both logarithmic and limited outputs. The logarithmic output is SOICs. Consult the factory for other packages and temperature from a three-pole post-demodulation low-pass filter and provides ranges. FUNCTIONAL BLOCK DIAGRAM INHI COMM PRUP VPOS FIL1 FIL2 LADJ LMHI 16 15 14 13 12 11 10 9 REFERENCE AND POWER-UP 30pF 360kV X1 30kV 30kV 30pF 360kV OFFSET-NULL LOW-PASS FILTER 1.5kV FINAL MAIN SIGNAL PATH LIMITER 250V 11.15dB/STAGE 1.5kV HIGH-END 12mA/dB 9.375kV 2pF STAWLLOE-PNO-KLEEY DETECTORS ONE-POLE 9.375kV FILTER FILTER X2 AD606 2mA/dB 2pF 1 2 3 4 5 6 7 8 INLO COMM ISUM ILOG BFIN VLOG OPCM LMLO REV.B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999

AD606–SPECIFICATIONS (@ T = +258C and supply = +5 V unless otherwise noted; dBm assumes 50 V) A Model AD606J Parameter Conditions Min Typ Max Units SIGNAL INPUT Log Amp f AC Coupled; Sinusoidal Input 50 MHz MAX Limiter f AC Coupled; Sinusoidal Input 100 MHz MAX Dynamic Range 80 dB Input Resistance Differential Input 500 2,500 W Input Capacitance Differential Input 2 pF SIGNAL OUTPUT Limiter Flatness –75 dBm to +5 dBm Input Signal at 10.7 MHz –1.5 +1.5 dB With Pin 9 to V via a 200 W Resistor POS and Pin 8 to V via a 200 W Resistor POS Output Current At Pins 8 or 9, Proportional to V , LADJ Grounded 1.2 mA POS LADJ Open Circuited 0.48 mA Phase Variation with Input Level –75 dBm to +5 dBm Input Signal at 10.7 MHz – 3 Degrees LOG (RSSI) OUTPUT Nominal Slope At 10.7 MHz; (0.0075 · V )/dB 37.5 mV/dB POS At 45 MHz 35 mV/dB Slope Accuracy Untrimmed at 10.7 MHz –15 – 5 +15 % Intercept Sinusoidal Input; Independent of V –88.33 dBm POS Logarithmic Conformance –75 dBm to +5 dBm Input Signal at 10.7 MHz –1.5 0.4 +1.5 dB Nominal Output Input Level = –75 dBm 0.5 V Input Level = –35 dBm 2 V Input Level = +5 dBm 3.5 V Accuracy over Temperature After Calibration at –35 dBm at 10.7 MHz –3 +3 dB T to T MIN MAX Video Response Time From Onset of Input Signal Until Output Reaches 400 ns 95% of Final Value POWER-DOWN INTERFACE Power-Up Response Time Time Delay Following HI Transition Until 3.5 m s Device Meets Full Specifications AC Coupled with 100 pF Coupling Capacitors Input Bias Current Logical HI Input (See Figure 12) 1 nA Logical LO Input 4 m A POWER SUPPLY Operating Range 4.5 5.5 V Powered-Up Current Zero Signal Input 13 mA T to T 13 20 mA MIN MAX Powered-Down Current T to T 65 200 m A MIN MAX Specifications subject to change without notice. –2– REV. B

AD606 ABSOLUTE MAXIMUM RATINGS1 PIN FUNCTION DESCRIPTIONS SupplyVoltage V . . . . . . . . . . . . . . . . . . . . . . . . . . . . +9V POS InternalPowerDissipation2 . . . . . . . . . . . . . . . . . . . 600 mW Pin Mnemonic Function Operating Temperature Range . . . . . . . . . . . . . 0(cid:176) C to +70(cid:176) C 1 INLO DIFFERENTIAL RF INPUT Storage Temperature Range . . . . . . . . . . . . –65(cid:176) C to +150(cid:176) C –75 dBm to +5 dBm, Inverting, AC Coupled. Lead Temperature Range (Soldering60sec) . . . . . . . . +300(cid:176) C 2 COMM POWER SUPPLY COMMON NOTES Connect to Ground. 1Stresses above those listed under Absolute Maximum Ratings may cause perma- 3 ISUM LOG DETECTOR SUMMING NODE nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational 4 ILOG LOG CURRENT OUTPUT section of this specification is not implied. Exposure to absolute maximum rating Normally No Connection; 2 m A/dB Output conditions for extended periods may affect device reliability. Current. 2Specification is for device in free air: 16-Lead Plastic DIP Package: q = 85(cid:176)C/W 5 BFIN BUFFER INPUT JA 16-Lead SOIC Package: q JA = 100(cid:176)C/W Optionally Used to Realize Low Frequency Post-Demodulation Filters. ORDERING GUIDE 6 VLOG BUFFERED LOG OUTPUT Temperature Package Package 37.5 mV/dB (100 mV to 4.5 V). Model Range Description Option 7 OPCM OUTPUT COMMON AD606JN 0(cid:176) C to +70(cid:176) C 16-Lead Plastic DIP N-16 Connect to Ground. AD606JR 0(cid:176) C to +70(cid:176) C 16-Lead Narrow-Body R-16A 8 LMLO DIFFERENTIAL LIMITER OUTPUT SOIC 1.2 mA Full-Scale Output Current. Open AD606JR-REEL 0(cid:176) C to +70(cid:176) C 13" Tape and Reel R-16A Collector Output Must Be “Pulled” Up to AD606JR-REEL7 0(cid:176) C to +70(cid:176) C 7" Tape and Reel R-16A VPOS with R £ 400 W . AD606-EB Evaluation Board 9 LMHI DIFFERENTIAL LIMITER OUTPUT AD606JCHIPS 0(cid:176) C to +70(cid:176) C Die 1.2 mA Full-Scale Output Current. Open Collector Output Must Be “Pulled” Up to VPOS with R £ 400 W . PIN DESCRIPTION Plastic DIP (N) 10 LADJ LIMITER LEVEL ADJUSTMENT and Optionally Used to Adjust Limiter Output Small Outline (R) Current. Packages 11 FIL1 OFFSET LOOP LOW-PASS FILTER Normally No Connection; a Capacitor Between FIL1 and FIL2 May Be Added to Lower the INLO 1 16 INHI Filter Cutoff Frequency. COMM 2 15 COMM ISUM 3 14 PRUP 12 FIL2 OFFSET LOOP LOW-PASS FILTER Normally No Connection; See Above. ILOG 4 AD606 13 VPOS BFIN 5 (NToOt Pto V SIEcaWle)12 FIL1 13 VPOS POSITIVE SUPPLY Connect to +5 V at 13 mA. VLOG 6 11 FIL2 OPCM 7 10 LADJ 14 PRUP POWER UP CMOS (5 V) Logical High = Device On LMLO 8 9 LMHI (» 65 mW). CMOS (0 V) Logical Low = Device Off (» 325 m W). 15 COMM POWER SUPPLY COMMON Connect to Ground. 16 INHI DIFFERENTIAL RF INPUT –75 dBm to +5 dBm, Noninverting, AC-Coupled. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD606 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. B –3–

AD606 INPUT LEVEL CONVENTIONS results in an alternating input voltage being transformed into a RF logarithmic amplifiers usually have their input specified in quasi-dc (rectified and filtered) output voltage. “dBm,” meaning “decibels with respect to 1 mW.” Unfortu- The single supply nature of the AD606 results in common-mode nately, this is not precise for several reasons. level of the inputs INHI and INLO being at about +2.5 V (us- 1. Log amps respond not to power but to voltage. In this re- ing the recommended +5 V supply). In normal ac operation, spect, it would be less ambiguous to use “dBV” (decibels this bias level is developed internally and the input signal is referred to 1 V) as the input metric. Also, power is dependent coupled in through dc blocking capacitors. Any residual dc on the rms (root mean-square) value of the signal, while log offset voltage in the first stage limits the logarithmic accuracy for amps are not inherently rms responding. small inputs. In ac operation, this offset is automatically and continuously nulled via a feedback path from the last stage, pro- 2. The response of a demodulating log amp depends on the vided that the pins INHI and INLO are not shorted together, as waveform. Convention assumes that the input is sinusoidal. would be the case if transformer coupling were used for the signal. However, the AD606 is capable of accurately handling any input waveform, including ac voltages, pulses and square While any logarithmic amplifier must eventually conform to the waves, Gaussian noise, and so on. See the AD640 data sheet, basic equation shown above, which, with appropriate elabora- which covers the effect of waveform on logarithmic intercept, tion, can also fully account for the effect of the signal waveform for more information. on the effective intercept,1 it is more convenient in RF applica- tions to use a simpler expression. This simplification results 3. The impedance in which the specified power is measured is from first, assuming that the input is always sinusoidal, and not always stated. In the log amp context it is invariably assumed to be 50 W . Thus, 0 dBm means “1 mW rms in 50 W ,” second, using a decibel representation for the input level. The and corresponds to an rms voltage of (1mW · 50W ),or standard representation of RF levels is (incorrectly, in a log amp context) in terms of power, specifically, decibels above 1 milli- 224 mV. watt (dBm) with a presumed impedance level of 50 W . That Popular convention requires the use of dBm to simplify the being the case, we can rewrite the transfer function as comparison of log amp specifications. Unless otherwise stated, sinusoidal inputs expressed as dBm in 50 W are used to specify V LOG =VY (PIN – PX) the performance of the AD606 throughout this data sheet. We where it must be understood that P means the sinusoidal input IN will also show the corresponding rms voltages where it helps to power level in a 50 W system, expressed in dBm, and P is the X clarify the specification. Noise levels will likewise be given in intercept, also expressed in dBm. In this case, P and P are IN X dBm; the response to Gaussian noise is 0.5 dB higher than for a simple, dimensionless numbers. (P is sometimes called the X sinusoidal input of the same rms value. “logarithmic offset,” for reasons which are obvious from the Note that dynamic range, being a simple ratio, is always speci- above equation.) VY is still defined as the logarithmic slope, fied simply as “dB”, and the slope of the logarithmic transfer usually specified as so many millivolts per decibel, or mV/dB. function is correctly specified as “mV/dB,” NOT as “mV/dBm.” In the case of the AD606, the slope voltage, V , is nominally Y 750 mV when operating at V = 5 V. This can also be ex- POS LOGARITHMIC SLOPE AND INTERCEPT pressed as 37.5 mV/dB or 750 mV/decade; thus, the 80 dB A generalized logarithmic amplifier having an input voltage V IN range equates to 3 V. Figure 1 shows the transfer function of the and output voltage V must satisfy a transfer function of the LOG AD606. The slope is closely proportional to V , and can more POS form generally be stated as V = 0.15 · V Thus, in those applica- V LOG = VY log10 (VIN/VX) tions where the scaling mY ust be indePpOeSn.dent of supply voltage, where, in the case of the AD606, the voltage V is the differ- this must be stabilized to the required accuracy. In applications IN ence between the voltages on pins INHI and INLO, and the where the output is applied to an A/D converter, the reference voltage V is that measured at the output pin VLOG. V and LOG Y V are fixed voltages that determine the slope and intercept of 4 X the logarithmic amplifier, respectively. These parameters are 3.5 inherent in the design of a particular logarithmic amplifier, although may be adjustable, as in the AD606. When V = V , 3 IN X the logarithmic argument is one, hence the logarithm is zero. V X DC 2.5 ioausgus, ietntp hVgue Ytbr eavifssoo eclrt-aea1n,g0 ce aal loVlslgoeLa OdbrG iett h hcienrm otlesso srgaepassr r esizttheheordmow ainfcso rhitn hettheree ri“sc. evipontlp tvsuo tpl.t eaTrg hdee eb csealcodapeue”s evw othlhte-en LOG – Volts 1.25 SLOPE = 37.5mV/dB V Note carefully that VLOG and VLOG in the above paragraph 1 (and elsewhere in this data sheet) are different. The first is a voltage; the second is a pin designation. 0.5 INTERCEPT AT –88.33dBm This equation suggests that the input V is a dc quantity, and, 0 IN –100 –80 –60 –40 –20 0 +20 if V is positive, that V must likewise be positive, since the X IN INPUT SIGNAL – dBm logarithm of a negative number has no simple meaning. In fact, in the AD606, the response is independent of the sign of V Figure 1. Nominal Transfer Function IN because of the particular way in which the circuit is built. This 1See, for example, the AD640 data sheet, which is published in Section 3 of is part of the demodulating nature of the amplifier, which the Special Linear Reference Manual or Section 9.3 of the 1992 Amplifier Applications Guide. –4– REV. B

AD606 for that converter should be a fractional part of VPOS, if possible. ILOG and OPCM (output common, which is usually grounded). The slope is essentially independent of temperature. The nominal slope at this point is 18.75 mV/dB (375 mV/ The intercept P is essentially independent of either the supply decade). X voltage or temperature. However, the AD606 is not factory In applications where V is taken to an A/D converter which LOG calibrated, and both the slope and intercept may need to be allows the use of an external reference, this reference input externally adjusted. Following calibration, the conformance to should also be connected to the same +5 V supply. The power an ideal logarithmic law will be found to be very close, particu- supply voltage may be in the range +4.5 V to +5.5 V, providing larly at moderate frequencies (see Figure 14), and still accept- a range of slopes from nominally 33.75 mV/dB (675 mV/ de- able at the upper end of the frequency range (Figure 15). cade) to 41.25 mV/dB (825 mV/decade). A buffer amplifier, having a gain of two, provides a final output CIRCUIT DESCRIPTION scaling at V of 37.5 mV/dB (750 mV/decade). This low- Figure 2 is a block diagram of the AD606, which is a complete LOG impedance output can run from close to ground to over +4 V logarithmic amplifier system in monolithic form. It uses a total (using the recommended +5 V supply) and is tolerant of resis- of nine limiting amplifiers in a “successive detection” scheme to tive and capacitive loads. Further filtering is provided by a con- closely approximate a logarithmic response over a total dynamic jugate pole pair, formed by internal capacitors which are an range of 90 dB (Figure 2). The signal input is differential, at integral part of the output buffer. The corner frequency of the nodes INHI and INLO, and will usually be sinusoidal and ac overall filter is 2 MHz, and the 10%–90% rise time is 150 ns. coupled. The source may be either differential or single-sided; Later, we will show how the slope and intercept can be altered the input impedance is about 2.5 kW in parallel with 2 pF. Seven using simple external adjustments. The direct buffer input of the amplifier/detector stages handle inputs from –80 dBm BFIN is used in these cases. (32 m V rms) up to about –14 dBm (45 mV rms). The noise floor is about –83 dBm (18 m V rms). Another two stages receive the The last limiter output is available as complementary currents input attenuated by 22.3 dB, and respond to inputs up to from open collectors at pins LMHI and LMLO. These currents +10 dBm (707 mV rms). The gain of each of these stages is are each 1.2 mA typical with LADJ grounded and may be con- 11.15 dB and is accurately stabilized over temperature by a verted to voltages using external load resistors connected to precise biasing system. VPOS; typically, a 200 W resistor is used on just one output. The voltage gain is then over 90 dB, resulting in a hard-limited The detectors provide full-wave rectification of the alternating output for all input levels down to the noise floor. The phasing signal present at each limiter output. Their outputs are in the is such that the voltage at LMHI goes high when the input form of currents, proportional to the supply voltage. Each cell (INHI to INLO) is positive. The overall delay time from the incorporates a low-pass filter pole, as the first step in recovering signal inputs to the limiter outputs is 8 ns. Of particular impor- the average value of the demodulated signal, which contains tance is the phase stability of these outputs versus input level. At appreciable energy at even harmonics of the input frequency. A 50 MHz, the phase typically remains within – 4(cid:176) from –70 dBm further real pole can be introduced by adding a capacitor be- to +5 dBm. The rise time of this output (essentially a square tween the summing node ISUM and VPOS. The summed de- wave) is about 1.2 ns, resulting in clean operation to more than tector output currents are applied to a 6:1 reduction current 70 MHz. mirror. Its output at ILOG is scaled 2 m A/dB, and is converted to voltage by an internal load resistor of 9.375 kW between INHI COMM PRUP VPOS FIL1 FIL2 LADJ LMHI 16 15 14 13 12 11 10 9 REFERENCE AND POWER-UP 30pF 360kV X1 30kV 30kV 30pF 360kV OFFSET-NULL LOW-PASS FILTER 1.5kV FINAL MAIN SIGNAL PATH LIMITER 250V 11.15dB/STAGE 1.5kV HIGH-END 12mA/dB 9.375kV 2pF STAWLLOE-PNO-KLEEY DETECTORS ONE-POLE 9.375kV FILTER FILTER X2 AD606 2pF 2mA/dB 1 2 3 4 5 6 7 8 INLO COMM ISUM ILOG BFIN VLOG OPCM LMLO Figure 2.Simplified Block Diagram REV. B –5–

AD606 Offset-Control Loop The loop’s effect is felt only at the lower end of the dynamic The offset-control loop nulls the input offset voltage, and sets range, that is, from about 80 dBm to –70 dBm, and when the up the bias voltages at the input pins INHI and INLO. A full signal frequency is near the lower edge of the passband. Thus, understanding of this offset-control loop is useful, particularly the small signal results which are obtained using the suggested when using larger input coupling capacitors and an external model are not indicative of the ac response at moderate to high filter capacitor to lower the minimum acceptable operating signal levels. Figure 4 shows the response of this model for the frequency. The loop’s primary purpose is to extend the lower default case (using C = 100 pF and C = 0) and with C = C Z Z end of the dynamic range in the case where the offset voltage of 150 pF. In general, a maximally flat ac response occurs when C Z the first stage should be high enough to cause later stages to is roughly twice C (making due allowance for the internal C prematurely enter limiting, because of the high dc gain (about 30 pF capacitors). Thus, for audio applications, one can use 8000) of the main amplifier system. For example, an offset C = 2.7 m F and C = 4.7 m F to achieve a high-pass corner C Z voltage of only 20 m V would become 160 mV at the output of (–3 dB) at 25 Hz. the last stage in the main amplifier (before the final limiter sec- tion), driving the last stage well into limiting. In the absence of 90 noise, this limiting would simply result in the logarithmic output 80 ceasing to become any lower below a certain signal level at the 70 input. The offset would also degrade the logarithmic conform- CZ = 150pF B 60 ance in this region. In practice, the finite noise of the first stage – d T 50 also plays a role in this regard, even if the dc offset were zero. PU CZ = 0pF T 40 Figure 3 shows a representation of this loop, reduced to essen- OU tials. The figure closely corresponds to the internal circuitry, VE 30 and correctly shows the input resistance. Thus, the forward gain ATI 20 L of the main amplifier section is 7 · 11.15 dB, but the loop gain RE 10 is lowered because of the attenuation in the network formed by 0 RB1 and RB2 and the input resistance RA. The connection –10 polarity is such as to result in negative feedback, which reduces –20 the input offset voltage by the dc loop gain, here about 50 dB, 10k 100k 1M 10M 100M INPUT FREQUENCY – Hz that is, by a factor of about 316. We use a differential representa- tion, because later we will examine the consequences to the Figure 4.Frequency Response of Offset Control Loop for power-up response time in the event that the ac coupling capaci- C = 0 pF and C = 150 pF (C = 100 pF) Z Z C tors C and C do not exactly match. Note that these capaci- C1 C2 However, the maximally flat ac response is not optimal in two tors, as well as forming a high-pass filter to the signal in the special cases. First, where the RF input level is rapidly pulsed, forward path, also introduce a pole in the feedback path. the fast edges will cause the loop filter to ring. Second, ringing can also occur when using the power-up feature, and the ac +1 coupling capacitors do not exactly match in value. We will ex- CF2 FIL2 amine the latter case in a moment. Ringing in a linear amplifier RB1 30pF RF2 is annoying, but in a log amp, with its much enhanced sensitiv- 30kV 360kV CZ ity to near zero signals, it can be very disruptive. CC1 To optimize the low level accuracy, that is, achieve a highly RA TO FINAL 2.5kV 78dB 0V LIMITER damped pulse response in this filter, it is recommended to in- STAGE clude a resistor R in series with an increased value of C . Some Z Z CC2 experimentation may be necessary, but for operation in the R30Bk2V C30Fp1F R36F01kV FIL1 RZ raanndg Re Z3 =M 2H kzW t oar 7e 0n eMarH ozp,t ivmalaul.e sF oorf oCpCe r=a t1io0n0 dpoFw, nC tZo =1 010 nkFHz +1 use C = 10 nF, C = 0.1 m F and R = 13 kW . Figure 5 shows C Z Z typical connections for the AD606 with these filter components Figure 3.Offset Control Loop added. Internal resistors RF1 and RF2 in conjunction with grounded capacitors CF1 and CF2 form a low-pass filter at 15 kHz. This CZ RZ frequency can optionally be lowered by the addition of an exter- ncoanl jcuanpcatcioitno rw CitZh, tahned loinw s-opmases cseacsetiso an sfeorrimese rde saits ttohre RinZp. uTth cios,u i-n INHI COMM PRUP VPOS FIL1 FIL2 LADJ LMHI pling, results in a two-pole high-pass response, falling of at AD606JN 4of0 tdhBis/ dfieltceard dee bpeelnodws tohne tchoer nraetri ofr eCqZu/CenCc (yw. Thehne CdaZm>>pCinFg) faancdtor INLO COMM ISUM ILOG BFIN VLOG OPCM LMLO also on the value of R . Z The inclusion of this control loop has no effect on the high frequency Figure 5. Use of C and R for Offset Control Loop Z Z response of the AD606. Nor does it have any effect on the low fre- Compensation quency response when the input amplitude is substantially above the input offset voltage. –6– REV. B

AD606 For operation above 10 MHz, it is not necessary to add the APPLICATIONS external capacitors CF1, CF2, and C , although an improve- Note that the AD606 has more than 70 MHz of input band- Z ment in low frequency noise can be achieved by so doing (see width and 90 dB of gain! Careful shielding is needed to realize APPLICATIONS). Note that the offset control loop does not its full dynamic range, since nearly all application sites will be materially affect the low-frequency cutoff at high input levels, pervaded by many kinds of interference, radio and TV stations, when the offset voltage is swamped by the signal. etc., all of which the AD606 faithfully hears. In bench evalua- tion, we recommend placing all of the components in a shielded Power-Up Interface box and using feedthrough decoupling networks for the supply The AD606 features a power-saving mode, controlled by the voltage. In many applications, the AD606’s low power drain logic level at Pin 14 (PRUP). When powered down, the quies- cent current is typically 65 m A, or about 325 m W. A CMOS allows the use of a 6 V battery inside the box. logical HIGH applied to PRUP activates both internal refer- Basic RSSI Application ences, and the system becomes fully functional within about Figure 6 shows the basic RSSI (Receiver Signal Strength Indica- 3.5 m s. When this input is a CMOS logical LOW, the system tor) application circuit, including the calibration adjustments, shuts down to the quiescent level within about 5 m s. either or both of which may be omitted in noncritical applica- tions. This circuit may be used “as is” in such measurement The power-up time is somewhat dependent on the signal level applications as the log/IF strip in a spectrum or network ana- and can be degraded by mismatch of the input coupling capaci- lyzer or, with the addition of an FM or QPSK demodulator fed tors. The explanation is as follows. When the AD606 makes the by the limiter outputs, as an IF strip in such communications transition from powered-down to fully active, the dc bias voltage applications as a GSM digital mobile radio or FM receiver. at the input nodes INHI and INLO (about +2.5 V) inevitably changes slightly, as base current in the input transistors flows in The slope adjustment works in this way: the buffer amplifier the bias resistors. In fact, first-order correction for this is in- (which forms part of a Sallen-Key two-pole filter, see Figure 2) cluded in the specially designed offset buffer amplifier, but even has a dc gain of plus two, and the resistance from BFIN (buffer a few millivolts of change at these inputs represents a significant in) to OPCM (output common) is nominally 9.375 kW . This equivalent “dBm” level. resistance is driven from the logarithmic detector sections with a current scaled 2 m A/dB, generating 18.75 mV/dB at BFIN, Now, if the coupling capacitors do not match exactly, some hence 37.5 mV/dB at V Now, a resistor (R4 in Figure 6) fractional part of this residual voltage step becomes coupled into LOG connected directly between BFIN and VLOG would form a the amplifier. For example, if there is a 10% capacitor mis- controlled positive-feedback network with the internal 9.375 kW match, and INHI and INLO jump 20 mV at power-up, there is resistor which would raise the gain, and thus increase the slope a 2 mV pulse input to the system, which may cause the offset voltage, while the same external resistor connected between control loop to ring. Note that 2 mV is roughly 40 times greater BFIN and ground would form a shunt across the internal resis- than the amplitude of a sinusoidal input at –75 dBm. As long as tor and reduce the slope voltage. By connecting R4 to a potenti- the ringing persists, the AD606 will be “blind” to the actual ometer R2 across the output, the slope may be adjusted either input, and V will show major disturbances. LOG way; the value for R4 shown in Figure 6 provides approximately The solution to this problem is first, to ensure that the loop – 10% range, with essentially no effect on the slope at the filter does not ring, and second, to use well-matched capacitors midposition. at the signal input. Use the component values suggested above The intercept may be adjusted by adding a small current into to minimize ringing. BFIN via R1 and R3. The AD606 is designed to have the nomi- nal intercept value of –88 dBm when R1 is centered using this network, which provides a range of – 5 dB. +5V 0.1mF 100pF RF INPUT NC NC INHI COMM PRUP VPOS FIL1 FIL2 LADJ LMHI 51.1V AD606 R2050V INLO COMM ISUM ILOG BFIN VLOG OPCM LMLO 100pF LIMITER OUTPUT +5V LOGARITHMIC R3 R4 OUTPUT 200kRV1 412kV 174kV R502kV INTERCEPT SLOPE ADJUSTMENT ADJUSTMENT NC = NO CONNECT 65dB 610% Figure 6.Basic Application Circuit Showing Optional Slope and Intercept Adjustments REV. B –7–

AD606 Adjustment Procedure In contrast to the limited dynamic range of the diode and The slope and intercept adjustments interact; this can be mini- thermistor-styled sensors used in power meters, the AD606 can mized by reducing the resistance of R1 and R2, chosen here to measure signals from below –80 dBm to over +10 dBm. An minimize power drain. Calibration can be achieved in several optional 50 W termination is included in the figure; this could ways: The simplest is to apply an RF input at the desired oper- form the lower arm of an external attenuator to accommodate ating frequency which is amplitude modulated at a relatively larger signal levels. By the simple expedient of using a 13 dB low frequency (say 1 kHz to 10 kHz) to a known modulation attenuator, the LCD reading now becomes dBV (decibels above index. Thus, one might choose a ratio of 2 between the maxi- 1 V rms). This requires a series resistor of 174 W , presenting an mum and minimum levels of the RF amplitude, corresponding input resistance of 224 W . Alternatively, the input resistance can to a 6 dB (strictly, 6.02 dB) change in input level. The average be raised to 600 W using 464 W and 133 W . It is important to RF level should be set to about –35 dBm (the midpoint of the note that the AD606 inputs must be ac coupled. To extend the AD606’s range). R2 is then adjusted so that the 6 dB input low frequency range, use larger coupling capacitors and an change results in the desired output voltage change, for ex- external loop filter, as outlined earlier. ample, 226 mV at 37.5 mV/dB. The nominal 0.5 V to 3.5 V output of the AD606 (for a –75 dBm A better choice would be a 4:1 ratio (12.04 dB), to spread the to +5 dBm input) must be scaled and level shifted to fit within residual error out over a larger segment of the whole transfer the +1 V to +4.5 V common-mode range of the ICL7136 for function. If a pulsed RF generator is available, the decibel incre- the +5 V supply used. This is achieved by the passive resistor ment might be enlarged to 20 dB or more. Using just a fixed- network of R1, R2, and R3 in conjunction with the bias net- level RF generator, the procedure is more time consuming, but works of R4 through R7, which provide the ICL7136 with its is carried out in just the same way: manually change the level by reference voltage, and R9 through R11, which set the intercept. a known number of decibels and adjust R2 until V varies by The ICL7136 measures the differential voltage between INHI LOG the corresponding voltage. and INLO, which ranges from –75 mV to +5 mV for a Having adjusted the slope, the intercept may now be simply ad- –75 dBm to +5 dBm input. justed using a known input level. A value of –35 dBm (397.6 mV To calibrate the power meter, first adjust R6 for 100 mV be- rms, or 400 mV to within 0.05 dB) is recommended, and if the tween REF HI and REF LO. This sets the initial slope. Then standard scaling is used (P = –88.33 dBm, V = 37.5 mV/dB), adjust R10 to set INLO 80 mV higher than INHI. This sets the X Y then V should be set to +2 V at this input level. initial intercept. The slope and intercept may now be adjusted LOG using a calibrated signal generator as outlined in the previous A Low Cost Audio Through RF Power Meter Figure 7 shows a simple power meter that uses the AD606 and section. an ICL7136 3-1/2 digit DMM IC driving an LCD readout. The To extend the low frequency limit of the system to audio fre- circuit operates from a single +5 V supply and provides direct quencies, simply change C1, C2, and C3 to 4.7 m F. readout in dBm, with a resolution of 0.1 dBm. The limiter output of the AD606 may be used to drive the high- impedance input of a frequency counter. +5V 0.1mF dBV +5V INPUT OPTIONAL 174VC1* 0.1mF +5V C3* FRCDEORQUIVUNEET TNEORCY 4.99kRV4 DISPLAY 100pF 150pF 36 REF HI –75.0 dBm R5 INPUT 4.32kV INHI COMM PRUP VPOS FIL1 FIL2 LADJ LMHI 200V 500RRV67 100mV 35 REF LO 40 180kV 51.1V AD606JN +5V +5V 162V 39 C2* INLO COMM ISUM ILOG BFIN VLOG OPCM LMLO 1050kkRRVV89 2.513V NOM 32 ICNOLMOM 38 50pF 100pF 34 NC NC NC R10 0.1mF 100kV 80mV 33 *FCCO1O,RN C NA2EU, CADTNIO DT O MC E3PA ITNSOSU 4R1.,7E 1mM6FE;N PTOSS CITHIVAEN GPOELARITY S0IFGdOBNRmAL 1mCF4 ICL7136CPL 0.1mF +5V INPUT 1.8MV NC = NO CONNECT 1RM1V 54.9kRV2 31 INHI 0.047mF 2.433V NOM R3 54.9kV V– Figure 7.A Low Cost RF Power Meter –8– REV. B

AD606 0.1mF +5V ATTE2N0UdBATOR 4.C7m1F LOFWIL-TPEARSS 4.C7m4F AC + INPUT R4 R1 453V 100V INHI COMM PRUP VPOS FIL1 FIL2 LADJ LMHI R5 C3 AD606JN 51.1V 680pF INLO COMM ISUM ILOG BFIN VLOG OPCM LMLO C2 4.7m+F 10R02V NC NC NC TO DVM R3 DIECAST BOX 1kV NC = NO CONNECT Figure 8.Circuit for Low Frequency Measurements Low Frequency Applications This low-pass filter introduces some attenuation due to R1 and With reasonably sized input coupling capacitors and an optional R2 in conjunction with the 2.5 kW input resistance of the input low-pass filter, the AD606 can operate to frequencies as AD606. To minimize this effect, the value of R1 and R2 should low as 200 Hz with good log conformance. Figure 8 shows the be kept as small as possible–100 W is a good value since it bal- schematic, with the low-pass filter included in the dashed box. ances the need to reduce the attenuation as mentioned above This circuit should be built inside a die cast box and the signal with the requirement for R1 and R2 to be much larger then the brought in through a coaxial connector. The circuit must also impedance of C1 and C2 at the low-pass corner frequency, in have a low-pass filter to reject the attenuated RF signals that our case about 1 MHz. would otherwise be rectified along with the desired signal and be added to the log output. The shielded and filtered circuit has 90dB 4 a 90 dB dynamic range, as shown in Figure 9. In this circuit, R4 and R5 form a 20 dB attenuator that extends 3.5V the input range to 10 V rms. R3 isolates loads from VLOG. 3 Capacitors C1 and C2 (4.7 m F each), R1, R2, and the AD606’s input resistance of 2.5 kW form a 100 Hz high-pass filter that is DC before the AD606; the corner frequency of this filter must be olts well below the lowest frequency of interest. In addition, the – V 2 offset-correction loop introduces another pole at low signal OG 1kHz – 10MHz L V levels that is transformed into another high-pass filter because it 100Hz is in a feedback path. This indicates that there has to be a 1 gradual transition from a 40 dB roll off at low signal levels to a 20 dB roll off at high signal levels, at which point the feedback low pass filter is effectively disabled since the incoming signal 0 swamps the feedback signal. –80 –60 –40 –20 0 20 40 INPUT SIGNAL – dBm Figure 9.Performance of Low Frequency Circuit at 100 Hz and 1 kHz to 10 MHz (Note Attenuation) REV. B –9–

8/30/99 9 AM AD606–Typical Performance Characteristics 0.5 5 14 10.7MHz MITER OUTPUT – dB–––201...555 10 .475MM7HH0zMzHz ASE SHIFT – Degrees ––1050 45MHz 70MHz Y CURRENT – mA11820 ORMALIZED LI–––543...555 RMALIZED PH ––2105 OWER SUPPL 624 N O P N –6.5 –25 0 –80 –70 –60 –50 –40 –30 –20 –10 0 20 –80 –60 –40 –20 0 20 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 INPUT LEVEL – dBm INPUT LEVEL – dBm PRUP VOLTAGE – Volts Figure 10.Normalized Limiter Figure 11.Normalized Limiter Figure 12.Supply Current vs. PRUP Amplitude Response vs. Input Level Phase Response vs. Input Level at Voltage at +25(cid:176)C at 10.7 MHz, 45 MHz and 70 MHz 10.7 MHz, 45 MHz, and 70 MHz 4.5 4 5 4 TA = +258C 3 4 olts DC 23..553 VS = 5.5V C ERROR – dB 021 TA = –258C TA = +258C C ERROR – dB 1023 TA = –258C TA = +258C V – VLOG1.52 VS = 5V ARITHMI–1 TA = +708C ARITHMI––21 1 VS = 4.5V LOG–2 LOG–3 TA = +708C 0.5 –3 –4 0 –4 –5 –80 –60 –40 –20 0 10 –80 –60 –40 –20 0 10 –80 –60 –40 –20 0 10 INPUT POWER – dBm INPUT AMPLITUDE – dBm INPUT AMPLITUDE – dBm Figure 13.V Plotted vs. Input Figure 14.Logarithmic Conform- Figure 15.Logarithmic Conform- LOG Level at 10.7 MHz as a Function of ance as a Function of Input Level at ance as a Function of Input Level at Power Supply Voltage 10.7 MHz at –25(cid:176)C, +25(cid:176)C, and 45 MHz at –25(cid:176)C, +25(cid:176)C, and +70(cid:176)C +70(cid:176)C Figure 16.Limiter Response at Figure 17.V Response to a Figure 18.Limiter Response at LOG Onset of 10.7 MHz Modulated Pulse 10.7 MHz CW Signal Modulated by Onset of 70 MHz Modulated Pulse at –75 dBm Using 200 pF Input a 25 m s Wide Pulse with a 25 kHz at –55 dBm Using 200 pF Input Coupling Capacitors Repetition Rate Using 200 pF Input Coupling Capacitors Coupling Capacitors. The Input Sig- nal Goes from +5 dBm to –75 dBm in 20 dB Steps. –10– REV. B

AD606 Figure 19.V Output for a Pulsed Figure 20.Example of Test Signal Figure 21.V Output for 10.7 MHz LOG LOG 10.7 MHz Input; Top Trace: –35 dBm Used for Figure 19 CW Input with PRUP Toggled ON to +5 dBm; Middle Trace: –15 dBm to and OFF; Top Trace: +5 dBm Input; –55 dBm; Bottom Trace: –35 dBm to – Middle Trace: –35 dBm Input; Bottom 75 dBm Trace: –75 dBm; PRUP Input from HP8112A: 0 to 4 V, 10 m s Pulsewidth with 10 kHz Repetition Rate +5V 0.1mF –10dB TO +30dB RF C1 C3 (10.7MHz SWEPT INPUT 100pF 150pF GAIN TESTS ONLY) FLUKE 6082A SYNTHESIZED GESNIEGRNAATLOR AD602 INHI COMM PRUP VPOS FIL1 FIL2 LADJ LMHI 200V MODUPLAUTLESDE 51.1V AD606JN +5V TESTS SWEPT GAIN HEWLETT PACTKEASRTDS INLO COMM ISUM ILOG BFIN VLOG OPCM LMLO 200V 8112A PULSE GENERATOR NC NC NC TEKTRONIX 7704A MAINFRAME C2 OSCILLOSCOPE 100pF 10 x P6201 7A18 7B53A NC = NO CONNECT ATTN PROBES AMP TIME-BASE 6137 7A24 PROBES AMP Figure 22.Test Setup for Characterization Data REV. B –11–

AD606 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Plastic DIP (N-16) 0.87 (22.1) MAX 9 9 16 9 8/ 0.31 (7.87) 0.25 (6.35) – 1 8 –0 PIN 1 0.35 0.300 (7.62) 98b (0.89) 6 0.18 (4.57) 1 MAX C 0.18 0.125 (3.18) (4.57) 0.011 MIN (0.28) 0.018 0.100 0.033 SEATING (0.46) (2.54) (0.84) PLANE BSC 16-Lead Narrow-Body SOIC (R-16A) 0.3937 (10.00) 0.3859 (9.80) 0.1574 (4.00) 16 9 0.2440 (6.20) 0.1497 (3.80) 0.2284 (5.80) 1 8 PIN 1 0.050 (1.27) 0.0688 (1.75) 0.0196 (0.50) BSC 0.0532 (1.35) 0.0099 (0.25)3 458 88 0.0098 (0.25) 0.0192 (0.49) SEATING 0.0099 (0.25)08 0.0500 (1.27) 0.0040 (0.10) 0.0138 (0.35) PLANE 0.0075 (0.19) 0.0160 (0.41) A. S. U. N D I E T N RI P –12– REV. B

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD606JNZ AD606JRZ AD606JN AD606JR AD606JR-REEL7 AD606JRZ-REEL7