Dual, Low Noise, Single-Supply Variable Gain Amplifier AD605 FEATURES FUNCTIONAL BLOCK DIAGRAM 2 independent linear-in-dB channels FIXED GAIN Input noise at maximum gain: 1.8 nV/√Hz, 2.7 pA/√Hz VGN GAIN IPNRPEUCTI SAITOTNE PNAUSASTIOVRE AM+3P4L.4IFdIBER Bandwidth: 40 MHz (−3 dB) CONTROL AND OUT Differential input SCALING VREF Absolute gain range programmable FBK −14 dB to +34 dB (FBK shorted to OUT) through 0 dB to 48 dB (FBK open) VOCM Variable gain scaling: 20 dB/V through 40 dB/V +IN DIFFERENTIAL Stable gain with temperature and supply variations ATTENUATOR SOiuntgpleu-te cnodmemd ounn impooldaer ginadine pcoenntdreonl tly set –IN 0 TO –48.4dB AD605 00541-001 Figure 1. Power shutdown at lower end of gain control Single 5 V supply Low power: 90 mW/channel Drives ADCs directly APPLICATIONS Ultrasound and sonar time-gain controls High performance AGC systems Signal measurement GENERAL DESCRIPTION The AD605 is a low noise, accurate, dual-channel, linear-in-dB Each independent channel of the AD605 provides a gain range variable gain amplifier (VGA), optimized for any application of 48 dB that can be optimized for the application. Gain ranges requiring high performance, wide bandwidth variable gain between −14 dB to +34 dB and 0 dB to +48 dB can be selected control. Operating from a single 5 V supply, the AD605 provides by a single resistor between Pin FBK and Pin OUT. The lower differential inputs and unipolar gain control for ease of use. and upper gain ranges are determined by shorting Pin FBK to Added flexibility is achieved with a user-determined gain range Pin OUT or leaving Pin FBK unconnected, respectively. The and an external reference input that provide user-determined two channels of the AD605 can be cascaded to provide 96 dB gain scaling (dB/V). of very accurate gain range in a monolithic package. The high performance linear-in-dB response of the AD605 is The gain control interface provides an input resistance of achieved with the differential input, single-supply, exponential approximately 2 MΩ and scale factors from 20 dB/V to 30 dB/V amplifier (DSX-AMP) architecture. Each of the DSX-AMPs for a VREF input voltage of 2.5 V to 1.67 V, respectively. Note comprises a variable attenuator of 0 dB to −48.4 dB followed by that scale factors up to 40 dB/V are achievable with reduced a high speed, fixed-gain amplifier. The attenuator is based on a accuracy for scales above 30 dB/V. The gain scales linearly in dB 7-stage R-1.5R ladder network. The attenuation between tap with control voltages (VGN) of 0.4 V to 2.4 V for the 20 dB/V points is 6.908 dB, and 48.360 dB for the entire ladder network. scale and 0.20 V to 1.20 V for the 40 dB/V scale. When VGN is The DSX-AMP architecture results in 1.8 nV/√Hz input noise <50 mV, the amplifier is powered down to draw 1.9 mA. Under spectral density and accepts a ±2.0 V input signal when VOCM normal operation, the quiescent supply current of each amplifier is biased at VP/2. channel is only 18 mA. The AD605 is available in a 16-lead PDIP and a 16-lead SOIC_N package and is guaranteed for operation over the −40°C to +85°C temperature range. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1996–2008 Analog Devices, Inc. All rights reserved.

AD605 TABLE OF CONTENTS Features .............................................................................................. 1 Gain Control Interface ............................................................... 14 Applications ....................................................................................... 1 Fixed Gain Amplifier and Interpolator Circuits—Applying an Functional Block Diagram .............................................................. 1 Active Feedback Amplifier ........................................................ 15 General Description ......................................................................... 1 Applications Information .............................................................. 16 Revision History ............................................................................... 2 Connecting Two Amplifiers to Double the Gain Range ....... 16 Specifications ..................................................................................... 3 Evaluation Board ............................................................................ 18 Absolute Maximum Ratings ............................................................ 5 Input Connections ..................................................................... 18 ESD Caution .................................................................................. 5 Adjusting Gain, Common-Mode, and Reference Levels ...... 18 Pin Configuration and Function Descriptions ............................. 6 Output Connections .................................................................. 18 Typical Performance Characteristics (per Channel) ................... 7 Outline Dimensions ....................................................................... 21 Theory of Operation ...................................................................... 13 Ordering Guide .......................................................................... 22 Differential Ladder (Attenuator) .............................................. 14 AC Coupling ............................................................................... 14 REVISION HISTORY 6/08—Rev. E to Rev. F 7/04—Rev. B to Rev. C Added Evaluation Board Section ................................................. 18 Edits to General Description ........................................................... 1 Added Figure 42 and Table 4......................................................... 18 Edits to Specifications ....................................................................... 2 Added Figure 43 and Figure 44..................................................... 19 Edits to Ordering Guide ................................................................... 3 Added Figure 45 to Figure 50 ........................................................ 20 Change to TPC 22 ............................................................................. 6 Updated Outline Dimensions ....................................................... 12 5/07—Rev. D to Rev. E Changes to Table 1 ............................................................................ 5 Changes to Fixed Gain Amplifier and Interpolator Circuits— Applying an Active Feedback Amplifier Section ........................ 15 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 1/06—Rev. C to Rev. D Updated Format .................................................................. Universal Changes to Table 2 ............................................................................ 5 Changes to Differential Ladder (Attenuator) Section ............... 14 Updated the Outline Dimensions ................................................ 18 Changes to the Ordering Guide .................................................... 19 Rev. F | Page 2 of 24

AD605 SPECIFICATIONS Each channel @ T = 25°C, V = 5 V, R = 50 Ω, R = 500 Ω, C = 5 pF, V = 2.5 V (scaling = 20 dB/V), −14 dB to +34 dB gain range, A S S L L REF unless otherwise noted. Table 1. AD605A AD605B Parameter Conditions Min Typ Max Min Typ Max Unit INPUT CHARACTERISTICS Input Resistance 175 ± 40 175 ± 40 Ω Input Capacitance 3.0 3.0 pF Peak Input Voltage At minimum gain 2.5 ± 2.5 2.5 ± 2.5 V Input Voltage Noise VGN = 2.9 V 1.8 1.8 nV/√Hz Input Current Noise VGN = 2.9 V 2.7 2.7 pA/√Hz Noise Figure R = 50 Ω, f = 10 MHz, VGN = 2.9 V 8.4 8.4 dB S R = 200 Ω, f = 10 MHz, VGN = 2.9 V 12 12 dB S Common-Mode Rejection Ratio f = 1 MHz, VGN = 2.65 V −20 −20 dB OUTPUT CHARACTERISTICS −3 dB Bandwidth Constant with gain 40 40 MHz Slew Rate VGN = 1.5 V, output = 1 V step 170 170 V/μs Output Signal Range R ≥ 500 Ω 2.5 ± 1.5 2.5 ± 1.5 V L Output Impedance f = 10 MHz 2 2 Ω Output Short-Circuit Current ±40 ±40 mA Harmonic Distortion VGN = 1 V, V = 1 V p-p OUT HD2 f = 1 MHz −64 −64 dBc HD3 f = 1 MHz −68 −68 dBc HD2 f = 10 MHz −51 −51 dBc HD3 f = 10 MHz −53 −53 dBc Two-Tone Intermodulation R = 0 Ω, VGN = 2.9 V, V = 1 V p-p S OUT Distortion (IMD) f = 1 MHz −72 −72 dBc f = 10 MHz −60 −60 dBc 1 dB Compression Point f = 10 MHz, VGN = 2.9 V, output referred 15 15 dBm Third-Order Intercept f = 10 MHz, VGN = 2.9 V, −1 −1 dBm V = 1 V p-p, input referred OUT Channel-to-Channel Crosstalk Ch1: VGN = 2.65 V, inputs shorted, −70 −70 dB Ch2: VGN = 1.5 V (mid gain), f = 1 MHz, V = 1 V p-p OUT Group Delay Variation 1 MHz < f < 10 MHz, full gain range ±2.0 ±2.0 ns VOCM Input Resistance 45 45 kΩ ACCURACY Absolute Gain Error −14 dB to −11 dB 0.25 V < VGN < 0.40 V −1.2 +1.0 +3.0 –1.2 +0.75 +3.0 dB −11 dB to +29 dB 0.40 V < VGN < 2.40 V −1.0 ±0.3 +1.0 –1.0 ±0.2 +1.0 dB +29 dB to +34 dB 2.40 V < VGN < 2.65 V −3.5 −1.25 +1.2 –3.5 −1.25 +1.2 dB Gain Scaling Error 0.4 V < VGN < 2.4 V ±0.25 ±0.25 dB/V Output Offset Voltage V = 2.500 V, VOCM = 2.500 V −30 ±20 +30 –30 ±20 +30 mV REF Output Offset Variation V = 2.500 V, VOCM = 2.500 V 30 57 30 50 mV REF Rev. F | Page 3 of 24

AD605 AD605A AD605B Parameter Conditions Min Typ Max Min Typ Max Unit GAIN CONTROL INTERFACE Gain Scaling Factor V = 2.5 V, 0.4 V < VGN < 2.4 V 19 20 21 19 20 21 dB/V REF V = 1.67 V 30 30 dB/V REF Gain Range FBK short to OUT −14 to +34 −14 to +34 dB FBK open 0 to 48 0 to 48 dB Input Voltage (VGN) Range 20 dB/V, VREF = 2.5 V 0.1 to 2.9 0.1 to 2.9 V Input Bias Current −0.4 −0.4 μA Input Resistance 2 2 MΩ Response Time 48 dB gain change 0.2 0.2 μs POWER SUPPLY Supply Voltage 4.5 5.0 5.5 4.5 5.0 5.5 V Power Dissipation 90 90 mW VREF Input Resistance 10 10 kΩ Quiescent Supply Current VPOS 18 23 18 23 mA Power-Down VPOS, VGN < 50 mV 1.9 3.0 1.9 3.0 mA Power-Up Response Time 48 dB gain, V = 2 V p-p 0.6 0.6 μs OUT Power-Down Response Time 0.4 0.4 μs Rev. F | Page 4 of 24

AD605 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 2. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Supply Voltage +VS other conditions above those indicated in the operational Pin 12, Pin 13 (with Pin 4, Pin 5 = 0 V) 6.5 V section of this specification is not implied. Exposure to absolute Input Voltage Pin 1 to Pin 3, Pin 6 to Pin 9, Pin 16 VPOS, 0 V maximum rating conditions for extended periods may affect Internal Power Dissipation device reliability. 16-Lead PDIP 1.4 W 16-Lead SOIC_N 1.2 W Operating Temperature Range −40°C to +85°C ESD CAUTION Storage Temperature Range −65°C to +150°C Lead Temperature, Soldering 60 sec 300°C Thermal Resistance θ JA 16-Lead PDIP 85°C/W 16-Lead SOIC_N 100°C/W Rev. F | Page 5 of 24

AD605 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VGN1 1 16 VREF –IN1 2 15 OUT1 +IN1 3 14 FBK1 AD605 GND1 4 13 VPOS TOP VIEW GND2 5 (Not to Scale)12 VPOS +IN2 6 11 FBK2 –IN2 7 10 OUT2 VGN2 8 9 VOCM 00541-002 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 VGN1 CH1 Gain Control Input and Power-Down Pin. If grounded, device is off; otherwise, positive voltage increases gain. 2 −IN1 CH1 Negative Input. 3 +IN1 CH1 Positive Input. 4 GND1 Ground. 5 GND2 Ground. 6 +IN2 CH2 Positive Input. 7 −IN2 CH2 Negative Input. 8 VGN2 CH2 Gain Control Input and Power-Down Pin. If grounded, device is off; otherwise, positive voltage increases gain. 9 VOCM Input to This Pin Defines Common-Mode Voltage for OUT1 and OUT2. 10 OUT2 CH2 Output. 11 FBK2 Feedback Pin That Selects Gain Range of CH2. 12 VPOS Positive Supply. 13 VPOS Positive Supply. 14 FBK1 Feedback Pin That Selects Gain Range of CH1. 15 OUT1 CH1 Output. 16 VREF Input to This Pin Sets Gain Scaling for Both Channels: 2.5 V = 20 dB/V and 1.67 V = 30 dB/V. Rev. F | Page 6 of 24

AD605 TYPICAL PERFORMANCE CHARACTERISTICS (PER CHANNEL) V = 2.5 V (20 dB/V scaling), f = 1 MHz, R = 500 Ω, C = 5 pF, T = 25°C, V = 5 V. REF L L A SS 40 40.0 37.5 THEORETICAL 30 –40°C, +25°C, +85°C 35.0 20 BV) d 32.5 ACTUAL B) G ( d N N ( 10 ALI 30.0 AI C G S N 27.5 0 AI G 25.0 –10 –20 00541-003 2202..05 00541-006 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 1.25 1.50 1.75 2.00 2.25 2.50 VGN (V) VREF (V) Figure 3. Gain vs. VGN Figure 6. Gain Scaling vs. VREF 50 3.0 2.5 40 2.0 1.5 30 FBK (OPEN) B) 1.0 –40°C d GAIN (dB) 2100 FBK (SHORT) N ERROR ( –00..505 +25°C GAI –1.0 +85°C 0 –1.5 –10 –2.0 –200.1 0.5 0.9 1.3 1.7 2.1 2.5 2.900541-004 ––32..050.2 0.7 1.2 1.7 2.2 2.700541-007 VGN (V) VGN (V) Figure 4. Gain vs. VGN for Different Gain Ranges Figure 7. Gain Error vs. VGN at Three Temperatures 40 2.0 1.5 30 30dB/V ACTUAL ACTUAL 1.0 20 (VREF = 1.67V) B) f = 1MHz d 0.5 N (dB) 10 20dB/V RROR ( 0 GAI (VREF = 2.50V) N E f = 5MHz AI –0.5 f = 10MHz 0 G –1.0 –10 –200.1 0.5 0.9 1.3 1.7 2.1 2.5 2.900541-005 ––21..050.2 0.7 1.2 1.7 2.2 2.700541-008 VGN (V) VGN (V) Figure 5. Gain vs. VGN for Different Gain Scalings Figure 8. Gain Error vs. VGN at Three Frequencies Rev. F | Page 7 of 24

AD605 2.0 60 VGN = 2.9V (FBK = OPEN) 1.5 40 VGN = 2.9V (FBK = SHORT) 1.0 VGN = 1.5V (FBK = OPEN) 20dB/V 20 R 0.5 VREF = 2.50V VGN = 1.5V (FBK = SHORT) ERRO 0 N (dB) 0 VGN = 0.1V (FBK = OPEN) N AI GAI –0.5 VRE3F0 d=B 1/.V67V G –20 VGN = 0.1V (FBK = SHORT) –1.0 VGN = 0.0V –40 ––12..50 00541-009 –60 00541-013 0.2 0.7 1.2 1.7 2.2 2.7 100k 1M 10M 100M VGN (V) FREQUENCY (Hz) Figure 9. Gain Error vs. VGN for Two Gain Scale Values Figure 12. AC Response for Three Values of VGN 20 2.525 N = 50 VOCM = 2.50V 18 ΔG(dB) = G(CH1) – G(CH2) 2.520 –40°C 16 2.515 14 2.510 +25°C GE 12 2.505 A V) NT 10 (S2.500 E O C V +85°C ER 8 2.495 P 6 2.490 4 2.485 02 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 00541-010 22..4478500 0.5 1.0 1.5 2.0 2.5 3.000541-014 DELTA GAIN (dB) VGN (V) Figure 10. Gain Match, VGN1 = VGN2 = 1.0 V Figure 13. Output Offset vs. VGN at Three Temperatures 20 130 N = 50 18 ΔG(dB) = G(CH1) – G(CH2) 125 +85°C 16 120 14 +25°C GE 12 Hz) 115 TA V/ CEN 10 E (n 110 PER 8 NOIS 105 –40°C 6 100 4 02 00541-011 9905 00541-015 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 0 0.5 1.0 1.5 2.0 2.5 3.0 DELTA GAIN (dB) VGN (V) Figure 11. Gain Match, VGN1 = VGN2 = 2.50 V Figure 14. Output Referred Noise vs. VGN at Three Temperatures Rev. F | Page 8 of 24

AD605 1000 100 VGN = 2.9V V/ Hz) 100 nV/ Hz) 10 E (n SE ( OIS NOI N 10 1.0 RSOURCE ALONE 1 00541-016 0.1 00541-019 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 1 10 100 1k VGN (V) RSOURCE (Ω) Figure 15. Input Referred Noise vs. VGN Figure 18. Input Referred Noise vs. RSOURCE 2.00 30 VGN = 2.9V VGN = 2.9V 1.95 25 1.90 B) d OISE (nV/ Hz) 111...788505 OISE FIGURE ( 1250 N N 1.70 10 11..6605 00541-017 5 00541-020 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 1 10 100 1k TEMPERATURE (°C) RSOURCE (Ω) Figure 16. Input Referred Noise vs. Temperature Figure 19. Noise Figure vs. RSOURCE 1.90 60 VGN = 2.9V RS = 50Ω 1.85 50 1.80 B) 40 E (nV/ Hz) 1.75 FIGURE (d 30 OIS SE N 1.70 NOI 20 1.65 10 1.60 00541-018 0 00541-021 100k 1M 10M 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 FREQUENCY (Hz) VGN (V) Figure 17. Input Referred Noise vs. Frequency Figure 20. Noise Figure vs. VGN Rev. F | Page 9 of 24

AD605 –30 15 –35 VOUT = 1V p-p 10 VGN = 1.0V c) B –40 N (d 5 ILNIMPUITT = G 2E1NdEBRmATOR RTIO –45 m) 0 O B NIC DIST ––5505 HD3 P (dIN –5 O HD2 M –10 R –60 A H ––6705 00541-022 ––2105 FFRREEQQ == 110MMHHzz 00541-025 100k 1M 10M 100M 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 FREQUENCY (Hz) VGN (V) Figure 21. Harmonic Distortion vs. Frequency Figure 24. 1 dB Compression vs. VGN –35 35 VOUT= 1V p-p –40 30 Bc) –45 HD3 25 d (10MHz) ORTION ( –50 H(1DM2Hz) H(1D0M2Hz) T (dBm) 20 f = 10MHz f = 1MHz ST –55 EP 15 MONIC DI –60 INTERC 10 AR –65 5 H ––7750 H(1DM3Hz) 00541-023 –05 00541-026 0.5 0.8 1.1 1.4 1.7 2.0 2.3 2.6 2.9 0.6 1.0 1.4 1.8 2.2 2.6 3.0 VGN (V) VGN (V) Figure 22. Harmonic Distortion vs. VGN at 1 MHz and 10 MHz Figure 25. Third-Order Intercept vs. VGN at 1 MHz and 10 MHz –20 2V –30 fV =O U1T0 M= H1Vz p-p VVOGUNT == 12.V5V p-p VGN = 1.0V –40 –50 P (dBm)OUT –––867000 –400mV/DIV –90 TRIG'D –100 ––112100 00541-024 2V 00541-027 9.92 9.96 10.00 10.02 10.04 253ns 1.253µs FREQUENCY (MHz) 100ns/DIV Figure 23. Intermodulation Distortion Figure 26. Large Signal Pulse Response Rev. F | Page 10 of 24

AD605 200 –30 VOUT = 200mV p-p VGN1 = 1V VGN = 1.5V VOUT1 = 1V p-p –40 VIN2 = GND B) –50 d V) K ( VGN2 = 2.9V 40mV (DI ROSSTAL –60 C –70 TRIG'D VGN2 = 2.5V VGN2 = 2.0V –80 –200 00541-028 –90 VGN2 = 0.1V 00541-031 253ns 1.253µs 100k 1M 10M 100M 100ns/DIV FREQUENCY (Hz) Figure 27. Small Signal Pulse Response Figure 30. Crosstalk (CH1 to CH2) vs. Frequency for Four Values of VGN2 0 VIN = 0dBm 500mV –10 2.9V 100 VGN = 2.9V 90 –20 B) VGN = 2.5V d V) RR ( –30 GN ( CM V –40 VGN = 2.0V 10 VGN = 0.1V –50 0% 0.0V 500mV 200ns 00541-029 –61000k 1MFREQUENCY (Hz)10M 100M00541-032 Figure 28. Power-Up/Power-Down Response Figure 31. CMRR vs. Frequency for Four Values of VGN 180 VGN = 2.9V 500mV 175 2.9V 100 170 90 Ω) CE ( 165 N A D N (V) MPE 160 VG UT I 155 P N I 150 10 0% 0.1V 500mV 100ns 00541-030 114410500k 1MFREQUENCY (Hz)10M 100M00541-033 Figure 29. Gain Response Figure 32. Input Impedance vs. Frequency Rev. F | Page 11 of 24

AD605 25 16 +IS (AD605) 14 20 A) NT (m 15 Y (ns) 12 E A R L R E 10 U D Y C 10 UP L O UPP GR 8 VGN = 0.1V S 5 6 0 +IS (VGN = 0) 00541-034 4 VGN = 2.9V 00541-035 –40 –30–20 –10 0 10 20 30 40 50 60 70 80 90 100k 1M 10M 100M TEMPERATURE (°C) FREQUENCY (Hz) Figure 33. Supply Current (One Channel) vs. Temperature Figure 34. Group Delay vs. Frequency Rev. F | Page 12 of 24

AD605 THEORY OF OPERATION The AD605 is a dual-channel, low noise VGA. Figure 35 shows The desired gain can then be achieved by setting the unipolar the simplified block diagram of one channel. Each channel consists gain control (VGN) to a voltage within its nominal operating of a single-supply X-AMP® (hereafter called DSX, differential range of 0.25 V to 2.65 V (for 20 dB/V gain scaling). The gain is single-supply X-AMP) comprising the following: monotonic for a complete gain control range of 0.1 V to 2.9 V. Maximum gain can be achieved at a VGN of 2.9 V. • Precision passive attenuator (differential ladder) Because the two channels are identical, only Channel 1 is used • Gain control block to describe their operation. VREF and VOCM are the only inputs • VOCM buffer with supply splitting resistors R3 and R4 that are shared by the two channels, and because they are normally • Active feedback amplifier1 (AFA) with gain setting resistors ac grounds, crosstalk between the two channels is minimized. For the highest gain scaling accuracy, VREF should have an R1 and R2 external low impedance voltage source. For low accuracy 20 dB/V The linear-in-dB gain response of the AD605 can generally be applications, the VREF input can be decoupled with a capacitor described by Equation 1. to ground. In this mode, the gain scaling is determined by the G (dB) = (Gain Scaling (dB/V)) × (Gain Control (V)) − midpoint between +VCC and GND; therefore, care should be (19 dB − (14 dB) × (FB)) (1) taken to control the supply voltage to 5 V. The input resistance looking into the VREF pin is 10 kΩ ± 20%. where: FB = 0, if FBK to OUT is shorted. The AD605 is a single-supply circuit, and the VOCM pin is used FB = 1, if FBK to OUT is open. to establish the dc level of the midpoint of this portion of the circuit. VOCM needs only an external decoupling capacitor to Each channel provides between −14 dB to +34.4 dB through ground to center the midpoint between the supply voltages (5 V, 0 dB to +48.4 dB of gain, depending on the value of the resistance GND). However, if the dc level of the output is important to the connected between Pin FBK and Pin OUT. The center 40 dB of user (see the Applications Information section of the AD9050 gain is exactly linear-in-dB while the gain error increases at the top data sheet for an example), VOCM can be specifically set. The and bottom of the range. The gain is set by the gain control voltage input resistance looking into the VOCM pin is 45 kΩ ± 20%. (VGN). The VREF input establishes the gain scaling. The useful gain scaling range is between 20 dB/V and 40 dB/V for a VREF 1 To understand the active-feedback amplifier topology, refer to the AD830 voltage of 2.5 V and 1.25 V, respectively. For example, if FBK to data sheet. The AD830 is a practical implementation of the idea. OUT is shorted and VREF is set to 2.50 V (to establish a gain scaling of 20 dB/V), the gain equation simplifies to G (dB) = (20 (dB/V)) × (VGN (V)) – 19 dB (2) VREF GAIN VGN CONTROL C1 175Ω DISTRIBUTEDgm +IN C2 EXT DAITFTFEENRUEANTTOIARL +G1 –IN + Ao OUT VPOS 175Ω R3 G2 3.36kΩ VOCM C3 2R040kΩ + 2R02Ω + 82R01Ω FBK 00541-036 200kΩ EXT Figure 35. Simplified Block Diagram of a Single Channel of the AD605 Rev. F | Page 13 of 24

AD605 R –6.908dB R –13.82dB R –20.72dB R –27.63dB R –34.54dB R –41.45dB R –48.36dB +IN 1.5R 1.5R 1.5R 1.5R 1.5R 1.5R 1.5R 175Ω MID 1.5R 1.5R 1.5R 1.5R 1.5R 1.5R 1.5R 175Ω R R R R R R R –IN NOTE: 1R. 5=R 9 =6 Ω144Ω 00541-037 Figure 36. R-1.5R Dual Ladder Network DIFFERENTIAL LADDER (ATTENUATOR) AC COUPLING The attenuator before the fixed gain amplifier is realized by a The DSX is a single-supply circuit; therefore, its inputs need to differential, 7-stage, R-1.5R resistive ladder network with an be ac-coupled to accommodate ground-based signals. External untrimmed input resistance of 175 Ω single ended or 350 Ω Capacitor C1 and Capacitor C2 in Figure 35 level-shift the input differentially. The signal applied at the input of the ladder signal from ground to the dc value established by VOCM (nominal network is attenuated by 6.908 dB per tap; therefore, the 2.5 V). C1 and C2, together with the 175 Ω looking into each of attenuation at the first tap is 6.908 dB, at the second, 13.816 dB, DSX inputs (+IN and −IN), act as high-pass filters with corner and so on all the way to the last tap where the attenuation is frequencies depending on the values chosen for C1 and C2. For 48.356 dB (see Figure 36). A unique circuit technique is used to example, if C1 and C2 are 0.1 μF, together with the 175 Ω input interpolate continuously between the tap points, thereby providing resistance of each side of the differential ladder of the DSX, a −3 dB continuous attenuation from 0 dB to −48.36 dB. One can think high-pass corner at 9.1 kHz is formed. of the ladder network together with the interpolation mechanism If the DSX output needs to be ground referenced, another ac as a voltage-controlled potentiometer. coupling capacitor is required for level shifting. This capacitor also Because the DSX is a single-supply circuit, some means of eliminates any dc offsets contributed by the DSX. With a nominal biasing its inputs must be provided. Node MID together with load of 500 Ω and a 0.1 μF coupling capacitor, this adds a high-pass the VOCM buffer performs this function. Without internal filter with −3 dB corner frequency at about 3.2 kHz. biasing, external biasing is required. If not done carefully, the The choice for all three of these coupling capacitors depends on biasing network can introduce additional noise and offsets. By the application. They should allow the signals of interest to pass providing internal biasing, the user is relieved of this task and unattenuated, while at the same time, they can be used to limit only needs to ac couple the signal into the DSX. It should be the low frequency noise in the system. made clear again that the input to the DSX is still fully differential if GAIN CONTROL INTERFACE driven differentially, that is, Pin +IN and Pin −IN see the same signal but with opposite polarity. What changes is the load seen The gain control interface provides an input resistance of by the driver; it is 175 Ω when each input is driven single ended, approximately 2 MΩ at Pin VGN1 and gain scaling factors from but 350 Ω when driven differentially. This can be easily explained 20 dB/V to 40 dB/V for VREF input voltages of 2.5 V to 1.25 V, when thinking of the ladder network as two 175 Ω resistors respectively. The gain varies linearly in decibels for the center connected back-to-back with the middle node, MID, being 40 dB of gain range, that is, for VGN equal to 0.4 V to 2.4 V for biased by the VOCM buffer. A differential signal applied between the 20 dB/V scale and 0.25 V to 1.25 V for the 40 dB/V scale. nodes +IN and −IN results in zero current into Node MID, but Figure 37 shows the ideal gain curves when the FBK-to-OUT a single-ended signal applied to either input +IN or −IN, while the connection is shorted as described by the following equations: other input is ac grounded, causes the current delivered by the G (20 dB/V) = 20 × VGN − 19, V = 2.500 V (3) REF source to flow into the VOCM buffer via Node MID. G (30 dB/V) = 30 × VGN − 19, V = 1.6666 V (4) REF A feature of the X-AMP architecture is that the output-referred G (40 dB/V) = 40 × VGN − 19, V = 1.250 V (5) noise is constant vs. gain over most of the gain range. Referring REF to Figure 36, the tap resistance is approximately equal for all The equations show that all gain curves intercept at the same taps within the ladder, excluding the end sections. The resistance −19 dB point; this intercept is 14 dB higher (−5 dB) if the FBK- seen looking into each tap is 54.4 Ω, which makes 0.95 nV/√Hz of to-OUT connection is left open. Outside the central linear Johnson noise spectral density. Because there are two attenuators, range, the gain starts to deviate from the ideal control law but the overall noise contribution of the ladder network is √2 times still provides another 8.4 dB of range. For a given gain scaling, 0.95 nV/√Hz or 1.34 nV/√Hz, a large fraction of the total DSX one can calculate V as REF noise. The rest of the DSX circuit components contribute another 2.500V×20dB/V 1.20 nV/√Hz, which together with the attenuator produces V = (6) REF GainScale 1.8 nV/√Hz of total DSX input referred noise. Rev. F | Page 14 of 24

AD605 40dB/V 30dB/V 20dB/V The AFA makes a differential input structure possible because 35 one of its inputs (G1) is fully differential; this input is made 30 up of a distributed gm stage. The second input (G2) is used for feedback. The output of G1 is some function of the voltages 25 sensed on the attenuator taps that is applied to a high gain 20 amplifier (A0). Because of negative feedback, the differential 15 LINEAR-IN-dB RANGE input to the high gain amplifier is zero; this in turn implies that OF AD605 the differential input voltage to G2 times g (the transconductance B)10 m2 N (d of G2) is equal to the differential input voltage to G1 times gm1 GAI 5 (the transconductance of G1). Therefore, the overall gain 0 function of the AFA is 0.5 1.0 1.5 2.0 2.5 3.0 –5 GAIN CONTROL VOLTAGE V g R1×R2 OUT = m1 × (7) –10 VATTEN gm2 R2 –15 where: –20 Figure 37. Ideal Gain Curves vs. VREF 00541-038 (VVROA1TUT T+E Ni s Ri ts2h )teh/ Reo 2ue tf=pfe u4ct2t i.vv oel tvaogleta. ge sensed on the attenuator. Usable gain control voltage ranges are 0.1 V to 2.9 V for the g /g = 1.25; the overall gain is therefore 52.5 (34.4 dB). m1 m2 20 dB/V scale and 0.1 V to 1.45 V for the 40 dB/V scale. VGN The AFA has additional features that include the following: voltages of less than 0.1 V are not used for gain control because inverting the output signal by switching the positive and negative below 50 mV the channel is powered down. This can be used to input to the ladder network; the possibility of using the −IN conserve power and at the same time gate-off the signal. The input as a second signal input; and independent control of the supply current for a powered-down channel is 1.9 mA, and the DSX common-mode voltage. Under normal operating conditions, response time to power the device on or off is less than 1 μs. it is best to connect a decoupling capacitor to Pin VOCM, in FIXED GAIN AMPLIFIER AND INTERPOLATOR which case, the common- mode voltage of the DSX is half of CIRCUITS—APPLYING AN ACTIVE FEEDBACK the supply voltage; this allows for maximum signal swing. AMPLIFIER Nevertheless, the common-mode voltage can be shifted up or down by directly applying a voltage to VOCM. It can also be A typical X-amp architecture is powered by a dual polarity used as another signal input, the only limitation being the power supply. Because the AD605 operates from a single supply, a rather low slew rate of the VOCM buffer. supply common equal to half the value of the supply voltage is required. An active feedback amplifier (AFA) is used to provide If the dc level of the output signal is not critical, another coupling a differential input and to implement the feedback loop. The capacitor is normally used at the output of the DSX; again, this AFA in the AD605 is an op amp with two gm stages; one is used is done for level shifting and to eliminate any dc offsets contributed in the feedback path, and the other is used as a highly linear by the DSX (see the AC Coupling section). differential input. The gain range of the DSX is programmable by a resistor connected A multisection distributed gm stage senses the voltages on the between Pin FBK and Pin OUT. The possible ranges are −14 dB to ladder network, one stage for each of the ladder nodes. Only a +34.4 dB when the pins are shorted together or 0 dB to +48.4 dB few of the stages are active at any time and are dependent on the when FBK is left open. For the higher gain range, the bandwidth gain control voltage. of the amplifier is reduced by a factor of five to about 8 MHz because the gain increased by 14 dB. This is the case for any constant gain bandwidth product amplifier that includes the active feedback amplifier. Rev. F | Page 15 of 24

AD605 APPLICATIONS INFORMATION The basic circuit in Figure 38 shows the connections for one VGN channel of the AD605 with a gain range of −14 dB to +34.4 dB. 0.C1µ1F 1 VGN1 VREF16 2.500V The signal is applied at +IN1. The ac coupling capacitors before 2 –IN1 OUT115 AD605 R1 Pin −IN1 and Pin +IN1 should be selected according to the VIN 3 +IN1 FBK114 C2 required lower cutoff frequency. In this example, the 0.1 μF 0.1µF 4 GND1 VPOS13 5V capacitors, together with the 175 Ω of each of the DSX input 0.C1µ3F 5 GND2 VPOS12 pins, provide a −3 dB high-pass corner of about 9.1 kHz. The 6 +IN2 FBK211 C5 R2 0.1µF upper cutoff frequency is determined by the amplifier and is 7 –IN2 OUT210 OUT C4 40 MHz. 0.1µF 8 VGN2 VOCM 9 C0.61µF 00541-040 VGN 0.1µF 1 VGN1 VREF 16 2.500V Figure 39. Doubling the Gain Range with Two Amplifiers 2 –IN1 OUT115 OUT VIN 3 +IN1 AD605FBK1 14 0.1µF Two other easy combinations are possible to provide a gain 0.1µF range of −14 dB to +82.8 dB: make R1 a short and R2 an open, 4 GND1 VPOS13 5V or make R1 an open and R2 a short. The bandwidth for both of 5 GND2 VPOS12 these cases is dominated by the channel that is set to the higher 6 +IN2 FBK2 11 gain and is about 8 MHz. From a noise standpoint, the second 7 –IN2 OUT210 choice is the best because by increasing the gain of the first 8 VGN2 VOCM 9 0.1µF 00541-039 aomn pthlief iteort, atlh oe untopiuste noof itshee. Osenceo nfudr tahmepr loifbieser rhvaast iloenss r oefg aarnd iimngp act Figure 38. Basic Connections for a Single Channel noise is that by increasing the gain, the output noise increases As shown in Figure 38, the output is ac-coupled for optimum proportionally; therefore, there is no increase in signal-to-noise performance. In the case of connecting to the 10-bit, 40 MSPS ratio. It actually stays fixed. ADC, AD9050, ac coupling can be eliminated as long as It should be noted that by selecting the appropriate values of R1 Pin VOCM is biased by the same 3.3 V common-mode voltage and R2, any gain range between −28 dB to +68.8 dB and 0 dB to as the AD9050. +96.8 dB can be achieved with the circuit in Figure 39. When Pin VREF requires a voltage of 1.25 V to 2.5 V, with gain scaling using any value other than shorts and opens for R1 and R2, the between 40 dB/V and 20 dB/V, respectively. Voltage VGN controls final value of the gain range depends on the external resistors the gain; its nominal operating range is from 0.25 V to 2.65 V matching the on-chip resistors. Because the internal resistors for 20 dB/V gain scaling and 0.125 V to 1.325 V for 40 dB/V can vary by as much as ±20%, the actual values for a particular scaling. When this pin is taken to ground, the channel powers gain have to be determined empirically. Note that the two channels down and disables its output. within one part match quite well; therefore, R1 tracks R2 in Figure 39. CONNECTING TWO AMPLIFIERS TO DOUBLE THE GAIN RANGE C3 is not required because the common-mode voltage at Pin OUT1 should be identical to the one at Pin +IN2 and Figure 39 shows the two channels of the AD605 connected in Pin −IN2. However, because only 1 mV of offset at the output series to provide a total gain range of 96.8 dB. When R1 and R2 of the first DSX introduces an offset of 53 mV when the second are shorts, the gain range is from −28 dB to +68.8 dB with a DSX is set to the maximum gain of the lowest gain range (34.4 dB), slightly reduced bandwidth of about 30 MHz. The reduction in and 263 mV when set to the maximum gain of the highest gain bandwidth is due to two identical low-pass circuits being connected range (48.4 dB), it is important to include ac coupling to get the in series; in the case of two identical single-pole, low-pass filters, maximum dynamic range at the output of the cascaded amplifiers. the bandwidth is reduced by exactly √2. If R1 and R2 are C5 is necessary if the output signal needs to be referenced to any replaced by open circuits, that is, Pin FBK1 and Pin FBK2 are left common-mode level other than half of the supply as is provided unconnected, the gain range shifts up by 28 dB to 0 dB to 96.8 dB. by Pin OUT2. As previously noted, the bandwidth of each individual channel is reduced by a factor of 5 to about 8 MHz because the gain increased by 14 dB. In addition, there is still the √2 reduction because the series connection of the two channels results in a final bandwidth of the higher gain version of about 6 MHz. Rev. F | Page 16 of 24

AD605 Figure 40 shows the gain vs. VGN for the circuit in Figure 39 4 f = 1MHz at 1 MHz and the lowest gain range (−14 dB to +34.4 dB). Note 3 that the gain scaling is 40 dB/V, double the 20 dB/V of an individual DSX; this is the result of the parallel connection of 2 the gain control inputs, VGN1 and VGN2. The gain can also be B) d 1 sequentially increased by first increasing the gain of Channel 1 R ( O and then Channel 2. In this case, VGN1 and VGN2 are driven RR 0 E from separate voltage sources, for instance two separate DACs. N AI –1 Figure 41 shows the gain error of Figure 39. G –2 80 THEORETICAL 756000 f = 1MHz ACTUAL ––430.2 0.7 1.2 1.7 2.2 2.700541-042 VGN (V) 40 Figure 41. Gain Error vs. VGN for the Circuit in Figure 39 B) 30 d N ( 20 AI G 10 0 –10 –20 ––4300 00541-041 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 VGN (V) Figure 40. Gain vs. VGN for the Circuit in Figure 39 Rev. F | Page 17 of 24

AD605 EVALUATION BOARD The AD605-EVALZ provides a platform for the circuit designer INPUT CONNECTIONS to become familiar with the many operating and performance The AD605 VGA accepts differential or single-ended input features of the AD605 variable gain amplifier. It is a factory- signals and provides single-ended outputs. The SMA connectors designed, surface-mount assembly fully tested and ready for enable either configuration to be used, as well as the output and service. Figure 42 is a photograph of the AD605-EVALZ. Multiple gain control signals. Each of the I/O ports is also available at a inputs, test points, and jumpers provide circuit configurations that test-loop labeled for easy identification. support any of the operating options of the device. Figure 43 is a The input resistance at each of the four input SMA connectors is schematic of the board. 50 Ω, consisting of the 175 Ω, ±40 Ω resistance of the attenuator Power is required from only a single 5 V supply capable of ladder network in parallel with the external 69.8 Ω resistors. For supplying 55 mA to 60 mA quiescent current. single-ended operation, unused inputs can be left disconnected or optional jumpers installed. Either VGA input is usable; for noninverting operation, the INPx is used, and for signal inversion, the INMx is used. ADJUSTING GAIN, COMMON-MODE, AND REFERENCE LEVELS The gain of each channel is adjusted with trimmers, GN1ADJ and GN2ADJ. Trimmer VREF ADJ adjusts the gain scaling in dB/V (or gain slope), and VOCM ADJ adjusts the output common-mode voltage for both channels. For dynamic gain control, JP1 and JP4 can be removed and the signal applied at the SMA connectors, GN1 and GN2. OUTPUT CONNECTIONS SMA connectors, OUT1 and OUT2, are the output connectors. Series resistors and capacitors are included for termination and dc blocking purposes. The output of the AD605 has a common- mode value of one-half the supply (unless amended by a voltage 00541-043 aTpapblliee 4d ltiost tsh jeu mVCpeMrs painnd). their functions, and Figure 44 shows Figure 42. AD605–EVALZ Evaluation Board the evaluation board in a typical test configuration. Table 4. Table of Jumpers Jumper Function Default Configuration JP1 Connects trimmer GN1ADJ to pin VGN1. This jumper can be removed for an ac signal at VGN1. Installed JP2 Grounds the IN1 pin via C2. User supplied JP3 Grounds the IN2 pin via C5. User supplied JP4 Connects trimmer GN2ADJ to Pin VGN2. This jumper can be removed for an ac signal at VGN2. Installed JP5 Connects trimmer VOCMADJ to the VOCM pin. This jumper can be removed for the half supply default VOCM. Installed JP6 Shifts the gain of Channel 2 up or down by 14 dB. Installed JP7 Shifts the gain of Channel 1 up or down by 14 dB. Installed JP8 Connects trimmer VREFADJ to the VREF pin to change the gain slope. Installed Rev. F | Page 18 of 24

AD605 CH1_GN +5V +5V VREF R1 R2 ADJ J1 DNI JP1 10kΩ R14 GN1 1CnF1 GADNJ1 JP8 C0.114µF 10kΩ VGA1_NEG C2 AD605 VREF 0.1µF INMJ21 R4 1 VGN1 VREF 16 OUT1 R13 0C.11µ3F INPJ13 69.8ΩVGA1_PJOPS2 0.C13µF 32 +–IINN11 OFBUKT11 1154 JCP172 C11RD1N2I 49.+95ΩV JO8UT1 R693.8Ω 4 GND1 VPOS 130.1µF0.1µF +5V +C8 C7 VGA2_POS C4 5 GND2 VPOS 12 1100µVF 0.1µF GND1 0.1µF INPJ24 R696.8ΩVGA2_NEG 0.C15µF 76 +–IINN22 OFBUKT22 1101JPV6OCM RD1N1I 4R9.190Ω 0C.11µ0F JO7UT2 INMJ52 8 VGN2 VOCM 9 OUT2 R695.8Ω JP3 JP5 +5VVAODJCM CH2_GN +5VR8 R9 J6 JP4 10kΩ C9 10kΩ GN2 GN2 0.1µF RD7NI 1CnF6 ADJ GND2GND3GND4 N1.O PTAERSTS IN GRAY ARE NOT INSTALLED. 00541-044 Figure 43. Schematic Diagram of the AD605-EVALZ Evaluation Board OSCILLOSCOPE POWER SUPPLY +5 V GND 5V FUNCTION GENERATOR SINGLE-ENDED VGA OUTPUT INPUT (TO SCOPE) 00541-045 Figure 44. Typical Test Configuration of the AD605-EVALZ Rev. F | Page 19 of 24

AD605 00541-046 00541-049 Figure 45. AD605-EVALZ Assembly Figure 48. AD605-EVALZ Internal Ground Plane 00541-047 00541-050 Figure 46. AD605-EVALZ Primary Side Copper Figure 49. AD605-EVALZ Internal Power Plane 00541-048 00541-051 Figure 47. AD605-EVALZ Secondary Side Copper Figure 50. AD605-EVALZ Primary Side Silkscreen Rev. F | Page 20 of 24

AD605 OUTLINE DIMENSIONS 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 16 9 0.280 (7.11) 0.250 (6.35) 1 8 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001-AB CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINOEFRPEANRREEREN NLCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 073106-B Figure 51. 16-Lead Plastic Dual In-Line Package [PDIP] (N-16) Dimensions shown in inches and (millimeters) 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 16 9 6.20 (0.2441) 3.80 (0.1496) 1 8 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 45° 1.75 (0.0689) 0.25 (0.0098) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AC C(RINOEFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 52. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches) Rev. F | Page 21 of 24

AD605 ORDERING GUIDE Model Temperature Range Package Description Package Option AD605AN −40°C to +85°C 16-Lead PDIP N-16 AD605ANZ1 −40°C to +85°C 16-Lead PDIP N-16 AD605AR −40°C to +85°C 16-Lead SOIC_N R-16 AD605AR-REEL −40°C to +85°C 16-Lead SOIC_N, 13" Tape and Reel R-16 AD605AR-REEL7 −40°C to +85°C 16-Lead SOIC_N, 7" Tape and Reel R-16 AD605ARZ1 −40°C to +85°C 16-Lead SOIC_N R-16 AD605ARZ-RL1 −40°C to +85°C 16-Lead SOIC_N, 13" Tape and Reel R-16 AD605ARZ-R71 −40°C to +85°C 16-Lead SOIC_N, 7" Tape and Reel R-16 AD605BN −40°C to +85°C 16-Lead PDIP N-16 AD605BR −40°C to +85°C 16-Lead SOIC_N R-16 AD605BR-REEL −40°C to +85°C 16-Lead SOIC_N, 13" Tape and Reel R-16 AD605BR-REEL7 −40°C to +85°C 16-Lead SOIC_N, 7" Tape and Reel R-16 AD605BRZ1 −40°C to +85°C 16-Lead SOIC_N R-16 AD605BRZ-RL1 −40°C to +85°C 16-Lead SOIC_N, 13" Tape and Reel R-16 AD605BRZ-R71 −40°C to +85°C 16-Lead SOIC_N, 7" Tape and Reel R-16 AD605-EVALZ1 Evaluation Board AD605ACHIPS DIE 1 Z = RoHS Compliant Part. Rev. F | Page 22 of 24

AD605 NOTES Rev. F | Page 23 of 24

AD605 NOTES ©1996–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00541-0-6/08(F) Rev. F | Page 24 of 24