a LVDT Signal Conditioner AD598 FEATURES FUNCTIONAL BLOCK DIAGRAM Single Chip Solution, Contains Internal Oscillator and Voltage Reference EXCITATION (CARRIER) No Adjustments Required Insensitive to Transducer Null Voltage 3 2 Insensitive to Primary to Secondary Phase Shifts VA DC Output Proportional to Position 11 OSC AMP 20 Hz to 20 kHz Frequency Range Single or Dual Supply Operation AD598 Unipolar or Bipolar Output 17 Will Operate a Remote LVDT at Up to 300 Feet A–B Position Output Can Drive Up to 1000 Feet of Cable A+B FILTER AMP 16 VOUT 10 Will Also Interface to an RVDT LVDT VB Outstanding Performance Linearity: 0.05% of FS max Output Voltage: (cid:54)11 V min Gain Drift: 50 ppm/(cid:56)C of FS max Offset Drift: 50 ppm/(cid:56)C of FS max PRODUCT HIGHLIGHTS PRODUCT DESCRIPTION 1. The AD598 offers a monolithic solution to LVDT and The AD598 is a complete, monolithic Linear Variable Differen- RVDT signal conditioning problems; few extra passive com- tial Transformer (LVDT) signal conditioning subsystem. It is ponents are required to complete the conversion from me- used in conjunction with LVDTs to convert transducer mechan- chanical position to dc voltage and no adjustments are ical position to a unipolar or bipolar dc voltage with a high required. degree of accuracy and repeatability. All circuit functions are 2. The AD598 can be used with many different types of included on the chip. With the addition of a few external passive LVDTs because the circuit accommodates a wide range of components to set frequency and gain, the AD598 converts the input and output voltages and frequencies; the AD598 can raw LVDT secondary output to a scaled dc signal. The device drive an LVDT primary with up to 24 V rms and accept sec- can also be used with RVDT transducers. ondary input levels as low as 100 mV rms. The AD598 contains a low distortion sine wave oscillator to 3. The 20 Hz to 20 kHz LVDT excitation frequency is deter- drive the LVDT primary. The LVDT secondary output consists mined by a single external capacitor. The AD598 input sig- of two sine waves that drive the AD598 directly. The AD598 nal need not be synchronous with the LVDT primary drive. operates upon the two signals, dividing their difference by their This means that an external primary excitation, such as the sum, producing a scaled unipolar or bipolar dc output. 400 Hz power mains in aircraft, can be used. The AD598 uses a unique ratiometric architecture (patent pend- 4. The AD598 uses a ratiometric decoding scheme such that ing) to eliminate several of the disadvantages associated with primary to secondary phase shifts and transducer null voltage traditional approaches to LVDT interfacing. The benefits of this have absolutely no effect on overall circuit performance. new circuit are: no adjustments are necessary, transformer null 5. Multiple LVDTs can be driven by a single AD598, either in voltage and primary to secondary phase shift does not affect sys- series or parallel as long as power dissipation limits are not tem accuracy, temperature stability is improved, and transducer exceeded. The excitation output is thermally protected. interchangeability is improved. 6. The AD598 may be used in telemetry applications or in hos- The AD598 is available in two performance grades: tile environments where the interface electronics may be re- mote from the LVDT. The AD598 can drive an LVDT at Grade Temperature Range Package the end of 300 feet of cable, since the circuit is not affected AD598JR 0(cid:176) C to +70(cid:176) C 20-Pin Small Outline (SOIC) by phase shifts or absolute signal magnitudes. The position AD598AD –40(cid:176) C to +85(cid:176) C 20-Pin Ceramic DIP output can drive as much as 1000 feet of cable. 7. The AD598 may be used as a loop integrator in the design of It is also available processed to MIL-STD-883B, for the military simple electromechanical servo loops. range of –55(cid:176) C to +125(cid:176) C. REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703

AD598–SPECIFICATIONS (typical @ +25(cid:56)C and (cid:54)15 V dc, C1 = 0.015 (cid:109)F, R2 = 80 k(cid:86), R = 2 k(cid:86), L unless otherwise noted. See Figure 7.) AD598J AD598A Parameter Min Typ Max Min Typ Max Unit (cid:86) (cid:177)(cid:86) (cid:86) = (cid:65) (cid:66) · (cid:53)(cid:48)(cid:48)m (cid:65)· (cid:82)(cid:50) TRANSFER FUNCTION1 (cid:79)(cid:85)(cid:84) (cid:86) +(cid:86) V (cid:65) (cid:66) OVERALL ERROR2 T to T 0.6 2.35 0.6 1.65 % of FS MIN MAX SIGNAL OUTPUT CHARACTERISTICS Output Voltage Range (T to T ) (cid:54)11 (cid:54)11 V MIN MAX Output Current (T to T ) 8 6 mA MIN MAX Short Circuit Current 20 20 mA Nonlinearity3 (T to T ) 75 (cid:54)500 75 (cid:54)500 ppm of FS MIN MAX Gain Error4 0.4 (cid:54)1 0.4 (cid:54)1 % of FS Gain Drift 20 (cid:54)100 20 (cid:54)50 ppm/(cid:176) C of FS Offset5 0.3 (cid:54)1 0.3 (cid:54)1 % of FS Offset Drift 7 (cid:54)200 7 (cid:54)50 ppm/(cid:176) C of FS Excitation Voltage Rejection6 100 100 ppm/dB Power Supply Rejection (– 12 V to – 18 V) PSRR Gain (T to T ) 300 100 400 100 ppm/V MIN MAX PSRR Offset (T to T ) 100 15 200 15 ppm/V MIN MAX Common-Mode Rejection (– 3 V) CMRR Gain (T to T ) 100 25 200 25 ppm/V MIN MAX CMRR Offset (T to T ) 100 6 200 6 ppm/V MIN MAX Output Ripple7 4 4 mV rms EXCITATION OUTPUT CHARACTERISTICS (@ 2.5 kHz) Excitation Voltage Range 2.1 24 2.1 24 V rms Excitation Voltage (R1 = Open)8 1.2 2.1 1.2 2.1 V rms (R1 = 12.7 kW )8 2.6 4.1 2.6 4.1 V rms (R1 = 487 W )8 14 20 14 20 V rms Excitation Voltage TC9 600 600 ppm/(cid:176) C Output Current 30 30 mA rms T to T 12 12 mA rms MIN MAX Short Circuit Current 60 60 mA DC Offset Voltage (Differential, R1 = 12.7 kW ) T to T 30 (cid:54)100 30 (cid:54)100 mV MIN MAX Frequency 20 20k 20 20k Hz Frequency TC, (R1 = 12.7 kW ) 200 200 ppm/(cid:176) C Total Harmonic Distortion –50 –50 dB SIGNAL INPUT CHARACTERISTICS Signal Voltage 0.1 3.5 0.1 3.5 V rms Input Impedance 200 200 kW Input Bias Current (AIN and BIN) 1 5 1 5 m A Signal Reference Bias Current 2 10 2 10 m A Excitation Frequency 0 20 0 20 kHz POWER SUPPLY REQUIREMENTS Operating Range 13 36 13 36 V Dual Supply Operation (– 10 V Output) – 13 – 13 V Single Supply Operation 0 to +10 V Output 17.5 17.5 V 0 to –10 V Output 17.5 17.5 V Current (No Load at Signal and Excitation Outputs) 12 15 12 15 mA T to T 16 18 mA MIN MAX TEMPERATURE RANGE JR (SOIC) 0 +70 (cid:176) C AD (DIP) –40 +85 (cid:176) C PACKAGE OPTION SOIC (R-20) AD598JR Side Brazed DIP (D-20) AD598AD –2– REV. A

AD598 NOTES 1V and V represent the Mean Average Deviation (MAD) of the detected sine waves. Note that for this Transfer Function to linearly represent positive displacement, A B the sum of V and V of the LVDT must remain constant with stroke length. See “Theory of Operation.” Also see Figures 7 and 12 for R2. A B 2From T , to T , the overall error due to the AD598 alone is determined by combining gain error, gain drift and offset drift. For example the worst case overall MIN MAX error for the AD598AD from T to T is calculated as follows: overall error = gain error at +25(cid:176)C (– 1% full scale) + gain drift from –40(cid:176)C to +25(cid:176)C (50 ppm/(cid:176)C MIN MAX of FS · +65(cid:176)C) + offset drift from –40(cid:176)C to +25(cid:176)C (50 ppm/(cid:176)C of FS · +65(cid:176)C) = – 1.65% of full scale. Note that 1000 ppm of full scale equals 0.1% of full scale. Full scale is defined as the voltage difference between the maximum positive and maximum negative output. 3Nonlinearity of the AD598 only, in units of ppm of full scale. Nonlinearity is defined as the maximum measured deviation of the AD598 output voltage from a straight line. The straight line is determined by connecting the maximum produced full-scale negative voltage with the maximum produced full-scale positive voltage. 4See Transfer Function. 5This offset refers to the (V –V )/(V +V ) input spanning a full-scale range of – 1. [For (V –V )/(V +V ) to equal +1, V must equal zero volts; and correspondingly A B A B A B A B B for (V –V )/(V +V ) to equal –1, V must equal zero volts. Note that offset errors do not allow accurate use of zero magnitude inputs, practical inputs are limited to A B A B A 100 mV rms.] The – 1 span is a convenient reference point to define offset referred to input. For example, with this input span a value of R2 = 20 kW would give V span a value of – 10 volts. Caution, most LVDTs will typically exercise less of the ((V –V ))/((V +V )) input span and thus require a larger value of R2 to OUT A B A B produce the – 10 V output span. In this case the offset is correspondingly magnified when referred to the output voltage. For example, a Schaevitz E100 LVDT requires 80.2 kW for R2 to produce a – 10.69 V output and (V –V )/(V +V ) equals 0.27. This ratio may be determined from the graph shown in Figure 18, A B A B (V –V )/(V +V ) = (1.71 V rms – 0.99 V rms)/(1.71 V rms + 0.99 V rms). The maximum offset value referred to the – 10.69 V output may be determined by A B A B multiplying the maximum value shown in the data sheet (– 1% of FS by 1/0.27 which equals – 3.7% maximum. Similarly, to determine the maximum values of offset drift, offset CMRR and offset PSRR when referred to the – 10.69 V output, these data sheet values should also be multiplied by (1/0.27). For this example for the AD598AD the maximum values of offset drift, PSRR offset and CMRR offset would be: 185 ppm/(cid:176)C of FS; 741 ppm/V and 741 ppm/V respectively when referred to the – 10.69 V output. 6For example, if the excitation to the primary changes by 1 dB, the gain of the system will change by typically 100 ppm. 7Output ripple is a function of the AD598 bandwidth determined by C2, C3 and C4. See Figures 16 and 17. 8R1 is shown in Figures 7 and 12. 9Excitation voltage drift is not an important specification because of the ratiometric operation of the AD598. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tested are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. THERMAL CHARACTERISTICS ORDERING GUIDE q q JC JA Temperature Package Package SOIC Package 22(cid:176) C/W 80(cid:176) C/W Model Range Description Option Side Brazed Package 25(cid:176) C/W 85(cid:176) C/W AD598JR 0(cid:176) C to +70(cid:176) C SOIC R-20 AD598AD –40(cid:176) C to +85C Ceramic DIP D-20 ABSOLUTE MAXIMUM RATINGS Total SupplyVoltage +V to –V . . . . . . . . . . . . . . . . . +36V S S Storage Temperature Range –VS 1 20 +VS R Package . . . . . . . . . . . . . . . . . . . . . . . . .–65(cid:176) C to +150(cid:176) C EXC 1 2 19 OFFSET 1 D Package . . . . . . . . . . . . . . . . . . . . . . . . .–65(cid:176) C to +150(cid:176) C Operating Temperature Range EXC 2 3 18 OFFSET 2 AD598JR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0(cid:176) C to +70(cid:176) C LEVEL 1 4 17 SIGNAL REFERENCE AD598AD . . . . . . . . . . . . . . . . . . . . . . . . . .–40(cid:176) C to +85(cid:176) C AD598 LEVEL 2 5 16 SIGNAL OUTPUT Lead Temperature Range (Soldering60sec) . . . . . . . . +300(cid:176) C TOP VIEW Power Dissipation Up to +65(cid:176) C . . . . . . . . . . . . . . . . . . .1.2 W FREQ 1 6 (Not to Scale) 15 FEEDBACK Derates Above +65(cid:176) C . . . . . . . . . . . . . . . . . . . . . . . 12 mW/(cid:176) C FREQ 2 7 14 OUTPUT FILTER B1 FILTER 8 13 A1 FILTER B2 FILTER 9 12 A2 FILTER VB 10 11 VA REV. A –3–

AD598–Typical Characteristics (at +25(cid:56)C and V = (cid:54)15 V, unless otherwise noted) S 40 120 OFFSET PSRR 12–15V 0 80 olt OFFSET PSRR 15–18V RR – ppm/V ––8400 GAIN PSRR 12–15V (cid:176)FT – ppm/C 2400 ET PS –120 GAIN PSRR 15–18V N DRI 0 S AI OFF –160 L G –20 AND PICA N –200 TY –40 AI G –240 –60 –80 –60 –20 0 20 60 100 140 –60 –20 0 20 60 100 140 TEMPERATURE – (cid:176)C TEMPERATURE – (cid:176)C Figure 1.Gain and Offset PSRR vs. Temperature Figure 2.Typical Gain Drift vs. Temperature 5 20 0 Volt OFFSET CMRR – 3V C m/ –5 (cid:176)m/ 10 R – pp –10 T – pp R F M RI C D ET –15 ET 0 S S OFF –20 OFF D L AN GAIN CMRR – 3V CA N –25 PI –10 GAI TY –30 –35 –20 –60 –20 0 20 60 100 140 –60 –20 0 20 60 100 140 TEMPERATURE – (cid:176)C TEMPERATURE – (cid:176)C Figure 3.Gain and Offset CMRR vs. Temperature Figure 4.Typical Offset Drift vs. Temperature THEORY OF OPERATION an external sine wave reference source, two secondary windings A block diagram of the AD598 along with an LVDT (Linear connected in series, and the moveable core to couple flux be- Variable Differential Transformer) connected to its input is tween the primary and secondary windings. shown in Figure 5. The LVDT is an electromechanical trans- The AD598 energizes the LVDT primary, senses the LVDT ducer whose input is the mechanical displacement of a core and secondary output voltages and produces a dc output voltage whose output is a pair of ac voltages proportional to core posi- proportional to core position. The AD598 consists of a sine tion. The transducer consists of a primary winding energized by wave oscillator and power amplifier to drive the primary, a de- coder which determines the ratio of the difference between the EXCITATION (CARRIER) LVDT secondary voltages divided by their sum, a filter and an output amplifier. 3 2 VA The oscillator comprises a multivibrator which produces a 11 triwave output. The triwave drives a sine shaper, which pro- OSC AMP duces a low distortion sine wave whose frequency is determined by a single capacitor. Output frequency can range from 20 Hz to AD598 17 20 kHz and amplitude from 2 V rms to 24 V rms. Total har- monic distortion is typically –50 dB. A–B 10 A+B FILTER AMP 16 VOUT The output from the LVDT secondaries consists of a pair of LVDT VB sine waves whose amplitude difference, (V –V ), is proportional A B to core position. Previous LVDT conditioners synchronously Figure 5.AD598 Functional Block Diagram detect this amplitude difference and convert its absolute value to –4– REV. A

AD598 a voltage proportional to position. This technique uses the pri- As shown in Figure 6, the input to the integrator is [(A+B)d]B. mary excitation voltage as a phase reference to determine the Since the integrator input is forced to 0, the duty cycle d = polarity of the output voltage. There are a number of problems B/(A+B). associated with this technique such as (1) producing a constant The output comparator which produces d = B/(A+B) also con- amplitude, constant frequency excitation signal, (2) compensating trols an output amplifier driven by a reference current. Duty for LVDT primary to secondary phase shifts, and (3) compen- cycle signals d and (1–d) perform separate modulations on the sating for these shifts as a function of temperature and frequency. reference current as shown in Figure 6, which are summed. The The AD598 eliminates all of these problems. The AD598 does summed current, which is the output current, is I · (1–2d). REF not require a constant amplitude because it works on the ratio of Since d = B/(A+B), by substitution the output current equals the difference and sum of the LVDT output signals. A constant I · (A–B)/(A+B). This output current is then filtered and frequency signal is not necessary because the inputs are rectified REF converted to a voltage since it is forced to flow through the scal- and only the sine wave carrier magnitude is processed. There is ing resistor R2 such that: no sensitivity to phase shift between the primary excitation and the LVDT outputs because synchronous detection is not em- (cid:86) =(cid:73) · (cid:40)(cid:65)(cid:177)(cid:66)(cid:41)(cid:47)(cid:40)(cid:65)+(cid:66)(cid:41)· (cid:82)(cid:50) (cid:79)(cid:85)(cid:84) (cid:82)(cid:69)(cid:70) ployed. The ratiometric principle upon which the AD598 oper- ates requires that the sum of the LVDT secondary voltages CONNECTING THE AD598 remains constant with LVDT stroke length. Although LVDT The AD598 can easily be connected for dual or single supply manufacturers generally do not specify the relationship between operation as shown in Figures 7 and 12. The following general VA+VB and stroke length, it is recognized that some LVDTs do design procedures demonstrate how external component values not meet this requirement. In these cases a nonlinearity will are selected and can be used for any LVDT which meets AD598 result. However, the majority of available LVDTs do in fact input/output criteria. meet these requirements. Parameters which are set with external passive components in- The AD598 utilizes a special decoder circuit. Referring to the clude: excitation frequency and amplitude, AD598 system block diagram and Figure 6 below, an implicit analog comput- bandwidth, and the scale factor (V/inch). Additionally, there are ing loop is employed. After rectification, the A and B signals are optional features, offset null adjustment, filtering, and signal in- multiplied by complementary duty cycle signals, d and (I–d) tegration which can be used by adding external components. respectively. The difference of these processed signals is inte- grated and sampled by a comparator. It is the output of this comparator that defines the original duty cycle, d, which is fed back to the multipliers. V TO I INPUT A FILT d BINARY SIGNAL d - DUTY CYCLE COMP 0<d<1 – 1 (cid:229) INTEG COMP V TO I (A+B) d–B INPUT B FILT 1–d B COMP – 1 dlA+B VOLTS I 1–d IREFlAA–+BB OUTPUT REF BANDGAP REFERENCE d (cid:229) FILT (cid:229) INTEG V TO I RTO OFFSET A–B V = R x I x OUT SCALE REF A+B Figure 6.Block Diagram of Decoder REV. A –5–

AD598 DESIGN PROCEDURE The AD598 signal input, V , should be in the range of SEC DUAL SUPPLY OPERATION 1 V rms to 3.5 V rms for maximum AD598 linearity and Figure 7 shows the connection method with dual – 15 volt power minimum noise susceptibility. Select V = 3 V rms. There- SEC supplies and a Schaevitz E100 LVDT. This design procedure fore, LVDT excitation voltage V should be: EXC can be used to select component values for other LVDTs as V = V · VTR = 3 · 1.75 = 5.25 V rms well. The procedure is outlined in Steps 1 through 10 as follows: EXC SEC Check the power supply voltages by verifying that the peak 1. Determine the mechanical bandwidth required for LVDT values of V and V are at least 2.5 volts less than the volt- position measurement subsystem, f . For this A B SUBSYSTEM ages at +V and –V . example, assume f = 250 Hz. S S SUBSYSTEM 6. Referring to Figure 7, for V = – 15 V, select the value of the 2. Select minimum LVDT excitation frequency, approximately S amplitude determining component R1 as shown by the curve 10 · f . Therefore, let excitation frequency = 2.5 kHz. SUBSYSTEM in Figure 8. 3. Select a suitable LVDT that will operate with an excitation 7. Select excitation frequency determining component C1. frequency of 2.5 kHz. The Schaevitz E100, for instance, will operate over a range of 50 Hz to 10 kHz and is an eligible C1 = 35 mF Hz/fEXCITATION candidate for this example. 30 4. Determine the sum of LVDT secondary voltages V and V . A B Energize the LVDT at its typical drive level V as shown in PRI the manufacturer’s data sheet (3 V rms for the E100). Set the core displacement to its center position where V = V . Mea- A B sure these values and compute their sum V +V . For the 20 A B E100, V +V = 2.70 V rms. This calculation will be used later in dAeterBmining AD598 output voltage. Vrms 5. Determine optimum LVDT excitation voltage, V . With –XC Vrms EXC VE the LVDT energized at its typical drive level V , set the PRI core displacement to its mechanical full-scale position and 10 measure the output V of whichever secondary produces SEC the largest signal. Compute LVDT voltage transformation ratio, VTR. VTR = V /V PRI SEC 0 For the E100, VSEC = 1.71 V rms for VPRI = 3 V rms. 0.01 0.1 1 10 100 1000 VTR = 1.75. R1 – kW Figure 8.Excitation Voltage V vs. R1 EXC +15V 6.8m F 0.1m F 6.8m F 0.1m F –15V 1 –VS +VS 20 R4 2 EXC 1 OFFSET 1 19 3 EXC 2 OFFSET 2 18 SIGNAL R3 REFERENCE 4 LEV 1 SIG REF 17 R1 RL 5 LEV 2 SIG OUT 16 R2 VOUT 6 FREQ 1 FEEDBACK 15 C1 C4 7 FREQ 2 OUT FILT 14 8 B1 FILT A1 FILT 13 C2 C3 9 B2 FILT A2 FILT 12 10 V AD598 V 11 V B A B NOTE FOR C1, C2, C3 AND C4 MYLAR CAPACITORS ARE RECOMMENDED. CERAMIC CAPACITORS MAY BE SUBSTITUTED. FOR R2, R3 AND R4 USE STANDARD 1% V A RESISTORS. SCHAEVITZ E100 LVDT Figure 7.Interconnection Diagram for Dual Supply Operation –6– REV. A

AD598 8. C2, C3 and C4 are a function of the desired bandwidth of For no offset adjustment R3 and R4 should be open circuit. the AD598 position measurement subsystem. They should To design a circuit producing a 0 V to +10 V output for a be nominally equal values. displacement of – 0.1 inch, set V to +10 V, d = 0.2 inch OUT C2 = C3 = C4 = 10–4 Farad Hz/f (Hz) and solve Equation (1) for R2. SUBSYSTEM If the desired system bandwidth is 250 Hz, then R2 = 37.6 kW C2 = C3 = C4 = 10–4 Farad Hz/250 Hz = 0.4 mF This will produce a response shown in Figure 10. See Figures 13, 14 and 15 for more information about V (VOLTS) OUT AD598 bandwidth and phase characterization. +5 9. In order to Compute R2, which sets the AD598 gain or full- scale output range, several pieces of information are needed: –0.1 +0.1d(INCHES) a. LVDT sensitivity, S –5 b.Full-scale core displacement, d c.Ratio of manufacturer recommended primary drive level, Figure 10. V (– 5 V Full Scale) OUT V to (V + V ) computed in Step 4. vs. Core Displacement (– 0.1 Inch) PRI A B LVDT sensitivity is listed in the LVDT manufacturer’s cata- In Equation (2) set V = 5 V and solve for R3 and R4. OS log and has units of millivolts output per volts input per inch Since a positive offset is desired, let R4 be open circuit. displacement. The E100 has a sensitivity of 2.4 mV/V/mil. Rearranging Equation (2) and solving for R3 In the event that LVDT sensitivity is not given by the manu- facturer, it can be computed. See section on Determining (cid:49)(cid:46)(cid:50)· (cid:82)(cid:50) (cid:82)(cid:51)= (cid:177)(cid:53)(cid:107)W= (cid:52)(cid:46)(cid:48)(cid:50)(cid:107)W LVDT Sensitivity. (cid:86) (cid:79)(cid:83) For a full-scale displacement of d inches, voltage out of the Figure 11 shows the desired response. AD598 is computed as V (VOLTS) OUT Ø (cid:86) ø (cid:86)(cid:79)(cid:85)(cid:84) =(cid:83)· ºŒ (cid:40)(cid:86) (cid:80)+(cid:82)(cid:86)(cid:73) (cid:41)ßœ · (cid:53)(cid:48)(cid:48)m (cid:65)· (cid:82)(cid:50)· (cid:100)(cid:46) +10 (cid:65) (cid:66) +5 V is measured with respect to the signal reference, –0.1 +0.1d(INCHES) OUT Pin 17 shown in Figure 7. Solving for R2, (cid:86) · (cid:40)(cid:86) +(cid:86) (cid:41) Figure 11. V (0 V–10 V Full Scale) (cid:82)(cid:50)= (cid:83)· (cid:79)(cid:86)(cid:85)(cid:84) · (cid:53)(cid:65)(cid:48)(cid:48)m (cid:65)(cid:66)· (cid:100) (1) vs. DisplacemOUeTnt (– 0.1 Inch) (cid:80)(cid:82)(cid:73) Note that VPRI is the same signal level used in Step 4 to DESIGN PROCEDURE determine (VA + VB). SINGLE SUPPLY OPERATION For V = 20 V full-scale range (– 10 V) and d = 0.2 inch Figure 12 shows the single supply connection method. OUT full-scale displacement (– 0.1 inch), For single supply operation, repeat Steps 1 through 10 of the design procedure for dual supply operation, then complete the (cid:50)(cid:48)(cid:86) · (cid:50)(cid:46)(cid:55)(cid:48)(cid:86) (cid:82)(cid:50)= =(cid:55)(cid:53)(cid:46)(cid:51)(cid:107)W additional Steps 11 through 14 below. R5, R6 and C5 are addi- (cid:50)(cid:46)(cid:52)· (cid:51)· (cid:53)(cid:48)(cid:48)m (cid:65)· (cid:48)(cid:46)(cid:50) tional component values to be determined. V is measured OUT V as a function of displacement for the above example is with respect to SIGNAL REFERENCE. OUT shown in Figure 9. 11.Compute a maximum value of R5 and R6 based upon the relationship V (VOLTS) OUT +10 R5 + R6 £ VPS/100 m A 12.The voltage drop across R5 must be greater than –0.1 +0.1 d(INCHES) (cid:230) (cid:49)(cid:46)(cid:50)(cid:86) (cid:86) (cid:246) (cid:50)+(cid:49)(cid:48)(cid:107)W (cid:42)(cid:231) +(cid:50)(cid:53)(cid:48)m (cid:65)+ (cid:79)(cid:85)(cid:84) (cid:247) (cid:86)(cid:111)(cid:108)(cid:116)(cid:115) –10 Ł (cid:82)(cid:52)+(cid:53)(cid:107)W (cid:52)· (cid:82)(cid:50)ł Figure 9. V (– 10 V Full Scale) Therefore OUT vs. Core Displacement (– 0.1 Inch) (cid:230) (cid:49)(cid:46)(cid:50)(cid:86) (cid:86) (cid:246) 10.Selections of R3 and R4 permit a positive or negative output (cid:50)+(cid:49)(cid:48)(cid:107)W (cid:42)(cid:231) +(cid:50)(cid:53)(cid:48)m (cid:65)+ (cid:79)(cid:85)(cid:84)(cid:247) Ł (cid:82)(cid:52)+(cid:53)(cid:107)W (cid:52)· (cid:82)(cid:50)ł voltage offset adjustment. (cid:82)(cid:53)‡ (cid:79)(cid:104)(cid:109)(cid:115) (cid:49)(cid:48)(cid:48)m (cid:65) (cid:230) (cid:49) (cid:49) (cid:246) (cid:86)(cid:79)(cid:83) =(cid:49)(cid:46)(cid:50)(cid:86) · (cid:82)(cid:50)· Ł(cid:231) (cid:82)(cid:51)+(cid:53)(cid:107)W (cid:42) (cid:177) (cid:82)(cid:52)+(cid:53)(cid:107)W (cid:42) ł(cid:247) (2) *These values have – 20% tolerance. Based upon the constraints of R5 + R6 (Step 11) and R5 *These values have a – 20% tolerance. (Step 12), select an interim value of R6. REV. A –7–

AD598 13.Load current through R returns to the junction of R5 and equal in value. Note also a shunt capacitor across R2 shown as a L R6, and flows back to V . Under maximum load condi- parameter (see Figure 7). The value of R2 used was 81 kW with PS tions, make sure the voltage drop across R5 is met as a Schaevitz E100 LVDT. defined in Step 12. As a final check on the power supply voltages, verify that the peak values of V and V are at least 2.5 volts less than the A B voltages at +V and –V . S S 14. C5 is a bypass capacitor in the range of 0.1 m F to 1 m F. +30V R5 Vps 6.8m F 0.1m F C5 R6 1 –VS +VS 20 R4 2 EXC 1 OFFSET 119 3 EXC 2 OFFSET 2 18 SIGNAL R3 REFERENCE 4 LEV 1 SIG REF 17 R1 RL 5 LEV 2 SIG OUT 16 C1 6 FREQ 1 FEEDBACK 15 R332k VOUT 15nF 7 FREQ 2 OUT FILT 14 C4 8 B1 FILT A1 FILT 13 C2 C3 9 B2 FILT A2 FILT 12 VB 10 VB AD598 VA 11 VA SCHAEVITZ E100 LVDT Figure 13.Gain and Phase Characteristics vs. Frequency Figure 12.Interconnection Diagram for Single (0 kHz–10 kHz) Supply Operation Gain Phase Characteristics To use an LVDT in a closed loop mechanical servo application, it is necessary to know the dynamic characteristics of the trans- ducer and interface elements. The transducer itself is very quick to respond once the core is moved. The dynamics arise prima- rily from the interface electronics. Figures 13, 14 and 15 show the frequency response of the AD598 LVDT Signal Condi- tioner. Note that Figures 14 and 15 are basically the same; the difference is frequency range covered. Figure 14 shows a wider range of mechanical input frequencies at the expense of accu- racy. Figure 15 shows a more limited frequency range with en- hanced accuracy. The figures are transfer functions with the input to be considered as a sinusoidally varying mechanical posi- tion and the output as the voltage from the AD598; the units of the transfer function are volts per inch. The value of C2, C3 and C4, from Figure 7, are all equal and designated as a parameter in the figures. The response is approximately that of two real poles. However, there is appreciable excess phase at higher fre- quencies. An additional pole of filtering can be introduced with a shunt capacitor across R2, (see Figure 7); this will also in- crease phase lag. When selecting values of C2, C3 and C4 to set the bandwidth of the system, a trade-off is involved. There is ripple on the “dc” position output voltage, and the magnitude is determined by the filter capacitors. Generally, smaller capacitors will give higher system bandwidth and larger ripple. Figures 16 and 17 show the Figure 14.Gain and Phase Characteristics vs. Frequency magnitude of ripple as a function of C2, C3 and C4, again all (0 kHz–50 kHz) –8– REV. A

AD598 1000 100 s m V r m – 10 E L P RIP 10kHz , CSHUNT= 0nF 1 10kHz , CSHUNT= 1nF 10kHz , CSHUNT= 10nF 0.1 0.001 0.01 0.1 1 10 C2, C3, C4; C2 = C3 = C4 – m F Figure 17. Output Voltage Ripple vs. Filter Capacitance Determining LVDT Sensitivity LVDT sensitivity can be determined by measuring the LVDT secondary voltages as a function of primary drive and core posi- tion, and performing a simple computation. Energize the LVDT at its recommended primary drive level, V (3 V rms for the E100). Set the core to midpoint where PRI V = V . Set the core displacement to its mechanical full-scale A B Figure 15.Gain and Phase Characteristics vs. Frequency position and measure secondary voltages V and V . A B (0 kHz–10 kHz) (cid:86) (cid:40)(cid:97)(cid:116) (cid:70)(cid:117)(cid:108)(cid:108) (cid:83)(cid:99)(cid:97)(cid:108)(cid:101)(cid:41)(cid:177)(cid:86) (cid:40)(cid:97)(cid:116) (cid:70)(cid:117)(cid:108)(cid:108) (cid:83)(cid:99)(cid:97)(cid:108)(cid:101)(cid:41) 1000 (cid:83)(cid:101)(cid:110)(cid:115)(cid:105)(cid:116)(cid:105)(cid:118)(cid:105)(cid:116)(cid:121) = (cid:65) (cid:66) (cid:86) · (cid:100) (cid:80)(cid:82)(cid:73) From Figure 18, (cid:49)(cid:46)(cid:55)(cid:49)(cid:177)(cid:48)(cid:46)(cid:57)(cid:57) 100 (cid:83)(cid:101)(cid:110)(cid:115)(cid:105)(cid:116)(cid:105)(cid:118)(cid:105)(cid:116)(cid:121) = (cid:51)· (cid:49)(cid:48)(cid:48)(cid:109)(cid:105)(cid:108)(cid:115) =(cid:50)(cid:46)(cid:52)(cid:109)(cid:86)(cid:47)(cid:86)(cid:47)(cid:109)(cid:105)(cid:108) ms VSECWHENVPRI= 3V rms V r VA m – 10 1.71V rms E L P P RI 2.5kHz, C = 0nF SHUNT 1 0.99V rms V 2.5kHz, C = 1nF B SHUNT 2.5kHz, C =10nF d = –100 mils d = 0 d =+100 mils SHUNT 0.1 0.01 0.1 1 10 Figure 18. LVDT Secondary Voltage vs. Core Displacement C2, C3, C4; C2 = C3 = C4 – m F Thermal Shutdown and Loading Considerations The AD598 is protected by a thermal overload circuit. If the die Figure 16.Output Voltage Ripple vs. Filter Capacitance temperature reaches 165(cid:176) C, the sine wave excitation amplitude gradually reduces, thereby lowering the internal power dissipa- tion and temperature. Due to the ratiometric operation of the decoder circuit, only small errors result from the reduction of the excitation ampli- tude. Under these conditions the signal-processing section of the AD598 continues to meet its output specifications. The thermal load depends upon the voltage and current deliv- ered to the load as well as the power supply potentials. An LVDT Primary will present an inductive load to the sine wave excitation. The phase angle between the excitation voltage and current must also be considered, further complicating thermal calculations. REV. A –9–

AD598–Applications PROVING RING-WEIGH SCALE The value of R3 or R4 can be calculated using one of two sepa- Figure 20 shows an elastic member (steel proving ring) com- rate methods. First, a potentiometer may be connected between bined with an LVDT to provide a means of measuring very Pins 18 and 19 of the AD598, with the wiper connected to small loads. Figure 19 shows the electrical circuit details. –V . This gives a small offset of either polarity; and the SUPPLY value can be calculated using Step 10 of the design procedures. The advantage of using a Proving Ring in combination with an For a large offset in one direction, replace either R3 or R4 with LVDT is that no friction is involved between the core and the a potentiometer with its wiper connected to –V . coils of the LVDT. This means that weights can be measured SUPPLY without confusion from frictional forces. This is especially im- The resolution of this weigh-scale was checked by placing a 100 portant for very low full-scale weight applications. gram weight on the scale and observing the AD598 output sig- nal deflection on an oscilloscope. The deflection was 4.8 mV. +15V The smallest signal deflection which could be measured on the 6.8mF 0.1mF oscilloscope was 450 m V which corresponds to a 10 gram 6.8mF 0.1mF weight. This 450 m V signal corresponds to an LVDT displace- ment of 1.32 microinches which is equivalent to one tenth of the –15V 1 –VS +VS 20 wave length of blue light. 2 EXC 1 OFFSET 119 3 EXC 2 OFFSET 2 18 SIGNAL The Proving Ring used in this circuit has a temperature coeffi- 4 LEV 1 SIG REF 17 REFERENCE cient of 250 ppm/(cid:176) C due to Young’s Modulus of steel. By put- 5 LEV 2 SIG OUT 16 RL ting a resistor with a temperature coefficient in place of R2 it is C1 6 FREQ 1 FEEDBACK 15 1mF VOUT possible to temperature compensate the weigh-scale. Since the 0.015mF 7 FREQ 2 OUT FILT 14 C4 634k 10k steel of the Proving Ring gets softer at higher temperatures, the 0.33mF C2 8 B1 FILT A1 FILT 13 C3 deflection for a given force is larger, so a resistor with a negative 0.1mF 9 B2 FILT A2 FILT 12 0.1mF temperature coefficient is required. VB 10 VB AD598 VA 11 SYNCHRONOUS OPERATION OF MULTIPLE LVDTS In many applications, such as multiple gaging measurement, a large number of LVDTs are used in close physical proximity. If VA these LVDTs are operated at similar carrier frequencies, stray SCHAEVITZ HR050 LVDT magnetic coupling could cause beat notes to be generated. The resulting beat notes would interfere with the accuracy of mea- Figure 19.Proving Ring-Weigh Scale Circuit surements made under these conditions. To avoid this situation all the LVDTs are operated synchronously. FORCE/LOAD The circuit shown in Figure 21 has one master oscillator and any number of slaves. The master AD598 oscillator has its fre- quency and amplitude programmed in the usual manner via R1 PROVING and C2 using Steps 6 and 7 in the design procedures. The slave RING AD598s all have Pins 6 and 7 connected together to disable their internal oscillators. Pins 4 and 5 of each slave are con- CORE LVDT nected to Pins 2 and 3 of the master via 15 kW resistors, thus setting the amplitudes of the slaves equal to the amplitude of the master. If a different amplitude is required the 15 kW resistor values should be changed. Note that the amplitude scales lin- early with the resistor value. The 15 kW value was selected be- cause it matches the nominal value of resistors internal to the Figure 20.Proving Ring-Weigh Scale Cross Section circuit. Tolerances of 20% between the slave amplitudes arise Although it is recognized that this type of measurement system due to differing internal resistors values, but this does not affect may best be applied to weigh very small weights, this circuit was the operation of the circuit. designed to give a full-scale output of 10 V for a 500 lb weight, Note that each LVDT primary is driven from its own power am- using a Morehouse Instruments model 5BT Proving Ring. The plifier and thus the thermal load is shared between the AD598s. LVDT is a Schaevitz type HR050 (– 50 mil full scale). Although There is virtually no limit on the number of slaves in this circuit, this LVDT provides – 50 mil full scale, the value of R2 was cal- since each slave presents a 30 kW load to the master AD598 culated for d = – 30 mil and VOUT equal to 10 V as in Step 9 of power amplifier. For a very large number of slaves (say 100 or the design procedures. more) one may need to consider the maximum output current The 1 m F capacitor provides extra filtering, which reduces noise drawn from the master AD598 power amplifier. induced by mechanical vibrations. The other circuit values were calculated in the usual manner using the design procedures. This weigh-scale can be designed to measure tare weight simply by putting in an offset voltage by selecting either R3 or R4 (as shown in Figures 7 and 12). Tare weight is the weight of a con- tainer that is deducted from the gross weight to obtain the net weight. –10– REV. A

AD598 –V MASTER +V –V SLAVE 1 +V –V SLAVE 2 +V 15k 15k 15k 15k 1 –VS +VS 20 1 –VS +VS 20 1 –VS +VS 20 2 EXC 1 OFFSET 119 2 EXC 1 OFFSET 119 2 EXC 1 OFFSET 119 3 EXC 2 OFFSET 2 18 3 EXC 2 OFFSET 2 18 3 EXC 2 OFFSET 2 18 4 LEV 1 SIG REF 17 4 LEV 1 SIG REF 17 4 LEV 1 SIG REF 17 82.5kW 82.5kW 82.5kW 0.015m F 5 LEV 2 SIG OUT 16 5 LEV 2 SIG OUT 16 5 LEV 2 SIG OUT 16 6 FREQ 1 FEEDBACK 15 6 FREQ 1 FEEDBACK 15 6 FREQ 1 FEEDBACK 15 7 FREQ 2 OUT FILT 14 0.33m F 7 FREQ 2 OUT FILT 14 0.33m F 7 FREQ 2 OUT FILT 14 0.33m F 8 B1 FILT A1 FILT 13 0.1m F 8 B1 FILT A1 FILT 13 0.1m F 8 B1 FILT A1 FILT 13 0.1m F 0.1m F 0.1m F 9 B2 FILT A2 FILT 12 9 B2 FILT A2 FILT 12 9 B2 FILT A2 FILT 12 0.1m F 10 VB AD598 VA 11 10 VB AD598 VA 11 10 VB AD598 VA 11 SCHAEVITZ E 100 LVDT SCHAEVITZ E 100 LVDT SCHAEVITZ E 100 LVDT MECHANICAL POSITION INPUT MECHANICAL POSITION INPUT MECHANICAL POSITION INPUT Figure 21.Multiple LVDTs—Synchronous Operation HIGH RESOLUTION POSITION-TO-FREQUENCY such circuits. The analog input signal to the AD652 is converted CIRCUIT to digital frequency output pulses which can be counted by In the circuit shown in Figure 22, the AD598 is combined with simple digital means. an AD652 voltage-to-frequency (V/F) converter to produce an This circuit is particularly useful if there is a large degree of effective, simple data converter which can make high resolution mechanical vibration (hum) on the position to be measured. measurements. The hum may be completely rejected by counting the digital fre- This circuit transfers the signal from the LVDT to the V/F con- quency pulses over a gate time (fixed period) equal to a multiple verter in the form of a current, thus eliminating the errors nor- of the hum period. For the effects of the hum to be completely mally caused by the offset voltage of the V/F converter. The V/F rejected, the hum must be a periodic signal. converter offset voltage is normally the largest source of error in –Vs +Vs GND 0.1m F 0.1m F 1 +VS AD652 COMP REF 16 1 –VS +VS 20 SYNCHRONOUS 2 TRIM COMP“+” 15 2 EXC 1 OFFSET 119 VOLTAGE TO FREQUENCY 3 EXC 2 OFFSET 2 18 3 TRIM CONVERTER COMP“–” 14 4 LEV 1 SIG REF 17 4 OP AMP OUT ANALOG GND 13 5 LEV 2 SIG OUT 16 0.02m F 0.015m F 5 OP AMP “–” DIGITAL GND 12 6 FREQ 1 FEEDBACK 15 2.5k 7 FREQ 2 OUT FILT 14 0.33m F 6 OP AMP “+” FREQ OUT 11 +VS 8 B1 FILT A1 FILT 13 FREQ 0.1m F 7 10 VOLT INPUT CLOCK INPUT 10 OUT 9 B2 FILT A2 FILT 12 500KHZ CK 0.1m F 10 VB AD598 VA 11 8 –VS COS 9 +VS LVDT SCHAEVITZ E 100 MECHANICAL POSITION INPUT Figure 22.High Resolution Position-to-Frequency Converter REV. A –11–

AD598 The V/F converter is currently set up for unipolar operation. signal is summed with the signal from the output position The AD652 data sheet explains how to set up for bipolar opera- LVDT; this summed signal is integrated such that the output tion. Note that when the LVDT core is centered, the output fre- position is now equal to the input position. This circuit is an quency is zero. When the LVDT core is positioned off center, efficient means of implementing a mechanical servo-loop since and to one side, the frequency increases to a full-scale value. only three ICs are required. To introduce bipolar operation to this circuit, an offset must be This circuit is similar to the previous circuit (Figure 23) with introduced at the LVDT as shown in Step 10 of the design one exception: the previous circuit uses a potentiometer instead procedures. of an LVDT to provide the input position signal. Replacing the potentiometer with an LVDT offers two advantages. First, the LOW COST SET-POINT CONTROLLER increased reliability and robustness of the LVDT can be ex- A low cost set-point controller can be implemented with the cir- ploited in applications where the position input sensor is located cuit shown in Figure 23. Such a circuit could possibly be used in a hostile environment. Second, the mechanical motions of the in automobile fuel control systems. The potentiometer, P1, is input and output LVDTs are guaranteed to be identical to attached to the gas pedal, and the LVDT is attached to the but- within the matching of their individual scale factors. These terfly valve of the fuel injection system or carburetor. The posi- particular advantages make this circuit ideal for application as a tion of the butterfly valve is electronically controlled by the hydraulic actuator controller. position of the gas pedal, without mechanical linkage. This circuit is a simple two IC closed loop servo-controller. It is DIFFERENTIAL GAGING simple because the LVDT circuit is functioning as the loop inte- LVDTs are commonly used in gaging systems. Two LVDTs grator. By putting a capacitor in the feedback path (normally oc- can be used to measure the thickness or taper of an object. To cupied by R2), the output signal from the AD598 corresponds measure thickness, the LVDTs are placed on either side of the to the time integral of the position being measured by the object to be measured. The LVDTs are positioned such that LVDT. The LVDT position signal is summed with the offset there is a known maximum distance between them in the fully signal introduced by the potentiometer, P1. Since this sum is in- retracted position. tegrated, it must be forced to zero. Thus the LVDT position is This circuit is both simple and inexpensive. It has the advantage forced to follow the value of the input potentiometer, P1. The that two LVDTs may be driven from one AD598, but the disad- output signal from the AD598 drives the LM675 power ampli- vantage is that the scale factor of each LVDT may not match fier, which in turn drives the solenoid. exactly. This causes the workpiece thickness measurement to This circuit has dual advantages of being both low cost and high vary depending upon its absolute position in the differential accuracy. The high accuracy results from avoiding the offset er- gage head. rors normally associated with converting the LVDT signal to a This circuit was designed to produce a – 10 V signal output voltage and then subsequently integrating that voltage. swing, composed of the sum of the two independent – 5 V swings from each LVDT. The output voltage swing is set with MECHANICAL FOLLOWER SERVO-LOOP an 80.9 kW resistor. The output voltage V for this circuit is OUT Figure 24 shows how two Schaevitz E100 LVDTs may be com- given by: bined with two AD598s in a mechanical follower servo-loop Ø (cid:40)(cid:86) (cid:177)(cid:86) (cid:41) (cid:40)(cid:86) (cid:177)(cid:86) (cid:41)ø cpoonsiftiigounr astiigonna.l ,O wnhei loef tthhee oLthVeDr TLsV pDrTov midiems itchse tmhee cmhoatnioicna.l input (cid:86) (cid:79)(cid:85)(cid:84) =ºŒ (cid:40)(cid:86)(cid:65)(cid:65) +(cid:86)(cid:66)(cid:66)(cid:41)+(cid:40)(cid:86)(cid:67)(cid:67)+(cid:86)(cid:68)(cid:68)(cid:41)ßœ · (cid:53)(cid:48)(cid:48)m (cid:65)· (cid:82)(cid:50)(cid:46) The signal from the input position circuit is fed to the output as a current so that voltage offset errors are avoided. This current MASS ON SPRING 620 N/m 33 GRAMS 100W 0.33m F 1000pF 0.1m F +V INPUT PI 10k 150k 1 –VS +VS 20 0.068m F +V 0.1m F INPUT MPOESCIHTAIONNICAL 2 EXC 1 OFFSET 119 50kW LM675 3 EXC 2 OFFSET 2 18 49.9k GUARDIAN SOLENOID 4 LEV 1 SIG REF 17 12 VDC 2–INT–12D OUTPUT 62 CONE POSITION 5 LEV 2 SIG OUT 16 4.99k SCHAEVITZ E 100 30k LVDT 0.015m F 6 FREQ 1 FEEDBACK 15 7 FREQ 2 OUT FILT 14 0.33m F 1m F +V +25V 20k 47m F 0.1m F 8 B1 FILT A1 FILT 13 33m F 9 B2 FILT A2 FILT 12 0.1m F IN4740A 47m F 0.01m F 10V 10 VB AD598 VA 11 GND POWER SUPPLY Figure 23.Low Cost Set-Point Controller –12– REV. A

AD598 MASS ON SPRING 620 N/m 33 GRAMS 100W 0.33m F 1000pF 0.1m F +V 10k 150k 1 –VS +VS 20 0.068m F +V 0.1m F OUTPUT MECHANICAL 2 EXC 1 OFFSET 119 LM675 POSITION 3 EXC 2 OFFSET 2 18 49.9k GUARDIAN SOLENOID 4 LEV 1 SIG REF 17 4.99k 12 VDC 2-INT-12D 62 CONE SCHAEVITZ E 100 5 LEV 2 SIG OUT 16 LVDT 30k 0.015m F 6 FREQ 1 FEEDBACK 15 7 FREQ 2 OUT FILT 14 0.33m F 1m F 0.1m F 8 B1 FILT A1 FILT 13 9 B2 FILT A2 FILT 12 0.1m F 0.01m F 10 VB AD598 VA 11 +V +25V 20k 47m F 0.1m F +V 33m F 47m F INPUT 1 –VS +VS 20 IN4740A GND MECHANICAL 2 EXC 1 OFFSET 119 10V POWER SUPPLY POSITION 4.99k 3 EXC 2 OFFSET 2 18 4 LEV 1 SIG REF 17 SCHAEVITZ E 100 LVDT 5 LEV 2 SIG OUT 16 0.015m F 6 FREQ 1 FEEDBACK 15 7 FREQ 2 OUT FILT 14 0.33m F 0.1m F 8 B1 FILT A1 FILT 13 9 B2 FILT A2 FILT 12 0.1m F 10 VB AD598 VA 11 Figure 24.Mechanical Follower Servo-Loop –V +V 0.1m F 0.1m F 1 –VS +VS 20 2 EXC 1 OFFSET 119 A 3 EXC 2 OFFSET 2 18 4 LEV 1 SIG REF 17 B 5 LEV 2 SIG OUT 16 VOUT– 10V LVDT 1 0.015m F R2 80.9kW FULL SCALE 6 FREQ 1 FEEDBACK 15 0.33m F 7 FREQ 2 OUT FILT 14 SCHAEVITZ E 100 8 B1 FILT A1 FILT 13 0.1m F 9 B2 FILT A2 FILT 12 0.1m F C 10 VB AD598 VA 11 D LVDT 2 SCHAEVITZ E 100 VOUT=((VVAA–+VVBB))++((VVCC–+VVDD))• 500m A • R2 Figure 25.Differential Gaging REV. A –13–

AD598 PRECISION DIFFERENTIAL GAGING R1 and R2 are chosen to be 80.9 kW resistors to give a – 10 V The circuit shown in Figure 26 is functionally similar to the dif- full-scale output signal for a single Schaevitz E100 LVDT. R3 is ferential gaging circuit shown in Figure 25. In contrast to Figure chosen to be 40.2 kW to give a – 10 V output signal when the 25, it provides a means of independently adjusting the scale fac- two E100 LVDT output signals are summed. The output volt- tor of each LVDT so that both scale factors may be matched. age for this circuit is given by: The two LVDTs are driven in a master-slave arrangement where the output signal from the slave LVDT is summed with Ø (cid:40)(cid:86) (cid:177)(cid:86) (cid:41) (cid:40)(cid:86) (cid:177)(cid:86) (cid:41) (cid:82)(cid:50)ø the output signal from the master LVDT. The scale factor of the (cid:86)(cid:79)(cid:85)(cid:84) =ºŒ (cid:40)(cid:86)(cid:65) +(cid:86)(cid:66)(cid:41)+(cid:40)(cid:86)(cid:67)+(cid:86)(cid:68)(cid:41)· (cid:82)(cid:49)ßœ · (cid:53)(cid:48)(cid:48)m (cid:65)· (cid:82)(cid:51)(cid:46) (cid:65) (cid:66) (cid:67) (cid:68) slave LVDT only is adjusted with R1 and R2. The summed scale factor of the master LVDT and the slave LVDT is ad- justed with R3. –V +V 0.1m F 0.1m F 1 –VS +VS 20 2 EXC 1 OFFSET 1 19 3 EXC 2 OFFSET 2 18 4 LEV 1 SIG REF 17 5 LEV 2 SIG OUT 16 VOUT– 10V 0.015m F R3 40.2kW FULL SCALE 6 FREQ 1 FEEDBACK 15 0.33m F 7 FREQ 2 OUT FILT 14 15kW 8 B1 FILT A1 FILT 13 0.1m F A 9 B2 FILT A2 FILT 12 15kW 0.1m F 10 V AD598 V 11 B A B MASTER LVDT R1 SCHAEVITZ E 100 –V +V 80.9kW 0.1m F 0.1m F C 1 –VS +VS 20 D 2 EXC 1 OFFSET 1 19 SLAVE 3 EXC 2 OFFSET 2 18 LVDT 4 LEV 1 SIG REF 17 R2 80.9kW 5 LEV 2 SIG OUT 16 6 FREQ 1 FEEDBACK 15 0.33m F 7 FREQ 2 OUT FILT 14 8 B1 FILT A1 FILT 13 0.1m F 9 B2 FILT A2 FILT 12 0.1m F 10 V AD598 V 11 B A VOUT= VVAA–+VVBB + VVCC–+VVDD•RR21 •500m A •R3 Figure 26.Precision Differential Gaging –14– REV. A

AD598 OPERATION WITH A HALF-BRIDGE TRANSDUCER trial and error. The 300 W resistors in this circuit optimize the Although the AD598 is not intended for use with a half-bridge nonlinearity of the transfer function to within several tenths of type transducer, it may be made to function with degraded 1%. This circuit uses a Sangamo AGH1 half-bridge transducer. performance. The 1 m F capacitor blocks the dc offset of the excitation output signal. The 4 nF capacitor sets the transducer excitation fre- A half-bridge type transducer is a popular transducer. It works quency to 10 kHz as recommended by the manufacturer. in a similar manner to the LVDT in that two coils are wound around a moveable core and the inductance of each coil is a ALTERNATE HALF-BRIDGE TRANSDUCER CIRCUIT function of core position. This circuit suffers from similar accuracy problems to those In the circuit shown in Figure 27 the VA and VB input voltages mentioned in the previous circuit description. In this circuit the are developed as two resistive-inductor dividers. If the inductors V input signal to the AD598 really and truly is a linear function A are equal (i.e., the core is centered), the VA and VB input volt- of core position, and the input signal VB, is one half of the exci- ages to the AD598 are equal and the output voltage VOUT is tation voltage level. However, a nonlinearity is introduced by zero. When the core is positioned off center, the inductors are the A–B/A+B transfer function. unequal and an output voltage V is developed. OUT The 500 W resistors in this circuit are chosen to minimize errors The linearity of this circuit is dependent upon the value of the caused by dc bias currents from the V and V inputs. Note that A B resistors in the resistive-inductor dividers. The optimum value in the previous circuit these bias currents see very low resistance may be transducer dependent and therefore must be selected by paths to ground through the coils. –V +V 0.1m F 0.1m F 1m F 1m F 1 –VS +VS 20 2 EXC 1 OFFSET 1 19 300W 300W 3 EXC 2 OFFSET 2 18 4 LEV 1 SIG REF 17 5kW 5 LEV 2 SIG OUT 16 VOUT– 10V SANGAMO 82.5kW FULL SCALE AGHI 6 FREQ 1 FEEDBACK 15 HALF-BRIDGE 4nF 0.33m F 7 FREQ 2 OUT FILT 14 8 B1 FILT A1 FILT 13 0.1m F 9 B2 FILT A2 FILT 12 0.1m F MECHANICAL 10 V AD598 V 11 POSITION B A INPUT Figure 27.Half-Bridge Operation –V +V 0.1m F 0.1m F 1 –VS +VS 20 2 EXC 1 OFFSET 1 19 3 EXC 2 OFFSET 2 18 1m F 4 LEV 1 SIG REF 17 1.87kW 5 LEV 2 SIG OUT 16 VOUT– 10V SANGAMO 143kW FULL SCALE AHGALHFI-BRIDGE 500W 4nF 6 FREQ 1 FEEDBACK 15 0.33m F 7 FREQ 2 OUT FILT 14 8 B1 FILT A1 FILT 13 500W 0.1m F 9 B2 FILT A2 FILT 12 0.1m F MECHANICAL 10 V AD598 V 11 POSITION B A INPUT Figure 28.Alternate Half-Bridge Circuit REV. A –15–

AD598 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Pin Sized Brazed Ceramic DIP 9 8 0/ 1 – 0 1 – 0 3 3 1 C 20-Lead Wide Body Plastic SOIC (R) Package A. S. U. N D I E T N RI P –16– REV. A

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