250 kSPS, 12-Bit Impedance Converter, Network Analyzer Data Sheet AD5934 FEATURES GENERAL DESCRIPTION Programmable output peak-to-peak excitation voltage to a The AD5934 is a high precision impedance converter system maximum frequency of 100 kHz solution that combines an on-board frequency generator with a Programmable frequency sweep capability with serial I2C 12-bit, 250 kSPS, analog-to-digital converter (ADC). The interface frequency generator allows an external complex impedance to Frequency resolution of 27 bits (<0.1 Hz) be excited with a known frequency. The response signal from Impedance measurement range from 1 kΩ to 10 MΩ the impedance is sampled by the on-board ADC and a discrete Capable of measuring 100 Ω to 1 kΩ with additional circuitry Fourier transform (DFT) is processed by an on-board DSP Phase measurement capability engine. The DFT algorithm returns a real (R) and imaginary (I) System accuracy of 0.5% data-word at each output frequency. 2.7 V to 5.5 V power supply operation Once calibrated, the magnitude of the impedance and relative Temperature range: −40°C to +125°C phase of the impedance at each frequency point along the sweep 16-lead SSOP package is easily calculated using the following two equations: APPLICATIONS Magnitude = R2 + I2 Electrochemical analysis Bioelectrical impedance analysis Phase = tan−1(I/R) Impedance spectroscopy A similar device, available from Analog Devices, Inc., is the Complex impedance measurement AD5933, which is a 2.7 V to 5.5 V, 1 MSPS, 12-bit impedance Corrosion monitoring and protection equipment converter, with an internal temperature sensor, available in a Biomedical and automotive sensors 16-lead SSOP. Proximity sensing Nondestructive testing Material property analysis Fuel/battery cell condition monitoring FUNCTIONAL BLOCK DIAGRAM MCLK AVDD DVDD DDS CORE DAC (27 BITS) ROUT VOUT SCL I2C VBIAS SDA INTERFACE Z(ω) AD5934 REAL IMAGINARY REGISTER REGISTER RFB 1024-POINT DFT VIN ADC GAIN (12 BITS) LPF VDD/2 AGND DGND 05325-001 Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5934 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Performing a Frequency Sweep .................................................... 19 Applications ....................................................................................... 1 Register Map ................................................................................... 20 General Description ......................................................................... 1 Control Register (Register Address 0x80, Register Address Functional Block Diagram .............................................................. 1 0x81) ............................................................................................. 20 Revision History ............................................................................... 3 Start Frequency Register (Register Address 0x82, Register Address 0x83, Register Address 0x84) .................................... 21 Specifications ..................................................................................... 4 Frequency Increment Register (Register Address 0x85, I2C Serial Interface Timing Characteristics .............................. 6 Register Address 0x86, Register Address 0x87) ..................... 21 Absolute Maximum Ratings ............................................................ 7 Number of Increments Register (Register Address 0x88, ESD Caution .................................................................................. 7 Register Address 0x89) .............................................................. 22 Pin Configuration and Function Descriptions ............................. 8 Number of Settling Time Cycles Register (Register Address Typical Performance Characteristics ............................................. 9 0x8A, Register Address 0x8B) .................................................. 22 Terminology .................................................................................... 11 Status Register (Register Address 0x8F) .................................. 22 System Description ......................................................................... 12 Real and Imaginary Data Registers (16 Bits—Register Address 0x94, Register Address 0x95, Register Address 0x96, Register Transmit Stage ............................................................................. 13 Address 0x97) .............................................................................. 23 Frequency Sweep Command Sequence ................................... 14 Serial Bus Interface ......................................................................... 24 Receive Stage ............................................................................... 14 General I2C Timing .................................................................... 24 DFT Operation ........................................................................... 14 Writing/Reading to the AD5934 .............................................. 25 Impedance Calculation .................................................................. 15 Block Write .................................................................................. 25 Magnitude Calculation .............................................................. 15 Read Operations ......................................................................... 26 Gain Factor Calculation ............................................................ 15 Typical Applications ....................................................................... 27 Impedance Calculation Using Gain Factor ............................. 15 Measuring Small Impedances ................................................... 27 Gain Factor Variation with Frequency .................................... 15 Biomedical: Noninvasive Blood impedance Measurement .. 28 2-Point Calibration ..................................................................... 16 Sensor/Complex Impedance Measurement ............................ 29 2-Point Gain Factor Calculation .............................................. 16 Electro-Impedance Spectroscopy ............................................. 29 Gain Factor Setup Configuration ............................................. 16 Layout and Configuration ............................................................. 30 Gain Factor Recalculation ......................................................... 16 Power Supply Bypassing and Grounding ................................ 30 Gain Factor Temperature Variation ......................................... 17 Outline Dimensions ....................................................................... 31 Impedance Error ......................................................................... 17 Ordering Guide .......................................................................... 31 Measuring the Phase Across an Impedance ........................... 17 Rev. E | Page 2 of 31

Data Sheet AD5934 REVISION HISTORY 9/2017—Rev. D to Rev. E Changes to Frequency Sweep Command Sequence Section and Changes to Control Register Section ............................................ 20 Receive Stage Section ...................................................................... 14 Changes to Gain Factor Calculation Section and Impedance 5/2017—Rev. C to Rev. D Calculation Using Gain Factor Section ........................................ 15 Changes to Bit D3 Description, Table 9 ....................................... 20 Changes to Figure 20 ...................................................................... 16 Changes to Impedance Error Section ........................................... 17 7/2012—Rev. B to Rev. C Added Measuring the Phase Across an Impedance Section ..... 19 Changes to Pin 10, Description Column, Table 4 and Pin 11, Added Figure 28 and Figure 29; Renumbered Sequentially ...... 20 Description Column, Table 4 ........................................................... 8 Added Table 6; Renumbered Sequentially ................................... 20 Changes to Table 6 .......................................................................... 18 Deleted Table 8 ................................................................................ 19 Deleted Choosing a Reference for the AD5934 and Table 17; Deleted Table 10 and Table 11 ....................................................... 20 Renumbered Sequentially .............................................................. 30 Changes to Table 9 .......................................................................... 22 Deleted Table 14, Table 16, and Table 17 ..................................... 22 2/2012—Rev. A to Rev. B Changes to Status Register (Register Address 0x8F) Section .... 24 Deleted Evaluation Board ................................................. Universal Added Measuring Small Impedances Section, Figure 37, and Changes to Impedance Error Section ........................................... 17 Table 16 ............................................................................................. 29 Changes to Table 17 ........................................................................ 32 5/2008—Rev. 0 to Rev. A Added Evaluation Board Section .................................................. 34 Changes to Layout .............................................................. Universal Added Figure 40 .............................................................................. 35 Changes to Features Section, General Description Section, and Added Figure 41 .............................................................................. 36 Figure 1 ............................................................................................... 1 Added Figure 42 .............................................................................. 37 Deleted Table 1; Renumbered Sequentially ................................... 1 Added Figure 43 .............................................................................. 38 Changes to Table 1 ............................................................................ 4 Added Table 18 ................................................................................ 39 Changes to Table 2 ............................................................................ 6 Changes to Ordering Guide ........................................................... 40 Changes to Figure 3 and Table 4 ..................................................... 8 Changes to System Description Section and Figure 14 .............. 12 6/2005—Revision 0: Initial Version Changes to Figure 16 ...................................................................... 13 Rev. E | Page 3 of 31

AD5934 Data Sheet SPECIFICATIONS VDD = 3.3 V, MCLK = 16.776 MHz, 2 V p-p output excitation voltage @ 30 kHz, 200 kΩ connected between Pin 5 and Pin 6; feedback resistor = 200 kΩ connected between Pin 4 and Pin 5; PGA gain = ×1, unless otherwise noted. Table 1. Y Version1 Parameter Min Typ Max Unit Test Conditions/Comments SYSTEM Impedance Range 1 k 10 M Ω 100 Ω to 1 kΩ requires extra buffer circuitry, see Measuring Small Impedances section Total System Accuracy 0.5 % 2 V p-p output excitation voltage at 30 kHz, 200 kΩ connected between Pin 5 and Pin 6 System Impedance Error Drift 30 ppm/°C TRANSMIT STAGE Output Frequency Range2 1 100 kHz Output Frequency Resolution 0.1 Hz <0.1 Hz resolution achievable using direct digital synthesis (DDS) techniques MCLK Frequency 16.776 MHz Maximum system clock frequency TRANSMIT OUTPUT VOLTAGE Range 1 AC Output Excitation Voltage3 1.98 V p-p Refer to Figure 4 for output voltage distribution DC Bias4 1.48 V DC bias of the ac excitation signal; see Figure 5 DC Output Impedance 200 Ω T = 25°C A Short-Circuit Current to Ground at VOUT ±5.8 mA T = 25°C A Range 2 AC Output Excitation Voltage3 0.97 V p-p See Figure 6 DC Bias4 0.76 V DC bias of output excitation signal; see Figure 7 DC Output Impedance 2.4 kΩ Short-Circuit Current to Ground at VOUT ±0.25 mA Range 3 AC Output Excitation Voltage3 0.383 V p-p See Figure 8 DC Bias4 0.31 V DC bias of output excitation signal; see Figure 9 DC Output Impedance 1 kΩ Short-Circuit Current to Ground at VOUT ±0.20 mA Range 4 AC Output Excitation Voltage3 0.198 V p-p See Figure 10 DC Bias4 0.173 V DC bias of output excitation signal; see Figure 11 DC Output Impedance 600 Ω Short-Circuit Current to Ground at VOUT ±0.15 mA SYSTEM AC CHARACTERISTICS Signal-to-Noise Ratio 60 dB Total Harmonic Distortion −52 dB Spurious-Free Dynamic Range Wide Band (0 MHz to 1 MHz) −56 dB Narrow Band (±5 kHz) −85 dB Rev. E | Page 4 of 31

Data Sheet AD5934 Y Version1 Parameter Min Typ Max Unit Test Conditions/Comments RECEIVE STAGE Input Leakage Current 1 nA To VIN pin Input Capacitance5 0.01 pF Pin capacitance between VOUT and GND Feedback Capacitance, C 3 pF Feedback capacitance around current-to- FB voltage amplifier; appears in parallel with feedback resistor ANALOG-TO-DIGITAL CONVERTER5 Resolution 12 Bits Sampling Rate 250 kSPS ADC throughput rate LOGIC INPUTS Input High Voltage, V 0.7 × VDD IH Input Low Voltage, V 0.3 × VDD IL Input Current6 1 µA T = 25° A Input Capacitance 7 pF T = 25°C A POWER REQUIREMENTS VDD 2.7 5.5 V I , Normal Mode 10 15 mA VDD = 3.3 V DD 17 25 mA VDD = 5.5 V I , Standby Mode 7 mA VDD = 3.3 V; see the Control Register section DD 9 mA VDD = 5.5 V I , Power-Down Mode 0.7 5 µA VDD = 3.3 V DD 1 8 µA VDD = 5.5 V 1 Temperature range for Y version = −40°C to +125°C, typical at +25°C. 2 The lower limit of the output excitation frequency can be lowered by scaling the clock supplied to the AD5934. 3 The peak-to-peak value of the ac output excitation voltage scales with supply voltage according to the following formula. VDD is the supply voltage. Output Excitation Voltage (V p-p) = [2/3.3] × VDD 4 The dc bias value of the output excitation voltage scales with supply voltage according to the following formula. VDD is the supply voltage. Output Excitation Voltage (V p-p) = [2/3.3] × VDD 5 Guaranteed by design or characterization, not production tested. Input capacitance at the VOUT pin is equal to pin capacitance divided by open-loop gain of current- to-voltage amplifier. 6 The accumulation of the currents into Pin 8, Pin 15, and Pin 16. Rev. E | Page 5 of 31

AD5934 Data Sheet I2C SERIAL INTERFACE TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V; all specifications T to T , unless otherwise noted (see Figure 2). MIN MAX Table 2. Parameter1 Limit at T , T Unit Description MIN MAX f 400 kHz max SCL clock frequency SCL t 2.5 µs min SCL cycle time 1 t 0.6 µs min t , SCL high time 2 HIGH t 1.3 µs min t , SCL low time 3 LOW t 0.6 µs min t , start/repeated start condition hold time 4 HD, STA t 100 ns min t , data setup time 5 SU, DAT t 2 0.9 µs max t , data hold time 6 HD, DAT 0 µs min t , data hold time HD, DAT t 0.6 µs min t , setup time for repeated start 7 SU, STA t 0.6 µs min t , stop condition setup time 8 SU, STO t 1.3 µs min t , bus free time between a stop and a start condition 9 BUF t 300 ns max t , rise time of SDA when transmitting 10 R 0 ns min t , rise time of SCL and SDA when receiving (CMOS compatible) R t 300 ns max t, fall time of SCL and SDA when transmitting 11 F 0 ns min t, fall time of SDA when receiving (CMOS compatible) F 250 ns max t, fall time of SDA when receiving F 20 + 0.1 C 3 ns min t, fall time of SCL and SDA when transmitting b F C 400 pF max Capacitive load for each bus line b 1 Guaranteed by design and characterization, not production tested. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH MIN of the SCL signal) to bridge the undefined falling edge of SCL. 3 Cb is the total capacitance of one bus line in pF. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD. SDA t9 t3 t10 t11 t4 SCL t4 t6 t2 t5 t7 t1 t8 COSNTDAIRTITON CROESPNTEDAAIRTTITEODN COSNTDOITPION 05325-002 Figure 2. I2C Interface Timing Diagram Rev. E | Page 6 of 31

Data Sheet AD5934 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 3. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational DVDD to GND −0.3 V to +7.0 V section of this specification is not implied. Operation beyond AVDD1 to GND −0.3 V to +7.0 V the maximum operating conditions for extended periods may AVDD2 to GND −0.3 V to +7.0 V affect product reliability. SDA/SCL to GND −0.3 V to VDD + 0.3 V VOUT to GND −0.3 V to VDD + 0.3 V VIN to GND −0.3 V to VDD + 0.3 V ESD CAUTION MCLK to GND −0.3 V to VDD + 0.3 V Operating Temperatures Extended Industrial Range (Y Grade) −40°C to +125°C Storage Temperature Range −65°C to +160°C Maximum Junction Temperature 150°C SSOP Package, Thermal Impedance θ 139°C/W JA θ 136°C/W JC Reflow Soldering (Pb-Free) Peak Temperature 260°C Time at Peak Temperature 10 sec to 40 sec Rev. E | Page 7 of 31

AD5934 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 16 SCL NC 2 15 SDA NC 3 AD5934 14 AGND2 RFB 4 TOP VIEW 13 AGND1 VIN 5 (Not to Scale) 12 DGND VOUT 6 11 AVDD2 NC 7 10 AVDD1 MCLK 8 NC = NO CONNECT 9 DVDD 05325-003 NOTES: 1. IT IS RECOMMENDED TO TIE ALL SUPPLY CONNECTIONS (PIN 9, PIN 10, AND PIN 11) AND RUN FROM A SINGLE SUPPLY BETWEEN 2.7V AND 5.5V. 2. IT IS ALSO RECOMMENDED TO CONNECT ALL GROUND SIGNALS TOGETHER (PIN 12, PIN 13, AND PIN 14). Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 to 3, 7 NC No Connect. Do not connect to this pin. 4 RFB External Feedback Resistor. Connect from Pin 4 to Pin 5. This pin sets the gain of the current-to-voltage amplifier on the receive side. 5 VIN Input to Receive Transimpedance Amplifier. VIN presents a virtual earth voltage of VDD/2. 6 VOUT Excitation Voltage Signal Output. 8 MCLK The master clock for the system is supplied by the user. 9 DVDD Digital Supply Voltage. 10 AVDD1 Analog Supply Voltage 1. Used for powering the analog core. 11 AVDD2 Analog Supply Voltage 2. Used for internal references. 12 DGND Digital Ground. 13 AGND1 Analog Ground 1. 14 AGND2 Analog Ground 2. 15 SDA I2C® Data Input. 16 SCL I2C Clock Input. Rev. E | Page 8 of 31

Data Sheet AD5934 TYPICAL PERFORMANCE CHARACTERISTICS 35 30 MEAN = 1.9824 MEAN = 0.7543 SIGMA = 0.0072 SIGMA = 0.0099 30 25 S 25 S CE CE 20 VI VI DE 20 DE OF OF 15 ER 15 ER B B M M U U 10 N 10 N 5 5 0 05325-064 0 05325-073 1.92 1.94 1.96 1.98 2.00 2.02 2.04 2.06 0.68 0.70 0.72 0.74 0.76 0.78 0.80 0.82 0.84 0.86 VOLTAGE (V) VOLTAGE (V) Figure 4. Range 1 Output Excitation Voltage Distribution, VDD = 3.3 V Figure 7. Range 2 DC Bias Distribution, VDD = 3.3 V 30 30 MEAN = 1.4807 MEAN = 0.3827 SIGMA = 0.0252 SIGMA = 0.00167 25 25 S S CE 20 CE 20 VI VI E E D D OF 15 OF 15 R R E E B B M M U 10 U 10 N N 5 5 0 05325-072 0 05325-077 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 0.370 0.375 0.380 0.385 0.390 0.395 0.400 VOLTAGE (V) VOLTAGE (V) Figure 5. Range 1 DC Bias Distribution, VDD = 3.3 V Figure 8. Range 3 Output Excitation Voltage Distribution, VDD = 3.3 V 30 30 MEAN = 0.9862 MEAN = 0.3092 SIGMA = 0.0041 SIGMA = 0.0014 25 25 S S CE 20 CE 20 VI VI E E D D OF 15 OF 15 R R E E B B M M U 10 U 10 N N 5 5 0 05325-066 0 05325-074 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 0.290 0.295 0.300 0.305 0.310 0.315 0.320 VOLTAGE (V) VOLTAGE (V) Figure 6. Range 2 Output Excitation Voltage Distribution, VDD = 3.3 V Figure 9. Range 3 DC Bias Distribution, VDD = 3.3 V Rev. E | Page 9 of 31

AD5934 Data Sheet 30 15.8 MEAN = 0.1982 AVDD1, AVDD2, DVDD CONNECTED TOGETHER SIGMA = 0.0008 15.3 OUTPUT EXCITATION FREQUENCY = 30kHz 25 RFB,ZCALIBRATION = 100kΩ 14.8 CES 20 14.3 DEVI A) 13.8 R OF 15 DD (m 13.3 BE I 12.8 M U 10 N 12.3 11.8 5 0 05325-070 1101..83 05325-088 0.192 0.194 0.196 0.198 0.200 0.202 0.204 0.206 0 2 4 6 8 10 12 14 16 18 VOLTAGE (V) MCLK FREQUENCY (MHz) Figure 10. Range 4 Output Excitation Voltage Distribution, VDD = 3.3 V Figure 12. Typical Supply Current (IDD) vs. MCLK Frequency 30 0.4 MEAN = 0.1792 VDD = 3.3V SIGMA = 0.0024 TA = 25°C 0.2 f = 32kHz 25 S es) 0 OF DEVICE 2105 ROR (Degre –0.2 ER ER –0.4 B E UM 10 AS N H –0.6 P 5 –0.8 0 05325-075 –1.0 05325-028 0.160 0.165 0.170 0.175 0.180 0.185 0.190 0.195 0.200 0.205 0 50 100 150 200 250 300 350 400 VOLTAGE (V) PHASE (Degrees) Figure 11. Range 4 DC Bias Distribution, VDD = 3.3 V Figure 13. Typical Phase Error Rev. E | Page 10 of 31

Data Sheet AD5934 TERMINOLOGY Total System Accuracy Signal-to-Noise Ratio (SNR) The AD5934 can accurately measure a range of impedance SNR is the ratio of the rms value of the measured output signal values to less than 0.5% of the correct impedance value for to the rms sum of all other spectral components below the supply voltages between 2.7 V to 5.5 V. Nyquist frequency. The value for SNR is expressed in decibels. Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Along with the frequency of interest, harmonics of the fundamental THD is the ratio of the rms sum of harmonics to the fundamental, frequency and images of these frequencies are present at the where V1 is the rms amplitude of the fundamental, and V2, V3, output of a DDS device. The spurious-free dynamic range refers V4, V5, and V6 are the rms amplitudes of the second through the to the largest spur or harmonic present in the band of interest. sixth harmonics. THD is defined as The wideband SFDR gives the magnitude of the largest harmonic V22+V32+V42+V52+V62 or spur relative to the magnitude of the fundamental frequency THD(dB)=20log in the 0 Hz to Nyquist bandwidth. The narrow-band SFDR V1 gives the attenuation of the largest spur or harmonic in a bandwidth of ±200 kHz, about the fundamental frequency. Rev. E | Page 11 of 31

AD5934 Data Sheet SYSTEM DESCRIPTION MCLK DDS CORE DAC (27 BITS) ROUT VOUT COS SIN SCL VBIAS MICROCONTROLLER I2C INTERFACE SDA Z(ω) AD5934 REAL IMAGINARY REGISTER REGISTER RFB MAC CORE (1024 DFT) MCLK PROGRAMMABLE WINDOWING GAIN AMPLIFIER OF DATA VIN ADC ×5 (12 BITS) ×1 LPF VDD/2 05325-078 Figure 14. Block Overview The AD5934 is a high precision, impedance converter system The AD5934 permits the user to perform a frequency sweep with solution that combines an on-board frequency generator with a a user-defined start frequency, frequency resolution, and number 12-bit, 250 kSPS ADC. The frequency generator allows an external of points in the sweep. In addition, the device allows the user to complex impedance to be excited with a known frequency. The program the peak-to-peak value of the output sinusoidal signal as response signal from the impedance is sampled by the on-board an excitation to the external unknown impedance connected ADC and DFT processed by an on-board DSP engine. The DFT between the VOUT and VIN pins. algorithm returns both a real (R) and imaginary (I) data-word at Table 5 gives the four possible output peak-to-peak voltages and each frequency point along the sweep. The impedance magnitude the corresponding dc bias levels for each range for 3.3 V. These and phase is easily calculated using the following equations: values are ratiometric with VDD. So for a 5 V supply: Magnitude = R2 + I2 5.0 OutputExcitationVoltage forRange1=1.98 × =3Vp−p 3.3 Phase = tan−1(I/R) 5.0 To characterize an impedance profile Z(ω), generally a frequency OutputDCBiasVoltage forRange1=1.48× =2.24Vp−p 3.3 sweep is required such as that shown in Figure 15. Table 5. Voltage Levels Respective Bias Levels for 3.3 V Range Output Excitation No. Voltage Amplitude Output DC Bias Level 1 1.98 V p-p 1.48 V Ω) 2 0.99 V p-p 0.74 V CE ( 3 383 mV p-p 0.31 V N A 4 198 mV p-p 0.179 V D E P M I The excitation signal for the transmit stage is provided on-chip using DDS techniques that permit subhertz resolution. The receive 05325-033 spteargfeo rremcesi vsiegsn tahle p inropcuets ssiignnga,l acnudrr denigt iftriozems tthhee urenskunlto. wTnh eim cploecdka nfocre , FREQUENCY (Hz) the DDS is generated from an external reference clock that is Figure 15. Impedance vs. Frequency Profile provided by the user at MCLK. Rev. E | Page 12 of 31

Data Sheet AD5934 TRANSMIT STAGE Frequency Increment As shown in Figure 16, the transmit stage of the AD5934 is made This is a 24-bit word that is programmed to the on-board RAM at up of a 27-bit phase accumulator DDS core that provides the output Register Address 0x85, Register Address 0x86, and Register Address excitation signal at a particular frequency. The input to the phase 0x87 (see the Register Map section). The required code loaded to accumulator is taken from the contents of the start frequency register the frequency increment register is the result of the formula shown in (see Register Address 0x82, Register Address 0x83, and Register Equation 2, based on the master clock frequency and the required Address 0x84). Although the phase accumulator offers 27 bits of increment frequency output from the DDS. resolution, the start frequency register has the three most significant FrequencyIncrementCode= bits (MSBs) set to 0 internally; therefore, the user has the ability to   program only the lower 24 bits of the start frequency register.   RequiredFrequencyIncrement (2) R(GAIN)  MCLK ×227    16  PHASE ACCUMULATOR DAC (27 BITS) VBIAS ROUT VOUT 05325-034 F10o rH ezx aanmdp hlea,s iaf t1h6e M usHezr crleoqcuki rseigsn tahle c sownneeepct teod htoa vMe Ca LrKes,o tlhuet icoond eo f Figure 16. Transmit Stage that needs to be programmed is given by The AD5934 offers a frequency resolution programmable by the FrequencyIncrementCode= user down to 0.1 Hz. The frequency resolution is programmed via   a 24-bit word loaded serially over the I2C interface to the frequency    10Hz  increment register. ≡0x00053E   16MHz The frequency sweep is fully described by the programming of    16  three parameters: the start frequency, the frequency increment, and the number of increments. The user programs the value 0x00 to Register Address 0x85, the Start Frequency value 0x05 to Register Address 0x86, and the value 0x3E to Register Address 0x87. This is a 24-bit word that is programmed to the on-board RAM Number of Increments at Register Address 0x82, Register Address 0x83, and Register Address 0x84 (see the Register Map section). The required code This is a 9-bit word that represents the number of frequency loaded to the start frequency register is the result of the formula points in the sweep. The number is programmed to the on-board shown in Equation 1, based on the master clock frequency and the RAM at Register Address 0x88 and Register Address 0x89 (see the required start frequency output from the DDS. Register Map section). The maximum number of points that can StartFrequencyCode= be programmed is 511. For example, if the sweep needs 150 points, the user programs   RequiredOutputStartFrequency (1) the value 0x00 to Register Address 0x88 and the value 0x96 to  ×227  MCLK  Register Address 0x89.    16  Once the three parameter values are programmed, the sweep is For example, if the user requires the sweep to begin at 30 kHz and initiated by issuing a start frequency sweep command to the has a 16 MHz clock signal connected to MCLK, the code that needs control register at Register Address 0x80 and Register Address to be programmed is given by 0x81 (see the Register Map section). Bit D2 in the status register (Register Address 0x8F) indicates the completion of the frequency     measurement for each sweep point. Incrementing to the next StartFrequencyCode= 30kHz ×227 =0x3D70A3 frequency sweep point is under the control of the user. The measured   16MHz result is stored in the two register groups that follow: 0x94, 0x95      16  (real data) and 0x96, 0x97 (imaginary data) that should be read before issuing an increment frequency command to the control The user programs the value of 0x3D to Register Address 0x82, register to move to the next sweep point. There is the facility to the value 0x70 to Register Address 0x83, and the value 0xA3 to repeat the current frequency point measurement by issuing a Register Address 0x84. repeat frequency command to the control register. This has the benefit of allowing the user to average successive readings. When the frequency sweep has completed all frequency points, Bit D3 in the status register is set, indicating the completion of the sweep. Once this bit is set, further increments are disabled. Rev. E | Page 13 of 31

AD5934 Data Sheet FREQUENCY SWEEP COMMAND SEQUENCE RECEIVE STAGE The following sequence must be followed to implement a The receive stage comprises a current-to-voltage amplifier, frequency sweep: followed by a programmable gain amplifier (PGA), antialiasing filter, and ADC. The receive stage schematic is shown in Figure 17. 1. Enter standby mode. Prior to issuing a start frequency sweep The unknown impedance is connected between the VOUT and command, the device must be placed in standby mode by VIN pins. The first stage current-to-voltage amplifier configuration issuing an enter standby mode command to the control means that a voltage present at the VIN pin is a virtual ground register (Register Address 0x80 and Register Address 0x81). with a dc value set at VDD/2. The signal current that is developed In this mode, the VOUT and VIN pins are connected internally across the unknown impedance flows into the VIN pin and to ground so there is no dc bias across the external impedance or develops a voltage signal at the output of the current-to-voltage between the impedance and ground. converter. The gain of the current-to voltage amplifier is determined 2. Enter initialize mode. In general, high Q complex circuits by a user-selectable feedback resistor connected between Pin 4 require a long time to reach steady state. To facilitate the (RFB) and Pin 5 (VIN). It is important for the user to choose a measurement of such impedances, this mode allows the user feedback resistance value which, in conjunction with the selected full control of the settling time requirement before entering gain of the PGA stage, maintains the signal within the linear range start frequency sweep mode where the impedance of the ADC (0 V to VDD). measurement takes place. R RFB An initialize with start frequency command to the control 5 × R C register enters initialize mode. In this mode, the impedance R is excited with the programmed start frequency but no measurement takes place. The user times out the required VIN R sthetet lcinogn ttrimole r begefiostreer i stsou einngte ar stthaer ts ftraerqtu ferenqcuy esnwceye ps wcoemepm manodd et.o VDD/2 LPF ADC 05325-038 3. Enter start frequency sweep mode. The user enters this mode Figure 17. Receive Stage by issuing a start frequency sweep command to the control The PGA allows the user to gain the output of the current-to- register. In this mode, the ADC starts measuring after the voltage amplifier by a factor of 5 or 1 depending upon the status programmed number of settling time cycles elapses. The user of Bit D8 in the control register (see the Register Map section can program an integer number of output frequency cycles Register Address 0x80). The signal is then low-pass filtered and (settling time cycles) to Register Address 0x8A and Register presented to the input of the 12-bit, 250 kSPS ADC. Address 0x8B before beginning the measurement at each The digital data from the ADC is passed directly to the DSP core frequency point (see Figure 24). of the AD5934 that performs a DFT on the sampled data. The DDS output signal is passed through a programmable DFT OPERATION gain stage to generate the four ranges of peak-to-peak output excitation signals listed in Table 5. The peak-to-peak output A DFT is calculated for each frequency point in the sweep. The excitation voltage is selected by setting Bit D10 and Bit D9 in AD5934 DFT algorithm is represented by the control register (see the Control Register section) and is 1023 ( ) made available at the VOUT pin. X(f)= ∑ x(n)(cos(n)−jsin(n)) n=0 where: X(f) is the power in the signal at the Frequency Point f. x(n) is the ADC output. cos(n) and sin(n) are the sampled test vectors provided by the DDS core at the Frequency f. The multiplication is accumulated over 1024 samples for each frequency point. The result is stored in two 16-bit registers representing the real and imaginary components of the result. The data is stored in twos complement format. Rev. E | Page 14 of 31

Data Sheet AD5934 IMPEDANCE CALCULATION MAGNITUDE CALCULATION IMPEDANCE CALCULATION USING GAIN FACTOR The first step in the impedance calculation for each frequency The next example illustrates how the calculated gain factor point is to calculate the magnitude of the DFT at that point. derived previously is used to measure an unknown impedance. For this example, assume that the unknown impedance is 510 kΩ. The DFT magnitude is given by After measuring the unknown impedance at a frequency of Magnitude= R2+I2 30 kHz, assume that the real data and imaginary data registers contain the following data: where: R is the real number stored at Register Address 0x94 and Real Data Register = 0xFA3F = −1473 decimal Register Address 0x95. Imaginary Data Register = 0x0DB3 = +3507 decimal I is the imaginary number stored at Register Address 0x96 and Register Address 0x97. Magnitude= ((−1473)2+(3507)2)=3802.863 For example, assume the results in the real data and imaginary The measured impedance at the frequency point is then given by data registers are as follows at a frequency point: 1 Impedance= Real Data Register = 0x038B = 907 decimal GainFactor×Magnitude Imaginary Data Register = 0x0204 = 516 decimal 1 = Ω = 509.791 kΩ Magnitude= (9072 + 5162)=1043.506 515.819273×10−12 × 3802.863 GAIN FACTOR VARIATION WITH FREQUENCY To convert this number into impedance, it must be multiplied by a scaling factor called the gain factor. The gain factor is Because the AD5934 has a finite frequency response, the gain calculated during the calibration of the system with a known factor also shows a variation with frequency. This variation in impedance connected between the VOUT and VIN pins. gain factor results in an error in the impedance calculation over a frequency range. Figure 18 shows an impedance profile based Once the gain factor is calculated, it can be used in the on a single-point gain factor calculation. To minimize this error, calculation of any unknown impedance between the VOUT and the frequency sweep should be limited to as small a frequency VIN pins. range as possible. GAIN FACTOR CALCULATION 101.5 VDD = 3.3V An example of a gain factor calculation follows, with these CALIBRATION FREQUENCY = 60kHz assumptions: 101.0 TA = 25°C MEASURED CALIBRATION IMPEDANCE = 100kΩ Output excitation voltage = 2 V p-p Calibration impedance value, Z = 200 kΩ Ω) 100.5 CALIBRATION k PGA gain = ×1 CE ( N 100.0 Current-to-voltage amplifier gain resistor = 200 kΩ A D E Calibration frequency = 30 kHz P M I 99.5 The typical contents of the real data and imaginary data registers after a frequency point conversion would then be 99.0 Real Data Register = 0xF064 = −3996 decimal 98.5 05325-085 Imaginary Data Register = 0x227E = +8830 decimal 54 56 58 60 62 64 66 FREQUENCY (kHz) Magnitude= (−3996)2 +(8830)2 =9692.106 Figure 18. Impedance Profile Using a Single-Point Gain Factor Calculation GainFactor=  1      Admittance Impedance  =  Code  Magnitude  1    GainFactor= 200kΩ =515.819×10−12   9692.106     Rev. E | Page 15 of 31

AD5934 Data Sheet 2-POINT CALIBRATION GAIN FACTOR SETUP CONFIGURATION Alternatively, it is possible to minimize this error by assuming When calculating the gain factor, it is important that the receive that the frequency variation is linear and adjusting the gain stage is operating in its linear region. This requires careful selection factor with a 2-point calibration. Figure 19 shows an impedance of the excitation signal range, current-to-voltage gain resistor profile based on a 2-point gain factor calculation. and PGA gain. The gain through the system shown in Figure 20 101.5 is given by VDD = 3.3V CALIBRATION FREQUENCY = 60kHz Output Excitation Voltage Range × 101.0 MTAE A= S2U5°RCED CALIBRATION IMPEDANCE = 100kΩ Gain Setting Resistor × PGA Gain Z Ω) 100.5 UNKNOWN E (k GCAUIRNR SEENTTT-ITNOG- VROELSTISATGOER C N 100.0 DA RFB E P M I 99.5 ZUNKNOWN VOUT 9998..05 05325-086 VDDV/2IFNigure 20. System Vo(×lt1aP OgGReA ×G5a)in LPF ADC 05325-089 54 56 58 60 62 64 66 For this example, assume the following system settings: FREQUENCY (kHz) Figure 19. Impedance Profile Using a 2-Point Gain Factor Calculation VDD = 3.3 V Gain setting resistor = 200 kΩ 2-POINT GAIN FACTOR CALCULATION Z = 200 kΩ UNKNOWN This is an example of a 2-point gain factor calculation assuming PGA setting = ×1 the following: The peak-to-peak voltage presented to the ADC input is 2 V p-p. Output excitation voltage = 2 V p-p However, had the user chosen a PGA gain of ×5, the voltage Calibration impedance value, ZUNKNOWN = 100.0 kΩ would saturate the ADC. PGA gain = ×1 GAIN FACTOR RECALCULATION Supply voltage = 3.3 V Current-to-voltage amplifier gain resistor = 100 kΩ The gain factor must be recalculated for a change in any of the Calibration frequencies = 55 kHz and 65 kHz following parameters: Typical values of the gain factor calculated at the two calibration • Current-to-voltage gain setting resistor frequencies read • Output excitation voltage Gain factor calculated at 55 kHz is 1.031224 × 10−9. • PGA gain Gain factor calculated at 65 kHz is 1.035682 × 10−9. Difference in gain factor (ΔGF) is 1.035682 × 10−9 − 1.031224 × 10−9 = 4.458000 × 10−12. Frequency span of sweep (ΔF) is 10 kHz. Therefore, the gain factor required at 60 kHz is given by 4.458000E-12   ×5 kHz +1.031224 × 10-9  10 kHz  The required gain factor is 1.033453 × 10−9. The impedance is calculated as previously described in the Impedance Calculation section. Rev. E | Page 16 of 31

Data Sheet AD5934 GAIN FACTOR TEMPERATURE VARIATION Where the gain factor is given by The typical impedance error variation with temperature is in  1    the order of 30 ppm/°C. Figure 21 shows an impedance profile   Admittance Impedance with a variation in temperature for 100 kΩ impedance using a GainFactor= =  Code  Magnitude 2-point gain factor calibration. 101.5 The user must calibrate the AD5934 system for a known impedance range to determine the gain factor before any valid 101.0 +125°C measurement can take place. Therefore, the user must know the impedance limits of the complex impedance (Z ) for UNKNOWN Ω) 100.5 the sweep frequency range of interest. The gain factor is simply E (k +25°C determined by placing a known impedance between the input/ C N 100.0 output of the AD5934 and measuring the resulting magnitude of A D E the code. The AD5934 system gain settings need to be chosen to P –40°C IM 99.5 place the excitation signal in the linear region of the on-board ADC. Because the AD5934 returns a complex output code made up of 9998..05 VCMDAEDLAI SB=U R3RA.3ETVDIO CNA FLRIBERQAUTEIONCNY IM =P 6E0DkHAzNCE = 100kΩ 05325-087 rtheael pahnads eim ofa gthinea rreys pcoomnspeo snigennatsl ,t thhreo uugsehr t ihse a slsigon aabl lpe attoh c oafl ctuhlea te 54 56 58 60 62 64 66 AD5934. The phase is given by the following formula: FREQUENCY (kHz) Phase (rads) = tan−1(I/R) (3) Figure 21. Impedance Profile Variation with Temperature Using a 2-Point Gain Factor Calibration The phase measured by Equation 3 accounts for the phase shift introduced to the DDS output signal as it passes through the IMPEDANCE ERROR internal amplifiers on the transmit and receive side of the AD5934, Refer to Circuit Note CN-0217 on the AD5933 product page, along with the low-pass filter, and also the impedance connected which highlights a method to improve accuracy. The EVAL- between the VOUT and VIN pins of the AD5934. AD5933EBZ board can be used to evaluate the AD5934 The parameters of interest for many users are the magnitude of performance. the impedance (|Z |) and the impedance phase (ZØ).The UNKNOWN MEASURING THE PHASE ACROSS AN IMPEDANCE measurement of the impedance phase (ZØ) is a 2-step process. The AD5934 returns a complex output code made up of a The first step involves calculating the AD5934 system phase. separate real and imaginary components. The real component is The AD5934 system phase can be calculated by placing a stored at Register Address 0x94 and Register Address 0x95, and resistor across the VOUT and VIN pins of the AD5934 and the imaginary component is stored at Register Address 0x96 calculating the phase (using Equation 3) after each measurement and Register Address 0x97 after each sweep measurement. These point in the sweep. By placing a resistor across the VOUT and correspond to the real and imaginary components of the DFT VIN pins, there is no additional phase lead or lag introduced to and not the resistive and reactive components of the impedance the AD5934 signal path, and the resulting phase is due entirely under test. to the internal poles of the AD5934, that is, the system phase. For example, it is a common misconception to assume that if a Once the system phase is calibrated using a resistor, the second user was analyzing a series RC circuit that the real value stored step involves calculating the phase of any unknown impedance in Register Address 0x94 and Register Address 0x95 and the can be calculated by inserting the unknown impedance between imaginary value stored in Register Address 0x96 and Register the VIN and VOUT terminals of the AD5934 and recalculating Address 0x97 would correspond to the resistance and capacitive the new phase (including the phase due to the impedance) using reactance, respectfully. However, this is incorrect because the the same formula. The phase of the unknown impedance (ZØ) magnitude of the impedance (|Z|) can be calculated by calculating is given by the magnitude of the real and imaginary components of the ZØ = (Φunknown − ∇system) DFT given by the following formula: where: Magnitude= R2 +I2 ∇system is the phase of the system with a calibration resistor connected between VIN and VOUT. After each measurement, multiply it by the calibration term and Φunknown is the phase of the system with the unknown invert the product. Therefore, the magnitude of the impedance impedance connected between VIN and VOUT. is given by the following formula: ZØ is the phase due to the impedance, that is, the impedance phase. 1 Impedance= GainFactor×Magnitude Rev. E | Page 17 of 31

AD5934 Data Sheet Note that it is possible to calculate the gain factor and to calibrate quadrant, the arctangent formula returns a negative angle, and the system phase using the same real and imaginary component it is necessary to add an additional 180° to calculate the correct values when a resistor is connected between the VOUT and standard angle. Likewise, when the real and imaginary components VIN pins of the AD5934, for example, measuring the impedance are both negative, that is, when data lies in the third quadrant, phase (ZØ) of a capacitor. the arctangent formula returns a positive angle, and it is necessary to add an additional 180° to calculate the correct standard The excitation signal current leads the excitation signal voltage phase. When the real component is positive and the imaginary across a capacitor by −90 degrees. Therefore, an approximate component is negative, that is, the data lies in the fourth quadrant, −90 degrees phase difference between the system phase responses the arctangent formula returns a negative angle, and it is necessary measured with a resistor and the system phase responses measured to add an additional 360° to calculate the correct standard phase. with a capacitive impedance exists. –100 As previously outlined, if the user wants to determine the phase –90 angle of the capacitive impedance (ZØ), the user first must determine the system phase response (∇system) and subtract –80 this from the phase calculated with the capacitor connected s) –70 e between VOUT and VIN (Φunknown). gre –60 e D Figure 22 shows the AD5934 system phase response calculated E ( –50 S using a 220 kΩ calibration resistor (RFB = 220 kΩ, PGA = ×1) HA –40 P and the repeated phase measurement with a 10 pF capacitive –30 impedance. –20 One important point to note about the phase formula used to –10 plot Figure 22 is that it uses the arctangent function that returns 0 afr opmha srea dainagnlse tion draegdriaeness. and, therefore, it is necessary to convert 0 15k 30k 4F5RkEQU6E0NkCY(H7z5)k 90k 105k 120k05325-091 Figure 23. Phase Response of a Capacitor 200 180 Therefore, the correct standard phase angle is dependent 160 upon the sign of the real and imaginary components, which is ees) 140 220kΩRESISTOR summarized in Table 6. gr e E (D 120 Table 6. Phase Angle AS 100 Real Imaginary Quadrant Phase Angle H EM P 80 Positive Positive First tan−1(I/R)×180° ST 60 10pFCAPACITOR π Y S 40 Positive Negative Second 180°+tan−1(I/R)×180°  π  20 00 15k 30k 4F5RkEQU6E0NkCY(H7z5)k 90k 105k 120k05325-090 NNeeggaattiivvee NPoesgitaitviev e TFohuirrdt h 180°+tan−1(I/R)×1188π00°° Figure 22. System Phase Response vs. Capacitive Phase 360°+tan−1(I/R)×   π  The phase difference (that is, ZØ) between the phase response of a capacitor and the system phase response using a resistor is Once the magnitude of the impedance (|Z|) and the impedance the impedance phase of the capacitor (ZØ) and is shown in phase angle (ZØ, in radians) are correctly calculated, it is possible Figure 23. to determine the magnitude of the real (resistive) and imaginary In addition, when using the real and imaginary values to interpret (reactive) components of the impedance (Z ) by the vector UNKNOWN the phase at each measurement point, care should be taken projection of the impedance magnitude onto the real and when using the arctangent formula. The arctangent function imaginary impedance axis using the following formulas: only returns the correct standard phase angle when the sign of The real component is given by the real and imaginary values are positive, that is, when the coordinates lie in the first quadrant. The standard angle is |ZREAL| = |Z| × cos(ZØ) taken counterclockwise from the positive real x-axis. If the sign The imaginary component is given by of the real component is positive and the sign of the imaginary |Z | = |Z| × sin(ZØ) component is negative, that is, the data lies in the second IMAG Rev. E | Page 18 of 31

Data Sheet AD5934 PERFORMING A FREQUENCY SWEEP PROGRAM FREQUENCY SWEEPPARAMETERS INTO RELEVANT REGISTERS (1) START FREQUENCY REGISTER (2) NUMBER OF INCREMENTS REGISTER (3) FREQUENCY INCREMENT REGISTER PLACE THEAD5934 INTO STANDBY MODE. RESET: BY ISSUING A RESET COMMANDTO THE CONTROL REGISTER, THE DEVICE IS PLACED IN STANDBY MODE. PROGRAM INITIALIZE WITH START FREQUENCY COMMANDTO THE CONTROL REGISTER. AFTER A SUFFICIENTAMOUNT OF SETTLING TIME HAS ELAPSED, PROGRAM START FREQUENCY SWEEP COMMAND IN THE CONTROL REGISTER. POLL STATUS REGISTERTO CHECK IF THE DFT CONVERSION IS COMPLETE. N Y READVALUES FROM REALAND PROGRAM THE INCREMENT FREQUENCY OR IMAGINARY DATA REGISTERS. THE REPEAT FREQUENCY COMMANDTO THE CONTROL REGISTER. Y POLL STATUS REGISTERTO CHECK IF N FREQUENCY SWEEP IS COMPLETE. Y INTPOR OPGORWAEMR -TDHOEWAND 5M9O34DE. 05325-047 Figure 24. Frequency Sweep Flowchart Rev. E | Page 19 of 31

AD5934 Data Sheet REGISTER MAP Table 7. Register Name Register Address Bits Function Control 0x80 D15 to D8 Read/write 0x81 D7 to D0 Read/write Start Frequency 0x82 D23 to D16 Read/write 0x83 D15 to D8 Read/write 0x84 D7 to D0 Read/write Frequency Increment 0x85 D23 to D16 Read/write 0x86 D15 to D8 Read/write 0x87 D7 to D0 Read/write Number of Increments 0x88 D15 to D8 Read/write 0x89 D7 to D0 Read/write Number of Settling Time Cycles 0x8A D15 to D8 Read/write 0x8B D7 to D0 Read/write Status 0x8F D7 to D0 Read only Real Data 0x94 D15 to D8 Read only 0x95 D7 to D0 Read only Imaginary Data 0x96 D15 to D8 Read only 0x97 D7 to D0 Read only CONTROL REGISTER (REGISTER ADDRESS 0x80, Table 9. D11 and D8 to D0 Control Register Map REGISTER ADDRESS 0x81) Bits Description The AD5934 contains a 16-bit control register (Register Address D11 No operation 0x80 and Register Address 0x81) that sets the control modes. D8 PGA gain; 0 = ×5, 1 = ×1 The default value of the control register upon reset is as follows: D7 Reserved; set to 0 D15 to D0 is reset to 0xA008 upon power-up. D6 Reserved; set to 0 The four MSBs of the control register are decoded to provide D5 Reserved; set to 0 control functions, such as performing a frequency sweep, D4 Reset powering down the part, and controlling various other functions D3 Reserved; set to 1 defined in the control register map. D2 Reserved; set to 0 D1 Reserved; set to 0 The user can choose to write only to Register Address 0x80 and D0 Reserved; set to 0 to not alter the contents of Register Address 0x81. Note that the control register should not be written to as part of a block write Table 10. D15 to D12 Control Register Map command. The control register also allows the user to program D15 D14 D13 D12 Description the excitation voltage and set the system clock. A reset command 0 0 0 0 No operation to the control register does not reset any programmed values 0 0 0 1 Initialize with start frequency associated with the sweep (that is, start frequency, number of 0 0 1 0 Start frequency sweep increments, frequency increment). After a reset command, 0 0 1 1 Increment frequency an initialize with start frequency command must be issued to 0 1 0 0 Repeat frequency the control register to restart the frequency sweep sequence 1 0 0 0 No operation (see Figure 24). 1 0 0 1 No operation Table 8. D10 to D9 Control Register Map 1 0 1 0 Power-down mode D10 D9 Range No. Output Voltage Range 1 0 1 1 Standby mode 0 0 1 2.0 V p-p typical 1 1 0 0 No operation 0 1 3 200 mV p-p typical 1 1 0 1 No operation 1 0 4 400 mV p-p typical 1 1 2 1.0 V p-p typical Rev. E | Page 20 of 31

Data Sheet AD5934 Control Register Decode START FREQUENCY REGISTER (REGISTER Initialize with Start Frequency ADDRESS 0x82, REGISTER ADDRESS 0x83, REGISTER ADDRESS 0x84) This command enables the DDS to output the programmed start frequency for an indefinite time. Initially, it is used to The start frequency register contains the 24-bit digital excite the unknown impedance. When the output unknown representation of the frequency from where the subsequent impedance has settled after a time determined by the user, the frequency sweep is initiated. For example, if the user requires user must initiate a start frequency sweep command to begin the sweep to start from a frequency of 30 kHz using a 16.0 MHz the frequency sweep. clock, the user must program the value 0x3D to Register Address 0x82, the value 0x70 to Register Address 0x83, and the value Start Frequency Sweep 0xA3 to Register Address 0x84. Doing this ensures the output In this mode, the ADC starts measuring after the programmed frequency starts at 30 kHz. number of settling time cycles has elapsed. The user has the The start frequency code is ability to program an integer number of output frequency cycles (settling time cycles) to Register Address 0x8A and Register StartFrequencyCode= Address 0x8B before the commencement of the measurement at     each frequency point (see Figure 24).  30kHz  ×227 ≡0x3D70A3 Increment Frequency 16MHz     The increment frequency command is used to step to the next  16  frequency point in the sweep. This usually happens after data The default value of the start frequency register upon reset is as from the previous step is transferred and verified by the DSP. follows: D23 to D0 are not reset at power-up. After the reset When the AD5934 receives this command, it waits for the command, the contents of this register are not reset. programmed number of settling time cycles before beginning FREQUENCY INCREMENT REGISTER (REGISTER the ADC conversion process. ADDRESS 0x85, REGISTER ADDRESS 0x86, Repeat Frequency REGISTER ADDRESS 0x87) There is the facility to repeat the current frequency point The frequency increment register contains a 24-bit representation measurement by issuing a repeat frequency command to the of the frequency increment between consecutive frequency control register. This command allows users to average points along the sweep. For example, if the user requires an successive readings. increment step of 30 Hz using a 16.0 MHz clock, the user must Power-Down Mode program the value 0x00 to Register Address 0x85, the value 0x0F to Register Address 0x86, and the value 0xBA to Register The default state at power-up of the AD5934 is power-down Address 0x87. mode. The control register contains the code 1010,0000,0000,0000 (0xA000). In this mode, both the output and input pins, VOUT The formula for calculating the frequency increment is given by and VIN, are connected internally to GND. FrequencyIncrementCode= Standby Mode     This mode powers up the part for general operation. In standby  10Hz  ×227 ≡0x00053E mode, the VIN and VOUT pins are internally connected to GND. 16MHz     Reset  16  A reset command allows the user to interrupt a sweep. The start The user programs the value 0x00 to Register Address 0x85, frequency, number of increments, and frequency increment the value 0x05 to Register Address 0x86, and the value 0x3E to register contents are not overwritten. An initialize with start Register Address 0x87. frequency command is required to restart the frequency sweep The default value of the frequency increment register upon reset command sequence. is as follows: D23 to D0 are not reset at power-up. After the reset Output Voltage Range command, the contents of this register are not reset. The output voltage range allows the user to program the excitation voltage range at VOUT. PGA Gain The PGA gain allows the user to amplify the response signal into the ADC by a multiplication factor of ×5 or ×1. Rev. E | Page 21 of 31

AD5934 Data Sheet NUMBER OF INCREMENTS REGISTER (REGISTER into the number of settling time cycles register can be increased ADDRESS 0x88, REGISTER ADDRESS 0x89) by a factor of 2 or 4, depending on the status of Bits D10 to D9. The five most significant bits, D15 to D11, are don’t care bits. The default value of the number of increments register upon The maximum number of output cycles that can be programmed is reset is as follows: D8 to D0 are not reset at power-up. After a 511 × 4 = 2044 cycles. For example, consider an excitation signal of reset command, the contents of this register are not reset. 30 kHz, the maximum delay between the programming of this Table 11. Number of Increments Register frequency and the time that this signal is first sampled by the Reg Addr Bits Description Function Format ADC is ≈ 511 × 4 × 33.33 µs = 68.126 ms. The ADC takes 1024 0x88 D15 to D9 Don’t care Read or Integer samples, and the result is stored as real data and imaginary data in write number Register Address 0x94 to Register Address 0x97. The conversion D8 Number of Read or stored process takes approximately 1 ms using a 16.777 MHz clock. increments write in binary format STATUS REGISTER (REGISTER ADDRESS 0x8F) 0x89 D7 to D0 Number of Read or Integer The status register is used to confirm that particular measurement increments write number tests have been successfully completed. Each of the bits from D7 to stored D0 indicate the status of a specific functionality of the AD5934. in binary format Bit D0 and Bit D4 to Bit D7 are treated as don’t care bits; these bits do not indicate the status of any measurement. This register determines the number of frequency points in the The status of Bit D1 indicates the status of a frequency point frequency sweep. The number of frequency points is represented impedance measurement. This bit is set when the AD5934 by a 9-bit word, D8 to D0. D15 to D9 are don’t care bits. This completes the current frequency point impedance measurement. register in conjunction with the start frequency register and the This bit indicates that there is valid real data and imaginary data frequency increment register determine the frequency sweep in Register Address 0x94 to Register Address 0x97. This bit is range for the sweep operation. The maximum number of reset on receipt of a start frequency sweep, increment frequency, increments that can be programmed is 511. repeat frequency, or reset command. This bit is also reset at NUMBER OF SETTLING TIME CYCLES REGISTER power-up. (REGISTER ADDRESS 0x8A, REGISTER ADDRESS The status of Bit D2 indicates the status of the programmed 0x8B) frequency sweep. This bit is set when all programmed increments The default value of the number of settling time cycles register to the number of increments register are complete. This bit is upon reset is as follows: D10 to D0 are not reset at power-up. reset at power-up and on receipt of a reset command. After a reset command, the contents of this register are not reset. Table 12. Status Register 0x8F This register determines the number of output excitation cycles Control Word Description allowed to passthrough the unknown impedance after receipt of 0000 0001 Reserved a start frequency sweep, increment frequency, or repeat frequency 0000 0010 Valid real/imaginary data command, before the ADC is triggered to perform a conversion 0000 0100 Frequency sweep complete of the response signal. The number of settling time cycles register 0000 1000 Reserved value determines the delay between a start frequency sweep/ 0001 0000 Reserved increment frequency/repeat frequency command and the time 0010 0000 Reserved an ADC conversion commences. The number of cycles is 0100 0000 Reserved represented by a 9-bit word, D8 to D0. The value programmed 1000 0000 Reserved Table 13. Number of Settling Times Cycles Register Register Address Bits Description Function Format 0x8A D15 to D11 Don’t care Read or write Integer number stored in binary format D10 to D9 2-bit decode D10 D9 Description 0 0 Default 0 1 No of cycles ×2 1 0 Reserved 1 1 No of cycles ×4 D8 MSB number of settling time cycles 0x8B D7 to D0 Number of settling time cycles Read or write Data Rev. E | Page 22 of 31

Data Sheet AD5934 Valid Real/Imaginary Data REAL AND IMAGINARY DATA REGISTERS (16 BITS— REGISTER ADDRESS 0x94, REGISTER This bit is set when data processing for the current frequency ADDRESS 0x95, REGISTER ADDRESS 0x96, point is finished, indicating real/imaginary data available for reading. The bit is reset when a start frequency sweep/increment REGISTER ADDRESS 0x97) frequency/repeat frequency DDS command is issued. In addition, These registers contain a digital representation of the real and this bit is reset to 0 when a reset command is issued to the imaginary components of the impedance measured for the control register. current frequency point. The values are stored in 16-bit, twos Frequency Sweep Complete complement format. To convert this number to an actual This bit is set when data processing for the last frequency point in impedance value, the magnitude, (Real2+Imaginary2), must the sweep is complete. This bit is reset when a start frequency be multiplied by an admittance/code number (called a gain sweep command is issued to the control register. This bit is also factor) to give the admittance and the result inverted to give the reset when a reset command is issued to the control register. impedance. The gain factor varies for each ac excitation voltage/gain combination. The default value upon reset: these registers are not reset at power-up or on receipt of a reset command. Note that the data in these registers is only valid if Bit D1 in the status register is set, indicating that the processing at the current frequency point is complete. Rev. E | Page 23 of 31

AD5934 Data Sheet SERIAL BUS INTERFACE Control of the AD5934 is carried out via the I2C-compliant Data is sent over the serial bus in sequences of nine clock serial interface protocol. The AD5934 is connected to this bus pulses, 8 bits of data followed by an acknowledge bit, which can as a slave device under the control of a master device. The be from the master or slave device. Data transitions on the data AD5934 has a 7-bit serial bus slave address. When the device is line must occur during the low period of the clock signal and powered up, it has a default serial bus address, 0001101 (0x0D). remain stable during the high period because a low-to-high GENERAL I2C TIMING transition when the clock is high can be interpreted as a stop signal. If the operation is a write operation, the first data byte Figure 25 shows the timing diagram for general read and write after the slave address is a command byte. This tells the slave operations using the I2C-compliant interface. device what to expect next. It may be an instruction telling the The master initiates data transfer by establishing a start condition, slave device to expect a block write, or it may be a register address defined as a high-to-low transition on the serial data line (SDA) that tells the slave where subsequent data is to be written. Because while the serial clock line (SCL) remains high. This indicates data can flow in only one direction as defined by the R/W bit, it that a data stream follows. The slave responds to the start condition is not possible to send a command to a slave device during a and shifts in the next 8 bits, consisting of a 7-bit slave address read operation. Before performing a read operation, it is sometimes (MSB first) and an R/W bit, which determines the direction of necessary to perform a write operation to tell the slave what sort the data transfer, that is, whether data is written to or read from of read operation to expect and/or the address from which data the slave device (0 = write, 1 = read). is to be read. The slave responds by pulling the data line low during the low When all data bytes are read or written, stop conditions are period before the ninth clock pulse, known as the acknowledge established. In write mode, the master pulls the data line high bit, and holding it low during the high period of this clock during the 10th clock pulse to assert a stop condition. In read pulse. All other devices on the bus remain idle while the selected mode, the master device releases the SDA line during the low device waits for data to be read from or written to it. If the R/W period before the ninth clock pulse, but the slave device does bit is 0, the master writes to the slave device. If the R/W bit is 1, not pull it low. This is known as a no acknowledge. The master the master reads from the slave device. then takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. SCL SDA 0 0 0 1 1 0 1 R/W D7 D6 D5 D4 D3 D2 D1 D0 STABRYT MCAOSNTDEIRTION SLAVE ADDRESS BYTE ACKNOAWDL5E9D34GED BY REGISTER ADDRESS ACMKNAOSTWELRE/SDLGAEVDE BY 05325-048 Figure 25. Timing Diagram Rev. E | Page 24 of 31

Data Sheet AD5934 WRITING/READING TO THE AD5934 8. The master asserts a stop condition on SDA to end the transaction. The I2C interface specification defines several different protocols fdoers cdriifbfeerse tnhte t ypproesto ocfo rles auds eadn din w trhiete A oDpe5r9a3t4io. nTsh. eT fhigisu sreecst iino nth is S ADSDLARVEESS W A RAEDGDIRSETSESR A REDGAISTTAER A P 05325-049 Figure 26. Writing Register Data to Register Address section use the abbreviations shown in Table 14. In the AD5934, the write byte protocol is also used to set a Table 14. I2C Abbreviation Table pointer to a register address (see Figure 27). This protocol is Abbreviation Condition used for a subsequent single-byte read from the same address, S Start block read, or block write starting at that address. P Stop To set a register pointer, the following sequence is applied: R Read W Write 1. The master device asserts a start condition on SDA. A Acknowledge 2. The master sends the 7-bit slave address followed by the A No acknowledge write byte/command byte write bit (low). 3. The addressed slave device asserts an acknowledge on SDA. User Command Codes 4. The master sends a pointer command code (see Table 15, an The command codes in Table 15 are used for reading/writing to address pointer = 1011 0000). the interface. They are explained in detail in this section but are 5. The slave asserts an acknowledge on SDA. grouped within Table 15 for easy reference. 6. The master sends a data byte (a register address to where the pointer is to point). Table 15. Command Codes 7. The slave asserts an acknowledge on SDA. Command Code Code Name Code Description 8. The master asserts a stop condition on SDA to end the 1010 0000 Block This command is used when writing transaction. Write multiple bytes to the RAM; see the 1010 0001 Block BThloisc kc oWmrimtea snedc tiiso uns. ed when reading S ADSDLARVEESS W A C1PO0O1MI1NM 0TA0E0NR0D A TORAE DPGDOIRSINETTSE SRTO A P 05325-050 Read multiple bytes from RAM/memory; see Figure 27. Setting Address Pointer to Register Address the Block Read section. BLOCK WRITE 1011 0000 Address This command enables the user to set Pointer the address pointer to any location in In this operation, the master device writes a block of data to a the memory; the data contains the slave device (see Figure 28). The start address for a block write address of the register to which the must previously have been set. In the case of the AD5934, this is pointer should be pointing. done by setting a pointer to set the register address. 1. The master device asserts a start condition on SDA. Write Byte/Command Byte 2. The master sends the 7-bit slave address followed by the In this operation, the master device sends a byte of data to the write bit (low). slave device. The write byte can either be a data byte write to a 3. The addressed slave device asserts an acknowledge on SDA. Register Address or it can be a command operation. To write data to a register, the command sequence is as follows (see Figure 26): 4. The master sends an 8-bit command code (1010 0000) that tells the slave device to expect a block write. 1. The master device asserts a start condition on SDA. 5. The slave asserts an acknowledge on SDA. 2. The master sends the 7-bit slave address followed by the 6. The master sends a data byte that tells the slave device the write bit (low). number of data bytes to be sent to it. 3. The addressed slave device asserts an acknowledge on SDA. 7. The slave asserts an acknowledge on SDA. 4. The master sends a register address. 8. The master sends the data bytes. 5. The slave asserts an acknowledge on SDA. 9. The slave asserts an acknowledge on SDA after each data byte. 6. The master sends a data byte. 10. The master asserts a stop condition on SDA to end the transaction. 7. The slave asserts an acknowledge on SDA. S ADSDLARVEESS W A BWLROICTEK A BYNTUEMS BWERRITE A BYTE 0 A BYTE 1 A BYTE 2 A P 05325-051 Figure 28. Writing a Block Write Rev. E | Page 25 of 31

AD5934 Data Sheet READ OPERATIONS Block Read The AD5934 uses two I2C read protocols: the receive byte and In this operation, the master device reads a block of data from a the block read. slave device (see Figure 30). The start address for a block read must previously have been set by setting the address pointer. Receive Byte 1. The master device asserts a start condition on SDA. In the AD5934, the receive byte protocol is used to read a single byte of data from a register address whose address has previously 2. The master sends the 7-bit slave address followed by the been set by setting the address pointer. write bit (low). 3. The addressed slave device asserts an acknowledge on SDA. In this operation, the master device receives a single byte from a slave device as follows (see Figure 29): 4. The master sends a command code (1010 0001) that tells the slave device to expect a block read. 1. The master device asserts a start condition on SDA. 5. The slave asserts an acknowledge on SDA. 2. The master sends the 7-bit slave address followed by the 6. The master sends a byte-count data byte that tells the slave read bit (high). how many data bytes to expect. 3. The addressed slave device asserts an acknowledge on SDA. 7. The slave asserts an acknowledge on SDA. 4. The master receives a data byte. 8. The master asserts a repeat start condition on SDA. This is required to set the read bit high. 5. The master asserts a no acknowledge on SDA (the slave 9. The master sends the 7-bit slave address followed by the needs to check that master has received data). read bit (high). 6. The master asserts a stop condition on SDA and the 10. The slave asserts an acknowledge on SDA. transaction ends. 11. The master receives the data bytes. S ADSDLARVEESS R A REDGAISTTAER A P 05325-052 12. Tdahtea mbyatset.e r asserts an acknowledge on SDA after each Figure 29. Reading Register Data 13. A no acknowledge is generated after the last byte to signal the end of the read. 14. The master asserts a stop condition on SDA to end the transaction. S ADSDLARVEESS W A BRLEOACDK A BYNTUEMSB REERAD A S ADSDLARVEESS R A BYTE 0 A BYTE 1 A BYTE 2 A P 05325-053 Figure 30. Performing a Block Read Rev. E | Page 26 of 31

Data Sheet AD5934 TYPICAL APPLICATIONS MEASURING SMALL IMPEDANCES The value of the output series resistance depends upon the selected output excitation range at VOUT and has a tolerance The AD5934 is capable of measuring impedance values up to from device to device like all discrete resistors manufactured in 10 MΩ if the system gain settings are chosen correctly for the a silicon fabrication process. Typical values of the output series impedance subrange of interest. resistance are outlined in Table 16. If the user places a small impedance value (≤500 Ω over the sweep frequency of interest) between the VOUT and VIN pins, Table 16. Output Series Resistance (ROUT) vs. Excitation Range it results in an increase in signal current flowing through the Parameter Value (Typ) Output Series Resistance Value impedance for a fixed excitation voltage in accordance with Range 1 2 V p-p 200 Ω typical Ohm’s law. The output stage of the transmit side amplifier Range 2 1 V p-p 2.4 kΩ typical available at the VOUT pin may not be able to provide the Range 3 0.4 V p-p 1.0 kΩ typical required increase in current through the impedance. To have a Range 4 0.2 V p-p 600 Ω typical unity gain condition about the receive side I-V amplifier, the Therefore, to accurately calibrate the AD5934 to measure small user needs to have a similar small value of feedback resistance impedances, it is necessary to reduce the signal current by for system calibration as outlined in the Gain Factor Setup attenuating the excitation voltage sufficiently and also account Configuration section. The voltage presented at the VIN pin is for the R value and factor it into the gain factor calculation hard biased at VDD/2 due to the virtual earth on the receive OUT (see the Gain Factor Calculation section). side I-V amplifier. The increased current sink/source requirement placed on the output of the receive side I-V Measuring the ROUT value during device characterization is amplifier may also cause the amplifier to operate outside of the achieved by selecting the appropriate output excitation range at linear region. This causes significant errors in subsequent VOUT and sinking and sourcing a known current at the pin impedance measurements. (for example, ±2 mA) and measuring the change in dc voltage. The output series resistance can be calculated by measuring the The value of the output series resistance, R , (see Figure 31) OUT inverse of the slope (that is, 1/slope) of the resultant I-V plot. at the VOUT pin must be taken into account when measuring small impedances (Z ), specifically when the value of A circuit that helps to minimize the effects of the issues UNKNOWN the output series resistance is comparable to the value of the previously outlined is shown in Figure 31. The aim of this impedance under test (Z ). If the R value is unac- circuit is to place the AD5934 system gain within its linear UNKNOWN OUT counted for in the system calibration (that is, the gain factor range when measuring small impedances by using an additional calculation) when measuring small impedances, there is an external amplifier circuit along the signal path. The external introduced error into any subsequent impedance measurement amplifier attenuates the peak-to-peak excitation voltage at that takes place. The introduced error depends on the relative VOUT by a suitable choice of resistors (R1 and R2), thereby magnitude of the impedance being tested compared to the value reducing the signal current flowing through the impedance and of the output series resistance. minimizing the effect of the output series resistance in the 2V p-p impedance calculations. TRANSMIT SIDE OUTPUTAMPLIFIER R1 In the circuit shown in Figure 31, ZUNKNOWN recognizes the ROUT VOUT R2 output series resistance of the external amplifier which is DDS typically much less than 1 Ω with feedback applied depending VDD AD8531 upon the op amp device used (for example, AD820, AD8641, AD820 AD8531) as well as the load current, bandwidth, and gain. 20kΩ AD8641 VDD/2 RFB 20kΩ 1µF AD8627 The key point is that the output impedance of the external amplifier in Figure 31 (which is also in series with Z ) UNKNOWN RFB has a far less significant effect on gain factor calibration and PGA I-V VIN ZUNKNOWN subsequent impedance readings in comparison to connecting VDD/2 05324-148 tsherei esms walilt him Rped)a.n Tche ed eirxetcetrlnya tlo a tmhpe lVifOierU bTu pffienr s( athned udnirkencotlwy nin OUT Figure 31. Additional External Amplifier Circuit for impedance from the effects of R and introduces a smaller Measuring Small Impedances OUT output impedance in series with Z . UNKNOWN Rev. E | Page 27 of 31

AD5934 Data Sheet For example, if the user measures Z that is known to The gain factor calculated is for a 100 Ω resistor connected UNKNOWN have a small impedance value within the range of 90 Ω to between VOUT and VIN, assuming the output series resistance 110 Ω over the frequency range of 30 kHz to 32 kHz, the of the external amplifier is small enough to be ignored. user may not be in a position to measure R directly in OUT When biasing the circuit shown in Figure 31, note that the the factory/lab. Therefore, the user may choose to add on receive side of the AD5934 is hard-biased about VDD/2 by an extra amplifier circuit like that shown in Figure 31 to the design. Therefore, to prevent the output of the external signal path of the AD5934. The user must ensure that the amplifier (attenuated AD5934 Range 1 excitation signal) from chosen external amplifier has a sufficiently low output series saturating the receive side amplifiers of the AD5934, a voltage resistance over the bandwidth of interest in comparison to the equal to VDD/2 must be applied to the noninverting terminal impedance range under test (for an op amp selection guide, see of the external amplifier. http://www.analog.com/opamps). Most amplifiers from Analog BIOMEDICAL: NONINVASIVE BLOOD IMPEDANCE Devices have a curve of closed-loop output impedance vs. MEASUREMENT frequency at different amplifier gains to determine the output series impedance at the frequency of interest. When a known strain of a virus is added to a blood sample that already contains a virus, a chemical reaction takes place whereby The system settings are as follows: the impedance of the blood under certain conditions changes. VDD = 3.3 V By characterizing this effect across different frequencies, it is VOUT = 2 V p-p possible to detect a specific strain of virus. For example, a strain R2 = 20 kΩ of the disease exhibits a certain characteristic impedance at one frequency but not at another, resulting in the need to sweep R1 = 4 kΩ different frequencies to check for different viruses. The AD5934, Gain setting resistor = 500 Ω with its 27-bit phase accumulator, allows for subhertz frequency Z = 100 Ω tuning. UNKNOWN The AD5934 can be used to inject a stimulus signal through the PGA setting = ×1 blood sample via a probe. The response signal is analyzed and To attenuate the excitation voltage at VOUT, choose a ratio the effective impedance of the blood is tabulated. The AD5934 of R1/R2. With the values of R1 = 4 kΩ and R2 = 20 kΩ, is ideal for this application because it allows the user to tune to attenuate the signal by 1/5th of 2 V p-p = 400 mV. The the specific frequency required for each test. maximum current flowing through the impedance is 400 mV/ 90 Ω = 4.4 mA. 1 16 ADuC702x The system is subsequently calibrated using the usual method TOP VIEW 2 15 (Not to Scale) with a midpoint impedance value of 100 Ω, a calibration AD5934 resistor, and a feedback resistor at a midfrequency point in the 3 TOP VIEW 14 RFB (Not to Scale) sweep. The dynamic range of the input signal to the receive side 4 13 of the AD5934 can be improved by increasing the value of the 5 12 I-V gain resistor at the RFB pin. For example, increasing the I-V 6 11 gain setting resistor at the RFB pin increases the peak-to-peak signal presented to the ADC input from 400 mV (RFB = 100 Ω) 7 10 PROBE to 2 V p-p (RFB = 500 Ω). 8 9 7V ADR43x 2 6 0.1µF 10µF 4 05325-057 Figure 32. Measuring a Blood Sample for a Strain of Virus Rev. E | Page 28 of 31

Data Sheet AD5934 SENSOR/COMPLEX IMPEDANCE MEASUREMENT ELECTRO-IMPEDANCE SPECTROSCOPY The operational principle of a capacitive proximity sensor is The AD5934 has found use in the area of corrosion monitoring. based on the change of a capacitance in a RLC resonant circuit. Corrosion in a metal, such as aluminum, which is used in air This leads to changes in the resonant frequency of the RLC craft and ships, requires continuous assessment because the metal circuit, which can be evaluated as shown Figure 33. is exposed to a wide variety of conditions, such as temperature and moisture. The AD5934 offers an accurate and compact solution It is first required to tune the RLC circuit to the area of resonance. for this type of measurement compared to the large and expensive At the resonant frequency, the impedance of the RLC circuit is existing units on the market. at a maximum. Therefore, a programmable frequency sweep and tuning capability is required, which is provided by the AD5934. Mathematically the corrosion of a metal is modeled using a RC network that consists of a resistance, R, in series with a parallel RESONANT CHANGE IN S FREQUENCY RESONANCE DUE resistor and capacitor, R and C. A system metal would typically TO APPROACHING P P OBJECT have values as follows: RS is 10 Ω to 10 kΩ, RP is 1 kΩ to 1 MΩ, E (Ω) and CP is 5 µF to 70 µF. C N The frequency range of interest when monitoring corrosion is A D E 0.1 Hz to 100 kHz. P M Y I To ensure that the measurement itself does not introduce a T MI corrosive effect, the metal needs to be excited with minimal XI RO voltage, typically in the 200 mV region, which the AD5934 is P capable of outputting. A nearby processor or control unit, such as the ADuc702x, would log a single impedance sweep from FREQFUOENCY (Hz) 05325-058 0b.a1c kk Htoz at oc o1n0t0r oklH uzn eitv. eTroy a1c0h mieivneu styesst eamnd a dcocuwrnalcoya fdr othme trheseu lts Figure 33. Detecting a Change in Resonant Frequency 0.1 kHz to 1 kHz region, the system clock needs to be scaled down from the 16.776 MHz nominal clock frequency to 500 kHz, An example of the use of this type of sensor is for a train proximity typically. The clock scaling can be achieved digitally using an measurement system. The magnetic fields of the train approaching external direct digital synthesizer, such as the AD9834, as a on the track change the resonant frequency to an extent that can programmable divider that supplies a clock signal to MCLK be characterized. This information can be sent back to a mainframe and that can be controlled digitally by the nearby microprocessor. system to show the train location on the network. Another application for the AD5934 is in parked vehicle detection. The AD5934 is placed in an embedded unit connected to a coil of wire underneath the parking location. The AD5934 outputs a single frequency within the 80 kHz to 100 kHz frequency range, depending upon the wire composition. The wire can be modeled as a resonant circuit. The coil is calibrated with a known impedance value and at a known frequency. The impedance of the loop is monitored constantly. If a car is parked over the coil, the impedance of the coil changes and the AD5934 detects the presence of the car. Rev. E | Page 29 of 31

AD5934 Data Sheet LAYOUT AND CONFIGURATION POWER SUPPLY BYPASSING AND GROUNDING The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch When accuracy is important in a circuit, carefully consider effects on the supply line. Clocks and other fast switching digital the power supply and ground return layout on the board. The signals should be shielded from other parts of the board by printed circuit board (PCB) containing the AD5934 should have digital ground. Avoid crossover of digital and analog signals separate analog and digital sections, each having its own area of if possible. When traces cross on opposite sides of the board, the board. If the AD5934 is in a system where other devices ensure that they run at right angles to each other to reduce feed- require an AGND-to-DGND connection, the connection should through effects on the board. The best board layout technique be made at one point only. This ground point should be as close is the microstrip technique where the component side of the board as possible to the AD5934. is dedicated to the ground plane only and the signal traces are The power supply to the AD5934 should be bypassed with 10 µF placed on the solder side. However, this is not always possible and 0.1 µF capacitors. The capacitors should be physically as with a 2-layer board. close as possible to the device, with the 0.1 µF capacitor ideally right up against the device. The 10 µF capacitors are the tantalum bead type. It is important that the 0.1 µF capacitor has low effective series resistance (ESR) and effective series inductance (ESI); common ceramic types of capacitors are suitable. The 0.1 µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. Rev. E | Page 30 of 31

Data Sheet AD5934 OUTLINE DIMENSIONS 6.50 6.20 5.90 16 9 5.60 5.30 5.00 8.20 7.80 1 7.40 8 1.85 0.25 2.00 MAX 1.75 0.09 1.65 COPL0A.01N.00A5R MITIYN 0.65 BSC 00..3282 SPLEAATNIENG 840°°° 000...975555 COMPLIANTTO JEDEC STANDARDS MO-150-AC 060106-A Figure 34. 16-Lead Shrink Small Outline Package [SSOP] (RS-16) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD5934YRSZ −40°C to +125°C 16-Lead Shrink Small Outline Package (SSOP) RS-16 AD5934YRSZ-REEL7 −40°C to +125°C 16-Lead Shrink Small Outline Package (SSOP) RS-16 1 Z = RoHS Compliant Part. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2005–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05325-0-9/17(E) Rev. E | Page 31 of 31

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5934YRSZ AD5934YRSZ-REEL7