True 18-Bit, Voltage Output DAC ±0.5 LSB INL, ±0.5 LSB DNL Data Sheet AD5781 FEATURES FUNCTIONAL BLOCK DIAGRAM Single 18-bit DAC, ±0.5 LSB INL VCC VDD VREFPF VREFPS 7.5 nV/√Hz noise spectral density 0.05 LSB long-term linearity stability AD5781 6.8kΩ 6.8kΩ IOVCC A1 RFB <0.05 ppm/°C temperature drift R1 RFB INV 1 µs settling time SDIN INPUT 1.4 nV-sec glitch impulse SCLK RESGHISIFTTER 18 RDEAGC 18 1D8-ABCIT VOUT SYNC AND Operating temperature range: −40°C to +125°C CONTROL SDO LOGIC 20-lead TSSOP package 6kΩ Wide power supply range of up to ±16.5 V LDAC 35 MHz Schmitt triggered digital interface CLR POWER-ON-RESET 1.8 V compatible digital interface RESET AND CLEAR LOGIC APPLICATIONS DGND VSS AGND VREFNFVREFNS 09092-001 Medical instrumentation Figure 1. Test and measurement Industrial control Scientific and aerospace instrumentation Data acquisition systems Digital gain and offset adjustment Power supply control GENERAL DESCRIPTION The AD57811 is a single 18-bit, unbuffered voltage output digital- PRODUCT HIGHLIGHTS to-analog converter (DAC) that operates from a bipolar supply of 1. True 18-Bit Accuracy. up to 33 V. The AD5781 accepts a positive reference input range 2. Wide Power Supply Range of Up to ±16.5 V. of 5 V to V − 2.5 V and a negative reference input range of V DD SS 3. −40°C to +125°C Operating Temperature Range. + 2.5 V to 0 V. The AD5781 offers a relative accuracy specifi- 4. Low 7.5 nV/√Hz Noise. cation of ±0.5 LSB maximum, and operation is guaranteed 5. Low 0.05 ppm/°C Temperature Drift. monotonic with a ±0.5 LSB differential nonlinearity (DNL) maximum specification. Table 1. Complementary Devices Part No. Description The part uses a versatile 3-wire serial interface that operates at AD8675 Ultraprecision, 36 V, 2.8 nV/√Hz rail-to-rail clock rates of up to 35 MHz and is compatible with standard output op amp serial peripheral interface (SPI), QSPI™, MICROWIRE™, and AD8676 Ultraprecision, 36 V, 2.8 nV/√Hz dual rail-to- DSP interface standards. The part incorporates a power-on rail output op amp reset circuit that ensures that the DAC output powers up to 0 V ADA4898-1 High voltage, low noise, low distortion, unity and in a known output impedance state and remains in this state gain stable, high speed op amp until a valid write to the device takes place. The part provides an output clamp feature that places the output in a defined load Table 2. Related Devices state. Part No. Description AD5791 20-bit, 1 ppm accurate DAC AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC 1 Protected by U.S. Patent No 7,884,747, and other patents are pending. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5781 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Hardware Control Pins .............................................................. 20 Applications ....................................................................................... 1 On-Chip Registers ...................................................................... 21 Functional Block Diagram .............................................................. 1 AD5781 Features ............................................................................ 24 General Description ......................................................................... 1 Power-On to 0 V ......................................................................... 24 Product Highlights ........................................................................... 1 Power-Up Sequence ................................................................... 24 Revision History ............................................................................... 2 Configuring the AD5781 .......................................................... 24 Specifications ..................................................................................... 3 DAC Output State ...................................................................... 24 Timing Characteristics ................................................................ 5 Linearity Compensation ............................................................ 24 Absolute Maximum Ratings ............................................................ 7 Output Amplifier Configuration.............................................. 24 ESD Caution .................................................................................. 7 Applications Information .............................................................. 26 Pin Configuration and Function Description .............................. 8 Typical Operating Circuit ......................................................... 26 Typical Performance Characteristics ............................................. 9 Evaluation Board ........................................................................ 26 Terminology .................................................................................... 17 Outline Dimensions ....................................................................... 27 Theory of Operation ...................................................................... 19 Ordering Guide .......................................................................... 27 DAC Architecture ....................................................................... 19 REVISION HISTORY 4/2018—Rev. D to Rev. E 8/2011—Rev. 0 to Rev. A Added Power-Up Sequence Section and Figure 50; Renumbered Change to Features Section .............................................................. 1 Sequentially ..................................................................................... 24 Changes to Specifications Section ................................................... 3 Deleted t Parameter from Timing Specifications Section, 14 7/2013—Rev. C to Rev. D Table 4 .................................................................................................5 Changes to t Test Conditions/Comments and Endnote 2 ......... 5 Changes to Figure 2 and Figure 3 .................................................... 6 1 Deleted Figure 4 ................................................................................ 7 Changes to Figure 4 ........................................................................... 7 Deleted Daisy-Chain Operation Section ..................................... 20 Replaced Figure 42 and Figure 43 ................................................ 16 Added New Figure 44, Figure 45, and Figure 46, Renumbered 11/2011—Rev. B to Rev. C Sequentially ..................................................................................... 16 Added Figure 48; Renumbered Sequentially .............................. 17 Change to Ideal Transfer Function Equation .............................. 22 7/2010—Revision 0: Initial Version 9/2011—Rev. A to Rev. B Added Patent Note ........................................................................... 1 Changes to Table 3 ............................................................................ 3 Changes to OPGND Description, Table 12 ................................ 23 Rev. E | Page 2 of 27

Data Sheet AD5781 SPECIFICATIONS V = +12.5 V to +16.5 V, V = −16.5 V to −12.5 V, V = +10 V, V = −10 V, V = +2.7 V to +5.5 V, IOV = +1.71 V to +5.5 V, DD SS REFP REFN CC CC R = unloaded, C = unloaded, T to T , unless otherwise noted. L L MIN MAX Table 3. A, B Version1 Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE2 Resolution 18 Bits Integral Nonlinearity Error (Relative −0.5 ±0.25 +0.5 LSB B version, V = +10 V, V = −10 V REFP REFN Accuracy) −0.5 ±0.25 +0.5 LSB B version, V = +10 V, V = 0 V3 REFP REFN −1 ±0.5 +1 LSB B version, V = +5 V, V = 0 V3 REFP REFN −4 ±2 +4 LSB A version4 Differential Nonlinearity Error −0.5 ±0.25 +0.5 LSB V = +10 V, V = −10 V REFP REFN −0.5 ±0.25 +0.5 LSB V = +10 V, V = 0 V3 REFP REFN −1 ±0.5 +1 LSB V = +5 V, V = 0 V3 REFP REFN Linearity Error Long-Term Stability5 0.04 LSB After 500 hours at T = 125°C A 0.05 LSB After 1000 hours at T = 125°C A 0.03 LSB After 1000 hours t T = 100°C A Full-Scale Error −1.75 ±0.25 +1.75 LSB V = +10 V, V = −10 V3 REFP REFN −2.75 ±0.062 +2.75 LSB V = +10 V, V = 0 V3 REFP REFN −5.25 ±0.2 +5.25 LSB V = +5 V, V = 0 V3 REFP REFN −1 ±0.25 +1 LSB V = +10 V, V = −10 V3, REFP REFN T = 0°C to 105°C A −1 ±0.062 +1 LSB V = 10 V, V = 0 V3, T = 0°C to 105°C REFP REFN A −1.5 ±0.2 +1.5 LSB V = 5 V, V = 0 V3, T = 0°C to 105°C REFP REFN A Full-Scale Error Temperature Coefficient3 ±0.02 ppm FSR/°C Zero-Scale Error −1.75 ±0.025 +1.75 LSB V = +10 V, V = −10 V3 REFP REFN −2.5 ±0.38 +2.5 LSB V = +10 V, V = 0 V3 REFP REFN −5.25 ±0.19 +5.25 LSB V = +5 V, V = 0 V3 REFP REFN −1 ±0.025 +1 LSB V = +10 V, V = −10 V3, REFP REFN T = 0°C to 105°C A −1 ±0.38 +1 LSB V = 10 V, V = 0 V3, T = 0°C to 105°C REFP REFN A −1.5 ±0.19 +1.5 LSB V = 5 V, V = 0 V3, T = 0°C to 105°C REFP REFN A Zero-Scale Error Temperature Coefficient3 ±0.04 ppm FSR/°C Gain Error −6 ±0.3 +6 ppm FSR V = +10 V, V = −10 V3 REFP REFN −10 ±0.4 +10 ppm FSR V = +10 V, V = 0 V3 REFP REFN −20 ±0.4 +20 ppm FSR V = +5 V, V = 0 V3 REFP REFN Gain Error Temperature Coefficient3 ±0.04 ppm FSR/°C R1, R Matching 0.01 % FB OUTPUT CHARACTERISTICS3 Output Voltage Range V V V REFN REFP Output Slew Rate 50 V/µs Unbuffered output, 10 MΩ||20 pF load Output Voltage Settling Time 1 µs 10 V step to 0.02%, using AD845 buffer in unity-gain mode 1 µs 125 code step to ±1 LSB6 Output Noise Spectral Density 7.5 nV/√Hz at 1 kHz, DAC code = midscale 7.5 nV/√Hz at 10 kHz, DAC code = midscale 7.5 nV/√Hz at 100 kHz, DAC code = midscale Output Voltage Noise 1.1 µV p-p DAC code = midscale, 0.1 Hz to 10 Hz bandwidth7 Rev. E | Page 3 of 27

AD5781 Data Sheet A, B Version1 Parameter Min Typ Max Unit Test Conditions/Comments Midscale Glitch Impulse 3.1 nV-sec V = +10 V, V = −10 V REFP REFN 1.7 nV-sec V = +10 V, V = 0 V REFP REFN 1.4 nV-sec V = +5 V, V = 0 V REFP REFN MSB Segment Glitch Impulse6 9.1 nV-sec V = +10 V, V = −10 V, see Figure 42 REFP REFN 3.6 nV-sec V = 10 V, V = 0 V, see Figure 43 REFP REFN 1.9 nV-sec V = 5 V, V = 0 V, see Figure 44 REFP REFN Output Enabled Glitch Impulse 45 nV-sec On removal of output ground clamp Digital Feedthrough 0.4 nV-sec DC Output Impedance (Normal Mode) 3.4 kΩ DC Output Impedance (Output 6 kΩ Clamped to Ground) Spurious Free Dynamic Range 100 dB 1 kHz tone, 10 kHz sample rate Total Harmonic Distortion 97 dB 1 kHz tone, 10 kHz sample rate REFERENCE INPUTS3 V Input Range 5 V − 2.5 V V REFP DD V Input Range V + 2.5 V 0 REFN SS DC Input Impedance 5 6.6 kΩ V , V , code dependent, REFP REFN typical at midscale code Input Capacitance 15 pF V , V REFP REFN LOGIC INPUTS3 Input Current8 −1 +1 µA Input Low Voltage, V 0.3 × IOV V IOV = 1.71 V to 5.5 V IL CC CC Input High Voltage, V 0.7 × IOV V IOV = 1.71 V to 5.5 V IH CC CC Pin Capacitance 5 pF LOGIC OUTPUT (SDO)3 Output Low Voltage, V 0.4 V IOV = 1.71 V to 5.5 V, sinking 1 mA OL CC Output High Voltage, V IOV − 0.5 V IOV = 1.71 V to 5.5 V, sourcing 1 mA OH CC CC High Impedance Leakage Current ±1 µA High Impedance Output Capacitance 3 pF POWER REQUIREMENTS All digital inputs at DGND or IOV CC V 7.5 V + 33 V DD SS V V − 33 −2.5 V SS DD V 2.7 5.5 V CC IOV 1.71 5.5 V IOV ≤ V CC CC CC I 4.2 5.2 mA DD I 4 4.9 mA SS I 600 900 µA CC IOI 52 140 µA SDO disabled CC DC Power Supply Rejection Ratio3, 9 ±0.6 µV/V V ± 10%, V = 15 V DD SS ±0.6 µV/V V ± 10%, V = 15 V SS DD AC Power Supply Rejection Ratio3 95 dB V ± 200 mV, 50 Hz/60 Hz, V = −15 V DD SS 95 dB V ± 200 mV, 50 Hz/60 Hz, V = 15 V SS DD 1 Temperature range: −40°C to +125°C, typical conditions: TA = 25°C, VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V. 2 Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer. 3 Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified. 4 Valid for all voltage reference spans. 5 Guaranteed by design and characterization, not production tested. 6 The AD5781 is configured in the bias compensation mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer, lead capacitance, and so forth). 7 Includes noise contribution from AD8676BRZ voltage reference buffers. 8 Current flowing in an individual logic pin. 9 Includes PSRR of AD8676BRZ voltage reference buffers. Rev. E | Page 4 of 27

Data Sheet AD5781 TIMING CHARACTERISTICS V = 2.7 V to 5.5 V; all specifications T to T , unless otherwise noted. CC MIN MAX Table 4. Limit1 Parameter IOV = 1.71 V to 3.3 V IOV = 3.3 V to 5.5 V Unit Test Conditions/Comments CC CC t 2 40 28 ns min SCLK cycle time 1 92 60 ns min SCLK cycle time (readback mode) t 15 10 ns min SCLK high time 2 t 9 5 ns min SCLK low time 3 t 5 5 ns min SYNC to SCLK falling edge setup time 4 t 2 2 ns min SCLK falling edge to SYNC rising edge hold time 5 t 48 40 ns min Minimum SYNC high time 6 t 8 6 ns min SYNC rising edge to next SCLK falling edge ignore 7 t 9 7 ns min Data setup time 8 t 12 7 ns min Data hold time 9 t 13 10 ns min LDAC falling edge to SYNC falling edge 10 t 20 16 ns min SYNC rising edge to LDAC falling edge 11 t 14 11 ns min LDAC pulse width low 12 t 130 130 ns typ LDAC falling edge to output response time 13 t 130 130 ns typ SYNC rising edge to output response time (LDAC tied low) 14 t 50 50 ns min CLR pulse width low 15 t 140 140 ns typ CLR pulse activation time 16 t 0 0 ns min SYNC falling edge to first SCLK rising edge 17 t 65 60 ns max SYNC rising edge to SDO tristate (C = 50 pF) 18 L t 62 45 ns max SCLK rising edge to SDO valid (C = 50 pF) 19 L t 0 0 ns min SYNC rising edge to SCLK rising edge ignore 20 t 35 35 ns typ RESET pulse width low 21 t 150 150 ns typ RESET pulse activation time 22 1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2. 2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback mode. Rev. E | Page 5 of 27

AD5781 Data Sheet t t 1 7 SCLK 1 2 24 t6 t3 t2 t t 4 5 SYNC t 9 t 8 SDIN DB23 DB0 t10 t t12 11 LDAC VOUT t13 VOUT t14 t 15 CLR t 16 VOUT t 21 RESET t 22 VOUT 09092-002 Figure 2. Write Mode Timing Diagram t17 t1 t7 t20 SCLK 1 2 24 1 2 24 t6 t3 t2 t t t4 t5 17 5 SYNC t 9 t 8 SDIN DB23 DB0 INPUTWORDSPECIFIES NOPCONDITION t REGISTERTOBEREAD 18 t 19 SDO DB23REGISTERCONTENTSCLOCKED OUTDB0 09092-003 Figure 3. Readback Mode Timing Diagram Rev. E | Page 6 of 27

Data Sheet AD5781 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents of up to A Stresses at or above those listed under Absolute Maximum 100 mA do not cause SCR latch-up. Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these Table 5. or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Operation beyond V to AGND −0.3 V to +34 V DD the maximum operating conditions for extended periods may V to AGND −34 V to +0.3 V SS affect product reliability. V to V −0.3 V to +34 V DD SS V to DGND −0.3 V to +7 V This device is a high performance integrated circuit with an CC IOV to DGND −0.3 V to V + 3 V or +7 V ESD rating of 1.5 kV, and it is ESD sensitive. Proper precautions CC CC (whichever is less) should be taken for handling and assembly. Digital Inputs to DGND −0.3 V to IOV + 0.3 V or CC ESD CAUTION +7 V (whichever is less) V to AGND −0.3 V to V + 0.3 V OUT DD V to AGND −0.3 V to V + 0.3 V REFPF DD V to AGND −0.3 V to V + 0.3 V REFPS DD V to AGND V − 0.3 V to +0.3 V REFNF SS VREFNS to AGND VSS − 0.3 V to +0.3 V DGND to AGND −0.3 V to +0.3 V Operating Temperature Range, T A Industrial −40°C to + 125°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature, 150°C T max J Power Dissipation (T max − T )/θ J A JA TSSOP Package θ Thermal Impedance 143°C/W JA θ Thermal Impedance 45°C/W JC Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 1.5 kV Rev. E | Page 7 of 27

AD5781 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTION INV 1 20 RFB VOUT 2 19 AGND VREFPS 3 AD5781 18 VSS VREFPF 4 TOP VIEW 17 VREFNS (Not to Scale) VDD 5 16 VREFNF RESET 6 15 DGND CLR 7 14 SYNC LDAC 8 13 SCLK VCC 9 12 SDIN IOVCC 10 11 SDO 09092-005 Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 INV Connection to Inverting Input of External Amplifier. See the AD5781 Features section for further details. 2 V Analog Output Voltage. OUT 3 V Positive Reference Sense Voltage Input. A voltage range of 5 V to V − 2.5 V can be connected. A unity gain amplifier REFPS DD must be connected at this pin, in conjunction with the V pin. See the AD5781 Features section for further details. REFPF 4 V Positive Reference Force Voltage Input. A voltage range of 5 V to V − 2.5 V can be connected. A unity gain amplifier REFPF DD must be connected at these pin, in conjunction with the V pin. See AD5781 Features section for further details. REFPS 5 V Positive Analog Supply Connection. A voltage range of 7.5 V to 16.5 V can be connected. V should be decoupled to DD DD AGND. 6 RESET Active Low Reset Logic Input Pin. Asserting this pin returns the AD5781 to its power-on status. 7 CLR Active Low Clear Logic Input Pin. Asserting this pin sets the DAC register to a user defined value (see Table 13) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. 8 LDAC Active Low Load DAC Logic Input Pin. This is used to update the DAC register and, consequently, the analog output. When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. The LDAC pin should not be left unconnected. 9 V Digital Supply Connection. A voltage in the range of 2.7 V to 5.5 V can be connected. V should be decoupled to DGND. CC CC 10 IOV Digital Interface Supply Pin. Digital threshold levels are referenced to the voltage applied to this pin. A voltage range of CC 1.71 V to 5.5 V can be connected. IOV should not be allowed to exceed V . CC CC 11 SDO Serial Data Output Pin. Data is clocked out on the rising edge of the serial clock input. 12 SDIN Serial Data Input Pin. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at clock rates of up to 35 MHz. 14 SYNC Active Low Digital Interface Synchronization Input Pin. This is the frame synchronization signal for the input data. When SYNC is low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks. The input shift register is updated on the rising edge of SYNC. 15 DGND Ground Reference Pin for Digital Circuitry. 16 V Negative Reference Force Voltage Input. A voltage range of V + 2.5 V to 0 V can be connected. A unity gain amplifier REFNF SS must be connected at this pin, in conjunction with the V pin. See the AD5781 Features section for further details. REFNS 17 V Negative Reference Sense Voltage Input. A voltage range of V + 2.5 V to 0 V can be connected. A unity gain amplifier REFNS SS must be connected at these pin, in conjunction with the V pin. See the AD5781 Features section for further details. REFNF 18 V Negative Analog Supply Connection. A voltage range of −16.5 V to −2.5 V can be connected. V should be decoupled to SS SS AGND. 19 AGND Ground Reference Pin for Analog Circuitry. 20 RFB Feedback Connection for External Amplifier. See the AD5781 Features section for further details. Rev. E | Page 8 of 27

Data Sheet AD5781 TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.5 TA = +125°C AD8676 REFERENCE BUFFERS TA = +25°C 0.4 TA = +25°C 0.4 AD8675 OUTPUT BUFFER TA = –40°C TA = –40°C VREFP = +10V TA = +125°C 0.3 0.3 VREFN = 0V VDD = +15V 0.2 0.2 VSS = –15V B) B) LS 0.1 LS 0.1 R ( R ( O 0 O 0 R R R R L E–0.1 L E–0.1 N N I–0.2 AD8676 REFERENCE BUFFERS I–0.2 AD8675 OUTPUT BUFFER –0.3 VREFP = +10V –0.3 VREFN = –10V –0.4 VDD = +15V –0.4 VSS = –15V –0.50 50000 10000D0AC CO15D0E000 200000 25000009092-006 –0.50 50000 10000D0AC CO15D0E000 200000 250000 09092-009 Figure 5. Integral Nonlinearity Error vs. DAC Code, ±10 V Span Figure 8. Integral Nonlinearity Error vs. DAC Code, ±10 V Span, X2 Gain Mode 0.5 0.5 AD8676 REFERENCE BUFFERS TA = +125°C AD8676 REFERENCE BUFFERS TA = +125°C 0.4 AD8675 OUTPUT BUFFER TA = +25°C 0.4 AD8675 OUTPUT BUFFER TA = +25°C TA = –40°C VREFP = +10V TA = –40°C 0.3 0.3 VREFN = –10V VDD = +15V B) 0.2 B) 0.2 VSS = –15V R (LS 0.1 R (LS 0.1 RO 0 RO 0 R R NL E–0.1 NL E–0.1 I–0.2 D–0.2 VREFP = +10V –0.3 VREFN = 0V –0.3 VDD = +15V –0.4 VSS = –15V –0.4 –0.50 50000 10000D0AC CO15D0E000 200000 25000009092-007 –0.50 50000 10000D0AC CO15D0E000 200000 25000009092-010 Figure 6. Integral Nonlinearity Error vs. DAC Code, +10 V Span Figure 9. Differential Nonlinearity Error vs. DAC Code, ±10 V Span 1.0 0.5 TA = +125°C AD8676 REFERENCE BUFFERS TA = +125°C 0.8 TA = +25°C 0.4 AD8675 OUTPUT BUFFER TA = +25°C TA = –40°C VREFP = +10V TA = –40°C 0.6 0.3 VREFN = 0V VDD = +15V B) 0.4 B) 0.2 VSS = –15V R (LS 0.2 R (LS 0.1 RO 0 RO 0 R R NL E–0.2 NL E–0.1 I–0.4 AD8676 REFERENCE BUFFERS D–0.2 AD8675 OUTPUT BUFFER –0.6 VREFP = +5V –0.3 VREFN = 0V –0.8 VDD = +15V –0.4 VSS = –15V –1.00 50000 10000D0AC CO15D0E000 200000 25000009092-008 –0.50 50000 10000D0AC CO15D0E000 200000 25000009092-011 Figure 7. Integral Nonlinearity Error vs. DAC Code, +5 V Span Figure 10. Differential Nonlinearity Error vs. DAC Code, +10 V Span Rev. E | Page 9 of 27

AD5781 Data Sheet 0.5 0.3 AD8676 REFERENCE BUFFERS TA = +125°C AD8676 REFERENCE BUFFERS 0.4 AD8675 OUTPUT BUFFER TA = +25°C AD8675 OUTPUT BUFFER 0.3 VVRREEFFPN == +05VV TA = –40°C 0.2 VVDSSD == –+1155VV 0.1 0.2 B) B) LS 0.1 LS 0 R ( R ( RO 0 RO–0.1 R R E E NL –0.1 NL –0.2 D D –0.2 –0.3 –0.3 ±10V SPAN MAX DNL +10V SPAN MAX DNL –0.4 VDD = +15V –0.4 +5V SPAN MAX DNL ±10V SPAN MIN DNL VSS = –15V +10V SPAN MIN DNL +5V SPAN MIN DNL –0.50 50000 10000D0AC CO15D0E000 200000 25000009092-012 –0.5–55 –35 –15 5TEMP2E5RATU4R5E (°C)65 85 105 125 09092-015 Figure 11. Differential Nonlinearity Error vs. DAC Code, +5 V Span Figure 14. Differential Nonlinearity Error vs. Temperature 0.5 0.14 AD8676 REFERENCE BUFFERS TA = +25°C 0.4 AD8675 OUTPUT BUFFER TA = –40°C 0.12 VREFP = +10V TA = +125°C 0.3 VREFN = 0V 0.10 INL MAX VDD = +15V B) 0.2 VSS = –15V B) 0.08 R (LS 0.1 R (LS 0.06 VTAR E=F P2 5=° C+10V RRO 0 RRO 0.04 AVRDE8F6N7 6= R–E10FVERENCE BUFFERS DNL E––00..12 INL E 0.020 AD8675 OUTPUT BUFFER –0.3 –0.02 INL MIN –0.4 –0.04 –0.50 50000 10000D0AC CO15D0E000 200000 25000009092-013 –0.0612.5 13.0 13.5 14.0VDD/1|V4S.5S| (V)15.0 15.5 16.0 16.5 09092-016 Figure 12. Differential Nonlinearity Error vs. DAC Code, ±10 V Span, Figure 15. Integral Nonlinearity Error vs. Supply Voltage, ±10 V Span X2 Gain Mode 0.5 0.4 AD8676 REFERENCE BUFFERS 0.4 AD8675 OUTPUT BUFFER VDD = +15V 0.3 0.3 VSS = –15V INL MAX 0.2 0.2 B) B) LS 0.1 LS TA = 25°C R ( R ( 0.1 VREFP = +5V RO 0 RO VREFN = 0V R R AD8676 REFERENCE BUFFERS L E–0.1 L E 0 AD8675 OUTPUT BUFFER N N I–0.2 I–0.1 –0.3 ±10V SPAN MAX INL +10V SPAN MAX INL –0.2 –0.4 +5V SPAN MAX INL ±10V SPAN MIN INL +10V SPAN MIN INL +5V SPAN MIN INL INL MIN –0.5–55 –35 –15 5TEMP2E5RATU4R5E (°C)65 85 105 125 09092-014 –0.–372..55 –83..59 –95..53 –160..75 –191VV..15DSDS (–(1VV12))0..55 –1132..59 –1144..52 –1155..55 –1166..55 09092-017 Figure 13. Integral Nonlinearity Error vs. Temperature Figure 16. Integral Nonlinearity Error vs. Supply Voltage, +5 V Span Rev. E | Page 10 of 27

Data Sheet AD5781 0.08 0.14 TA = 25°C 0.06 DNL MAX 0.12 VVRREEFFPN == +05VV 0.04 B) AD8676 REFERENCE BUFFERS LS0.10 AD8675 OUTPUT BUFFER R (LSB) 0.02 TVAR E=F P2 5=° C+10V RROR (0.08 RO 0 VREFN = –10V E E ER AD8676 REFERENCE BUFFERS AL0.06 NL –0.02 AD8675 OUTPUT BUFFER SC D O- R0.04 –0.04 ZE 0.02 –0.06 DNL MIN –0.0812.5 13.0 13.5 14.0VDD/1|V4S.5S| (V)15.0 15.5 16.0 16.5 09092-018 –072..55 –83..59 –95..53 –106..75 1–91VV..51DSDS (–(1VV12))0..55 –1132..59 –1144..52 –1155..55 –1166..55 09092-021 Figure 17. Differential Nonlinearity Error vs. Supply Voltage, ±10 V Span Figure 20. Zero-Scale Error vs. Supply Voltage, +5 V Span 0.10 0.05 TA = 25°C 0.05 0.04 VVRREEFFPN == +–1100VV AD8676 REFERENCE BUFFERS DNL MAX B) 0.03 AD8675 OUTPUT BUFFER 0 S RROR (LSB)–0.05 TVVAARRD EE8=FF6 PN27 5 6==° RC+0E5VVFERENCE BUFFERS E ERROR (L 00..0021 DNL E–0.10 AD8675 OUTPUT BUFFER D-SCAL 0 –0.15 DNL MIN MI–0.01 –0.20 –0.02 –0.25–72..55 –83..59 –95..53 1–06..57 1–19VV..51DSDS (–(1VV12))0..55 –1132..59 –1144..52 –1155..55 –1166..55 09092-019 –0.0312.5 13.0 13.5 14.0VDD/1|V4S.5S| (V)15.0 15.5 16.0 16.5 09092-022 Figure 18. Differential Nonlinearity Error vs. Supply Voltage, +5 V Span Figure 21. Midscale Error vs. Supply Voltage, ±10 V Span 0.14 0.05 0.12 0 LSB)0.10 SB) RROR (0.08 ROR (L–0.05 E R LE E E A0.06 L SC CA–0.10 ERO-0.04 TVAR E=F P2 5=° C+10V MID-S TA = 25°C Z0.02 VARDE8F6N7 6= R–E10FVERENCE BUFFERS –0.15 VVRREEFFPN == +05VV AD8675 OUTPUT BUFFER AD8676 REFERENCE BUFFERS AD8675 OUTPUT BUFFER 102.5 13.0 13.5 14.0VDD/1|V4S.5S| (V)15.0 15.5 16.0 16.5 09092-020 –0.20–72..55 –83..59 –95..53 1–06..57 1–19VV..51DSDS (–(1VV12))0..55 –1132..59 –1144..52 –1155..55 –1166..55 09092-023 Figure 19. Zero-Scale Error vs. Supply Voltage, ±10 V Span Figure 22. Midscale Error vs. Supply Voltage, +5 V Span Rev. E | Page 11 of 27

AD5781 Data Sheet –0.015 0.10 TA = 25°C 0.05 VREFP = +5V –0.020 VREFN = 0V SB) R) 0 AADD88667765 ROEUFTEPRUETN BCUEF BFEURFFERS ROR (L–0.025 pm FS––00..1005 E ER–0.030 OR (p–0.15 LL-SCAL–0.035 AIN ERR––00..2250 FU TVAR E=F P2 5=° C+10V G–0.30 –0.040 VREFN = –10V AD8676 REFERENCE BUFFERS –0.35 AD8675 OUTPUT BUFFER –0.04512.5 13.0 13.5 14.0VDD/1|V4S.5S| (V)15.0 15.5 16.0 16.5 09092-024 –0.40–72..55 –83..59 –95..53 1–06..57 1–19VV..51DSDS (–(1VV12))0..55 –1132..59 –1144..52 –1155..55 –1166..55 09092-027 Figure 23. Full-Scale Error vs. Supply Voltage, ±10 V Span Figure 26. Gain Error vs. Supply Voltage, +5 V Span 0.07 0.15 0.06 0.10 INL MAX 0.05 B) S OR (L 0.04 LSB) 0.05 TA = 25°C RR 0.03 R ( VDD = +15V CALE E 0.02 L ERRO 0 VAASDDS88 66=77 –651 RO5VEUFTEPRUETN BCUEF BFEURFFERS L-S 0.01 IN–0.05 UL TA = 25°C F 0 VREFP = +5V VREFN = 0V –0.10 –0.01 AD8676 REFERENCE BUFFERS INL MIN AD8675 OUTPUT BUFFER –0.02–72..55 –83..59 –95..53 –106..57 1–19VV..51DSDS (–(1VV12))0..55 –1132..59 –1144..52 –1155..55 –1166..55 09092-025 –0.155.0 5.5 6.0 6.5 V7R.E0FP/|V7.R5EFN|8 (.0V) 8.5 9.0 9.5 10.0 09092-028 Figure 24. Full-Scale Error vs. Supply Voltage, +5 V Span Figure 27. Integral Nonlinearity Error vs. Reference Voltage –0.30 0.10 TA = 25°C DNL MAX –0.35 VVRREEFFPN == +–1100VV AD8676 REFERENCE BUFFERS 0.05 R)–0.40 AD8675 OUTPUT BUFFER S OR (ppm F–0.45 ROR (LSB) 0 VVTADSS D= = =2 5–+°11C55VV R R AD8676 REFERENCE BUFFERS ER–0.50 L E–0.05 AD8675 OUTPUT BUFFER N N AI D G–0.55 –0.10 –0.60 DNL MIN –0.6512.5 13.0 13.5 14.0VDD/1|V4S.5S| (V)15.0 15.5 16.0 16.5 09092-026 –0.155.0 5.5 6.0 6.5 V7R.E0FP/|V7.R5EFN|8 (.0V) 8.5 9.0 9.5 10.0 09092-029 Figure 25. Gain Error vs. Supply Voltage, ±10 V Span Figure 28. Differential Nonlinearity Error vs. Reference Voltage Rev. E | Page 12 of 27

Data Sheet AD5781 0.16 –0.30 TA = 25°C 0.14 VDD = +15V –0.35 VSS = –15V SB)0.12 R) AADD88667765 ROEUFTEPRUETN BCUEF BFEURFFERS L S OR (0.10 m F–0.40 E ERR0.08 TVAD D= =2 5+°1C5V OR (pp–0.45 ZERO-SCAL00..0064 VAASDDS88 66=77 –651 RO5VEUFTEPRUETN BCUEF BFEURFFERS GAIN ERR–0.50 –0.55 0.02 05.0 5.5 6.0 6.5 V7R.E0FP/|V7.R5EFN|8 (.0V) 8.5 9.0 9.5 10.0 09092-030 –0.605.0 5.5 6.0 6.5 V7R.E0FP/|V7.R5EFN|8 (.0V) 8.5 9.0 9.5 10.0 09092-033 Figure 29. Zero-Scale Error vs. Reference Voltage Figure 32. Gain Error vs. Reference Voltage 0.03 0.3 ±10V SPAN 0.02 0.2 +10V SPAN ±5V SPAN MID-SCALE ERROR (LSB)–––0000....000012310 VVATADSDS D8= 6= =27 5–+6°1 1RC55VEVFERENCE BUFFERS FULL-SCALE ERROR (LSB)––––00000.....123410 AAVVDSDDSD88 66==77 –+651 1RO55VEUVFTEPRUETN BCUEF BFEURFFERS AD8675 OUTPUT BUFFER VREFP = +10V –0.04 –0.5 VREFN = –15V –0.055.0 5.5 6.0 6.5 V7R.E0FP/|V7.R5EFN|8 (.0V) 8.5 9.0 9.5 10.0 09092-031 –0.6–55 –35 –15 5TEMP2E5RATU4R5E (°C)65 85 105 125 09092-034 Figure 30. Midscale Error vs. Reference Voltage Figure 33. Full-Scale Error vs. Temperature 0.04 0.40 ±10V SPAN 0.03 VTAD D= =2 5+°1C5V 0.35 +±51V0V S SPPAANN VSS = –15V FULL-SCALE ERROR (LSB)––0000....000012210 AADD88667765 ROEUFTEPRUETN BCUEF BFEURFFERS MID-SCALE ERROR (LSB)00000.....3221150050 AAVDDDD88 66=77 +65 1RO5EUVFTEPRUETN BCUEF BFEURFFERS VSS = –15V –0.03 0.05 VVRREEFFPN == +–1105VV –0.045.0 5.5 6.0 6.5 V7R.E0FP/|V7.R5EFN|8 (.0V) 8.5 9.0 9.5 10.0 09092-032 0–55 –35 –15 5TEMP2E5RATU4R5E (°C)65 85 105 125 09092-035 Figure 31. Full-Scale Error vs. Reference Voltage Figure 34. Midscale Error vs. Temperature Rev. E | Page 13 of 27

AD5781 Data Sheet 1.2 5 ±10V SPAN TA = 25°C 1.0 +10V SPAN 4 ±5V SPAN IDD 0.8 3 s) SB 0.6 2 L OR ( 0.4 A) 1 ERR 0.2 (mS 0 SCALE –0.20 AD8676 REFERENCE BUFFERS I, IDDS –1 O- AD8675 OUTPUT BUFFER –2 R –0.4 E VDD = +15V Z –0.6 VVSRSE F=P –=1 5+V10V –3 ISS –0.8 VREFN = –15V –4 –1.0–55 –35 –15 5TEMP2E5RATU4R5E (°C6)5 85 105 125 09092-036 –5–20 –15 –10 –5VDD, V0SS (V) 5 10 15 20 09092-039 Figure 35. Zero-Scale Error vs. Temperature Figure 38. Power Supply Currents vs. Power Supply Voltages 4 AD8676 REFERENCE BUFFERS ±10V SPAN 3 AD8675 OUTPUT BUFFER +10V SPAN VDD = +15V +5V SPAN 2 VSS = –15V R (ppm FSR) 10 VVRREEFFPN == +–1105VV 3 VVVVDSRRSDEE FF ==PN –+==11 5+–5V11V00VV RO –1 AD8676 REFERENCE BUFFERS R OUTPUT UNBUFFERED E N –2 LOAD = 10MΩ||20pF AI G –3 –4 –5–55 –35 –15 5TEMP2E5RATU4R5E (°C)65 85 105 125 09092-037 4 CH3 5V CH4 5V 200ns 09092-040 Figure 36. Gain Error vs. Temperature Figure 39. Rising Full-Scale Voltage Step 900 800 TA = 25°C IIINOOCVVRCCCCE A==S 55IVVN,,G LLOOGGIICC VVOOLLTTAAGGEE VVVDSRSDE F ==P –+=11 5+5V1V0V 700 DIOEVCCRCE =A 3SVIN, LGOGIC VOLTAGE VARDE8F6N7 6= R–E10FVERENCE BUFFERS INCREASING OUTPUT UNBUFFERED 600 IOVCC = 3V, LOGIC VOLTAGE LOAD = 10MΩ||20pF DECREASING (µA)C500 3 OIC400 I 300 200 10000 1 LO2GIC INPUT3 VOLTAGE4 (V) 5 6 09092-038 4 CH3 5V CH4 5V 200ns 09092-041 Figure 37. IOICC vs. Logic Input Voltage Figure 40. Falling Full-Scale Voltage Step Rev. E | Page 14 of 27

Data Sheet AD5781 10.8 3.0 ±10VVREF 5VVREF OUTPUT GAIN OF 1 OUTPUT GAIN OF 1 2.6 10.6 BIAS COMPENSATION MODE BIAS COMPENSATION MODE 20pF COMPENSATION CAPACITOR 20pF COMPENSATION CAPACITOR 10.4 RC LOW-PASS FILTER –sec) 2.2 RC LOW-PASS FILTER NCEHGANAGTIEVE CODE nV 1.8 POSITIVE CODE mV) 10.2 CH ( CHANGE (UT GLIT 1.4 VO 10.0 UT 1.0 P T 9.8 OU 0.6 9.6 0.2 9.40 1 2 TIME (µs)3 4 5 09092-063 –0.21638465536114688163840212992262144311296360448409600458752C507904OD557056E606208655360704512753664802816851968901120950272999424 09092-061 Figure 41. 125 Code Step Settling Time Figure 44. 6 MSB Segment Glitch Energy for 5 V VREF 10 40 5VVREF ±10VVREF 9 OUTPUT GAIN OF 1 NEGATIVE CODE OUTPUT GAIN OF 1 BIAS COMPENSATION MODE CHANGE 30 BIAS COMPENSATION MODE 8 20pF COMPENSATION CAPACITOR 20pF COMPENSATION CAPACITOR c) RC LOW-PASS FILTER RC LOW-PASS FILTER e V–s 7 20 n CH ( 6 mV) GLIT 5 PCOHASNITGIVEE CODE (UT 10 UT 4 VO P T 0 U 3 O 2 –10 CCXX == 114433ppFF ++ 02p20FpF 1 CX = 143pF + 470pF CX = 143pF + 1,000pF 01638465536114688163840212992262144311296360448409600458752C507904OD557056E606208655360704512753664802816851968901120950272999424 09092-059 –20–1.0 –0.5 0 TIM0E.5 (µs) 1.0 1.5 2.0 09092-062 Figure 42. 6 MSB Segment Glitch Energy for ±10 V VREF Figure 45. Midscale Peak-to-Peak Glitch for ±10 V 4.0 800 10VVREF TA = 25°C MID-SCALE CODE LOADED OUTPUT GAIN OF 1 VDD = +15V OUTPUT UNBUFFERED 3.5 BIAS COMPENSATION MODE 600 VSS = –15V AD8676 REFERENCE BUFFERS 20pF COMPENSATION CAPACITOR VREFP = +10V –sec) 3.0 RC LOW-PASS FILNTEEGRATIVE CODE PCOHASNITGIVEE CODE nV) 400 VREFN = –10V nV 2.5 CHANGE E ( H ( AG 200 C T LIT 2.0 OL G V PUT 1.5 PUT 0 OUT 1.0 OUT –200 –400 0.5 01638465536114688163840212992262144311296360448409600458752C507904OD557056E606208655360704512753664802816851968901120950272999424 09092-060 –6000 1 2 3 T4IME (S5econd6s) 7 8 9 10 09092-044 Figure 43. 6 MSB Segment Glitch Energy for 10 V VREF Figure 46. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth Rev. E | Page 15 of 27

AD5781 Data Sheet 100 350 VVVVCDSRROSDEED FF ==EPN –+===11 5M+–5V11VID00VVSCALE V)320500 VVVTVADSRRS DEE= FF = =PN2 5 –+==°11 C5+–5V11V00VV m AD8675 OUTPUT BUFFER Hz) AGE (200 nV/ 10 OLT150 NSD ( PUT V100 T U O 50 0 10.1 1 10FREQU1E0N0CY (Hz)1k 10k 100k 09092-064 –50–1 0 1 2TIME (µs3) 4 5 6 09092-049 Figure 47. Noise Spectral Density vs. Frequency Figure 48. Glitch Impulse on Removal of Output Clamp Rev. E | Page 16 of 27

Data Sheet AD5781 TERMINOLOGY Relative Accuracy Midscale Error Temperature Coefficient Relative accuracy, or integral nonlinearity (INL), is a measure of Midscale error temperature coefficient is a measure of the the maximum deviation, in LSB, from a straight line passing change in mid-scale error with a change in temperature. It is through the endpoints of the DAC transfer function. A typical expressed in ppm FSR/°C. INL error vs. code plot is shown in Figure 5. Output Slew Rate Differential Nonlinearity (DNL) Slew rate is a measure of the limitation in the rate of change of Differential nonlinearity is the difference between the measured the output voltage. The slew rate of the AD5781 output voltage change and the ideal 1 LSB change between any two adjacent is determined by the capacitive load presented to the V pin. OUT codes. A specified differential nonlinearity of ±1 LSB maximum The capacitive load in conjunction with the 3.4 kΩ output impe- ensures monotonicity. This DAC is guaranteed monotonic. A dance of the AD5781 set the slew rate. Slew rate is measured typical DNL error vs. code plot is shown in Figure 9. from 10% to 90% of the output voltage change and is expressed in V/µs. Linearity Error Long-Term Stability Linearity error long-term stability is a measure of the stability of Output Voltage Settling Time the linearity of the DAC over a long period of time. It is Output voltage settling time is the amount of time it takes for specified in LSB for a time period of 500 hours and 1000 hours the output voltage to settle to a specified level for a specified at an elevated ambient temperature. change in voltage. For fast settling applications, a high speed buffer amplifier is required to buffer the load from the 3.4 kΩ Zero-Scale Error output impedance of the AD5781, in which case, it is the Zero-scale error is a measure of the output error when zero-scale amplifier that determines the settling time. code (0x00000) is loaded to the DAC register. Ideally, the output voltage should be VREFNS. Zero-scale error is expressed in LSBs. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the Zero-Scale Error Temperature Coefficient analog output when the input code in the DAC register changes Zero-scale error temperature coefficient is a measure of the state. It is specified as the area of the glitch in nV-sec and is change in zero-scale error with a change in temperature. It is measured when the digital input code is changed by 1 LSB at expressed in ppm FSR/°C. the major carry transition (see Figure 42). Full-Scale Error Output Enabled Glitch Impulse Full-scale error is a measure of the output error when full-scale Output enabled glitch impulse is the impulse injected into the code (0x3FFFF) is loaded to the DAC register. Ideally, the analog output when the clamp to ground on the DAC output is output voltage should be V − 1 LSB. Full-scale error is REFPS removed. It is specified as the area of the glitch in nV-sec (see expressed in LSBs. Figure 48). Full-Scale Error Temperature Coefficient Digital Feedthrough Full-scale error temperature coefficient is a measure of the Digital feedthrough is a measure of the impulse injected into change in full-scale error with a change in temperature. It is the analog output of the DAC from the digital inputs of the expressed in ppm FSR/°C. DAC but is measured when the DAC output is not updated. It is Gain Error specified in nV-sec and measured with a full-scale code change Gain error is a measure of the span error of the DAC. It is the on the data bus, that is, from all 0s to all 1s, and vice versa. deviation in slope of the DAC transfer characteristic from ideal, Spurious Free Dynamic Range (SFDR) expressed in ppm of the full-scale range. Spurious free dynamic range is the usable dynamic range of a Gain Error Temperature Coefficient DAC before spurious noise interferes or distorts the fundamental Gain error temperature coefficient is a measure of the change in signal. It is measured by the difference in amplitude between the gain error with a change in temperature. It is expressed in ppm fundamental and the largest harmonically or nonharmonically FSR/°C. related spur from dc to full Nyquist bandwidth (half the DAC Midscale Error sampling rate, or f/2). SFDR is measured when the signal is a S Midscale error is a measure of the output error when midscale digitally generated sine wave. code (0x20000) is loaded to the DAC register. Ideally, the output Total Harmonic Distortion (THD) voltage should be (V – V )/2 +V . Midscale error is REFPS REFNS REFNS Total harmonic distortion is the ratio of the rms sum of the expressed in LSBs. harmonics of the DAC output to the fundamental value. Only the second to fifth harmonics are included. Rev. E | Page 17 of 27

AD5781 Data Sheet DC Power Supply Rejection Ratio. AC Power Supply Rejection Ratio (AC PSRR) DC power supply rejection ratio is a measure of the rejection of AC power supply rejection ratio is a measure of the rejection of the output voltage to dc changes in the power supplies applied the output voltage to ac changes in the power supplies applied to the DAC. It is measured for a given dc change in power to the DAC. It is measured for a given amplitude and frequency supply voltage and is expressed in µV/V. change in power supply voltage and is expressed in decibels. Rev. E | Page 18 of 27

Data Sheet AD5781 THEORY OF OPERATION The AD5781 is a high accuracy, fast settling, single, 18-bit, R R R VOUT serial input, voltage output DAC. It operates from a VDD supply 2R 2R 2R ..................... 2R 2R 2R.......... 2R voltage of 7.5 V to 16.5 V and a VSS supply of −16.5 V to −2.5 V. S0 S1 ..................... S11 E62 E61.......... E0 Data is written to the AD5781 in a 24-bit word format via a 3-wire VREFPF serial interface. The AD5781 incorporates a power-on reset VVRREEFFNPSF circuit that ensures the DAC output powers up to 0 V with the VREFNS VOUT pin clamped to AGND through a ~6 kΩ internal resistor. 12-BITR-RLADDER SI6X3MESQBUsADLESCEOGDMEEDN ITNSTO 09092-053 DAC ARCHITECTURE Figure 49. DAC Ladder Structure Serial Interface The architecture of the AD5781 consists of two matched DAC The AD5781 has a 3-wire serial interface (SYNC, SCLK, and sections. A simplified circuit diagram is shown in Figure 49. The SDIN) that is compatible with SPI, QSPI, and MICROWIRE six MSBs of the 18-bit data-word are decoded to drive 63 switches, interface standards, as well as most DSPs (see Figure 2 for a E0 to E62. Each of these switches connects one of 63 matched timing diagram). resistors to either the V or V voltage. The remaining REFP REFN Input Shift Register 12 bits of the data-word drive the S0 to S11 switches of a 12-bit voltage mode R-R ladder network. The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK, which can operate at up to 35 MHz. The input register consists of an R/W bit, three address bits, and twenty data bits as shown in Table 7. The timing diagram for this operation is shown in Figure 2. Table 7. Input Shift Register Format MSB LSB DB23 DB22 DB21 DB20 DB19 DB0 R/W Register address Register data Table 8. Decoding the Input Shift Register R/W Register Address Description X1 0 0 0 No operation (NOP). Used in readback operations. 0 0 0 1 Write to the DAC register. 0 0 1 0 Write to the control register. 0 0 1 1 Write to the clearcode register. 0 1 0 0 Write to the software control register. 1 0 0 1 Read from the DAC register. 1 0 1 0 Read from the control register. 1 0 1 1 Read from the clearcode register. 1 X is don’t care. Rev. E | Page 19 of 27

AD5781 Data Sheet Standalone Operation HARDWARE CONTROL PINS The serial interface works with both a continuous and noncon- Load DAC Function (LDAC) tinuous serial clock. A continuous SCLK source can be used After data has been transferred into the input register of the only if SYNC is held low for the correct number of clock cycles. DAC, there are two ways to update the DAC register and DAC In gated clock mode, a burst clock containing the exact number output. Depending on the status of both SYNC and LDAC, one of clock cycles must be used, and SYNC must be taken high of two update modes is selected: synchronous DAC updating or after the final clock to latch the data. The first falling edge of asynchronous DAC updating. SYNC starts the write cycle. Exactly 24 falling clock edges must Synchronous DAC Update be applied to SCLK before SYNC is brought high again. If SYNC is brought high before the 24th falling SCLK edge, the In this mode, LDAC is held low while data is being clocked into data written is invalid. If more than 24 falling SCLK edges are the input shift register. The DAC output is updated on the rising applied before SYNC is brought high, the input data is also edge of SYNC. invalid. The input shift register is updated on the rising edge of Asynchronous DAC Update SYNC. For another serial transfer to take place, SYNC must be In this mode, LDAC is held high while data is being clocked brought low again. After the end of the serial data transfer, data into the input shift register. The DAC output is asynchronously is automatically transferred from the input shift register to the updated by taking LDAC low after SYNC has been taken high. addressed register. Once the write cycle is complete, the output The update now occurs on the falling edge of LDAC. can be updated by taking LDAC low while SYNC is high. Reset Function (RESET) Readback The AD5781 can be reset to its power-on state by two means: The contents of all the on-chip registers can be read back via the SDO pin. Table 8 outlines how the registers are decoded. either by asserting the RESET pin or by utilizing the software After a register has been addressed for a read, the next 24 clock RESET control function (see Table 14). If the RESET pin is not cycles clock the data out on the SDO pin. The clocks must be used, it should be hardwired to IOVCC. applied while SYNC is low. When SYNC is returned high, the Asynchronous Clear Function (CLR) SDO pin is placed in tristate. For a read of a single register, the The CLR pin is an active low clear that allows the output to be NOP function can be used to clock out the data. Alternatively, cleared to a user defined value. The 18-bit clear code value is if more than one register is to be read, the data of the first register programmed to the clearcode register (see Table 13). It is to be addressed can be clocked out at the same time the second necessary to maintain CLR low for a minimum amount of time register to be read is being addressed. The SDO pin must be to complete the operation (see Figure 2). When the CLR signal enabled to complete a readback operation. The SDO pin is enabled by default. is returned high, the output remains at the clear value (if LDAC is high) until a new value is loaded to the DAC register. The output cannot be updated with a new value while the CLR pin is low. A clear operation can also be performed by setting the CLR bit in the software control register (see Table 14). Rev. E | Page 20 of 27

Data Sheet AD5781 Table 9. Hardware Control Pins Truth Table LDAC CLR RESET Function X1 X1 0 The AD5781 is in reset mode. The device cannot be programmed. X1 X1 The AD5781 is returned to its power-on state. All registers are set to their default values. 0 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly. 0 1 1 The output is set according to the DAC register value. 1 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly. 1 1 The output is set according to the DAC register value. 0 1 The output remains at the clear code value. 1 1 The output remains set according to the DAC register value. 0 1 The output remains at the clear code value. 1 1 The DAC register is loaded with the clearcode register value and the output is set accordingly. 0 1 The DAC register is loaded with the clearcode register value and the output is set accordingly. 1 1 The output remains at the clear code value. 0 1 The output is set according to the DAC register value. 1 X is don’t care. ON-CHIP REGISTERS DAC Register Table 10 outlines how data is written to and read from the DAC register. Table 10. DAC Register MSB LSB DB23 DB22 DB21 DB20 DB19 DB2 DB1 DB0 R/W Register address DAC register data R/W 0 0 1 18-bits of data X1 X1 1 X is don’t care. The following equation describes the ideal transfer function of the DAC: (V −V )×D V = REFP REFN +V OUT 218−1 REFN where: V is the negative voltage applied at the V input pin. REFN REFNS V is the positive voltage applied at the V input pin. REFP REFPS D is the 18-bit code programmed to the DAC. Rev. E | Page 21 of 27

AD5781 Data Sheet Control Register The control register controls the mode of operation of the AD5781. Table 11. Control Register MSB LSB DB23 DB22 DB21 DB20 DB19...DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R/W Register address Control register data R/W 0 1 0 Reserved Reserved LIN COMP SDODIS BIN/2sC DACTRI OPGND RBUF Reserved Table 12. Control Register Functions Function Description Reserved These bits are reserved and should be programmed to zero. RBUF Output amplifier configuration control. 0: internal amplifier, A1, is powered up and resistors RFB and R1 are connected in series as shown in Figure 53. This allows an external amplifier to be connected in a gain of two configurations. See the AD5781 Features section for further details. 1: (default) internal amplifier, A1, is powered down and resistors RFB and R1 are connected in parallel as shown in Figure 52 so that the resistance between the RFB and INV pins is 3.4 kΩ, equal to the resistance of the DAC. This allows the RFB and INV pins to be used for input bias current compensation for an external unity gain amplifier. See the AD5781 Features section for further details. OPGND Output ground clamp control. 0: DAC output clamp to ground is removed, and the DAC is placed in normal mode. 1: (default) DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate mode. Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated. Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit. DACTRI DAC tristate control. 0: DAC is in normal operating mode. 1: (default) DAC is in tristate mode. BIN/2sC DAC register coding select. 0: (default) DAC register uses twos complement coding. 1: DAC register uses offset binary coding. SDODIS SDO pin enable/disable control. 0: (default) SDO pin is enabled. 1: SDO pin is disabled (tristate). LIN COMP Linearity error compensation for varying reference input spans. See the AD5781 Features section for further details. 0 0 0 0 (Default) reference input span up to 10 V. 1 1 0 0 Reference input span of 20 V. Clearcode Register The clearcode register sets the value to which the DAC output is set when the CLR pin or CLR bit is asserted. The output value depends on the DAC coding that is being used, either binary or twos complement. The default register value is 0. Table 13. Clearcode Register MSB LSB DB23 DB22 DB21 DB20 DB19 DB2 DB1 DB0 R/W Register address Clearcode register data R/W 0 1 1 18-bits of data X1 X1 1 X is don’t care. Rev. E | Page 22 of 27

Data Sheet AD5781 Software Control Register This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low. Table 14. Software Control Register MSB LSB DB23 DB22 DB21 DB20 DB19 DB3 DB2 DB1 DB0 R/W Register address Software control register data 0 1 0 0 Reserved RESET CLR1 LDAC2 1 The CLR function has no effect if the LDAC pin is low. 2 The LDAC function has no effect if the CLR pin is low. Table 15. Software Control Register Functions Function Description LDAC Setting this bit to 1 updates the DAC register and consequently the DAC output. CLR Setting this bit to 1 sets the DAC register to a user defined value (see Table 13) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. RESET Setting this bit to 1 returns the AD5781 to its power-on state. Rev. E | Page 23 of 27

AD5781 Data Sheet AD5781 FEATURES POWER-ON TO 0 V LINEARITY COMPENSATION The AD5781 contains a power-on reset circuit that, as well as The integral nonlinearity (INL) of the AD5781 can vary resetting all registers to their default values, controls the output according to the applied reference voltage span; the LIN COMP voltage during power-up. Upon power-on, the DAC is placed in bits of the control register can be programmed to compensate tristate (its reference inputs are disconnected), and its output is for this variation in INL. The specifications in this data sheet clamped to AGND through a ~6 kΩ resistor. The DAC remains are obtained with LIN COMP = 0000 for reference spans up to in this state until programmed otherwise via the control and including 10 V and with LIN COMP = 1100 for a reference register. This is a useful feature in applications where it is span of 20 V. The default value of the LIN COMP bits is 0000. important to know the state of the DAC output while it is in the OUTPUT AMPLIFIER CONFIGURATION process of powering up. There are a number of different ways that an output amplifier POWER-UP SEQUENCE can be connected to the AD5781, depending on the voltage To power up the part in a known safe state, ensure that V does references applied and the desired output voltage span. CC not come up while VDD is unpowered during power-on by Unity Gain Configuration powering up the V supply before the V supply. If this DD CC Figure 51 shows an output amplifier configured for unity gain, cannot be achieved, connect an external Schottky diode across in this configuration the output spans from V to V the V and V supplies as shown in Figure 50. REFN REFP. DD CC VREFP VCC VDD 1/2AD8676 VCC VDD VREFPF VREFPS AD5781 R1 RFB RFB A1 09092-050 6.8kΩ 6.8kΩ INV AAADDD8AA644780590,84--11, Figure 50. Schottky Diode Connection 18-BIT DAC VOUT VOUT CONFIGURING THE AD5781 AD5781 After power-on, the AD5781 must be configured for normal VREFNF VREFNS operating mode before programming the output. To do this, the control register must be programmed. The DAC is removed 1/2AD8676 fisr ormem torivsetadt eb yb yc lcelaerairnign gth teh eO DPGACNTDR bI ibt.i tA, ta nthdi st hpeo ionutt, ptuhte coluamtppu t VREFN 09092-054 goes to VREFN unless an alternative value is first programmed to Figure 51. Output Amplifier in Unity Gain Configuration the DAC register. A second unity gain configuration for the output amplifier is DAC OUTPUT STATE one that removes an offset from the input bias currents of the The DAC output can be placed in one of three states, controlled amplifier. It does this by inserting a resistance in the feedback by the DACTRI and OPGND bits of the control register, as path of the amplifier that is equal to the output resistance of the shown in Table 16. DAC. The DAC output resistance is 3.4 kΩ. By connecting R1 and R in parallel, a resistance equal to the DAC resistance is FB Table 16. AD5781 Output State Truth Table available on-chip. Because the resistors are all on one piece of DACTRI OPGND Output State silicon, they are temperature coefficient matched. To enable this 0 0 Normal operating mode. mode of operation, the RBUF bit of the control register must be set 0 1 Output is clamped via ~6 kΩ to AGND. to Logic 1. Figure 52 shows how the output amplifier is connected 1 0 Output is in tristate. to the AD5781. In this configuration, the output amplifier is in 1 1 Output is clamped via ~6 kΩ to AGND. unity gain and the output spans from V to V . This unity REFN REFP gain configuration allows a capacitor to be placed in the amplifier feedback path to improve dynamic performance. Rev. E | Page 24 of 27

Data Sheet AD5781 VREFP VREFP 1/2AD8676 1/2AD8676 VREFPF VREFPS VREFPF VREFPS RFB R1 RFB RFB A1 R1 6.8kΩ RFB 6.8kΩ 10pF 6.8kΩ 6.8kΩ 10pF INV 18-BIT INV VOUT 18-BIT VOUT DAC VOUT AD8675, DAC VOUT AD8675, ADA4898-1, ADA4898-1, ADA4004-1 ADA4004-1 AD5781 AD5781 VREFNF VREFNS VREFNF VREFNS 1/2AD8676 1/2AD8676 VREFN 09092-055 VREFN = 0V 09092-056 Figure 52. Output Amplifier in Unity Gain with Amplifier Input Bias Current Figure 53. Output Amplifier in Gain of Two Configuration Compensation Gain of Two Configuration Figure 53 shows an output amplifier configured for a gain of two. The gain is set by the internal matched 6.8 kΩ resistors, which are exactly twice the DAC resistance, having the effect of removing an offset from the input bias current of the external amplifier. In this configuration, the output spans from 2 × V − REFN V to V This configuration is used to generate a bipolar REFP REFP. output span from a single-ended reference input, with V = REFN 0 V. For this mode of operation, the RBUF bit of the control register must be cleared to Logic 0. Rev. E | Page 25 of 27

AD5781 Data Sheet APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT 09092-057 Figure 54. Typical Operating Circuit Figure 54 shows a typical operating circuit for the AD5781 EVALUATION BOARD using an AD8676 for reference buffers and an AD8675 as an An evaluation board is available for the AD5781 to aid output buffer. To meet the specified linearity, force sense buffers designers in evaluating the high performance of the part with must be used on the reference inputs. Because the output minimum effort. The AD5781 evaluation kit includes a impedance of the AD5781 is 3.4 kΩ, an output buffer is populated and tested AD5781 PCB. The evaluation board required for driving low resistive, high capacitive loads. interfaces to the USB port of a PC. Software is available with the evaluation board to allow the user to easily program the AD5781. The software runs on any PC that has Microsoft® Windows® XP (SP2) or Vista (32 bits) installed. The EVAL- AD5781 data sheet is available, which gives full details on the operation of the evaluation board Rev. E | Page 26 of 27

Data Sheet AD5781 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 0.15 1.20 MAX 0.20 0.05 0.09 0.75 0.30 8° 0.60 COPLANARITY 0.19 SEATING 0° 0.45 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 55. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range INL Package Description Package Option AD5781BRUZ −40°C to +125°C ±0.5 LSB 20-Lead TSSOP RU-20 AD5781BRUZ-REEL7 −40°C to +125°C ±0.5 LSB 20-Lead TSSOP RU-20 AD5781ARUZ −40°C to +125°C ±4 LSB 20-Lead TSSOP RU-20 AD5781ARUZ-REEL7 −40°C to +125°C ±4 LSB 20-Lead TSSOP RU-20 EVAL-AD5781SDZ Evaluation Board 1 Z = RoHS Compliant Part. ©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09092-0-4/18(E) Rev. E | Page 27 of 27

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5781SDZ AD5781BRUZ-REEL7 AD5781ARUZ AD5781SRU-EP AD5781BRUZ AD5781ARUZ-REEL7 AD5781SRUZ-EP