System Ready, 18-Bit ±1 LSB INL, Voltage Output DAC Data Sheet AD5780 FEATURES FUNCTIONAL BLOCK DIAGRAM True 18-bit voltage output DAC, ±1 LSB INL VCC VDD VREFP 8 nV/√Hz output noise spectral density R1 RFB 0.025 LSB long-term linearity error stability AD5780 6.8kΩ 6.8kΩ IOVCC A1 RFB ±0.018 ppm/°C gain error temperature coefficient INV 2.5 µs output voltage settling time SDIN INPUT 3.5 nV-sec midscale glitch impulse SCLK RESGHISIFTTER 18 RDEAGC 18 1D8-ABCIT VOUT SYNC AND Integrated precision reference buffers CONTROL SDO LOGIC Operating temperature range: −40°C to +125°C 6kΩ LDAC 4 mm × 5 mm LFCSP package Wide power supply range of up to ±16.5 V CLR POWER-ON RESET RESET AND CLEAR LOGIC 315.8 M V-Hczo mScphamtiibttl et rdigiggietarel din dteigrfitaacle i nterface DGND VSS AGND VREFN 09649-001 APPLICATIONS Figure 1. Medical instrumentation Test and measurement Industrial control Scientific and aerospace instrumentation Data acquisition systems Digital gain and offset adjustment Power supply control GENERAL DESCRIPTION The AD57801 is a true 18-bit, unbuffered voltage output digital- PRODUCT HIGHLIGHTS to-analog converter (DAC) that operates from a bipolar supply 1. True 18-bit accuracy. of up to 33 V. The AD5780 accepts a positive reference input 2. Wide power supply range of up to ±16.5 V. range of 5 V to V − 2.5 V and a negative reference input range DD 3. −40°C to +125°C operating temperature range. of V + 2.5 V to 0 V. Both reference inputs are buffered on chip SS 4. Low 8 nV/√Hz noise. and external buffers are not required. The AD5780 offers a 5. Low ±0.018 ppm/°C gain error temperature coefficient. relative accuracy specification of ±1 LSB maximum range, and operation is guaranteed monotonic with a ±1 LSB differential COMPANION PRODUCTS nonlinearity (DNL) maximum range specification. Output Amplifier Buffer: AD8675, ADA4898-1, ADA4004-1 The part uses a versatile 3-wire serial interface that operates at External Reference: ADR445, ADR4550 clock rates of up to 35 MHz and is compatible with standard DC-to-DC Design Tool: ADIsimPower™ serial peripheral interface (SPI), QSPI™, MICROWIRE™, and DSP interface standards. The part incorporates a power-on Additional companion products on the AD5780 product page. reset circuit that ensures that the DAC output powers up to 0 V Table 1. Related Devices in a known output impedance state and remains in this state Part No. Description until a valid write to the device takes place. The part provides AD5790 20-bit, 2 LSB accurate DAC an output clamp feature that places the output in a defined load AD5791 20-bit, 1 ppm accurate DAC state. AD5781 18-bit, 0.5 LSB accurate DAC AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC AD5760 16-bit, 0.5 LSB accurate DAC 1 Protected by U.S. Patent No. 7,884,747 and 8,089,380. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5780 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DAC Architecture ....................................................................... 18 Applications ....................................................................................... 1 Serial Interface ............................................................................ 18 Functional Block Diagram .............................................................. 1 Hardware Control Pins .............................................................. 19 General Description ......................................................................... 1 On-Chip Registers ...................................................................... 19 Product Highlights ........................................................................... 1 AD5780 Features ............................................................................ 23 Companion Products ....................................................................... 1 Power-On to 0 V ......................................................................... 23 Revision History ............................................................................... 2 Power-Up Sequence ................................................................... 23 Specifications ..................................................................................... 3 Configuring the AD5780 .......................................................... 23 Timing Characteristics ................................................................ 5 DAC Output State ...................................................................... 23 Absolute Maximum Ratings ............................................................ 7 Output Amplifier Configuration.............................................. 23 ESD Caution .................................................................................. 7 Applications Information .............................................................. 25 Pin Configuration and Function Descriptions ............................. 8 Typical Operating Circuit ......................................................... 25 Typical Performance Characteristics ............................................. 9 Evaluation Board ........................................................................ 26 Terminology .................................................................................... 17 Outline Dimensions ....................................................................... 27 Theory of Operation ...................................................................... 18 Ordering Guide .......................................................................... 27 REVISION HISTORY 4/2018—Rev. E to Rev. F 3/2012—Rev. B to Rev. C Added Power-Up Sequence Section and Figure 50; Renumbered Changes to Data Sheet Title and added Patent 8,089,380 ............ 1 Sequentially ..................................................................................... 23 Updated Outline Dimensions ....................................................... 27 2/2012—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 27 Deleted Linearity Compensation Section ................................... 24 7/2013—Rev. D to Rev. E 12/2011—Rev. 0 to Rev. A Changes to t Test Conditions/Comments and Endnote 2 ......... 5 Edits to Table 2 ................................................................................... 3 1 Deleted Figure 4 ................................................................................ 7 Changes to Figure 48 ...................................................................... 17 Changes to Pin 11 Description ....................................................... 8 Changes to DAC Register Section ................................................ 21 Deleted Daisy-Chain Operation Section ..................................... 19 Changes to Table 10 and Table 11 ................................................ 22 7/2012—Rev. C to Rev. D 11/2011—Revision 0: Initial Version Changes to Figure 53 ...................................................................... 24 Changes to Figure 55 ...................................................................... 26 Rev. F | Page 2 of 27

Data Sheet AD5780 SPECIFICATIONS V = 12.5 V to 16.5 V, V = −16.5 V to −12.5 V, V = 10 V, V = −10 V, V = 2.7 V to 5.5 V, IOV = 1.71 V to 5.5 V, DD SS REFP REFN CC CC R = unloaded, C = unloaded, T to T , unless otherwise noted. L L MIN MAX Table 2. A Version, B Version1 Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE2 Resolution 18 Bits Integral Nonlinearity Error (Relative −0.85 +0.85 LSB B grade, V = +10 V, V = −10 V, REFP REFN Accuracy) T = 25°C A −1 +1 LSB B grade, V = ±10 V, +10 V, and +5 V REFx −2 +2 LSB A grade, V = ±10 V, +10 V, and +5 V REFx Differential Nonlinearity Error −0.25 +0.75 LSB B grade, V = ±10 V, +10 V, and +5 V REFx −1 +1 LSB A grade, V = ±10 V, +10 V, and +5 V REFx Long-Term Linearity Error Stability3 0.025 LSB After 750 hours at T = 135°C A Full-Scale Error −3 ±0.95 +3 LSB V = +10 V, V = −10 V REFP REFN −5.5 ±0.675 +0.5 LSB V = 10 V, V = 0 V REFP REFN −10 ±0.45 +10 LSB V = 5 V, V = 0 V REFP REFN Full-Scale Error Temperature ±0.026 ppm/°C V = +10 V, V = −10 V REFP REFN Coefficient Zero-Scale Error −4.8 ±0.325 +4.8 LSB V = +10 V, V = −10 V REFP REFN −10 ±0.175 +10 LSB V = 10 V, V = 0 V REFP REFN −20.5 ±0.225 +20.5 LSB V = 5 V, V = 0 V REFP REFN Zero-Scale Error Temperature ±0.025 ppm/°C V = +10 V, V = −10 V REFP REFN Coefficient Gain Error −19 ±2.3 +19 ppm FSR V = +10 V, V = −10 V REFP REFN −35 ±1.9 +35 ppm FSR V = 10 V, V = 0 V REFP REFN −68 ±0.9 +68 ppm FSR V = 5 V, V = 0 V REFP REFN Gain Error Temperature Coefficient ±0.018 ppm/°C V = +10 V, V = −10 V REFP REFN R1, R Matching 0.015 % FB OUTPUT CHARACTERISTICS Output Voltage Range V V V REFN REFP Output Voltage Settling Time 2.5 µs 10 V step to 0.02%, using the ADA4898-1 buffer in unity-gain mode 3.5 µs 500 code step to ±1 LSB4 Output Noise Spectral Density 8 nV/√Hz At 1 kHz, DAC code = midscale 8 nV/√Hz At 10 kHz, DAC code = midscale Output Voltage Noise 1.1 µV p-p DAC code = midscale, 0.1 Hz to 10 Hz bandwidth Midscale Glitch Impulse4 14 nV-sec V = +10 V, V = −10 V REFP REFN 3.5 nV-sec V = 10 V, V = 0 V REFP REFN 4 nV-sec V = 5 V, V = 0 V REFP REFN MSB Segment Glitch Impulse4 14 nV-sec V = +10 V, V = −10 V, see Figure 42 REFP REFN 3.5 nV-sec V = 10 V, V = 0 V, see Figure 43 REFP REFN 4 nV-sec V = 5 V, V = 0 V, see Figure 44 REFP REFN Output Enabled Glitch Impulse 57 nV-sec On removal of output ground clamp Digital Feedthrough 0.27 nV-sec DC Output Impedance (Normal Mode) 3.4 kΩ DC Output Impedance (Output 6 kΩ Clamped to Ground) Rev. F | Page 3 of 27

AD5780 Data Sheet A Version, B Version1 Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUTS V Input Range 5 V − 2.5 V REFP DD V Input Range V + 2.5 0 V REFN SS Input Bias Current −20 −0.63 +20 nA −4 −0.63 +4 T = 0°C to 105°C A Input Capacitance 1 pF V , V REFP REFN LOGIC INPUTS Input Current5 −1 +1 µA Input Low Voltage, V 0.3 × IOV V IOV = 1.71 V to 5.5 V IL CC CC Input High Voltage, V 0.7 × IOV V IOV = 1.71 V to 5.5 V IH CC CC Pin Capacitance 5 pF LOGIC OUTPUT (SDO) Output Low Voltage, V 0.4 V IOV = 1.71 V to 5.5 V, sinking 1 mA OL CC Output High Voltage, V IOV − 0.5 V IOV = 1.71 V to 5.5 V, sourcing 1 mA OH CC CC High Impedance Leakage Current ±1 µA High Impedance Output Capacitance 3 pF POWER REQUIREMENTS All digital inputs at DGND or IOV CC V 7.5 V + 33 V DD SS V V − 33 −2.5 V SS DD V 2.7 5.5 V CC IOV 1.71 5.5 V IOV ≤ V CC CC CC I 10.3 14 mA DD I −10 −14 mA SS I 600 900 µA CC IOI 52 140 µA SDO disabled CC DC Power Supply Rejection Ratio ±7.5 µV/V ∆V ± 10%, V = −15 V DD SS ±1.5 µV/V ∆V ± 10%, V = 15 V SS DD AC Power Supply Rejection Ratio 90 dB ∆V ± 200 mV, 50 Hz/60 Hz, V = −15 V DD SS 90 dB ∆V ± 200 mV, 50 Hz/60 Hz, V = 15 V SS DD 1 Temperature range: −40°C to +125°C, typical conditions: TA = 25°C, VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V. 2 Performance characterized with the AD8675ARZ output buffer. 3 Linearity error refers to both INL error and DNL error, either parameter can be expected to drift by the amount specified after the length of time specified. 4 The AD5780 is configured in the unity-gain mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer, lead capacitance, and so forth). 5 Current flowing in an individual logic pin. Rev. F | Page 4 of 27

Data Sheet AD5780 TIMING CHARACTERISTICS V = 2.7 V to 5.5 V; all specifications T to T , unless otherwise noted. CC MIN MAX Table 3. Limit1 Parameter IOV = 1.71 V to 3.3 V IOV = 3.3 V to 5.5 V Unit Test Conditions/Comments CC CC t 2 40 28 ns min SCLK cycle time 1 92 60 ns min SCLK cycle time (readback mode) t 15 10 ns min SCLK high time 2 t 9 5 ns min SCLK low time 3 t 5 5 ns min SYNC to SCLK falling edge setup time 4 t 2 2 ns min SCLK falling edge to SYNC rising edge hold time 5 t 48 40 ns min Minimum SYNC high time 6 t 8 6 ns min SYNC rising edge to next SCLK falling edge ignore 7 t 9 7 ns min Data setup time 8 t 12 7 ns min Data hold time 9 t 13 10 ns min LDAC falling edge to SYNC falling edge 10 t 20 16 ns min SYNC rising edge to LDAC falling edge 11 t 14 11 ns min LDAC pulse width low 12 t 130 130 ns typ LDAC falling edge to output response time 13 t 130 130 ns typ SYNC rising edge to output response time (LDAC tied low) 14 t 50 50 ns min CLR pulse width low 15 t 140 140 ns typ CLR pulse activation time 16 t 0 0 ns min SYNC falling edge to first SCLK rising edge 17 t 65 60 ns max SYNC rising edge to SDO tristate (C = 50 pF) 18 L t 62 45 ns max SCLK rising edge to SDO valid (C = 50 pF) 19 L t 0 0 ns min SYNC rising edge to SCLK rising edge ignore 20 t 35 35 ns typ RESET pulse width low 21 t 150 150 ns typ RESET pulse activation time 22 1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2. 2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback mode. Rev. F | Page 5 of 27

AD5780 Data Sheet t t 1 7 SCLK 1 2 24 t6 t3 t2 t t 4 5 SYNC t 9 t 8 SDIN DB23 DB0 t10 t t12 11 LDAC VOUT t13 VOUT t14 t 15 CLR t 16 VOUT t 21 RESET t 22 VOUT 09649-002 Figure 2. Write Mode Timing Diagram t17 t1 t7 t20 SCLK 1 2 24 1 2 24 t6 t3 t2 t t t4 t5 17 5 SYNC t 9 t 8 SDIN DB23 DB0 INPUTWORDSPECIFIES NOPCONDITION t REGISTERTOBEREAD 18 t 19 SDO DB23 DB0 REGISTERCONTENTSCLOCKED OUT 09649-003 Figure 3. Readback Mode Timing Diagram Rev. F | Page 6 of 27

Data Sheet AD5780 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents of up to A Stresses at or above those listed under Absolute Maximum 100 mA do not cause SCR latch-up. Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these Table 4. or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Operation beyond V to AGND −0.3 V to +34 V DD the maximum operating conditions for extended periods may V to AGND −34 V to +0.3 V SS affect product reliability. V to V −0.3 V to +34 V DD SS V to DGND −0.3 V to +7 V This device is a high performance integrated circuit with an CC IOV to DGND −0.3 V to V + 3 V or +7 V ESD rating of 1.6 kV, and it is ESD sensitive. Proper precautions CC CC (whichever is less) must be taken for handling and assembly. Digital Inputs to DGND −0.3 V to IOV + 0.3 V or CC +7 V (whichever is less) V to AGND −0.3 V to V + 0.3 V ESD CAUTION OUT DD V to AGND −0.3 V to V + 0.3 V REFP DD V to AGND V − 0.3 V to +0.3 V REFN SS DGND to AGND −0.3 V to +0.3 V Operating Temperature Range, T A Industrial −40°C to +125°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature, 150°C T max J Power Dissipation (T max − T )/θ J A JA LFCSP Package θ Thermal Impedance 31.0°C/W JA Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 1.6 kV Rev. F | Page 7 of 27

AD5780 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VNICNDCNDCNDRBF 4232221202 VOUT1 19AGND VREFP2 18VSS VDD3 AD5780 17VSS RESET4 TOP VIEW 16VREFN VDD5 (Not to Scale) 15DGND CLR6 14SYNC LDAC7 13SCLK 89011121 C CCON VCVOCNDDSIDS I NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. NEGATIVE ANALOG SUPPLY CONNECTION (VSS). A VOLTAGE IN THE RANGE OF –16.5 V TO –2.5 V CAN BE CONNECTED. VSS SHOULD BE DECOUPLED TO AGND. THE PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CRCTHOEOECNNRONNMMEEACCMLTTE EIPNODEDN RTE IOFDSO MTARH ACMADOATEPN TPACHETEER .T PHPAELDA VDNSLESE F PBOIENR ST E.H NITEH RIASMNACLELDY 09649-005 Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 V Analog Output Voltage. OUT 2 V Positive Reference Voltage Input. A voltage in the range of 5 V to V − 2.5 V can be connected to this pin. REFP DD 3, 5 V Positive Analog Supply Connection. A voltage in the range of 7.5 V to 16.5 V can be connected to this pin. V must DD DD be decoupled to AGND. 4 RESET Active Low Reset. Asserting this pin returns the AD5780 to its power-on status. 6 CLR Active Low Input. Asserting this pin sets the DAC register to a user defined value (see Table 12) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. 7 LDAC Active Low Load DAC Logic Input. This pin is used to update the DAC register and, consequently, the analog output. When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. Do not leave the LDAC pin unconnected. 8 V Digital Supply. Voltage range is from 2.7 V to 5.5 V. V should be decoupled to DGND. CC CC 9 IOV Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. Voltage range is CC from 1.71 V to 5.5 V. 10, 21, DNC Do Not Connect. Do not connect to these pins. 22, 23 11 SDO Serial Data Output. Data is clocked out on the rising edge of the serial clock input. 12 SDIN Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 35 MHz. 14 SYNC Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks. The DAC is updated on the rising edge of SYNC. 15 DGND Ground Reference Pin for Digital Circuitry. 16 V Negative Reference Voltage Input. REFN 17, 18 V Negative Analog Supply Connection. A voltage in the range of −16.5 V to −2.5 V can be connected to this pin. SS V must be decoupled to AGND. SS 19 AGND Ground Reference Pin for Analog Circuitry. 20 R Feedback Connection for External Amplifier. See the AD5780 Features section for further details. FB 24 INV Inverting Input Connection for External Amplifier. See the AD5780 Features section for further details. EPAD V Negative Analog Supply Connection (V ). A voltage in the range of −16.5 V to −2.5 V can be connected to this pin. SS SS V must be decoupled to AGND. The paddle can be left electrically unconnected provided that a supply connection is SS made at the V pins. It is recommended that the paddle be thermally connected to a copper plane for enhanced SS thermal performance. Rev. F | Page 8 of 27

Data Sheet AD5780 TYPICAL PERFORMANCE CHARACTERISTICS 0.4 AD8675 OUTPUT BUFFER 0.4 0.3 TA = 25°C 0.3 ATAD 8=6 2755° OCUTPUT BUFFER 0.2 0.2 0.1 0.1 0 INL (LSB) –0.10 INL (LSB) ––00..21 –0.3 –0.2 –0.4 ––00..430 50000 100000 DA1C50 C0O00DE 200000 VVVV2RRDS5SEED0 FF 0==PN0 –+0==11 5+–5V11V003VV00000 09649-006 –––000...7650 50000 100000 DA1C50 C0O00DE 200000 2VVVV5RRDS0S0DEE0 FF ==PN0 –+==11 5+05V35VV0V0000 09649-009 Figure 5. Integral Nonlinearity Error vs. DAC Code, ±10 V Span Figure 8. Integral Nonlinearity Error vs. DAC Code, 5 V Span, ×2 Gain Mode 0.6 0.5 AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER 0.5 TA = 25°C 0.4 TA = 25°C 0.4 0.3 0.3 0.2 INL (LSB) 00..120 DNL (LSB) 0.10 –0.1 –0.1 –0.2 –0.2 –0.3 VVVVRRDSSDEE FF ==PN –+==11 5+05VV1V0V –0.3 VVVVRRDSSEED FF ==PN –+==11 5+–5V11V00VV –0.40 50000 100000 DA1C50 C0O00DE 200000 250000 300000 09649-007 –0.40 50000 100000 DA1C50 C0O00DE 200000 250000 300000 09649-010 Figure 6. Integral Nonlinearity Error vs. DAC Code, 10 V Span Figure 9. Differential Nonlinearity Error vs. DAC Code, ±10 V Span 0.8 0.7 AD8675 OUTPUT BUFFER AD8675 OUTPUT BUFFER 0.6 TA = 25°C TA = 25°C 0.5 0.4 0.3 0.2 SB) 0 SB) 0.1 INL (L –0.2 DNL (L –0.1 –0.4 –0.3 –0.6 –0.8 VVRREEFFPN == +0V5V –0.5 VVRREEFFPN == +0V10V VDD = +15V VDD = +15V VSS = –15V VSS = –15V –1.00 50000 100000 DA1C50 C0O00DE 200000 250000 300000 09649-008 –0.70 50000 100000 DA1C50 C0O00DE 200000 250000 300000 09649-011 Figure 7. Integral Nonlinearity Error vs. DAC Code, 5 V Span Figure 10. Differential Nonlinearity Error vs. DAC Code, 10 V Span Rev. F | Page 9 of 27

AD5780 Data Sheet 0.5 0.40 ±10V SPAN MAX DNL ±10V SPAN MIN DNL +10V SPAN MAX DNL +10V SPAN MIN DNL 0.4 0.35 +5V SPAN MAX DNL +5V SPAN MIN DNL 0.3 0.30 0.2 SB) 0.25 L SB) 0.1 OR ( 0.20 DNL (L 0 L ERR 0.15 VVDSSD == –+1155VV N AD8675 OUTPUT BUFFER –0.1 D 0.10 –0.2 0.05 VREFP = +5V –0.3 AD8675 OUTPUT BUFFER VVRDDEF =N +=1 05VV 0 TA = 25°C VSS = –15V –0.4 –0.05 0 50000 100000 DA1C50 C0O00DE 200000 250000 300000 09649-012 –40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 09649-015 Figure 11. Differential Nonlinearity Error vs. DAC Code, 5 V Span Figure 14. Differential Nonlinearity Error vs. Temperature 0.6 0.4 AD8675 OUTPUT BUFFER VREFP = +5V TA = 25°C VREFN = 0V 0.5 VVDSSD == –+1155VV 0.3 INL MAX 0.4 0.2 0.3 SB) 0.1 DNL (LSB) 0.2 ERROR (L 0 ATVVARRD EE8=FF6 PN27 5 5==° OC+–11U00TVVPUTBUFFER 0.1 L –0.1 N I 0 –0.2 INL MIN –0.1 –0.3 –0.2 –0.4 0 50000 100000 DA1C50 C0O00DE 200000 250000 300000 09649-013 12.5 13.0 13.5 14.0VDD/1|V4S.5S| (V)15.0 15.5 16.0 16.5 09649-016 Figure 12. Differential Nonlinearity Error vs. DAC Code, 5 V Span, Figure 15. Integral Nonlinearity Error vs. Supply Voltage, ±10 V Span ×2 Gain Mode ±10V SPAN MAX INL ±10V SPAN MIN INL 0.7 +10V SPAN MAX INL +10V SPAN MIN INL 0.4 INL MAX +5V SPAN MAX INL +5V SPAN MIN INL 0.5 0.2 RROR (LSB) 00..13 ERROR (LSB) 0 TVAVARRD EE8=FF6 PN27 5 5==° CO50VVUTPUTBUFFER L E NL –0.2 N I I –0.1 INL MIN –0.4 –0.3 VDD = +15V VSS = –15V AD8675 OUTPUT BUFFER –0.6 –0.5–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 09649-014 7.5 8.5 9.5 10.5 V1D1D.5/|VSS1|2 (.V5) 13.5 14.5 15.5 16.5 09649-017 Figure 13. Integral Nonlinearity Error vs. Temperature Figure 16. Integral Nonlinearity Error vs. Supply Voltage, 5 V Span Rev. F | Page 10 of 27

Data Sheet AD5780 0.35 4 TA = 25°C 0.30 DNL MAX 3 VVARRDEE8FF6PN7 5== O50VVUTPUT BUFFER 0.25 B) S LSB)0.20 TA = 25°C OR (L 2 ROR (0.15 VVARRDEE8FF6PN7 5== O+–11U00TVVPUT BUFFER E ERR 1 R L E A NL 0.10 SC D O- 0 R 0.05 ZE DNL MIN –1 0 –0.05 –2 12.5 13.0 13.5 14.0VDD/1|V4S.5S| (V)15.0 15.5 16.0 16.5 09649-018 7.5 8.5 9.5 10.5 V1D1D.5/|VSS1|2 (.V5) 13.5 14.5 15.5 16.5 09649-021 Figure 17. Differential Nonlinearity Error vs. Supply Voltage, ±10 V Span Figure 20. Zero-Scale Error vs. Supply Voltage, 5 V Span 0.35 0 0.30 DNL MAX –0.1 TVVAARRD EE8=FF6 PN27 5 5==° OC+–11U00TVVPUT BUFFER 0.25 B) RROR (LSB)00..1250 TVVAARRD EE8=FF6 PN27 5 5==° OC50VVUTPUT BUFFER E ERROR (LS––00..23 E L NL 0.10 CA D DS–0.4 MI 0.05 –0.5 0 DNL MIN –0.05 –0.6 7.5 8.5 9.5 10.5 V1D1D.5/|VSS1|2 .(5V) 13.5 14.5 15.5 16.5 09649-019 12.5 13.0 13.5 14.0VDD/1|V4S.5S| (V)15.0 15.5 16.0 16.5 09649-022 Figure 18. Differential Nonlinearity Error vs. Supply Voltage, 5 V Span Figure 21. Midscale Error vs. Supply Voltage, ±10 V Span 0.5 2.0 TA = 25°C 0.4 VREFP = +10V VREFN = –10V 1.5 0.3 AD8675 OUTPUT BUFFER SB) B) 1.0 L 0.2 S ROR ( 0.1 OR (L 0.5 R R E R LE 0 E E 0 A L C–0.1 A S C–0.5 ZERO-–0.2 MIDS–1.0 –0.3 TA = 25°C –0.4 –1.5 VVRREEFFPN == 50VV AD8675 OUTPUT BUFFER –0.5 –2.0 12.5 13.0 13.5 14.0VDD/1|V4S.5S| (V)15.0 15.5 16.0 16.5 09649-020 7.5 8.5 9.5 10.5 V1D1D.5/|VSS1|2 (.5V) 13.5 14.5 15.5 16.5 09649-023 Figure 19. Zero-Scale Error vs. Supply Voltage, ±10 V Span Figure 22. Midscale Error vs. Supply Voltage, 5 V Span Rev. F | Page 11 of 27

AD5780 Data Sheet 0.50 1.50 TA = 25°C 0.45 VREFP = +10V 1.45 VREFN = –10V 0.40 AD8675 OUTPUT BUFFER 1.40 B) R (LS0.35 SB)1.35 E ERRO00..2350 RROR (L11..2350 CAL0.20 N E1.20 S AI LL-0.15 G1.15 U F 0.10 1.10 TA = 25°C 0.05 1.05 VVRREEFFNP == 50VV AD8675 OUTPUT BUFFER 0 1.00 12.5 13.0 13.5 14.0VDD/1|V4S.5S| (V)15.0 15.5 16.0 16.5 09649-024 7.5 8.5 9.5 10.5 V1D1D.5/|VSS1|2 (.V5) 13.5 14.5 15.5 16.5 09649-027 Figure 23. Full-Scale Error vs. Supply Voltage, ±10 V Span Figure 26. Gain Error vs. Supply Voltage, 5 V Span 1.5 0.3 TA = 25°C 1.0 VREFP = 5V INL MAX VREFN = 0V 0.2 AD8675 OUTPUT BUFFER B) 0.5 LS 0.1 R ( 0 B) O S L-SCALE ERR–––110...550 INL ERROR (L–0.10 TVVAADSDS D8= 6= =27 5–+5°1 1OC55VUVTPUT BUFFER UL –0.2 F–2.0 INL MIN –0.3 –2.5 –3.07.5 8.5 9.5 10.5 V1D1D.5/|VSS1|2 (.V5) 13.5 14.5 15.5 16.5 09649-025 –0.45.0 5.5 6.0 6.5 V7R.E0FP/|7V.R5EFN|8 (.V0) 8.5 9.0 9.5 10.0 09649-028 Figure 24. Full-Scale Error vs. Supply Voltage, 5 V Span Figure 27. Integral Nonlinearity Error vs. Reference Voltage 0.35 0.30 TA = 25°C VREFP = +10V INL MAX 0.25 VREFN = –10V 0.25 AD8675 OUTPUT BUFFER 0.20 AIN ERROR (LSB) 00..0155 NL ERROR (LSB)00..1105 TVVAADSDS D8= 6= =27 5–+5°1 1OC55VUVTPUT BUFFER G–0.05 D 0.05 –0.15 INL MIN 0 –0.25 –0.05 12.5 13.0 13.5 14.0VDD/1|V4S.5S| (V)15.0 15.5 16.0 16.5 09649-026 5.0 5.5 6.0 6.5 V7R.E0FP/|V7.R5EFN|8 (.V0) 8.5 9.0 9.5 10.0 09649-029 Figure 25. Gain Error vs. Supply Voltage, ±10 V Span Figure 28. Differential Nonlinearity Error vs. Reference Voltage Rev. F | Page 12 of 27

Data Sheet AD5780 0 –1.0 TA = 25°C TA = 25°C –0.05 VVDSSD == –+1155VV –1.1 VVDSSD == –+1155VV AD8675 OUTPUT BUFFER –1.2 AD8675 OUTPUT BUFFER B)–0.10 RO-SCALE ERROR (LS–––000...221505 GAIN ERROR (LSB) –––––11111.....76543 E–0.30 Z –1.8 –0.35 –1.9 –0.40 –2.0 5.0 5.5 6.0 6.5 V7R.0EFP/|7V.5REFN8| .(0V) 8.5 9.0 9.5 10.0 09649-030 5.0 5.5 6.0 6.5 V7R.E0FP/|7V.R5EFN|8 (.V0) 8.5 9.0 9.5 10.0 09649-033 Figure 29. Zero-Scale Error vs. Reference Voltage Figure 32. Gain Error vs. Reference Voltage –0.2 1.8 –0.3 VTVADSS D= = =2 5–+°11C55VV ±++1510V0VV S SSPPPAAANNN AD8675 OUTPUT BUFFER 1.6 DSCALE ERROR (LSB) ––––0000....7654 L-SCALE ERROR (LSB) 111...024 MI –0.8 UL F 0.8 –0.9 VDD = +15V VSS = –15V AD8675 OUTPUT BUFFER –1.0 0.6 5.0 5.5 6.0 6.5 V7R.0EFP/|7V.R5EFN8| .(0V) 8.5 9.0 9.5 10.0 09649-031 –40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 09649-034 Figure 30. Midscale Error vs. Reference Voltage Figure 33. Full-Scale Error vs. Temperature 0.6 1.7 TA = 25°C ±+1100VV SSPPAANN VDD = +15V 0.4 +5V SPAN VSS = –15V AD8675 OUTPUT BUFFER 0.2 L-SCALE ERROR (LSB) 111...135 DSCALE ERROR (LSB) –––000...6420 UL MI F –0.8 0.9 –1.0 VDD = +15V VSS = –15V AD8675 OUTPUT BUFFER 0.75.0 5.5 6.0 6.5 V7R.0EFP/|7V.R5EFN8| .(0V) 8.5 9.0 9.5 10.0 09649-032 –1.2–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 09649-035 Figure 31. Full-Scale Error vs. Reference Voltage Figure 34. Midscale Error vs. Temperature Rev. F | Page 13 of 27

AD5780 Data Sheet 1.0 0.010 ±10V SPAN +10V SPAN 0.5 +5V SPAN 0.008 IDD 0.006 B) 0 S L 0.004 ROR (–0.5 A) 0.002 R m ALE E–1.0 /I (DSS 0 SC–1.5 ID –0.002 O- R –0.004 ZE–2.0 –0.006 –2.5 VDD = +15V ISS VSS = –15V –0.008 AD8675 OUTPUT BUFFER –3.0–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 09649-036 –0.010–20 –15 –10 –5VDD/V0SS (V) 5 10 15 20 09649-039 Figure 35. Zero-Scale Error vs. Temperature Figure 38. Power Supply Currents vs. Power Supply Voltages 0 6 ±10V SPAN +10V SPAN –0.5 +5V SPAN 4 –1.0 2 B) LS–1.5 0 ERROR (–2.0 V (V)OUT –2 VVVDSRSDE F ==P –+=11 5+5V1V0V AIN –2.5 –4 VARDEAF4N8 0=8 –-11 0BVUFFERED G LOAD = 10MΩ || 20pF –3.0 –6 –3.5 VDD = +15V –8 VSS = –15V AD8675 OUTPUT BUFFER –4.0–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 09649-037 –10–1 0 1 TIME2 (µs) 3 4 5 09649-040 Figure 36. Gain Error vs. Temperature Figure 39. Rising Full-Scale Voltage Step 900 6 800 TA = 25°C IIIONOCVVRCCCCE A==S 55IVVN,,G LLOOGGIICC VVOOLLTTAAGGEE 4 VVVDSRSED F ==P –+=11 5+5V1V0V DECREASING VREFN = –10V 700 IINOCVRCCE A=S 3IVN,G LOGIC VOLTAGE 2 ALODAA4D8 =0 81-01M BΩU F||F 2E0RpEFD 600 IOVCC = 3V, LOGIC VOLTAGE DECREASING 0 (µA)C500 (V)UT –2 C O OI400 V I –4 300 –6 200 –8 100 00 1 LO2GIC INPUT3 VOLTAGE4 (V) 5 6 09649-038 –10–1 0 1 TIME2 (µs) 3 4 5 09649-041 Figure 37. IOICC vs. Logic Input Voltage Figure 40. Falling Full-Scale Voltage Step Rev. F | Page 14 of 27

Data Sheet AD5780 10 6 VREFP = 5V NEGATIVE 9 VURNEITFYN -=G 0AVIN MODE POSITIVE 5 ADA4898-1 OUTPUT BUFFER 8 RC LOW-PASS FILTER 7 nV-s) 4 mV) 6 TCH ( (UT 5 GLI 3 VO 4 UT P UT 2 3 O 2 VREFP = +10V VREFN = –10V 1 RC LOW-PASS FILTER 1 UNITY-GAIN MODE ADA4898-1 OUTPUT BUFFER 0–1 0 1 TIM2E (µs) 3 4 5 09649-042 0 1638465536114688163840212992262144311296360448409600458752CO507904D557056E 606208655360704512753664802816851968901120950272999424 09649-047 Figure 41. 500 Code Step Settling Time Figure 44. 6 MSB Segment Glitch Energy for 5 V VREF 25 55 VREFP = +10V NEGATIVE ±10V SPAN VREFN = –10V POSITIVE +10V SPAN UNITY-GAIN MODE 45 +5V SPAN ADA4898-1 OUTPUT BUFFER 20 RC LOW-PASS FILTER NEGATIVE POSITIVE 35 V-s) CODE CHANGE CODE CHANGE mV) OUTPUT GLITCH (n 1105 OUTPUT GLITCH ( 12555 –5 5 –15 0 –25 163844915281920114688147456180224212992245760278528311296344064376832409600442368475136C507904OD540672E5734406062086389766717447045127372807700488028168355848683529011209338889666569994241032192 09649-043 –1 0 TIME1 (µs) 2 3 09649-046 Figure 42. 6 MSB Segment Glitch Energy for ±10 V VREF Figure 45. Midscale Peak-to-Peak Glitch for ±10 V 4.0 800 VREFP = 10V NEGATIVE TA = 25°C MIDSCALE CODE LOADED 3.5 VUARNDEIATF4YN8 -=9G 80A-V1IN MODE POSITIVE 600 VVDSSD == –+1155VV OUTPUT UNBUFFERED OUTPUT BUFFER VREFP = +10V 3.0 RC LOW-PASS FILTER VREFN = –10V s) V) 400 H(nV- 2.5 GE (n C A 200 UTPUT GLIT 12..50 UTPUT VOLT 0 O O–200 1.0 0.5 –400 0 1638465536114688163840212992262144311296360448409600458752C507904OD557056E 606208655360704512753664802816851968901120950272999424 09649-044 –6000 1 2 3 T4IME (S5econd6s) 7 8 9 10 09649-045 Figure 43. 6 MSB Segment Glitch Energy for 10 V VREF Figure 46. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth Rev. F | Page 15 of 27

AD5780 Data Sheet 100 200 VVVVDSRRSDEE FF ==PN –+==11 5+–5V11V00VV 116800 VVVVRDSRSEDE FF ==NP –+==11 5+–5V11V00VV UNITY GAIN V) 140 ADA4898-1 m Hz) GE ( 120 nV/√ 10 OLTA 100 NSD ( UT V 80 P 60 T U O 40 20 0 10.1 1 FR10EQUENCY 1(H00z) 1k 10k 09649-055 –200 1 2 TIME3 (µs) 4 5 6 09649-048 Figure 47. Noise Spectral Density vs. Frequency Figure 48. Glitch Impulse on Removal of Output Clamp Rev. F | Page 16 of 27

Data Sheet AD5780 TERMINOLOGY Relative Accuracy Output Voltage Settling Time Relative accuracy, or integral nonlinearity (INL), is a measure of Output voltage settling time is the amount of time it takes for the maximum deviation, in LSB, from a straight line passing the output voltage to settle to a specified level for a specified through the endpoints of the DAC transfer function. A typical change in voltage. For fast settling applications, a high speed INL error vs. code plot is shown in Figure 5. buffer amplifier is required to buffer the load from the 3.4 kΩ output impedance of the AD5780, in which case, it is the Differential Nonlinearity (DNL) amplifier that determines the settling time. Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent Digital-to-Analog Glitch Impulse codes. A specified differential nonlinearity of ±1 LSB maximum Digital-to-analog glitch impulse is the impulse injected into the ensures monotonicity. This DAC is guaranteed monotonic. A analog output when the input code in the DAC register changes typical DNL error vs. code plot is shown in Figure 9. state. It is specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at Linearity Error Long-Term Stability the major carry transition (see Figure 48). Linearity error long-term stability is a measure of the stability of the linearity of the DAC over a long period of time. It is speci- Output Enabled Glitch Impulse fied in LSB for a time period of 500 hours and 1000 hours at an Output enabled glitch impulse is the impulse injected into the elevated ambient temperature. analog output when the clamp to ground on the DAC output is removed. It is specified as the area of the glitch in nV-sec (see Zero-Scale Error Figure 48). Zero-scale error is a measure of the output error when zero-scale code (0x00000) is loaded to the DAC register. Ideally, the output Digital Feedthrough voltage should be VREFN. Zero-scale error is expressed in LSBs. Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the Zero-Scale Error Temperature Coefficient DAC but is measured when the DAC output is not updated. It is Zero-scale error temperature coefficient is a measure of the specified in nV-sec and measured with a full-scale code change change in zero-scale error with a change in temperature. It is on the data bus, that is, from all 0s to all 1s, and vice versa. expressed in ppm FSR/°C. Total Harmonic Distortion (THD) Full-Scale Error Total harmonic distortion is the ratio of the rms sum of the Full-scale error is a measure of the output error when full-scale harmonics of the DAC output to the fundamental value. Only code (0x3FFFF) is loaded to the DAC register. Ideally, the the second to fifth harmonics are included. output voltage should be V − 1 LSB. Full-scale error is REFP expressed in LSBs. DC Power Supply Rejection Ratio DC power supply rejection ratio is a measure of the rejection of Full-Scale Error Temperature Coefficient the output voltage to dc changes in the power supplies applied Full-scale error temperature coefficient is a measure of the to the DAC. It is measured for a given dc change in power change in full-scale error with a change in temperature. It is supply voltage and is expressed in µV/V. expressed in ppm FSR/°C. AC Power Supply Rejection Ratio (AC PSRR) Gain Error AC power supply rejection ratio is a measure of the rejection of Gain error is a measure of the span error of the DAC. It is the the output voltage to ac changes in the power supplies applied deviation in slope of the DAC transfer characteristic from the to the DAC. It is measured for a given amplitude and frequency ideal, expressed in ppm of the full-scale range. change in power supply voltage and is expressed in decibels. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with a change in temperature. It is expressed in ppm FSR/°C. Midscale Error Midscale error is a measure of the output error when midscale code (0x20000) is loaded to the DAC register. Ideally, the output voltage should be (V – V )/2 + V . Midscale error is REFP REFN REFN expressed in LSBs. Rev. F | Page 17 of 27

AD5780 Data Sheet THEORY OF OPERATION The AD5780 is a high accuracy, fast settling, single, 18-bit, SERIAL INTERFACE serial input, voltage output DAC. It operates from a V supply DD The AD5780 has a 3-wire serial interface (SYNC, SCLK, and voltage of 7.5 V to 16.5 V and a V supply of −16.5 V to −2.5 V. SS SDIN) that is compatible with SPI, QSPI, and MICROWIRE Data is written to the AD5780 in a 24-bit word format via a 3-wire interface standards, as well as most DSPs (see Figure 2 for a serial interface. The AD5780 incorporates a power-on reset timing diagram). circuit that ensures the DAC output powers up to 0 V with the V pin clamped to AGND through a ~6 kΩ internal resistor. Input Shift Register OUT DAC ARCHITECTURE The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial The architecture of the AD5780 consists of two matched DAC clock input, SCLK, which can operate at up to 35 MHz. The sections. A simplified circuit diagram is shown in Figure 49. input register consists of an R/W bit, three address bits, and The six MSBs of the 18-bit data-word are decoded to drive 20 data bits as shown in Table 6. The timing diagram for this 63 switches, E0 to E62. Each of these switches connects one operation is shown in Figure 2. of 63 matched resistors to either the buffered V or buffered REFP V voltage. The remaining 12 bits of the data-word drive the REFN S0 to S11 switches of a 12-bit voltage mode R-2R ladder network. R R R VOUT 2R 2R 2R... 2R 2R 2R... 2R VREFP S0 S1... S11 E62 E61... E0 VREFN 12-BITR-2RLADDER SI6X3MESQBUsADLESCEOGDMEEDN ITNSTO 09649-049 Figure 49. DAC Ladder Structure Serial Interface Table 6. Input Shift Register Format MSB LSB DB23 DB22 DB21 DB20 DB19 to DB0 R/W Register address Register data Table 7. Decoding the Input Shift Register R/W Register Address Description X1 0 0 0 No operation (NOP). Used in readback operations. 0 0 0 1 Write to the DAC register. 0 0 1 0 Write to the control register. 0 0 1 1 Write to the clearcode register. 0 1 0 0 Write to the software control register. 1 0 0 1 Read from the DAC register. 1 0 1 0 Read from the control register. 1 0 1 1 Read from the clearcode register. 1 X is don’t care. Rev. F | Page 18 of 27

Data Sheet AD5780 Standalone Operation Synchronous DAC Update The serial interface works with both a continuous and noncon- In this mode, LDAC is held low while data is being clocked into tinuous serial clock. A continuous SCLK source can be used the input shift register. The DAC output is updated on the rising only if SYNC is held low for the correct number of clock cycles. edge of SYNC. In gated clock mode, a burst clock containing the exact number Asynchronous DAC Update of clock cycles must be used, and SYNC must be taken high after In this mode, LDAC is held high while data is being clocked the final clock to latch the data. The first falling edge of SYNC into the input shift register. The DAC output is asynchronously starts the write cycle. Exactly 24 falling clock edges must be updated by taking LDAC low after SYNC has been taken high. applied to SCLK before SYNC is brought high again. If SYNC is The update now occurs on the falling edge of LDAC. brought high before the 24th falling SCLK edge, the data written Reset Function (RESET) is invalid. If more than 24 falling SCLK edges are applied before SYNC is brought high, the input data is also invalid. The AD5780 can be reset to its power-on state by two means: The input shift register is updated on the rising edge of SYNC. either by asserting the RESET pin or by using the reset function For another serial transfer to take place, SYNC must be brought in the software control register (see Table 13). If the RESET pin is not used, hardwire it to IOV . low again. After the end of the serial data transfer, data is CC automatically transferred from the input shift register to the Asynchronous Clear Function (CLR) addressed register. When the write cycle is complete, the output The CLR pin is an active low clear that allows the output to be can be updated by taking LDAC low while SYNC is high. cleared to a user defined value. The 18-bit clearcode value is Readback programmed to the clearcode register (see Table 12). It is The contents of all the on-chip registers can be read back via necessary to maintain CLR low for a minimum amount of time the SDO pin. Table 7 outlines how the registers are decoded. to complete the operation (see Figure 2). When the CLR signal After a register has been addressed for a read, the next 24 clock is returned high, the output remains at the clear value (if LDAC cycles clock the data out on the SDO pin. The clocks must be is high) until a new value is loaded to the DAC register. The applied while SYNC is low. When SYNC is returned high, the output cannot be updated with a new value while the CLR pin is SDO pin is placed in tristate. For a read of a single register, the low. A clear operation can also be performed by setting the CLR NOP function can be used to clock out the data. Alternatively, bit in the software control register (see Table 13). if more than one register is to be read, the data of the first ON-CHIP REGISTERS register to be addressed can be clocked out at the same time DAC Register that the second register to be read is being addressed. The SDO pin must be enabled to complete a readback operation. The Table 9 outlines how data is written to and read from the DAC SDO pin is enabled by default. register. HARDWARE CONTROL PINS The following equation describes the ideal transfer function of Load DAC Function (LDAC) the DAC: (V −V )×D After data has been transferred into the input register of the V = REFP REFN +V DAC, there are two ways to update the DAC register and DAC OUT 218 REFN output. Depending on the status of both SYNC and LDAC, one where: of two update modes is selected: synchronous DAC update or VREFN is the negative voltage applied at the VREFN input pin. asynchronous DAC update. VREFP is the positive voltage applied at the VREFP input pin. D is the 18-bit code programmed to the DAC. Rev. F | Page 19 of 27

AD5780 Data Sheet Table 8. Hardware Control Pins Truth Table LDAC CLR RESET Function X1 X1 0 The AD5780 is in reset mode. The device cannot be programmed. X1 X1 The AD5780 is returned to its power-on state. All registers are set to their default values. 0 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly. 0 1 1 The output is set according to the DAC register value. 1 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly. 1 1 The output is set according to the DAC register value. 0 1 The output remains at the clearcode register value. 1 1 The output remains set according to the DAC register value. 0 1 The output remains at the clearcode register value. 1 1 The DAC register is loaded with the clearcode register value and the output is set accordingly. 0 1 The DAC register is loaded with the clearcode register value and the output is set accordingly. 1 1 The output remains at the clearcode register value. 0 1 The output is set according to the DAC register value. 1 X is don’t care. Table 9. DAC Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0 R/W Register address DAC register data R/W 0 0 1 18 bits of data X1 X1 1 X is don’t care. Rev. F | Page 20 of 27

Data Sheet AD5780 Control Register Clearcode Register The control register controls the mode of operation of the The clearcode register sets the value to which the DAC output is AD5780. set when the CLR pin or CLR bit in the software control register is asserted. The output value depends on the DAC coding that is being used, either binary or twos complement. The default register value is 0. Table 10. Control Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R/W Register address Control register data R/W 0 1 0 Reserved Reserved 0000 SDODIS BIN/2sC DACTRI OPGND RBUF Reserved Table 11. Control Register Functions Bit Name Description Reserved These bits are reserved and should be programmed to zero. RBUF Output amplifier configuration control. 0: the internal amplifier, A1, is powered up and Resistors R and R1 are connected in series as shown in Figure 53. This allows FB an external amplifier to be connected in a gain of two configuration. See the AD5780 Features section for further details. 1: (default) the internal amplifier, A1, is powered down and Resistors R and R1 are connected in parallel, as shown in Figure 52, FB so that the resistance between the R and INV pins is 3.4 kΩ, equal to the resistance of the DAC. This allows the R and INV FB FB pins to be used for input bias current compensation for an external unity-gain amplifier. See the AD5780 Features section for further details. OPGND Output ground clamp control. 0: the DAC output clamp to ground is removed, and the DAC is placed in normal mode. 1: (default) the DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate mode. Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated. Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit. DACTRI DAC tristate control. 0: the DAC is in normal operating mode. 1: (default) the DAC is in tristate mode. BIN/2sC DAC register coding selection. 0: (default) the DAC register uses twos complement coding. 1: the DAC register uses offset binary coding. SDODIS SDO pin enable/disable control. 0: (default) the SDO pin is enabled. 1: the SDO pin is disabled (tristate). R/W Read/write select bit. 0: AD5780 is addressed for a write operation. 1: AD5780 is addressed for a read operation. Table 12. Clearcode Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0 R/W Register address Clearcode register data R/W 0 1 1 18 bits of data X1 X1 1 X is don’t care. Rev. F | Page 21 of 27

AD5780 Data Sheet Software Control Register This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low. Table 13. Software Control Register MSB LSB DB23 DB22 DB21 DB20 DB19 to DB3 DB2 DB1 DB0 R/W Register address Software control register data 0 1 0 0 Reserved Reset CLR1 LDAC2 1 The CLR function has no effect when the LDAC pin is low. 2 The LDAC function has no effect when the CLR pin is low. Table 14. Software Control Register Functions Bit Name Description LDAC Setting this bit to 1 updates the DAC register and consequently the DAC output. CLR Setting this bit to 1 sets the DAC register to a user defined value (see Table 12) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. Reset Setting this bit to 1 returns the AD5780 to its power-on state. Rev. F | Page 22 of 27

Data Sheet AD5780 AD5780 FEATURES POWER-ON TO 0 V OUTPUT AMPLIFIER CONFIGURATION The AD5780 contains a power-on reset circuit that, as well as There are a number of different ways that an output amplifier resetting all registers to their default values, controls the output can be connected to the AD5780, depending on the voltage voltage during power-up. Upon power-on, the DAC is placed in references applied and the desired output voltage span. tristate (its reference inputs are disconnected), and its output is clamped to AGND through a ~6 kΩ resistor. The DAC remains Unity-Gain Configuration in this state until programmed otherwise via the control register. Figure 51 shows an output amplifier configured for unity gain. This is a useful feature in applications where it is important to In this configuration, the output spans from V to V . REFN REFP know the state of the DAC output while it is in the process of VREFP powering up. POWER-UP SEQUENCE R1 RFB RFB A1 To power up the part in a known safe state, ensure that VCC does 6.8kΩ 6.8kΩ AD8675, ADA4898-1, not come up while V is unpowered during power-on by DD INV ADA4004-1 powering up the V supply before the V supply. If this cannot 18-BIT be achieved, conneDcDt an external SchottCkCy diode across the V DAC VOUT VOUT DD and V supplies as shown in Figure 50. CC VCC VDD VREFN AD5780 09649-051 Figure 51. Output Amplifier in Unity-Gain Configuration VCC VDD A second unity-gain configuration for the output amplifier is one that removes an offset from the input bias currents of the AD5780 amplifier. It does this by inserting a resistance in the feedback 09649-050 path of the amplifier that is equal to the output resistance of the DAC. The DAC output resistance is 3.4 kΩ. By connecting R1 Figure 50. Schottky Diode Connection and R in parallel, a resistance equal to the DAC resistance is FB CONFIGURING THE AD5780 available on chip. Because the resistors are all on one piece of After power-on, the AD5780 must be configured for normal silicon, they are temperature coefficient matched. To enable this operating mode before programming the output. To do this, the mode of operation, the RBUF bit of the control register must be control register must be programmed. The DAC is removed set to Logic 1. Figure 52 shows how the output amplifier is from tristate by clearing the DACTRI bit, and the output clamp connected to the AD5780. In this configuration, the output is removed by clearing the OPGND bit. At this point, the output amplifier is in unity gain and the output spans from V to REFN goes to VREFN unless an alternative value is first programmed to VREFP. This unity-gain configuration allows a capacitor to be the DAC register. placed in the amplifier feedback path to improve dynamic performance. DAC OUTPUT STATE VREFP The DAC output can be placed in one of three states, controlled by the DACTRI and OPGND bits of the control register, as shown in Table 15. RFB R1 RFB 10pF 6.8kΩ 6.8kΩ Table 15. Output State Truth Table INV VOUT DACTRI OPGND Output State 18-BIT DAC VOUT AD8675, 0 0 Normal operating mode. ADA4898-1, 0 1 Output is clamped via ~6 kΩ to AGND. ADA4004-1 11 10 OOuuttppuutt iiss cinla tmrispteadte v. ia ~6 kΩ to AGND. VREFN AD5780 09649-052 Figure 52. Output Amplifier in Unity Gain with Amplifier Input Bias Current Compensation Rev. F | Page 23 of 27

AD5780 Data Sheet Gain of Two Configuration (×2 Gain Mode) VREFP Figure 53 shows an output amplifier configured for a gain of two. The gain is set by the internal matched 6.8 kΩ resistors, R1 RFB RFB A1 which are exactly twice the DAC resistance, having the effect 6.8kΩ 6.8kΩ 10pF of removing an offset from the input bias current of the external INV VOUT amplifier. In this configuration, the output spans from 2 × V − 18-BIT REFN DAC VOUT AD8675, VREFP to VREFP. This configuration is used to generate a bipolar ADA4898-1, output span from a single-ended reference input, with V = ADA4004-1 REFN 0re Vgi. sFteorr mthuiss tm boed cele oafr eodp etora Ltioogni,c t 0h.e RBUF bit of the control VREFN AD5780 09649-050 Figure 53. Output Amplifier in Gain-of-Two Configuration Rev. F | Page 24 of 27

Data Sheet AD5780 APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT Figure 54 shows a typical operating circuit for the AD5780 using an AD8675 as an output buffer. Because the output impedance of the AD5780 is 3.4 kΩ, an output buffer is required for driving low resistive, high capacitive loads. 450-94690 Figure 54. Typical Operating Circuit Rev. F | Page 25 of 27

AD5780 Data Sheet EVALUATION BOARD An evaluation board is available for the AD5780 to aid designers in with the evaluation board to allow the user to easily program evaluating the high performance of the part with minimum the AD5780. The software runs on any PC that has Microsoft® effort. The AD5780 evaluation kit includes a populated and Windows® XP (SP2), Vista (32-bit or 64-bit), or Windows 7 tested AD5780 printed circuit board (PCB). The evaluation installed. The AD5780 user guide, UG-256, is available, which board interfaces to the USB port of a PC. Software is available gives full details on the operation of the evaluation board. Rev. F | Page 26 of 27

Data Sheet AD5780 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 4.10 2.75 4.00 2.65 PIN 1 3.90 2.50 INDICATOR PININD I1CATOR AREA OPTIONS 20 24 (SEE DETAIL A) 19 1 0.50 5.10 BSC 3.75 5.00 EXPPAODSED 3.65 4.90 3.50 13 7 0.50 12 8 TOP VIEW BOTTOM VIEW 0.40 1.00 0.30 0.90 SIDE VIEW 0.05 MAX FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.02 NOM THE PIN CONFIGURATION AND COPLANARITY FUNCTION DESCRIPTIONS SEATING 0.30 0.08 SECTION OF THIS DATA SHEET. PKG-003573 PLANE 00..2250 0.20 REF 08-18-2017-B Figure 55. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 5 mm Body and 0.90 mm Package Height (CP-24-5) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range INL Package Description Package Option AD5780ACPZ −40°C to +125°C ±2 LSB 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-5 AD5780ACPZ-REEL7 −40°C to +125°C ±2 LSB 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-5 AD5780BCPZ −40°C to +125°C ±1 LSB 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-5 AD5780BCPZ-REEL7 −40°C to +125°C ±1 LSB 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-5 EVAL-AD5780SDZ Evaluation Board 1 Z = RoHS Compliant Part. ©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09649-0-4/18(F) Rev. F | Page 27 of 27

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5780SDZ AD5780ACPZ AD5780BCPZ AD5780BCPZ-REEL7 AD5780ACPZ-REEL7