Complete Dual, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC Data Sheet AD5762R FEATURES GENERAL DESCRIPTION Complete dual, 16-bit, digital-to-analog converter (DAC) The AD5762R is a dual, 16-bit, serial input, bipolar voltage output Programmable output range: ±10 V, ±10.2564 V, or ±10.5263 V DAC that operates from supply voltages of ±11.4 V to ±16.5 V. ±1 LSB maximum INL error, ±1 LSB maximum DNL error Nominal full-scale output range is ±10 V. The AD5762R provides Low noise: 60 nV/√Hz integrated output amplifiers, reference buffers, and proprietary Settling time: 10 µs maximum power-up/power-down control circuitry. The device also features a Integrated reference buffers digital input/output port, programmed via the serial interface, Internal reference: 10 ppm/°C maximum and an analog temperature sensor. The device incorporates On-chip die temperature sensor digital offset and gain adjust registers per channel. Output control during power-up/brownout The AD5762R is a high performance converter that provides Programmable short-circuit protection guaranteed monotonicity, an integral nonlinearity (INL) of Simultaneous updating via LDAC ±1 LSB, low noise, and a 10 µs settling time. The AD5762R Asynchronous CLR to zero code includes an on-chip 5 V reference with a reference temperature Digital offset and gain adjust coefficient of 10 ppm/°C maximum. During power-up when the Logic output control pins supply voltages are changing, VOUTx is clamped to 0 V via a low DSP-/microcontroller-compatible serial interface impedance path. Temperature range: −40°C to +85°C Industrial complementary metal-oxide semiconductor The AD5762R is based on the iCMOS® technology platform, which (iCMOS) process technology is designed for analog systems designers within industrial/instru- mentation equipment original equipment manufacturers (OEMs) APPLICATIONS who need high performance ICs at higher voltage levels. iCMOS Industrial automation enables the development of analog ICs capable of 30 V and Open-loop/closed-loop servo control operation at ±15 V supplies, while allowing reductions in power Process control consumption and package size coupled with increased ac and dc Data acquisition systems performance. Automatic test equipment The AD5762R uses a serial interface that operates at clock rates Automotive test and measurement of up to 30 MHz and is compatible with DSP and microcontroller High accuracy instrumentation interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is programmable to either twos complement or offset binary formats. The asynchronous clear function clears all DAC registers to either bipolar zero or zero scale, depending on the coding used. The AD5762R is ideal for both closed-loop servo control and open-loop control applications. The AD5762R is available in a 32-lead TQFP and offers guaranteed specifications over the −40°C to +85°C industrial temperature range (see Figure 1 for the functional block diagram). Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5762R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Function Register ....................................................................... 24 Applications ....................................................................................... 1 Data Register ............................................................................... 25 General Description ......................................................................... 1 Coarse Gain Register ................................................................. 25 Revision History ............................................................................... 2 Fine Gain Register ...................................................................... 25 Functional Block Diagram .............................................................. 3 Offset Register ............................................................................ 26 Specifications ..................................................................................... 4 Offset and Gain Adjustment Worked Example ......................... 26 AC Performance Characteristics ................................................ 6 Design Features ............................................................................... 27 Timing Characteristics ................................................................ 7 Analog Output Control ............................................................. 27 Absolute Maximum Ratings .......................................................... 10 Digital Offset and Gain Control ............................................... 27 Thermal Resistance .................................................................... 10 Programmable Short-Circuit Protection ................................ 27 ESD Caution ................................................................................ 10 Digital I/O Port ........................................................................... 27 Pin Configuration and Function Descriptions ........................... 11 Die Temperature Sensor ............................................................ 27 Typical Performance Characteristics ........................................... 13 Local Ground Offset Adjust ...................................................... 27 Terminology .................................................................................... 19 Applications Information .............................................................. 28 Theory of Operation ...................................................................... 21 Typical Operating Circuit ......................................................... 28 DAC Architecture ....................................................................... 21 Layout Guidelines ........................................................................... 30 Reference Buffers ........................................................................ 21 Galvanically Isolated Interface ................................................. 30 Serial Interface ............................................................................ 21 Microprocessor Interfacing ....................................................... 30 Simultaneous Updating via LDAC ........................................... 22 Evaluation Board ........................................................................ 31 Transfer Function ....................................................................... 23 Outline Dimensions ....................................................................... 32 Asynchronous Clear (CLR) ....................................................... 23 Ordering Guide .......................................................................... 32 Registers ........................................................................................... 24 REVISION HISTORY 6/2016—Rev. C to Rev. D 8/2009—Rev. 0 to Rev. A Changes to Table 7 and Table 8 ..................................................... 23 Deleted Endnote 1, Table 1 .............................................................. 4 Deleted Endnote 1, Table 2 .............................................................. 6 9/2011—Rev. B to Rev. C Deleted Endnote 1, Table 3 .............................................................. 7 Changed 50 MHz to 30 MHz Throughout.................................... 1 Changes to t Parameter, Table 3 ..................................................... 7 6 Changes to t, t, and t Parameters, Table 3 .................................. 7 1 2 3 12/2008—Revision 0: Initial Version 7/2011—Rev. A to Rev. B Changed 30 MHz to 50 MHz Throughout.................................... 1 Changes to t, t, and t Parameters, Table 3 .................................. 7 1 2 3 Rev. D | Page 2 of 32

Data Sheet AD5762R FUNCTIONAL BLOCK DIAGRAM PGND AVDD AVSS AVDD AVSS REFOUT REFGND REFA RSTOUT RSTIN VOLTAGE DVCC MONITOR AD5762R 5V REFERENCE AND DGND REFERENCE BUFFERS CONTROL ISCC 16 16 G1 INPUT DAC SDIN INPUT REG A REG A DAC A VOUTA SHIFT G2 SCLK REGISTER AND GAIN REG A SYNC CONTROL OFFSET REG A AGNDA LOGIC SDO 16 G1 INPUT DAC REG B REG B DAC B VOUTB D0 G2 GAIN REG B D1 OFFSET REG B AGNDB BIN/2sCOMP REFERENCE TEMP BUFFERS SENSOR CLR LDAC REFB TEMP 07248-001 Figure 1. Rev. D | Page 3 of 32

AD5762R Data Sheet SPECIFICATIONS AV = 11.4 V to 16.5 V, AV = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA = REFB = 5 V external; DD SS DV = 2.7 V to 5.25 V, R = 10 kΩ, C = 200 pF. All specifications T to T , unless otherwise noted. CC LOAD L MIN MAX Table 1. Parameter Min Typ Max Unit Test Conditions/Comments1 ACCURACY Outputs unloaded Resolution 16 Bits Relative Accuracy (INL) −1 +1 LSB Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Bipolar Zero Error −2 +2 mV 25°C; error at other temperatures obtained using bipolar zero tempco −3 +3 mV Bipolar Zero Tempco2 −2 +2 ppm FSR/°C Zero-Scale Error −2 +2 mV 25°C; error at other temperatures obtained using zero-scale tempco −2.5 +2.5 mV Zero-Scale Tempco2 −2 +2 ppm FSR/°C Gain Error −0.02 +0.02 % FSR Gain Tempco2 −2 +2 ppm FSR/°C DC Crosstalk2 0.5 LSB REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage 5 V ±1% for specified performance DC Input Impedance 1 100 MΩ Input Current −10 ±0.03 +10 µA Reference Range 1 7 V Reference Output Output Voltage 4.995 5 5.005 V 25°C, AV /AV = ±13.5 V DD SS Reference Tempco2 −10 ±1.7 +10 ppm/°C R 2 1 MΩ LOAD Power Supply Sensitivity2 300 µV/V Output Noise2 18 µV p-p 0.1 Hz to 10 Hz Noise Spectral Density2 75 nV/√Hz 10 kHz Output Voltage Drift vs. Time2 ±40 ppm/500 hr ±50 ppm/1000 hr Thermal Hysteresis2 70 ppm First temperature cycle 30 ppm Subsequent temperature cycles OUTPUT CHARACTERISTICS2 Output Voltage Range3 −10.5263 +10.5263 V AV /AV = ±11.4 V, REFA = REFB = 5 V DD SS −14.7368 +14.7368 V AV /AV = ±16.5 V, REFA = REFB = 7 V DD SS Output Voltage Drift vs. Time ±13 ppm FSR/ 500 hr ±15 ppm FSR/ 1000 hr Short-Circuit Current 10 mA R = 6 kΩ, see Figure 31 ISCC Load Current −1 +1 mA For specified performance Capacitive Load Stability R = ∞ 200 pF LOAD R = 10 kΩ 1000 pF LOAD DC Output Impedance 0.3 Ω Rev. D | Page 4 of 32

Data Sheet AD5762R Parameter Min Typ Max Unit Test Conditions/Comments1 DIGITAL INPUTS2 DV = 2.7 V to 5.25 V CC Input High Voltage, V 2.4 V IH Input Low Voltage, V 0.8 V IL Input Current −1.2 +1.2 µA Per pin Pin Capacitance 10 pF Per pin DIGITAL OUTPUTS (D0, D1, SDO)2 Output Low Voltage 0.4 V DV = 5 V ± 5%, sinking 200 µA CC Output High Voltage DV − 1 V DV = 5 V ± 5%, sourcing 200 µA CC CC Output Low Voltage 0.4 V DV = 2.7 V to 3.6 V, sinking 200 µA CC Output High Voltage DV − 0.5 V DV = 2.7 V to 3.6 V, sourcing 200 µA CC CC High Impedance Leakage Current −1 +1 µA SDO only High Impedance Output Capacitance 5 pF SDO only DIE TEMPERATURE SENSOR2 Output Voltage at 25°C 1.47 V Die temperature Output Voltage Scale Factor 5 mV/°C Output Voltage Range 1.175 1.9 V −40°C to +105°C Output Load Current 200 µA Current source only Power-On Time 80 ms POWER REQUIREMENTS AV +11.4 +16.5 V DD AV −16.5 −11.4 SS DV 2.7 5.25 V CC Power Supply Sensitivity2 ∆V /∆ΑV −85 dB OUT DD AI 4.25 mA/channel Outputs unloaded DD AI 3.9 mA/channel Outputs unloaded SS DI 1.2 mA V = DV , V = DGND, 750 µA typ CC IH CC IL Power Dissipation 180 mW ±12 V operation output unloaded 1 Temperature range: −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance. 2 Guaranteed by design and characterization; not production tested. 3 Output amplifier headroom requirement is 1.4 V minimum. Rev. D | Page 5 of 32

AD5762R Data Sheet AC PERFORMANCE CHARACTERISTICS AV = 11.4 V to 16.5 V, AV = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA, REFB= 5 V external; DD SS DV = 2.7 V to 5.25 V, R = 10 kΩ, C = 200 pF. All specifications T to T , unless otherwise noted. CC LOAD L MIN MAX Table 2. Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE1 Output Voltage Settling Time 8 10 µs Full-scale step to ±1 LSB 2 µs 512 LSB step settling Slew Rate 5 V/µs Digital-to-Analog Glitch Energy 8 nV-sec Glitch Impulse Peak Amplitude 25 mV Channel-to-Channel Isolation 80 dB DAC-to-DAC Crosstalk 8 nV-sec Digital Crosstalk 2 nV-sec Digital Feedthrough 2 nV-sec Effect of input bus activity on DAC outputs Output Noise (0.1 Hz to 10 Hz) 0.1 LSB p-p Output Noise (0.1 Hz to 100 kHz) 45 µV rms 1/f Corner Frequency 1 kHz Output Noise Spectral Density 60 nV/√Hz Measured at 10 kHz Complete System Output Noise Spectral Density2 80 nV/√Hz Measured at 10 kHz 1 Guaranteed by design and characterization; not production tested. 2 Includes noise contributions from integrated reference buffers, 16-bit DAC, and output amplifier. Rev. D | Page 6 of 32

Data Sheet AD5762R TIMING CHARACTERISTICS AV = 11.4 V to 16.5 V, AV = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFA = REFB = 5 V external; DD SS DV = 2.7 V to 5.25 V, R = 10 kΩ, C = 200 pF. All specifications T to T , unless otherwise noted. CC LOAD L MIN MAX Table 3. Parameter1, 2, 3 Limit at T , T Unit Description MIN MAX t 33 ns min SCLK cycle time 1 t 13 ns min SCLK high time 2 t 13 ns min SCLK low time 3 t 13 ns min SYNC falling edge to SCLK falling edge setup time 4 t 4 13 ns min 24th SCLK falling edge to SYNC rising edge 5 t 90 ns min Minimum SYNC high time 6 t 2 ns min Data setup time 7 t 5 ns min Data hold time 8 t 1.7 µs min SYNC rising edge to LDAC falling edge (all DACs updated) 9 480 ns min SYNC rising edge to LDAC falling edge (single DAC updated) t 10 ns min LDAC pulse width low 10 t 500 ns max LDAC falling edge to DAC output response time 11 t 10 µs max DAC output settling time 12 t 10 ns min CLR pulse width low 13 t 2 µs max CLR pulse activation time 14 t 5, 6 25 ns max SCLK rising edge to SDO valid 15 t 13 ns min SYNC rising edge to SCLK falling edge 16 t 2 µs max SYNC rising edge to DAC output response time (LDAC = 0) 17 t 170 ns min LDAC falling edge to SYNC rising edge 18 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 Standalone mode only. 5 Measured with the load circuit of Figure 5. 6 Daisy-chain mode only. Rev. D | Page 7 of 32

AD5762R Data Sheet Timing Diagrams t 1 SCLK 1 2 24 t6 t3 t2 t4 t5 SYNC t 8 t 7 SDIN DB23 DB0 t10 t t10 9 LDAC t18 t12 t 11 VOUTA/ VOUTB LDAC = 0 t 12 t VOUTA/ 17 VOUTB t CLR 13 t 14 VOUTA/ VOUTB 07248-002 Figure 2. Serial Interface Timing Diagram t 1 SCLK 24 48 t6 t3 t2 t5 t t 16 4 SYNC t 8 t 7 SDIN DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N INPUT WORD FOR DAC N – 1 t 15 SDO DB23 DB0 UNDEFINED INPUT WORD FOR DAC N t9 t 10 LDAC 07248-003 Figure 3. Daisy-Chain Timing Diagram Rev. D | Page 8 of 32

Data Sheet AD5762R SCLK 24 48 SYNC SDIN DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ SDO DB23 DB0 UNDEFINED SELECCTLEOD CRKEEGDIS OTUETR DATA 07248-004 Figure 4. Readback Timing Diagram 200µA IOL TO OUTPUT VOH (MIN) OR PIN CL VOL (MAX) 50pF 200µA IOH 07248-005 Figure 5. Load Circuit for SDO Timing Diagram Rev. D | Page 9 of 32

AD5762R Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum T = 25°C unless, otherwise noted. Transient currents of up to A Ratings may cause permanent damage to the product. This is a 100 mA do not cause SCR latch-up. stress rating only; functional operation of the product at these Table 4. or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Operation beyond AV to AGND, DGND −0.3 V to +17 V the maximum operating conditions for extended periods may DD AV to AGND, DGND +0.3 V to −17 V affect product reliability. SS DVCC to DGND −0.3 V to +7 V THERMAL RESISTANCE Digital Inputs to DGND −0.3 V to (DV + 0.3 V) or +7 V, CC θ is specified for the worst-case conditions, that is, a device whichever is less JA soldered in a circuit board for surface-mount packages. Digital Outputs to DGND −0.3 V to DV + 0.3 V CC REFx to AGND, PGND −0.3 V to AV + 0.3 V DD Table 5. Thermal Resistance REFOUT to AGND AV to AV SS DD Package Type θ θ Unit JA JC TEMP AV to AV SS DD 32-Lead TQFP 65 12 °C/W VOUTx to AGND AV to AV SS DD AGND to DGND −0.3 V to +0.3 V ESD CAUTION Operating Temperature Range Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 150°C J Lead Temperature (Soldering) JEDEC Industry Standard J-STD-020 Rev. D | Page 10 of 32

Data Sheet AD5762R PIN CONFIGURATION AND FUNCTION DESCRIPTIONS P M BIN/2sCO AVDDAVSS TEMP REFGND REFOUT REFB REFA 32 31 30 29 28 27 26 25 SYNC 1 24 NC SCLK 2 PIN 1 23 NC SDIN 3 AD5762R 22 VOUTA SDO 4 21 AGNDA TOP VIEW CLR 5 (Not to Scale) 20 AGNDB LDAC 6 19 VOUTB D0 7 18 NC D1 8 17 NC 9 10 11 12 13 14 15 16 T N D C D D S C NC = NO CORSTOUNNERSTICTDGN DVCAVD PGN AVS ISC 07248-006 Figure 6. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. 2 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds of up to 30 MHz. 3 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 4 SDO Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. 5 CLR Negative Edge Triggered Input.1 Asserting this pin sets the DAC registers to 0x0000. 6 LDAC Load DAC. This logic input is used to update the DAC registers and, consequently, the analog outputs. When tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected. 7, 8 D0, D1 Digital I/O Port. D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are configurable and readable over the serial interface. When configured as inputs, these pins have weak internal pull-ups to DV . When programmed as outputs, D0 and D1 are referenced by DV and DGND. CC CC 9 RSTOUT Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it can be used to control other system components. 10 RSTIN Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1. Register values remain unchanged. 11 DGND Digital Ground Pin. 12 DV Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V. CC 13, 31 AV Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V. DD 14 PGND Ground Reference Point for Analog Circuitry. 15, 30 AV Negative Analog Supply Pins. Voltage ranges from −11.4 V to −16.5 V. SS 16 ISCC This pin is used in association with an optional external resistor to AGND to program the short-circuit current of the output amplifiers. Refer to the Design Features section for more information. 17 NC Do not connect to this pin. 18 NC Do not connect to this pin. 19 VOUTB Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. 20 AGNDB Ground Reference Pin for DAC B Output Amplifier. 21 AGNDA Ground Reference Pin for DAC A Output Amplifier. Rev. D | Page 11 of 32

AD5762R Data Sheet Pin No. Mnemonic Description 22 VOUTA Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. 23 NC Do not connect to this pin. 24 NC Do not connect to this pin. 25 REFA External Reference Voltage. The reference input range is 1 V to 7 V, and it programs the full-scale output voltage. REFA = 5 V for specified performance. 26 REFB External Reference Voltage. The reference input range is 1 V to 7 V, and it programs the full-scale output voltage. REFB = 5 V for specified performance. 27 REFOUT Reference Output. This is the reference output from the internal voltage reference. The internal reference is 5 V ± 3 mV at 25°C, with a reference temperature coefficient of 10 ppm/°C. 28 REFGND Reference Ground Return for the Reference Generator and Buffers. 29 TEMP This pin provides an output voltage proportional to temperature. The output voltage is 1.47 V typical at 25°C die temperature; variation with temperature is 5 mV/°C. 32 BIN/2sCOMP This pin determines the DAC coding. This pin should be hardwired to either DV or DGND. When hardwired to CC DV , input coding is offset binary (see Table 7). When hardwired to DGND, input coding is twos complement (see CC Table 8). 1 Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition. Rev. D | Page 12 of 32

Data Sheet AD5762R TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 TA = 25°C TA = 25°C 0.8 VDD/VSS = ±15V 0.8 VDD/VSS = ±12V REFIN = 5V REFIN = 5V 0.6 0.6 0.4 0.4 B) B) R (LS 0.2 R (LS 0.2 O 0 O 0 R R R R NL E –0.2 NL E –0.2 I –0.4 D –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 10,000 20,000 3D0A,0C0 0COD4E0,000 50,000 60,000 07248-007 0 10,000 20,000 3D0A,0C0 0COD4E0,000 50,000 60,000 07248-012 Figure 7. Integral Nonlinearity Error vs. DAC Code, Figure 10. Differential Nonlinearity Error vs. DAC Code, VDD/VSS = ±15 V VDD/VSS = ±12 V 1.0 0.5 TA = 25°C 0.8 RVDEDF/IVNS =S 5=V ±12V 0.4 VRDEDF/IVNS =S 5=V ±15V 0.6 0.4 0.3 B) B) R (LS 0.2 R (LS 0.2 O 0 O R R NL ER –0.2 NL ER 0.1 I –0.4 I 0 –0.6 –0.1 –0.8 –1.00 10,000 20,000 3D0A,0C0 0COD4E0,000 50,000 60,000 07248-008 –0.2–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 07248-015 Figure 8. Integral Nonlinearity Error vs. DAC Code, Figure 11. Integral Nonlinearity Error vs. Temperature, VDD/VSS = ±12 V VDD/VSS = ±15 V 1.0 0.5 TA = 25°C 0.8 RVDEDF/IVNS =S 5=V ±15V VDD/VSS = ±12V 0.4 REFIN = 5V 0.6 0.4 B) B) 0.3 R (LS 0.2 R (LS O 0 O 0.2 R R R R DNL E ––00..42 INL E 0.1 –0.6 0 –0.8 –1.0 –0.1 0 10,000 20,000 3D0A,0C0 0COD4E0,000 50,000 60,000 07248-011 –40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 07248-016 Figure 9. Differential Nonlinearity Error vs. DAC Code, Figure 12. Integral Nonlinearity Error vs. Temperature, VDD/VSS = ±15 V VDD/VSS = ±12 V Rev. D | Page 13 of 32

AD5762R Data Sheet 0.15 0.15 TA = 25°C REFIN = 5V 0.10 0.10 0.05 0.05 B) B) S 0 S 0 L L R ( R ( O–0.05 O–0.05 R R R R E E L –0.10 L –0.10 N N D D –0.15 –0.15 –0.20 –0.20 VDD/VSS = ±15V REFIN = 5V –0.25 –0.25 –40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 07248-019 11.4 12.4 SU1P3P.4LY VOLTA14G.4E (V) 15.4 16.4 07248-025 Figure 13. Differential Nonlinearity Error vs. Temperature, Figure 16. Differential Nonlinearity Error vs. Supply Voltage VDD/VSS = ±15 V 0.15 0.8 TA = 25°C 0.10 0.6 0.4 0.05 R (LSB) 0 R (LSB) 0.02 O–0.05 O R R R R –0.2 DNL E–0.10 INL E –0.4 –0.15 –0.6 –0.20 –0.8 VDD/VSS = ±12V REFIN = 5V –0.25 –1.0 –40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 07248-020 1 2 RE3FERENCE 4VOLTAGE5 (V) 6 7 07248-027 Figure 14. Differential Nonlinearity Error vs. Temperature, Figure 17. Integral Nonlinearity Error vs. Reference Voltage, VDD/VSS = ±12 V VDD/VSS = ±16.5 V 0.5 0.4 TA = 25°C TA = 25°C REFIN = 5V 0.3 0.4 0.2 0.3 INL ERROR (LSB) 00..21 DNL ERROR (LSB) –00..101 0 –0.2 –0.1 –0.3 –0.211.4 12.4 SU1P3P.4LY VOLTA14G.4E (V) 15.4 16.4 07248-023 –0.41 2 RE3FERENCE 4VOLTAGE5 (V) 6 7 07248-031 Figure 15. Integral Nonlinearity Error vs. Supply Voltage Figure 18. Differential Nonlinearity Error vs. Reference Voltage, VDD/VSS = ±16.5 V Rev. D | Page 14 of 32

Data Sheet AD5762R 0.6 0.8 TA = 25°C REFIN = 5V 0.4 VDD/VSS = ±15V 0.2 0.6 V) 0 m R ( 0.4 –0.2 RO VDD/VSS = ±12V UE (mV) ––00..64 ERO ER 0.2 T Z –0.8 LAR 0 –1.0 PO BI –1.2 –0.2 –1.4 –1.6 –0.4 1 2 RE3FERENCE 4VOLTAGE5 (V) 6 7 07248-035 –40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 07248-039 Figure 19. Total Unadjusted Error vs. Reference Voltage, Figure 22. Bipolar Zero Error vs. Temperature VDD/VSS = ±16.5 V 9.0 1.4 REFIN = 5V 8.5 1.2 8.0 |IDD| 1.0 7.5 VDD/VSS = ±12V V) mA) 7.0 R (m 0.8 (S 6.5 RO 0.6 /IDDS 6.0 N ER I 5.5 |ISS| GAI 0.4 VDD/VSS = ±15V 0.2 5.0 4.5 0 4.011.4 12.4 13.4VDD/VSS (1V4).4 15.4 16.4 07248-037 –0.2–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 07248-040 Figure 20. IDD/ISS vs. VDD/VSS Figure 23. Gain Error vs. Temperature 0.25 0.0014 REFIN = 5V VDD/VSS = ±15V TA = 25°C 0.20 0.0013 0.15 5V mV) 0.10 VDD/VSS = ±12V 0.0012 R ( 0.0011 E ERRO 0.050 (mA)C0.0010 L C SCA–0.05 DI0.0009 O- R–0.10 E 0.0008 Z –0.15 3V 0.0007 –0.20 –0.25 0.0006 –40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 07248-038 0 0.5 1.0 1.5 2.0VLO2G.I5C (V)3.0 3.5 4.0 4.5 5.0 07248-041 Figure 21. Zero-Scale Error vs. Temperature Figure 24. DICC vs. Logic Input Voltage Rev. D | Page 15 of 32

AD5762R Data Sheet 7000 –4 TA = 25°C REFIN = 5V –6 6000 VDD/VSS = ±15V –8 V) µ 5000 A ( VDD/VSS = ±12V –10 T EL 4000 –12 GE D mV) –14 OLTA 3000 V (OUT –16 T V 2000 –18 U P –20 UT 1000 VDD/VSS = ±12V, O –22 REFIN = 5V, 0 TA = 25°C, –24 0x8000 TO 0x7FFF, 500ns/DIV –1000 –26 –10 –5SOURCE/SIN0K CURRENT (5mA) 10 07248-042 –2.0–1.5–1.0–0.5 0 0.51.01T.5IM2E.0 (µ2s.)53.03.54.04.55.05.56.0 07248-047 Figure 25. Source and Sink Capability of Output Amplifier with Figure 28. Major Code Transition Glitch Energy, VDD/VSS = ±12 V Positive Full Scale Loaded 10,000 9000 TRAE F=I N25 =° C5V VMDIDDS/VCSASL =E ± L1O5VADED REFIN = 0V 8000 µV) VDD/VSS = ±15V A ( 7000 T EL 6000 E D 5000 VDD/VSS = ±12V G 4 A LT 4000 O T V 3000 U P 2000 T U O 1000 0 50µV/DIV –1000–12 –7 SOURCE/–S2INK CURREN3T (mA) 8 07248-043 CH4 50.0µV M1.00s CH4 26µV 07248-048 Figure 26. Source and Sink Capability of Output Amplifier with Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth) Negative Full Scale Loaded VRTADE DF=/I VN2S5 =S°C 5=V ±15V T VRRDAEDFM/IVPNS T=SI M5=V E±, 1 =T2 AV1 0,=0 2µ5s°,C, LOAD = 200pF||10kΩ 1 2 3 1 1µs/DIV CH1 3.00V M1.00µs CH1 –120mV 07248-044 CCHH13 1100..00VmVBWBWCH2 10.0V MT 1 2090.µ6s0%A CH1 7.80mV 07248-055 Figure 27. Full-Scale Settling Time Figure 30. VOUTx vs. VDD/VSS on Power-Up Rev. D | Page 16 of 32

Data Sheet AD5762R 10 9 VTAD D=/ V2S5S°C = ±15V VTAD D=/ V2S5S°C = ±12V REFIN = 5V A) 8 m T ( 7 N E RR 6 U T C 5 1 UI RC 4 CI T- 3 R O H 2 S 1 5µV/DIV 00 20 40 RISC6C0 (kΩ) 80 100 120 07248-050 M1.00s A CH1 18mV 07248-053 Figure 31. Short-Circuit Current vs. RISCC Figure 34. REFOUT Output Noise, 0.1 Hz to 10 Hz T VTAD D=/ V2S5S°C = ±12V 6 TVAD D=/ V2S5S°C = ±15V V) 5 E ( G A 1 LT 4 2 VO T U P 3 T U O E NC 2 E R E F 3 RE 1 CCHH13 150.0.00VVBBWW CH2 10.0V MT 4 2090.µ6s0%A CH1 7.80mV 07248-054 00 20 40 60LOA80D CU1R0R0EN1T2 (0µA)140 160 180 200 07248-032 Figure 32. REFOUT Turn-On Transient Figure 35. REFOUT Load Regulation 1.9 VT10ADµ D=F/ V 2CS5AS°C P=,A ±C1I2TVOR ON REFOUT V) 1.8 TVAD D=/ V2S5S°C = ±15V E ( G 1.7 A T L O 1.6 V T PU 1.5 1 T U O 1.4 E R TU 1.3 A R PE 1.2 M E T 1.1 50µV/DIV CH1 50.0µV M1.00s A CH1 15µV 07248-052 1.0–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 07248-033 Figure 33. REFOUT Output Noise, 100 kHz Bandwidth Figure 36. Temperature Output Voltage vs. Temperature Rev. D | Page 17 of 32

AD5762R Data Sheet 5.003 40 20 DEVICES SHOWN MAX: 10ppm/°C TYP: 1.7ppm/°C 35 V)5.002 GE ( 30 A OLT5.001 %) 25 PUT V5.000 TION ( 20 T A U L O U NCE 4.999 POP 15 E R 10 E F RE4.998 5 4.997–40 –20 0 TEM2P0ERATU4R0E(°C)60 80 100 07248-070 0 0.5 1.5 2.5TEM3P.5ERA4T.U5RE 5D.5RIFT6 (.p5pm/7°C.5) 8.5 9.5 07248-072 Figure 37. Reference Output Voltage vs. Temperature Figure 38. Reference Output Temperature Drift (−40°C to +85°C) Rev. D | Page 18 of 32

Data Sheet AD5762R TERMINOLOGY Total Unadjusted Error (TUE) Relative Accuracy or Integral Nonlinearity (INL) A measure of the output error, considering all the various For the DAC, a measure of the maximum deviation, in LSBs, errors. Figure 19 shows a plot of total unadjusted error vs. from a straight line passing through the endpoints of the DAC reference voltage. transfer function. Zero-Scale Error Temperature Coefficient Differential Nonlinearity (DNL) A measure of the change in zero-scale error with a change in The difference between the measured change and the ideal 1 LSB temperature. It is expressed as parts per million of full-scale change between any two adjacent codes. A specified differential range per degree Celsius (ppm FSR/°C). nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic. Gain Error Temperature Coefficient A measure of the change in gain error with changes in tempera- Monotonicity ture. It is expressed as parts per million of full-scale range per A DAC is monotonic if the output either increases or remains degree Celsius (ppm FSR/°C). constant for increasing digital input code. The AD5762R is monotonic over its full operating temperature range. Digital-to-Analog Glitch Energy The impulse injected into the analog output when the input Bipolar Zero Error code in the DAC register changes state. It is normally specified The deviation of the analog output from the ideal half-scale as the area of the glitch in nanovolt-seconds (nV-sec) and is output of 0 V when the DAC register is loaded with 0x8000 measured when the digital input code is changed by 1 LSB at the (offset binary coding) or 0x0000 (twos complement coding). major carry transition (0x7FFF to 0x8000), as seen in Figure 28. Figure 22 shows a plot of bipolar zero error vs. temperature. Digital Feedthrough Bipolar Zero Temperature Coefficient A measure of the impulse injected into the analog output of the The measure of the change in the bipolar zero error with a DAC from the digital inputs of the DAC but is measured when change in temperature. It is expressed as parts per million of the DAC output is not updated. It is specified in nanovolt-seconds full-scale range per degree Celsius (ppm FSR/°C). (nV-sec) and measured with a full-scale code change on the Full-Scale Error data bus, that is, from all 0s to all 1s, and vice versa. The measure of the output error when full-scale code is loaded Power Supply Sensitivity to the DAC register. Ideally, the output voltage should be 2 × Indicates how the output of the DAC is affected by changes in V − 1 LSB. Full-scale error is expressed as a percentage of REFIN the power supply voltage. full-scale range (% FSR). DC Crosstalk Negative Full-Scale Error/Zero-Scale Error The dc change in the output level of one DAC in response to a The error in the DAC output voltage when 0x0000 (offset binary change in the output of another DAC. It is measured with a full- coding) or 0x8000 (twos complement coding) is loaded to the scale output change on one DAC while monitoring another DAC register. Ideally, the output voltage should be −2 × VREFIN. DAC, and is expressed in least significant bits (LSBs). Figure 21 shows a plot of zero-scale error vs. temperature. DAC-to-DAC Crosstalk Output Voltage Settling Time The glitch impulse transferred to the output of one DAC due to a The amount of time it takes for the output to settle to a specified digital code change and subsequent output change of another DAC. level for a full-scale input change. This includes both digital and analog crosstalk. It is measured by Slew Rate loading one of the DACs with a full-scale code change (from all A limitation in the rate of change of the output voltage. The 0s to all 1s, and vice versa) with LDAC low and monitoring the output slewing speed of a voltage-output DAC is usually limited output of another DAC. The energy of the glitch is expressed in by the slew rate of the amplifier used at its output. Slew rate is nanovolt-seconds (nV-sec). measured from 10% to 90% of the output signal and is given in Channel-to-Channel Isolation volts per microsecond (V/μs). The ratio of the amplitude of the signal at the output of one DAC Gain Error to a sine wave on the reference input of another DAC. It is A measure of the span error of the DAC. It is the deviation in measured in decibels (dB). slope of the DAC transfer characteristic from the ideal, expressed Reference Temperature Coefficient as a percentage of the full-scale range (% FSR). Figure 23 shows a plot of gain error vs. temperature. A measure of the change in the reference output voltage with a change in temperature. It is expressed in parts per million per degree Celsius (ppm/°C). Rev. D | Page 19 of 32

AD5762R Data Sheet Digital Crosstalk Thermal Hysteresis A measure of the impulse injected into the analog output of one The change of reference output voltage after the device is cycled DAC from the digital inputs of another DAC but is measured through temperatures from −40°C to +85°C and back to −40°C. when the DAC output is not updated. It is specified in nanovolt- This is a typical value from a sample of devices put through seconds (nV-sec) and measured with a full-scale code change such a cycle. on the data bus, that is, from all 0s to all 1s, and vice versa. Rev. D | Page 20 of 32

Data Sheet AD5762R THEORY OF OPERATION The AD5762R is a dual, 16-bit, serial input, bipolar voltage output SERIAL INTERFACE DAC that operates from supply voltages of ±11.4 V to ±16.5 V and The AD5762R is controlled over a versatile 3-wire serial has a buffered output voltage of up to ±10.5263 V. Data is written to interface that operates at clock rates of up to 30 MHz and is the AD5762R in a 24-bit word format via a 3-wire serial interface. compatible with SPI, QSPI™, MICROWIRE, and DSP standards. The AD5762R also offers an SDO pin that is available for daisy Input Shift Register chaining or readback. The input shift register is 24 bits wide. Data is loaded into the The AD5762R incorporates a power-on reset circuit that ensures device, MSB first, as a 24-bit word under the control of a serial that the DAC registers are loaded with 0x0000 on power-up. clock input, SCLK. The input register consists of a read/write The AD5762R features a digital input/output port that can be bit, a reserved bit that must be set to 0, three register select bits, programmed via the serial interface, an analog die temperature three DAC address bits, and 16 data bits, as shown in Table 9. sensor, on-chip 10 ppm/°C voltage reference, on-chip reference The timing diagram for this operation is shown in Figure 2. buffers, and per channel digital gain and offset registers. Upon power-up, the DAC registers are loaded with zero code DAC ARCHITECTURE (0x0000), and the outputs are clamped to 0 V via a low impedance The DAC architecture of the AD5762R consists of a 16-bit path. The outputs can be updated with the zero code value by current mode segmented R-2R DAC. The simplified circuit asserting either LDAC or CLR. The corresponding output voltage diagram for the DAC section is shown in Figure 39. depends on the state of the BIN/2sCOMP pin. If the BIN/2sCOMP VREF R R R pin is tied to DGND, the data coding is twos complement and the outputs update to 0 V. If the BIN/2sCOMP pin is tied to DV , CC 2R 2R 2R 2R 2R 2R 2R the data coding is offset binary and the outputs update to negative full scale. To have the outputs power-up with zero code loaded R/8 E15 E14 E1 S11 S10 S0 to the outputs, the CLR pin should be held low during power-up. IOUT Standalone Operation VOUTx The serial interface works with both a continuous and noncon- AGNDx 41 M5 SEBQsU DAELC SOEDGEMDE INNTTSO 12-BIT, R-2R LADDER 07248-060 tifi nSuYoNuCs siesr hiaell dc lloocwk .f oAr cthoen tcionrureocuts n SuCmLbKe rs oouf rccloec cka cny bclee su.s Iend g oantelyd Figure 39. DAC Ladder Structure clock mode, a burst clock containing the exact number of clock The four MSBs of the 16-bit data-word are decoded to drive cycles must be used and SYNC must be taken high after the final 15 switches, E1 to E15. Each of these switches connects one of clock to latch the data. The first falling edge of SYNC starts the the 15 matched resistors to either AGNDx or I . The remaining OUT write cycle. Exactly 24 falling clock edges must be applied to SCLK 12 bits of the data-word drive Switch S0 to Switch S11 of the before SYNC is brought high again. If SYNC is brought high before 12-bit R-2R ladder network. the 24th falling SCLK edge, the data written is invalid. If more than REFERENCE BUFFERS 24 falling SCLK edges are applied before SYNC is brought high, The AD5762R can operate with either an external or an internal the input data is also invalid. The input register addressed is reference. The reference inputs (REFA and REFB) have an input updated on the rising edge of SYNC. For another serial transfer range up to 7 V. This input voltage is then used to provide a buf- to take place, SYNC must be brought low again. After the end of fered positive and negative reference for the DAC cores. The the serial data transfer, data is automatically transferred from the positive reference is given by input shift register to the addressed register. +V = 2 × V When the data has been transferred into the chosen register of REF REFIN the addressed DAC, all DAC registers and outputs can be updated The negative reference to the DAC cores is given by by taking LDAC low. −V = −2 × V REF REFIN These positive and negative reference voltages (along with the gain register values) define the output ranges of the DACs. Rev. D | Page 21 of 32

AD5762R Data Sheet A continuous SCLK source can be used only if SYNC is held low 68HC11* AD5762R* for the correct number of clock cycles. In gated clock mode, a MOSI SDIN burst clock containing the exact number of clock cycles must be SCK SCLK used, and SYNC must be taken high after the final clock to latch PC7 SYNC the data. PC6 LDAC Readback Operation MISO SDO Before a readback operation is initiated, the SDO pin must be SDIN enabled by writing to the function register and clearing the SDO AD5762R* disable bit; this bit is cleared by default. Readback mode is invoked by setting the R/W bit = 1 in the serial input register SCLK write. With R/W = 1, Bit A2 to Bit A0, in association with SYNC Bit REG2, Bit REG1, and Bit REG0, select the register to be LDAC read. The remaining data bits in the write sequence are don’t SDO care. During the next SPI write, the data appearing on the SDO output contains the data from the previously addressed register. SDIN For a read of a single register, the NOP command can be used in AD5762R* clocking out the data from the selected register on SDO. The readback diagram in Figure 4 shows the readback sequence. For SCLK example, to read back the fine gain register of Channel A on the SYNC AD5762R, implement the following sequence: LDAC 1. Write 0xA0XXXX to the input register. This write configures SDO *ADDITIONAL PINS OMITTED FOR CLARITY. 07248-061 Cthhea AnDne5l7 A62 sRe lfeocrt erde.a dN omteo dthea wt iatlhl othf eth fein dea gtaa ibni trse, gDisBte1r5 o tfo Figure 40. Daisy-Chaining the AD5762R DB0, are don’t care. Daisy-Chain Operation 2. Follow with a second write: an NOP condition, 0x00XXXX. During this write, the data from the fine gain register is For systems that contain several devices, the SDO pin can be clocked out on the SDO line; that is, data clocked out contains used to daisy-chain several devices together. This daisy-chain the data from the fine gain register in Bit DB5 to Bit DB0. mode can be useful in system diagnostics and in reducing the SIMULTANEOUS UPDATING VIA LDAC number of serial interface lines. The first falling edge of SYNC starts the write cycle. The SCLK is continuously applied to the Depending on the status of both SYNC and LDAC, and after input shift register when SYNC is low. If more than 24 clock data has been transferred into the input register of the DACs, pulses are applied, the data ripples out of the shift register and there are two ways to update the DAC registers and DAC outputs. appears on the SDO line. This data is clocked out on the rising Individual DAC Updating edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the SDIN input of the next device in In this mode, LDAC is held low while data is being clocked into the chain, a multidevice interface is constructed. Each device in the input shift register. The addressed DAC output is updated the system requires 24 clock pulses. Therefore, the total number on the rising edge of SYNC. of clock cycles must equal 24n, where n is the total number of Simultaneous Updating of All DACs AD5762R devices in the chain. When the serial transfer to all In this mode, LDAC is held high while data is being clocked devices is complete, SYNC is taken high. This latches the input into the input shift register. All DAC outputs are updated by data in each device in the daisy chain and prevents any further taking LDAC low any time after SYNC has been taken high. data from being clocked into the input shift register. The serial The update then occurs on the falling edge of LDAC. clock can be a continuous or a gated clock. Rev. D | Page 22 of 32

Data Sheet AD5762R See Figure 41 for a simplified block diagram of the DAC load The output voltage expression for the AD5762R is given by circuitry.  D  OUTPUT VOUT 2VREFIN 4VREFIN  I/V AMPLIFIER 65,536 REFA, REFB 16-BIT VOUTx DAC where: D is the decimal equivalent of the code loaded to the DAC. V is the reference voltage applied at the REFA, REFB pins. DAC REFIN LDAC REGISTER ASYNCHRONOUS CLEAR (CLR) CLR is a negative edge triggered clear that allows the outputs to INPUT REGISTER be cleared to either 0 V (twos complement coding) or negative full scale (offset binary coding). It is necessary to maintain CLR low for a minimum amount of time (see Figure 2) for the operation SSSYCDNLICKN INTLEORGFIACCE SDO 07248-062 rtoem coaminps laett et.h We chleeanr ethde v CalLuRe usingtnila al ins erwet uvranlueed ihs ipgrho,g trhaem omuetpdu. Itf Figure 41. Simplified Serial Interface of Input Loading Circuitry for One DAC Channel CLR is at 0 V at power-on, all DAC outputs are updated with the TRANSFER FUNCTION clear value. A clear can also be initiated through software by writing the command of 0x04XXXX to the AD5762R. Table 7 and Table 8 show the ideal input code to output voltage relationship for both offset binary data coding and twos complement data coding, respectively. Table 7. Ideal Output Voltage to Input Code Relationship—Offset Binary Data Coding Digital Input Analog Output MSB LSB V OUT 1111 1111 1111 1111 +2 V × (32,767/32,768) REFIN 1000 0000 0000 0001 +2 V × (1/32,768) REFIN 1000 0000 0000 0000 0 V 0111 1111 1111 1111 −2 V × (1/32,768) REFIN 0000 0000 0000 0000 −2 V × (32,768/32,768) REFIN Table 8. Ideal Output Voltage to Input Code Relationship—Twos Complement Data Coding Digital Input Analog Output MSB LSB V OUT 0111 1111 1111 1111 +2 V × (32,767/32,768) REFIN 0000 0000 0000 0001 +2 V × (1/32,768) REFIN 0000 0000 0000 0000 0 V 1111 1111 1111 1111 −2 V × (1/32,768) REFIN 1000 0000 0000 0000 −2 V × (32,768/32,768) REFIN Rev. D | Page 23 of 32

AD5762R Data Sheet REGISTERS Table 9. Input Shift Register Format MSB LSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB0 R/W 0 REG2 REG1 REG0 A2 A1 A0 Data Table 10. Input Shift Register Bit Function Descriptions Register Bit Descriptions R/W Indicates a read from or a write to the addressed register REG2, REG1, REG0 Used in association with the address bits, determines if a read or write operation is to the data register, offset register, gain register, or function register REG2 REG1 REG0 Function 0 0 0 Function register 0 1 0 Data register 0 1 1 Coarse gain register 1 0 0 Fine gain register 1 0 1 Offset register A2, A1, A0 Decodes the DAC channels A2 A1 A0 Channel Address 0 0 0 DAC A 0 0 1 DAC B 1 0 0 Both DACs Data Data bits FUNCTION REGISTER The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine the function addressed. The functions available via the function register are outlined in Table 11 and Table 12. Table 11. Function Register Options REG2 REG1 REG0 A2 A1 A0 DB15 to DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 NOP, data = don’t care 0 0 0 0 0 1 Don’t care Local ground D1 D1 D0 D0 SDO offset adjust direction value direction value disable 0 0 0 1 0 0 Clear, data = don’t care 0 0 0 1 0 1 Load, data = don’t care Table 12. Explanation of Function Register Options Option Description NOP No operation instruction used in readback operations. Local Ground Offset Adjust Set by the user to enable the local ground offset adjust function. Cleared by the user to disable the local ground offset adjust function (default). See the Design Features section for more information. D0, D1 Direction Set by the user to enable the D0 and D1 pins as outputs. Cleared by the user to enable the D0 and D1 pins as inputs (default). See the Design Features section for more information. D0, D1 Value Input/output port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when configured as outputs. These bits indicate the status of the D0 and D1 pins when the input/output port is active as an input. When enabled as inputs, these bits are don’t cares during a write operation. SDO Disable Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). Clear Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode. Load Addressing this function updates the DAC registers and, consequently, the analog outputs. Rev. D | Page 24 of 32

Data Sheet AD5762R DATA REGISTER The data register is addressed by setting the three REG bits to 010. The DAC address bits select the DAC channel with which the data transfer takes place (see Table 10). The data bits are positioned in DB15 to DB0, as shown in Table 13. Table 13. Programming the Data Register REG2 REG1 REG0 A2 A1 A0 DB15 to DB0 0 1 0 DAC address 16-bit DAC data COARSE GAIN REGISTER The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select the DAC channel with which the data transfer takes place (see Table 10). The coarse gain register is a 2-bit register that allows the user to select the output range of each DAC, as shown in Table 15. Table 14. Programming the Coarse Gain Register REG2 REG1 REG0 A2 A1 A0 DB15 to DB2 DB1 DB0 0 1 1 DAC address Don’t care CG1 CG0 Table 15. Output Range Selection Output Range CG1 CG0 ±10 V (Default) 0 0 ±10.2564 V 0 1 ±10.5263 V 1 0 FINE GAIN REGISTER The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select the DAC channel with which the data transfer takes place (see Table 10). The AD5762R fine gain register is a 6-bit register that allows the user to adjust the gain of each DAC channel by −32 LSBs to +31 LSBs in 1 LSB steps, as shown in Table 16 and Table 17. The adjustment is made to both the positive full-scale points and the negative full-scale points simultaneously, with each point adjusted by one-half of one step. The fine gain register coding is twos complement. Table 16. Programming the Fine Gain Register REG2 REG1 REG0 A2 A1 A0 DB15 to DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 DAC address Don’t care FG5 FG4 FG3 FG2 FG1 FG0 Table 17. Fine Gain Register Options Gain Adjustment FG5 FG4 FG3 FG2 FG1 FG0 +31 LSBs 0 1 1 1 1 1 +30 LSBs 0 1 1 1 1 0 No Adjustment (Default) 0 0 0 0 0 0 −31 LSBs 1 0 0 0 0 1 −32 LSBs 1 0 0 0 0 0 Rev. D | Page 25 of 32

AD5762R Data Sheet OFFSET REGISTER The offset register is addressed by setting the three REG bits to 101. The DAC address bits select the DAC channel with which the data transfer is to take place (see Table 10). The AD5762R offset register is an 8-bit register and allows the user to adjust the offset of each channel by −16 LSBs to +15.875 LSBs in steps of ⅛ LSB, as shown in Table 18 and Table 19. The offset register coding is twos complement. Table 18. Programming the Offset Register REG2 REG1 REG0 A2 A1 A0 DB15:DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 DAC address Don’t care OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 Table 19. Offset Register Options Offset Adjustment OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0 +15.875 LSBs 0 1 1 1 1 1 1 1 +15.75 LSBs 0 1 1 1 1 1 1 0 No Adjustment (Default) 0 0 0 0 0 0 0 0 −15.875 LSBs 1 0 0 0 0 0 0 1 −16 LSBs 1 0 0 0 0 0 0 0 OFFSET AND GAIN ADJUSTMENT WORKED The required offset register value can be calculated as follows: EXAMPLE 1. Convert the adjustment value to binary: 00010000. Using the information provided in the previous section, the 2. Convert this value to a negative twos complement number following worked example demonstrates how the AD5762R by inverting all bits and adding 1: 11110000. functions can be used to eliminate both offset and gain errors. 3. Program 11110000 to the offset register. As the AD5762R is factory calibrated, offset and gain errors Note that this twos complement conversion is not necessary should be negligible. However, errors can be introduced by the in the case of a positive offset adjustment. The value to be system that the AD5762R is operating within, for example, a programmed to the offset register is simply the binary voltage reference value that is not equal to +5 V introduces a representation of the adjustment value. gain error. An output range of ±10 V and twos complement Removing Gain Error data coding is assumed. The AD5762R can eliminate a gain error at a negative full-scale Removing Offset Error output in the range of −9.77 mV to +9.46 mV with a step size of The AD5762R can eliminate an offset error in the range of ½ of a 16-bit LSB. −4.88 mV to +4.84 mV with a step size of ⅛ of a 16-bit LSB. 1. Calculate the step size of the gain adjustment using the 1. Calculate the step size of the offset adjustment following equation: 20 Offset Adjust Step Size = = 38.14 μV 20 2168 Gain Adjust Step Size = = 152.59 μV 2162 2. Measure the offset error by programming 0x0000 to the 2. Measure the gain error by programming 0x8000 to the data register and measuring the resulting output voltage. data register and measuring the resulting output voltage. For this example, the measured value is +614 μV. The gain error is the difference between this value and 3. Determine the number of offset adjustment steps this −10 V. For this example, the gain error is −1.2 mV. value represents, using the following equation: 3. Determine how many gain adjustment steps this value MeasuredOffsetValue 614μV represents by using the following equation: Number Steps =  = 16 Steps OffsetStepSize 38.14μV MeasuredGainValue 1.2mV Number of Steps =  = 8 Steps Gain Step Size 152.59μV The offset error measured is positive; therefore, a negative adjustment of 16 steps is required. The offset register is 8 bits The gain error measured is negative (in terms of magnitude); wide, and the coding is twos complement. therefore, a positive adjustment of eight steps is required. The gain register is 6 bits wide, and the coding is twos complement. The required gain register value can be determined as follows: 1. Convert the adjustment value to binary: 001000. 2. 001000 is the value to be programmed to the gain register. Rev. D | Page 26 of 32

Data Sheet AD5762R DESIGN FEATURES ANALOG OUTPUT CONTROL If the ISCC pin is left unconnected, the short-circuit current limit defaults to 5 mA. It should be noted that limiting the short-circuit In many industrial process control applications, it is vital that current to a small value can affect the slew rate of the output the output voltage be controlled during power-up and during when driving into a capacitive load. Therefore, the value of the brownout conditions. When the supply voltages are changing, short-circuit current that is programmed should take into account the VOUTx pins are clamped to 0 V via a low impedance path. the size of the capacitive load being driven. To prevent the output amp from being shorted to 0 V during this DIGITAL INPUT/OUTPUT PORT time, Transmission Gate G1 is also opened (see Figure 42). The AD5762R contains a 2-bit digital input/output port (D1 RSTOUT RSTIN and D0). These bits can be configured independently as inputs or outputs and can be driven or have their values read back via the VOLTAGE MONITOR serial interface. The input/output port signals are referenced to AND CONTROL DV and DGND. When configured as outputs, they can be CC used as control signals to multiplexers or can be used to control G1 calibration circuitry elsewhere in the system. When configured VOUTA as inputs, the logic signals from limit switches, for example, can G2 AGNDA 07248-063 binet earpfpalciee.d to D0 and D1 and can be read back using the digital Figure 42. Analog Output Control Circuitry DIE TEMPERATURE SENSOR These conditions are maintained until the power supplies stabilize The on-chip die temperature sensor provides a voltage output and a valid word is written to the DAC register. G2 then opens, that is linearly proportional to the Celsius temperature scale. Its and G1 closes. Both transmission gates are also externally control- nominal output voltage is 1.47 V at 25°C die temperature, varying lable via the reset in (RSTIN) control input. For example, if at 5 mV/°C, giving a typical output range of 1.175 V to 1.9 V over RSTIN is driven from a battery supervisor chip, the RSTIN the full temperature range. Its low output impedance and linear input is driven low to open G1 and close G2 on power-off or output simplify interfacing to temperature control circuitry and during a brownout. Conversely, the on-chip voltage detector analog-to-digital converters (ADCs). The temperature sensor is output (RSTOUT) is also available to the user to control other provided as more of a convenience than as a precise feature; it is parts of the system. The basic transmission gate functionality is intended for indicating a die temperature change for recali- shown in Figure 42. bration purposes. DIGITAL OFFSET AND GAIN CONTROL LOCAL GROUND OFFSET ADJUST The AD5762R incorporates a digital offset adjust function with The AD5762R incorporates a local ground offset adjust feature a ±16 LSB adjust range and 0.125 LSB resolution. The gain register that, when enabled in the function register, adjusts the DAC allows the user to adjust the AD5762R full-scale output range. outputs for voltage differences between the individual DAC ground The full-scale output can be programmed to achieve full-scale pins and the REFGND pin, ensuring that the DAC output voltages ranges of ±10 V, ±10.25 V, and ±10.5 V. A fine gain trim is also are always referenced to the local DAC ground pin. For example, if available. the AGNDA pin is at +5 mV with respect to the REFGND pin PROGRAMMABLE SHORT-CIRCUIT PROTECTION and VOUTA is measured with respect to AGNDA, a −5 mV error results, enabling the local ground offset adjust feature to adjust The short-circuit current (I ) of the output amplifiers can be SC VOUTA by +5 mV, thereby eliminating the error. programmed by inserting an external resistor between the ISCC pin and PGND. The programmable range for the current is 500 μA to 10 mA, corresponding to a resistor range of 120 kΩ to 6 kΩ. The resistor value is calculated as follows: 60 R ≈ I SC Rev. D | Page 27 of 32

AD5762R Data Sheet APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT Initial accuracy error on the output voltage of an external reference can lead to a full-scale error in the DAC. Therefore, Figure 43 shows the typical operating circuit for the AD5762R. to minimize these errors, a reference with low initial accuracy The only external components needed for this precision 16-bit error specification is preferred. Choosing a reference with an DAC are decoupling capacitors on the supply pins and reference output trim adjustment, such as the ADR425, allows a system inputs, and an optional short-circuit current setting resistor. designer to trim system errors out by setting the reference voltage Because the AD5762R incorporates a voltage reference and to a voltage other than the nominal. The trim adjustment can reference buffers, it eliminates the need for an external bipolar also be used at temperature to trim out any error. reference and associated buffers, resulting in an overall savings in both cost and board space. Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight long-term drift In Figure 43, AV and AV are both connected to ±15 V, but DD SS specification ensures that the overall solution remains relatively AV and AV can operate with supplies from ±11.4 V to ±16.5 V. DD SS stable over its entire lifetime. In Figure 43, AGNDA and AGNDB are connected to REFGND. The temperature coefficient of a reference output voltage affects Precision Voltage Reference Selection INL, DNL, and TUE. A reference with a tight temperature coeffi- To achieve the optimum performance from the AD5762R over cient specification should be chosen to reduce the dependence of its full operating temperature range, an external voltage reference the DAC output voltage on ambient conditions. must be used. Care must be taken in the selection of a precision In high accuracy applications, which have a relatively low noise voltage reference. The voltage applied to the reference input is budget, reference output voltage noise must be considered. It is used to provide a buffered positive and negative reference for the important to choose a reference with as low an output noise DAC cores. Therefore, any error in the voltage reference is voltage as practical for the system resolution that is required. reflected in the outputs of the device. Precision voltage references such as the ADR435 (XFET® design) There are four possible sources of error to consider when choosing produce low output noise in the 0.1 Hz to 10 Hz region. However, a voltage reference for high accuracy applications: initial accuracy, as the circuit bandwidth increases, filtering the output of the temperature coefficient of the output voltage, long-term drift, reference may be required to minimize the output noise. and output voltage noise. Table 20. Some Precision References Recommended for Use with the AD5762R Initial Accuracy Long-Term Drift Temperature Drift 0.1 Hz to 10 Hz Noise Device No. (mV Maximum) (ppm Typical) (ppm/°C Maximum) (μV p-p Typical) ADR435 ±6 30 3 3.5 ADR425 ±6 50 3 3.4 ADR02 ±5 50 3 10 ADR395 ±6 50 25 5 AD586 ±2.5 15 10 4 Rev. D | Page 28 of 32

Data Sheet AD5762R +15V –15V 10µF 10µF 100nF 100nF TEMP µF 0 1 BIN/2sCOMP 32 31 30 29 28 27 26 25 +5V P D S P D T B A SYNC 1 SYNC N/2sCOM AVDAVS TEM REFGN REFOU REF REF NC 24 SCLK 2 SCLK BI NC 23 SDIN 3 SDIN VOUTA 22 VOUTA SDO 4 SDO AD5762R AGNDA 21 5 CLR AGNDB 20 LDAC 6 LDAC VOUTB 19 VOUTB D0 7 D0 NC 18 D1 8 D1 T NC 17 RSTOU RSTIN DGND DVCCAVDDPGND AVSSISCC 9 10 11 12 13 14 15 16 RSTOUT nF nF 0 0 RSTIN 10µ10F 10 0µF 1 100nF 10µF +5V +15V –15V 07248-064 Figure 43. Typical Operating Circuit Rev. D | Page 29 of 32

AD5762R Data Sheet LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration to each other to reduce the effects of feedthrough on the board. A of the power supply and ground return layout helps to ensure the microstrip technique is recommended, but not always possible, rated performance. Design the printed circuit board (PCB) on with a double-sided board. In this technique, the component side which the AD5762R is mounted such that the analog and digital of the board is dedicated to the ground plane, and signal traces sections are separated and confined to certain areas of the board. are placed on the solder side. If the AD5762R is in a system where multiple devices require an GALVANICALLY ISOLATED INTERFACE AGNDx-to-DGND connection, establish the connection at one In many process control applications, it is necessary to point only. Establish the star ground point as close as possible to provide an isolation barrier between the controller and the the device. The AD5762R should have ample supply bypassing of unit being controlled to protect and isolate the controlling 10 μF in parallel with 0.1 μF on each supply located as close to the circuitry from any hazardous common-mode voltages that may package as possible, ideally right up against the device. The 10 occur. Isocouplers provide voltage isolation in excess of 2.5 kV. μF capacitors are of the tantalum bead type. The 0.1 μF capacitor The serial loading structure of the AD5762R makes it ideal for should have low effective series resistance (ESR) and low effective isolated interfaces because the number of interface lines is kept series inductance (ESI), such as the common ceramic types that to a minimum. Figure 44 shows a 4-channel isolated interface to provide a low impedance path to ground at high frequencies to the AD5762R using an ADuM1400 iCoupler® product. For more handle transient currents due to internal logic switching. information on iCoupler products, go to www.analog.com. The power supply lines of the AD5762R should use as large a trace MICROPROCESSOR INTERFACING as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast-switching signals, Microprocessor interfacing to the AD5762R is accomplished such as clocks, with digital ground to avoid radiating noise to other using a serial bus that uses standard protocol that is compatible parts of the board; they should never be run near the reference with microcontrollers and DSP processors. The communication inputs. A ground line routed between the SDIN and SCLK lines channel is a 3-wire (minimum) interface consisting of a clock helps reduce cross talk between them. (A ground line is not signal, a data signal, and a synchronization signal. The AD5762R required on a multilayer board because it has a separate ground requires a 24-bit data-word with data valid on the falling edge plane; however, it is helpful to separate the lines.) It is essential of SCLK. to minimize noise on the reference inputs because it couples For all the interfaces, a DAC output update can be performed through to the DAC output. Avoid crossover of digital and analog automatically when all the data is clocked in, or it can be done signals. Run traces on opposite sides of the board at right angles under the control of LDAC. The contents of the DAC register can be read using the readback function. MICROCONTROLLER ADuM1400* SERIAL CLOCK OUT VIA ENCODE DECODE VOA TO SCLK SERIAL DATA OUT VIB ENCODE DECODE VOB TO SDIN SYNC OUT VIC ENCODE DECODE VOC TO SYNC CONTROL OUT VID ENCODE DECODE VOD TO LDAC *ADDITIONAL PINS OMITTED FOR CLARITY. 07248-065 Figure 44. Isolated Interface Rev. D | Page 30 of 32

Data Sheet AD5762R EVALUATION BOARD AD5764R PCB. The evaluation board interfaces to the USB interface of the PC. Software is available with the evaluation The performance of the AD5762R can be evaluated using the board that allows the user to easily program the AD5764R. The AD5764R evaluation board. software runs on any PC that has Microsoft Windows® 2000/XP The evaluation board aids designers in evaluating the high per- installed. formance of the device with a minimum of effort. All that is An application note is available that gives full details on operating required with the evaluation board is a power supply and a PC. the evaluation board. The AD5764R evaluation kit includes a populated, tested Rev. D | Page 31 of 32

AD5762R Data Sheet OUTLINE DIMENSIONS 0.75 1.20 MAX 9.00 BSC SQ 0.60 0.45 32 25 1 24 PIN 1 7.00 TOP VIEW BSC SQ 1.05 0° MIN 0.20 (PINS DOWN) 1.00 0.09 0.95 7° 3.5° 8 17 0.15 SEATING 0° 9 16 0.05 PLANE 0C.O08P LMAANXARITY VIEW A 0.80 0.45 BSC LEAD PITCH 0.37 VIEW A 0.30 ROTATED 90° CCW COMPLIANTTO JEDEC STANDARDS MS-026-ABA 020607-A Figure 45. 32-Lead Thin Plastic Dual Flat Package [TQFP] (SU-32-2) Dimensions shown in millimeters ORDERING GUIDE Temperature Internal Package Package Model1 Function INL Range Reference Description Option AD5762RCSUZ Dual 16-Bit DAC ±1 LSB Max −40°C to +85°C +5 V 32-Lead TQFP SU-32-2 AD5762RCSUZ-REEL7 Dual 16-Bit DAC ±1 LSB Max −40°C to +85°C +5 V 32-Lead TQFP SU-32-2 1 Z = RoHS Compliant Part. ©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07248-0-6/16(D) Rev. D | Page 32 of 32

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