Quad Channel, 16-Bit, Serial Input, 4 mA to 20 mA and Voltage Output DAC, Dynamic Power Control, HART Connectivity Data Sheet AD5755-1 FEATURES achieved by regulating the voltage on the output driver from 7.4 V 16-bit resolution and monotonicity to 29.5 V using a dc-to-dc boost converter optimized for minimum Dynamic power control for thermal management on-chip power dissipation. Each channel has a corresponding Current and voltage output pins connectable to a single CHART pin so that HART signals can be coupled onto the terminal current output of the AD5755-1. Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA, The device uses a versatile 3-wire serial interface that operates or 0 mA to 24 mA at clock rates of up to 30 MHz and is compatible with standard ±0.05% total unadjusted error (TUE) maximum SPI, QSPI™, MICROWIRE™, DSP, and microcontroller interface Voltage output ranges (with 20% overrange): 0 V to 5 V, 0 V to 10 V, ±5 V, and ±10 V standards. The interface also features optional CRC-8 packet ±0.04% total unadjusted error (TUE) maximum error checking, as well as a watchdog timer that monitors activity User programmable offset and gain on the interface. On-chip diagnostics PRODUCT HIGHLIGHTS On-chip reference (±10 ppm/°C maximum) 1. Dynamic power control for thermal management. −40°C to +105°C temperature range 2. 16-bit performance. APPLICATIONS 3. Multichannel. Process control 4. HART compliant. Actuator control Programmable logic controllers (PLCs) COMPANION PRODUCTS HART network connectivity Product Family: AD5755, AD5757 HART Modem: AD5700, AD5700-1 GENERAL DESCRIPTION External References: ADR445, ADR02 The AD5755-1 is a quad, voltage and current output digital-to- Digital Isolators: ADuM1410, ADuM1411 analog converter (DAC) that operates with a power supply Power: ADP2302, ADP2303 range from −26.4 V to +33 V. On-chip dynamic power control Additional companion products on the AD5755-1 product page minimizes package power dissipation in current mode. This is FUNCTIONAL BLOCK DIAGRAM AVCC 5.0V AVSS AVDD –15V/0V AGND +15V SWx VBOOST_x DVDD 7.4VTO 29.5V DGND LDAC DC-TO-DC CONVERTER SCLK SDIN SYNC INDTIEGRITFAALCE IOUT_x SDO + DAC A RSET_x CLEAR CURRENTAND VOLTAGE CHARTx FAULT OUTPUT RANGE ALERT GAIN REG A SCALING +VSENSE_x AD1 OFFSET REG A VOUT_x AD0 DAC CHANNEL A REFOUT REFERENCE REFIN DAC CHANNEL B DAC CHANNEL C AD5755-1 DAC CHANNEL D 09226-101 NOTES 1. x =A, B, C,AND D. Figure 1. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5755-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Readback Operation .................................................................. 38 Applications ....................................................................................... 1 Device Features ............................................................................... 40 General Description ......................................................................... 1 Output Fault ................................................................................ 40 Product Highlights ........................................................................... 1 Voltage Output Short-Circuit Protection ................................ 40 Companion Products ....................................................................... 1 Digital Offset and Gain Control ............................................... 40 Functional Block Diagram .............................................................. 1 Status Readback During a Write .............................................. 40 Revision History ............................................................................... 3 Asynchronous Clear ................................................................... 41 Detailed Functional Block Diagram .............................................. 4 Packet Error Checking ............................................................... 41 Specifications ..................................................................................... 5 Watchdog Timer ......................................................................... 41 AC Performance Characteristics ................................................ 8 Output Alert ................................................................................ 41 Timing Characteristics ................................................................ 9 Internal Reference ...................................................................... 41 Absolute Maximum Ratings .......................................................... 12 External Current Setting Resistor ............................................ 41 ESD Caution ................................................................................ 12 HART Connectivity ................................................................... 42 Pin Configuration and Function Descriptions ........................... 13 Digital Slew Rate Control .......................................................... 42 Typical Performance Characteristics ........................................... 16 Power Dissipation control ......................................................... 43 Voltage Outputs .......................................................................... 16 DC-to-DC Converters ............................................................... 43 Current Outputs ......................................................................... 20 AI Supply Requirements—Static .......................................... 44 CC DC-to-DC Block ......................................................................... 24 AI Supply Requirements—Slewing ...................................... 44 CC Reference ..................................................................................... 25 Applications Information .............................................................. 46 General ......................................................................................... 26 Voltage and Current Output Ranges on the Same Terminal 46 Terminology .................................................................................... 27 Current Output Mode with Internal R ................................ 46 SET Theory of Operation ...................................................................... 29 Precision Voltage Reference Selection ..................................... 46 DAC Architecture ....................................................................... 29 Driving Inductive Loads ............................................................ 47 Power-On State of the AD5755-1 ............................................. 29 Transient Voltage Protection .................................................... 47 Serial Interface ............................................................................ 30 Microprocessor Interfacing ....................................................... 47 Transfer Function ....................................................................... 30 Layout Guidelines....................................................................... 47 Registers ........................................................................................... 31 Galvanically Isolated Interface ................................................. 48 Programming Sequence to Write/Enable the Output Industrial HART Capable Analog Output Application— Correctly ...................................................................................... 32 Shared V and I Pin ...................................................... 49 OUT_x OUT_x Changing and Reprogramming the Range ............................. 32 Outline Dimensions ....................................................................... 50 Data Registers ............................................................................. 33 Ordering Guide .......................................................................... 50 Control Registers ........................................................................ 35 Rev. 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Data Sheet AD5755-1 REVISION HISTORY 4/2017—Rev. F to Rev. G 7/2012—Rev. C to Rev. D Changes to Table 1, DI Parameter ............................................... 8 Changes to Figure 89 ...................................................................... 49 CC Changes to Table 3 ............................................................................ 9 Updated Outline Dimensions ........................................................ 50 Changes to Figure 3 and Figure 4 .................................................. 10 5/2012—Rev. B to Rev. C Changes to Figure 5 ......................................................................... 11 Changes to Companion Products Section ..................................... 1 Changes to the Readback Operation Section .............................. 38 Changes to Figure 2 .......................................................................... 3 Deleted Table 28 and Table 29, Renumbered Sequentially ........ 38 Changes to Table 5 .......................................................................... 15 Changes to Status Readback During a Write Section ................. 40 Changes to Figure 22 ...................................................................... 18 Changes to Packet Error Checking Section ................................. 41 Added Industrial HART Capable Analog Output Application— Updated Outline Dimensions ........................................................ 50 Shared V and I Pin Section and Figure 89, OUT_x OUT_X 9/2014—Rev. E to Rev. F Renumbered Sequentially .............................................................. 49 Changes to Thermal Hysteresis Parameter, Table 1 ...................... 7 Updated Outline Dimensions ........................................................ 50 Changes to Table 3 ............................................................................ 9 11/2011—Rev. A to Rev. B Changes to Figure 4 ......................................................................... 10 Removed Voltage Output Test Conditions/Comments, Table 1 .... 5 Added Figure 5; Renumbered Sequentially ................................. 11 Changed Headroom and Footroom Test Conditions/Comments, Changes to Table 5 .......................................................................... 14 Table 1 .......................................................................................................... 5 Changes to Figure 56 through Figure 59 ...................................... 24 Changes to Figure 4 ........................................................................ 10 Change to Figure 70 and Figure 71 ............................................... 26 Changes to Figure 5 ........................................................................ 11 Change to Voltage Reference Thermal Hysteresis Definition ........ 27 Changes to SCLK Description, Table 5 ........................................ 13 Changes to Table 7 .......................................................................... 31 Changes to Figure 12 ...................................................................... 16 Changes to Offset Register Section, Table 12, and Table 14 ...... 34 Changes to Figure 21 ...................................................................... 18 Changes to Software Register Section, Table 22, and Table 23 ....... 37 Changes to Figure 37 ...................................................................... 20 Changes to Readback Operation Section, Added Table 28 and Changes to Figure 44 ...................................................................... 22 Table 29; Renumbered Sequentially .............................................. 38 Changes to Figure 71 ...................................................................... 29 Changes to Status Register Section, Table 31, and Table 32 ...... 40 Changes to Power-On State of the AD5755-1 Section ............... 30 Changes to Status Readback During a Write Section ................. 41 Changes to Table 17 ........................................................................ 35 Changes to Packet Error Checking Section ................................. 42 Changes to Readback Operation section and Table 26 .............. 38 Changes to HART Connectivity Section ...................................... 43 Changes to Voltage Output Short-Circuit Protection Section .. 40 Changes to Table 36 ........................................................................ 44 Changes to Figure 78 ...................................................................... 41 11/2012—Rev. D to Rev. E Changes to Figure 82 ...................................................................... 44 Changes to Figure 2 ........................................................................... 4 Changes to Figure 83, Figure 84, and Figure 85 ................................. 45 Changed Thermal Impedance from 20°C/W to 28°C/W .......... 12 Changes to Transient Voltage Protection Section and Figure 86 ... 47 Changes to Pin 6 Description ........................................................ 13 Changes to Galvanically Isolated Interface Section .................... 48 Changes to Pin 27 Description ...................................................... 14 5/2011—Rev. 0 to Rev. A Changes to Figure 26 ...................................................................... 19 Removed Endnote 6 (Table 1) ......................................................... 6 Changes to DUT_AD1, DUT_AD0 Description, Table 9 ......... 33 Changed AV Minimum Value from 10.8 V to 9 V .................... 6 Changes to Packet Error Checking Section and Internal DD Changed AI Minimum Value from −1.4 mA to −1.7 mA ......... 7 Reference Section ............................................................................ 41 SS Changed AV Voltage in Pin 19 Description ............................. 13 Changes to Figure 81 ...................................................................... 43 DD Changes to Ordering Guide ........................................................... 48 Changes to Figure 86 ...................................................................... 47 Changes to Figure 89 ...................................................................... 49 4/2011—Revision 0: Initial Version Rev. G | Page 3 of 50

AD5755-1 Data Sheet DETAILED FUNCTIONAL BLOCK DIAGRAM AVCC 5.0V AVSS AVDD –15V/0V AGND +15V SWA VBOOST_A DVDD POWER-ON DC-TO-DC DGND RESET CONVERTER LDAC POWER 7.4VTO 29.5V VSEN1 VSEN2 CONTROL REG CLEAR INPUT SHIFT SSCDLINK REGAINSDTER 16 INPUT DAC 16 DAC A R2 R3 SYNC CONTROL REG A REG A SDO FAULT GAIN REG A IOUT_A OFFSET REG A STATUS REGISTER R1 ALERT WATTICMHEDROG RSET_A (SPIACTIVITY) CHARTA REFOUT VREF 30kΩ +VSENSE_A VOUT REFERENCE RANGE VOUT_A REFIN BUFFERS DAC CHANNEL A SCALING IOUT_B, IOUT_C, IOUT_D DAC CHANNEL B RSET_B, RSET_C, RSET_D AD1 AD5755-1 DAC CHANNEL C CHARTB, CHARTC, CHARTD AD0 DAC CHANNEL D +VSENSE_B, +VSENSE_C, +VSENSE_D SWB, SWC, SWD VBOOST_B,VBOOST_C,VBOOST_D VOUT_B,VOUT_C,VOUT_D 09226-001 Figure 2. Rev. G | Page 4 of 50

Data Sheet AD5755-1 SPECIFICATIONS AV = V = 15 V; AV = −15 V/0 V; DV = 2.7 V to 5.5 V; AV = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = DD BOOST_x SS DD CC GNDSW = 0 V; REFIN = 5 V; voltage outputs: R = 1 kΩ, C = 220 pF; current outputs: R = 300 Ω; all specifications T to T , unless x L L L MIN MAX otherwise noted. Table 1. Parameter1 Min Typ Max Unit Test Conditions/Comments VOLTAGE OUTPUT Output Voltage Ranges 0 5 V 0 10 V −5 +5 V −10 +10 V 0 6 V 0 12 V −6 +6 V −12 +12 V ACCURACY BIPOLAR SUPPLY AV = −15 V, loaded and unloaded SS Resolution 16 Bits Total Unadjusted Error (TUE) −0.04 +0.04 % FSR −0.03 ±0.0032 +0.03 % FSR T = 25°C A TUE Long-Term Stability 35 ppm FSR Drift after 1000 hours, T = 150°C J Relative Accuracy (INL) −0.006 ±0.0012 +0.006 % FSR 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V ranges −0.008 ±0.0012 +0.008 % FSR On overranges Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Zero-Scale Error −0.03 ±0.002 +0.03 % FSR Zero-Scale TC2 ±2 ppm FSR/°C Bipolar Zero Error −0.03 ±0.002 +0.03 % FSR Bipolar Zero TC2 ±1 ppm FSR/°C Offset Error −0.03 ±0.002 +0.03 % FSR Offset TC2 ±2 ppm FSR/°C Gain Error −0.03 ±0.004 +0.03 % FSR Gain TC2 ±3 ppm FSR/°C Full-Scale Error −0.03 ±0.002 +0.03 % FSR Full-Scale TC2 ±2 ppm FSR/°C ACCURACY UNIPOLAR SUPPLY2 AV = 0 V SS Total Unadjusted Error (TUE) −0.06 ±0.025 +0.06 % FSR Relative Accuracy (INL)3 −0.009 +0.009 % FSR Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Zero-Scale Error +0.22 % FSR Offset Error −0.07 ±0.025 +0.07 % FSR Gain Error −0.07 ±0.015 +0.07 % FSR Full-Scale Error −0.06 ±0.015 +0.06 % FSR OUTPUT CHARACTERISTICS2 Headroom 1 2.2 V With respect to V supply BOOST Footroom 0.7 1.4 V With respect to the AV supply, bipolar output SS ranges Output Voltage Drift vs. Time 20 ppm FSR Drift after 1000 hours, ¾ scale output, T = 150°C, J AV = −15 V SS Short-Circuit Current 12/6 16/8 mA Programmable by user, defaults to 16 mA typical level Load 1 kΩ For specified performance Rev. G | Page 5 of 50

AD5755-1 Data Sheet Parameter1 Min Typ Max Unit Test Conditions/Comments Capacitive Load Stability 10 nF 2 µF External compensation capacitor of 220 pF connected DC Output Impedance 0.06 Ω DC PSRR 50 µV/V DC Crosstalk 24 µV CURRENT OUTPUT Output Current Ranges 0 24 mA 0 20 mA 4 20 mA Resolution 16 Bits ACCURACY (EXTERNAL R ) Assumes ideal resistor, see the External Current SET Setting Resistor section for more information Total Unadjusted Error (TUE) −0.05 ±0.009 +0.05 % FSR TUE Long-Term Stability 100 ppm FSR Drift after 1000 hours, T = 150°C J Relative Accuracy (INL) −0.006 +0.006 % FSR Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.05 ±0.005 +0.05 % FSR Offset Error Drift2 ±4 ppm FSR/°C Gain Error −0.05 ±0.004 +0.05 % FSR Gain TC2 ±3 ppm FSR/°C Full-Scale Error −0.05 ±0.008 +0.05 % FSR Full-Scale TC2 ±5 ppm FSR/°C DC Crosstalk 0.0005 % FSR External R SET ACCURACY (INTERNAL R ) SET Total Unadjusted Error (TUE)4, 5 −0.14 +0.14 % FSR −0.11 ±0.009 +0.11 % FSR T = 25°C A TUE Long-Term Stability 180 ppm FSR Drift after 1000 hours, T = 150°C J Relative Accuracy (INL) −0.006 +0.006 % FSR Relative Accuracy (INL) −0.004 +0.004 % FSR T = 25°C A Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error4, 5 −0.05 +0.05 % FSR −0.04 ±0.007 +0.04 % FSR T = 25°C A Offset Error Drift2 ±6 ppm FSR/°C Gain Error −0.12 +0.12 % FSR −0.06 ±0.002 +0.06 % FSR T = 25°C A Gain TC2 ±9 ppm FSR/°C Full-Scale Error4, 5 −0.14 +0.14 % FSR −0.1 ±0.007 +0.1 % FSR T = 25°C A Full-Scale TC2 ±14 ppm FSR/°C DC Crosstalk5 −0.011 % FSR Internal R SET OUTPUT CHARACTERISTICS2 Current Loop Compliance Voltage V − V − V BOOST_x BOOST_x 2.4 2.7 Output Current Drift vs. Time Drift after 1000 hours, ¾ scale output, T = 150°C J 90 ppm FSR External R SET 140 ppm FSR Internal R SET Resistive Load 1000 Ω The dc-to-dc converter has been characterized with a maximum load of 1 kΩ, chosen such that compli- ance is not exceeded; see Figure 54 and DC-DC MaxV bits in Table 25 Output Impedance 100 MΩ DC PSRR 0.02 1 µA/V Rev. G | Page 6 of 50

Data Sheet AD5755-1 Parameter1 Min Typ Max Unit Test Conditions/Comments REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage 4.95 5 5.05 V For specified performance DC Input Impedance 45 150 MΩ Reference Output Output Voltage 4.995 5 5.005 V T = 25°C A Reference TC2 −10 ±5 +10 ppm/°C Output Noise (0.1 Hz to 10 Hz)2 7 µV p-p Noise Spectral Density2 100 nV/√Hz At 10 kHz Output Voltage Drift vs. Time2 180 ppm Drift after 1000 hours, T = 150°C J Capacitive Load2 1000 nF Load Current 9 mA See Figure 65 Short-Circuit Current 10 mA Line Regulation2 3 ppm/V See Figure 65 Load Regulation2 95 ppm/mA See Figure 65 Thermal Hysteresis2 200 ppm DC-TO-DC Switch Switch On Resistance 0.425 Ω Switch Leakage Current 10 nA Peak Current Limit 0.8 A Oscillator Oscillator Frequency 11.5 13 14.5 MHz This oscillator is divided down to give the dc-to-dc converter switching frequency Maximum Duty Cycle 89.6 % At 410 kHz dc-to-dc switching frequency DIGITAL INPUTS2 JEDEC compliant V , Input High Voltage 2 V IH V , Input Low Voltage 0.8 V IL Input Current −1 +1 µA Per pin Pin Capacitance 2.6 pF Per pin DIGITAL OUTPUTS2 SDO, ALERT V , Output Low Voltage 0.4 V Sinking 200 µA OL V , Output High Voltage DVDD − 0.5 V Sourcing 200 µA OH High Impedance Leakage −1 +1 µA Current High Impedance Output 2.5 pF Capacitance FAULT V , Output Low Voltage 0.4 V 10 kΩ pull-up resistor to DV OL DD V , Output Low Voltage 0.6 V At 2.5 mA OL V , Output High Voltage 3.6 V 10 kΩ pull-up resistor to DV OH DD POWER REQUIREMENTS AV 9 33 V DD AV −26.4 −10.8/0 V SS DV 2.7 5.5 V DD AV 4.5 5.5 V CC Rev. G | Page 7 of 50

AD5755-1 Data Sheet Parameter1 Min Typ Max Unit Test Conditions/Comments AI 8.6 10.5 mA Voltage output mode on all channels, output DD unloaded, over supplies 7 7.5 mA Current output mode on all channels AI −11 −8.8 mA Voltage output mode on all channels, output SS unloaded, over supplies −1.7 mA Current output mode on all channels DI 4 6 mA V = DV , V = DGND, internal oscillator running, CC IH DD IL over supplies AI 1 mA Output unloaded, over supplies CC I 2.7 mA Per channel, voltage output mode, output BOOST unloaded, over supplies I 6 1 mA Per channel, current output mode, 0 mA output BOOST Power Dissipation 173 mW AV = +15 V, AV = −15 V, dc-to-dc converter DD SS enable, current output mode, outputs disabled 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 Guaranteed by design and characterization; not production tested. 3 For voltage output ranges in unipolar supply mode, the INL and TUE are measured beginning from Code 4096. 4 For current outputs with internal RSET, the offset, full-scale, and TUE measurements exclude dc crosstalk. The measurements are made with all four channels enabled loaded with the same code. 5 See the Current Output Mode with Internal RSET section for more explanation of the dc crosstalk. 6 Efficiency plots in Figure 56, Figure 57, Figure 58, and Figure 59 include the IBOOST quiescent current. AC PERFORMANCE CHARACTERISTICS AV = V = 15 V; AV = −15 V; DV = 2.7 V to 5.5 V; AV = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = DD BOOST_x SS DD CC GNDSW = 0 V; REFIN = 5 V; voltage outputs: R = 2 kΩ, C = 220 pF; current outputs: R = 300 Ω; all specifications T to T , unless x L L L MIN MAX otherwise noted. Table 2. Parameter1 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE Voltage Output Output Voltage Settling Time 11 µs 5 V step to ±0.03% FSR, 0 V to 5 V range 18 µs 10 V step to ±0.03% FSR, 0 V to 10 V range 13 µs 100 mV step to 1 LSB (16-bit LSB), 0 V to 10 V range Slew Rate 1.9 V/µs 0 V to 10 V range Power-On Glitch Energy 150 nV-sec Digital-to-Analog Glitch Energy 6 nV-sec Glitch Impulse Peak Amplitude 25 mV Digital Feedthrough 1 nV-sec DAC to DAC Crosstalk 2 nV-sec 0 V to 10 V range Output Noise (0.1 Hz to 10 Hz 0.15 LSB p-p 16-bit LSB, 0 V to 10 V range Bandwidth) Output Noise Spectral Density 150 nV/√Hz Measured at 10 kHz, midscale output, 0 V to 10 V range AC PSRR 83 dB 200 mV 50 Hz/60 Hz sine wave superimposed on power supply voltage Current Output Output Current Settling Time 15 µs To 0.1% FSR (0 mA to 24 mA) See test conditions/ ms See Figure 50, Figure 51, and Figure 52 comments Output Noise (0.1 Hz to 10 Hz 0.15 LSB p-p 16-bit LSB, 0 mA to 24 mA range Bandwidth) Output Noise Spectral Density 0.5 nA/√Hz Measured at 10 kHz, midscale output, 0 mA to 24 mA range 1 Guaranteed by design and characterization; not production tested. Rev. G | Page 8 of 50

Data Sheet AD5755-1 TIMING CHARACTERISTICS AV = V = 15 V; AV = −15 V; DV = 2.7 V to 5.5 V; AV = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = DD BOOST_x SS DD CC GNDSW = 0 V; REFIN = 5 V; voltage outputs: R = 1 kΩ, C = 220 pF; current outputs: R = 300 Ω; all specifications T to T , unless x L L L MIN MAX otherwise noted. Table 3. Parameter1, 2, 3 Limit at T , T Unit Description MIN MAX t 50 ns min SCLK cycle time 1 t 17 ns min SCLK high time 2 t 17 ns min SCLK low time 3 t4 20 ns min SYNC falling edge to SCLK falling edge setup time t5 15 ns min 24th/32nd SCLK falling edge to SYNC rising edge (see Figure 79) t6 500 ns min SYNC high time following a configuration write 5 µs min SYNC high time following a DAC update write 20 µs min SYNC high time following a DAC update write (slew rate control enabled) t 15 ns min Data setup time 7 t 10 ns min Data hold time 8 t9 20 µs min SYNC rising edge to LDAC falling edge (applies to any channel with digital slew rate control enabled; single DAC updated) 5 µs min SYNC rising edge to LDAC falling edge (applies to any channel with digital slew rate control disabled; single DAC updated) t10 10 ns min LDAC pulse width low t11 520 ns max LDAC falling edge to DAC output response time t See the AC Performance µs max DAC output settling time 12 Characteristics section t 5 µs min CLEAR high time 13 t 9 µs max CLEAR activation time 14 t 45 ns max SCLK rising edge to SDO valid 15 t16 5 µs min SYNC rising edge to DAC output response time (LDAC = 0) (single DAC updated) t17 500 ns min LDAC falling edge to SYNC rising edge t18 1 µs min RESET pulse width 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. 3 See Figure 3, Figure 4, Figure 6, and Figure 7. Rev. G | Page 9 of 50

AD5755-1 Data Sheet Timing Diagrams t1 SCLK 1 2 24 t6 t3 t2 t4 t5 SYNC t7 t8 t6 SDIN MSB LSB t10 t9 t10 LDAC t17 t12 t11 VOUT_x LDAC = 0 t12 t16 VOUT_x t13 CLEAR t14 VOUT_x RESET t18 09226-002 Figure 3. Serial Interface Timing Diagram SCLK 1 24 1 24 t6 SYNC SDIN MSB LSB MSB LSB INPUT WORD SPECIFIES NOP CONDITION REGISTERTO BE READ SDO MSB LSB UNDEFINED t16 SELECCTLEODC RKEEGDIS OTUETR1 DATA 09226-003 Figure 4. Readback Timing Diagram (Packet Error Checking Disabled) Rev. G | Page 10 of 50

Data Sheet AD5755-1 SCLK 1 24 32 1 24 32 t6 SYNC SDIN MSB LSB CRC7 CRC0 MSB LSB CRCP CRC0 INPUT WORD SPECIFIES 8-BIT CRC NOP 8-BIT CRC REGISTERTO BE READ CONDITION SDO MSB LSB UNDEFINED 8-BIT CRC t16 SELECCTLEOD CRKEEGDIS OTUETR1 DATA 09226-004 Figure 5. Readback Timing Diagram (Packet Error Checking Enabled) LSB MSB 1 2 24 SCLK SYNC SDIN R/W DUT_ DUT_ X X X D15 D14 D1 D0 AD1 AD0 SDO SDO DISABLED ESNDAOB_ STATUS STATUS STATUS STATUS 09226-004 Figure 6. Status Readback During Write 200µA IOL TO OUTPUT VOH (MIN) OR PIN CL VOL (MAX) 50pF 200µA IOH 09226-005 Figure 7. Load Circuit for SDO Timing Diagram Rev. G | Page 11 of 50

AD5755-1 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents of up to Stresses above those listed under Absolute Maximum Ratings A 100 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 4. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute AV , V to AGND, DGND −0.3 V to +33 V DD BOOST_x maximum rating conditions for extended periods may affect AV to AGND, DGND +0.3 V to −28 V SS device reliability. AV to AV −0.3 V to +60 V DD SS ESD CAUTION AV to AGND −0.3 V to +7 V CC DV to DGND −0.3 V to +7 V DD Digital Inputs to DGND −0.3 V to DV + 0.3 V or +7 V DD (whichever is less) Digital Outputs to DGND −0.3 V to DV + 0.3 V or +7 V DD (whichever is less) REFIN, REFOUT to AGND −0.3 V to AV + 0.3 V or +7 V DD (whichever is less) V to AGND AV to V or 33 V if using OUT_x SS BOOST_x the dc-to-dc circuitry +V to AGND AV to V or 33 V if using SENSE_x SS BOOST_x the dc-to-dc circuitry I to AGND AV to V or 33 V if using OUT_x SS BOOST_x the dc-to-dc circuitry SW to AGND −0.3 to +33 V x AGND, GNDSW to DGND −0.3 V to +0.3 V x Operating Temperature Range (T) A Industrial1 −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 125°C J 64-Lead LFCSP θ Thermal Impedance2 28°C/W JA Power Dissipation (T max − T )/θ J A JA Lead Temperature JEDEC industry standard Soldering J-STD-020 1 Power dissipated on chip must be derated to keep the junction temperature below 125°C. 2 Based on a JEDEC 4-layer test board. Rev. G | Page 12 of 50

Data Sheet AD5755-1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D RSET_CRSET_DREFOUTREFINCOMPLV_DCHARTD+VSENSE_DCOMPDCDC_VBOOST_DVOUT_DIOUT_DAVSSCOMPLV_CCHARTC+VSENSE_CVOUT_C 4321098765432109 6666655555555554 PIN 1 INDICATOR RSET_B 1 48COMPDCDC_C RSET_A 2 47IOUT_C REFGND 3 46VBOOST_C REFGND 4 45AVCC AD0 5 44SWC AD1 6 43GNDSWC SYNC 7 AD5755-1 42GNDSWD SCLK 8 TOP VIEW 41SWD SDIN 9 (Not to Scale) 40AVSS SDO10 39SWA DVDD 11 38GNDSWA DGND12 37GNDSWB LDAC13 36SWB CLEAR14 35AGND ALERT15 34VBOOST_B FAULT16 33IOUT_B 7890123456789012 1112222222222333 POCRESETAVDDCOMPLV_ACHARTA+VSENSE_AOMPDCDC_AVBOOST_AVOUT_AIOUT_AAVSSCOMPLV_BCHARTB+VSENSE_BVOUT_BOMPDCDC_B C C NOTES 1. THE EXPOSED PAD SHOULD BE CONNECTED TO THE POTENTIAL OF THE AVSS PIN, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY UCNOCNONNECNTEECDT ETDO. IAT CISO RPEPCERO M PMLEANNDEE FDO TRH EANTH TAHNEC PEADD T BHEE RTMHAELR MPAERLLFYORMANCE. 09266-006 Figure 8. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 R An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I SET_B OUT_B temperature drift performance. See the Device Features section. 2 R An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I SET_A OUT_A temperature drift performance. See the Device Features section. 3, 4 REFGND Ground Reference Point for Internal Reference. 5 AD0 Address Decode for the Device Under Test (DUT) on the Board. 6 AD1 Address Decode for the DUT on the Board. It is not recommended to tie both AD1 and AD0 low when using PEC, see the Packet Error Checking section. 7 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. 8 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This operates at clock speeds of up to 30 MHz. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 10 SDO Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 4 and Figure 6. 11 DV Digital Supply. The voltage range is from 2.7 V to 5.5 V. DD 12 DGND Digital Ground. 13 LDAC Load DAC, Active Low Input. This is used to update the DAC register and consequently the DAC outputs. When tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the DAC output update only takes place at the falling edge of LDAC (see Figure 3). Using this mode, all analog outputs can be updated simultaneously. The LDAC pin must not be left unconnected. 14 CLEAR Active High, Edge Sensitive Input. Asserting this pin sets the output current and voltage to the preprogrammed clear code bit setting. Only channels enabled to be cleared are cleared. See the Device Features section for more Rev. G | Page 13 of 50

AD5755-1 Data Sheet Pin No. Mnemonic Description information. When CLEAR is active, the DAC output register cannot be written to. 15 ALERT Active High Output. This pin is asserted when there has been no SPI activity on the interface pins for a predetermined time. See the Device Features section for more information. 16 FAULT Active Low Output. This pin is asserted low when an open circuit in current mode is detected, a short circuit in voltage mode is detected, a PEC error is detected, or an overtemperature is detected (see the Device Features section). Open-drain output. 17 POC Power-On Condition. This pin determines the power-on condition and is read during power-on or, alternatively, after a device reset. If POC = 0, the device is powered up with the voltage and current channels in tristate mode. If POC = 1, the device is powered up with a 30 kΩ pull-down resistor to ground on the voltage output channel, and the current channel is in tristate mode. 18 RESET Hardware Reset, Active Low Input. 19 AV Positive Analog Supply. The voltage range is from 9 V to 33 V. DD 20 COMP Optional Compensation Capacitor Connection for V Output Buffer. Connecting a 220 pF capacitor between LV_A OUT_A this pin and the V pin allows the voltage output to drive up to 2 µF. Note that the addition of this capacitor OUT_A reduces the bandwidth of the output amplifier, increasing the settling time. 21 CHARTA HART Input Connection for DAC Channel A. For more information, see the HART Connectivity section. If unused, leave as an open circuit. 22 +V Sense Connection for the Positive Voltage Output Load Connection for V . SENSE_A OUT_A 23 COMP DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback DCDC_A loop of the Channel A dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and the AI Supply Requirements—Slewing sections in the Device Features section for more information). CC 24 V Supply for Channel A Current Output Stage (see Figure 74). This is also the supply for the V stage, which is BOOST_A OUT_x regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 81. 25 V Buffered Analog Output Voltage for DAC Channel A. OUT_A 26 I Current Output Pin for DAC Channel A. OUT_A 27 AV Negative Analog Supply. Voltage range is from 0 V to −26.4 V. SS 28 COMP Optional Compensation Capacitor Connection for V Output Buffer. Connecting a 220 pF capacitor between LV_B OUT_B this pin and the V pin allows the voltage output to drive up to 2 µF. Note that the addition of this capacitor OUT_B reduces the bandwidth of the output amplifier, increasing the settling time. 29 CHARTB HART Input Connection for DAC Channel B. For more information, see the HART Connectivity section. If unused, leave as an open circuit. 30 +V Sense Connection for the Positive Voltage Output Load Connection for V . SENSE_B OUT_B 31 V Buffered Analog Output Voltage for DAC Channel B. OUT_B 32 COMP DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback DCDC_B loop of the Channel B dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and AI Supply Requirements—Slewing sections in the Device Features section for more information). CC 33 I Current Output Pin for DAC Channel B. OUT_B 34 V Supply for Channel B Current Output Stage (see Figure 74). This is also the supply for the V stage, which is BOOST_B OUT_x regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 81. 35 AGND Ground Reference Point for Analog Circuitry. This must be connected to 0 V. 36 SW Switching Output for Channel B DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown B in Figure 81. 37 GNDSW Ground Connection for DC-to-DC Switching Circuit. This pin must always be connected to ground. B 38 GNDSW Ground Connection for DC-to-DC Switching Circuit. This pin must always be connected to ground. A 39 SW Switching Output for Channel A DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown A in Figure 81. 40 AV Negative Analog Supply Pin. The voltage range is from −10.8 V to −26.4 V. This pin can be connected to 0 V if SS using the device in unipolar supply mode. 41 SW Switching Output for Channel D DC-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in D Figure 81. Rev. G | Page 14 of 50

Data Sheet AD5755-1 Pin No. Mnemonic Description 42 GNDSW Ground Connections for DC-to-DC Switching Circuit. This pin must always be connected to ground. D 43 GNDSW Ground Connections for DC-to-DC Switching Circuit. This pin must always be connected to ground. C 44 SW Switching Output for Channel C DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown C in Figure 81. 45 AV Supply for DC-to-DC Circuitry. CC 46 V Supply for Channel C Current Output Stage (see Figure 74). This is also the supply for the V stage, which is BOOST_C OUT_x regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 81. 47 I Current Output Pin for DAC Channel C. OUT_C 48 COMP DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the DCDC_C feedback loop of the Channel C dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more information). 49 V Buffered Analog Output Voltage for DAC Channel C. OUT_C 50 +V Sense Connection for the Positive Voltage Output Load Connection for V . SENSE_C OUT_C 51 CHARTC HART Input Connection for DAC Channel C. For more information, see the HART Connectivity section. If unused, leave as an open circuit. 52 COMP Optional Compensation Capacitor Connection for V Output Buffer. Connecting a 220 pF capacitor between LV_C OUT_C this pin and the V pin allows the voltage output to drive up to 2 µF. Note that the addition of this capacitor OUT_C reduces the bandwidth of the output amplifier, increasing the settling time. 53 AV Negative Analog Supply Pin. SS 54 I Current Output Pin for DAC Channel D. OUT_D 55 V Buffered Analog Output Voltage for DAC Channel D. OUT_D 56 V Supply for Channel D Current Output Stage (see Figure 74). This is also the supply for the V stage, which is BOOST_D OUT_x regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 81. 57 COMP DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the DCDC_D feedback loop of the Channel D dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more information). 58 +V Sense Connection for the Positive Voltage Output Load Connection for V . SENSE_D OUT_D 59 CHARTD HART Input Connection for DAC Channel D. For more information, see the HART Connectivity section. If unused, leave as an open circuit. 60 COMP Optional Compensation Capacitor Connection for V Output Buffer. Connecting a 220 pF capacitor between LV_D OUT_D this pin and the V pin allows the voltage output to drive up to 2 µF. Note that the addition of this capacitor OUT_D reduces the bandwidth of the output amplifier, increasing the settling time. 61 REFIN External Reference Voltage Input. 62 REFOUT Internal Reference Voltage Output. Place a 0.1 µF capacitor between REFOUT and REFGND. REFOUT must be connected to REFIN to use the internal reference. 63 R An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I SET_D OUT_D temperature drift performance. See the Device Features section. 64 R An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I SET_C OUT_C temperature drift performance. See the Device Features section. EPAD Exposed Pad. Connect this exposed pad to the potential of the AV pin, or, alternatively, leave it electrically SS unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance. Rev. G | Page 15 of 50

AD5755-1 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUTS 0.0015 0.0015 ±10V RANGE AVDD = +15V ±5V RANGE AVSS = –15V 0.0010 ++150VV R RAANNGGEE TA = 25°C 0.0010 +10V RANGE WITH DCDC OR (%FSR) 0.0005 OR (%FSR) 0.00050 +±+±5555VVVV RRRRAAAANNNNGGGGEEEE MMMMAIAINNXX II NNIINNLLLL +±+±11110000VVVV RRRRAAAANNNNGGGGEEEE MMMMAIAINNXX II NNIINNLLLL INL ERR 0 INL ERR–0.0005 AAOVVUDSTSDP U== T–+ 11U55NVVLOADED –0.0005 –0.0010 –0.00100 10k 20k 3C0kODE 40k 50k 60k 09226-023 –0.001–540 –20 0 TEMP20ERATUR4E0 (°C) 60 80 100 09226-127 Figure 9. Integral Nonlinearity Error vs. DAC Code Figure 12. Integral Nonlinearity Error vs. Temperature 1.0 1.0 00..68 ±±++15150V0VVV RR RRAAAANNNNGGGGEEEE AATAVV DS=SD 2 ==5 °–+C1155VV 00..68 AAAVLVLDSS DR ==A N–+11G55EVVS +10V RANGE WITH DCDC B) 0.4 B) 0.4 S S R (L 0.2 R (L 0.2 RRO 0 RRO 0 DDNNLL EERRRROORR MMAINX NL E–0.2 NL E–0.2 D D –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.00 10k 20k 30kCODE 40k 50k 60k 09226-024 –1.0–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 09226-128 Figure 10. Differential Nonlinearity Error vs. DAC Code Figure 13. Differential Nonlinearity Error vs. Temperature 0.006 0.012 ±10V RANGE AVDD = +15V +5V RANGE SR) 0.004 ±++515V0VV RR RAAANNNGGGEEE ATAV S=S 2 =5 °–C15V SR) 0.010 +±±511V00VV R RRAAANNNGGGEEE R (%F 0.002 +10V RANGE WITH DCDC R (%F 0.008 AVDD = +15V RRO 0 RRO 0.006 AOVUSTSP U= T– 1U5NVLOADED E E D D 0.004 TE–0.002 TE US US 0.002 J J D–0.004 D NA NA 0 U U L –0.006 L A A–0.002 T T O O T––00..0010080 10k 20k 30kCODE 40k 50k 60k 09226-025 T––00..000064–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 09226-129 Figure 11. Total Unadjusted Error vs. DAC Code Figure 14. Total Unadjusted Error vs. Temperature Rev. G | Page 16 of 50

Data Sheet AD5755-1 0 0.0025 0.0020 R)–0.005 %FS SR) 0.0015 R (–0.010 %F RO R ( 0.0010 NADJUSTED ER––00..002105 AAOVVUDST++SDP51 V2U==V T0R+ VR1UA5ANNVNLGGOEEADED AR ZERO ERRO–00..000000550 ±±51V0V R RAANNGGEE TAL U–0.025 BIPOL–0.0010 AAVVDSSD == –+1155VV O OUTPUT UNLOADED T––00..003350 09226-130 ––00..00002150 09226-134 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Total Unadjusted Error vs. Temperature, Single Supply Figure 18. Bipolar Zero Error vs. Temperature 0.012 0.010 +5V RANGE 0.010 +±51V0V R RAANNGGEE 0.008 ++51V0V R RAANNGGEE ±10V RANGE ±5V RANGE OR (%FSR) 00..000068 AOAVVUDSTSDP U== T–+ 11U55NVVLOADED %FSR) 00..000046 AOAVVU±DST1SDP0 U==V T –+R 11UA55NVNVLGOEADED CALE ERR 00..000024 N ERROR ( 0.0020 L-S 0 GAI L U –0.002 F–0.002 ––00..000064 09226-132 ––00..000046 09226-135 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. Full-Scale Error vs. Temperature Figure 19. Gain Error vs. Temperature 0.0015 0.0015 0.0010 0.0010 R) 0.0005 S F 0.0005 % ET (%FSR)–0.00050 E ERROR ( 0 FS AL–0.0005 OF––00..00001150 AVD++D51 V0=V +R R1A5ANVNGGEE ERO-SC–0.0010 ++±551VV0V RR RAAANNNGGGEEE AVSS = –15V Z ±10V RANGE ––00..00002250 OUTPUT UNLOADED 09226-133 ––00..00002105 AOAVVUDSTSDP U== T–+ 11U55NVVLOADED 09226-136 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. Offset Error vs. Temperature Figure 20. Zero-Scale Error vs. Temperature Rev. G | Page 17 of 50

AD5755-1 Data Sheet 0.0020 0.0020 8mA LIMIT, CODE = 0xFFFF 0.0015 0.0015 16mA LIMIT, CODE = 0xFFFF V) 0.0010 A ( 0.0010 INL ERROR (%FSR)–00..000000550 00TAVVAV STT=S OO2 = 511 °–00C2VV6 RR.4AAVNN FGGOEER MM AAIVNXD I DNIN L>L +26.4V PUT VOLTAGE DELT–00..000000550 T –0.0010 OU–0.0010 AVDD = +15V AVSS = –15V –0.0015 –0.0015 ±10V RANGE TA = 25°C –0.002010 15 S2U0PPLY (V) 25 30 09226-034 –0.0020–20 –16 –12 –8OUTP–U4T CU0RREN4T (mA)8 12 16 20 09226-036 Figure 21. Integral Nonlinearity Error vs. AVDD/|AVSS| Figure 24. Source and Sink Capability of Output Amplifier 1.0 12 0.8 AAAVVLLDSS DR ==A N–+11G55EVVS AAVVDSSD == –+1155VV 8 ±10V RANGE LSB) 000...246 ATAV S=S 2 =5 °–C26.4V FOR AVDD > +26.4V GE (V) 4 OTAU T= P2U5°TC UNLOADED R ( TA RRO 0 DDNNLL EERRRROORR MMAINX VOL 0 E T L –0.2 U N P D–0.4 OUT –4 –0.6 –8 –0.8 –1.010 15 S2U0PPLY (V) 25 30 09226-138 –12–5 0 TIME5 (µs) 10 15 09226-037 Figure 22. Differential Nonlinearity Error vs. AVDD/|AVSS| Figure 25. Full-Scale Positive Step 0.008 12 0V TO 10V RANGE MAX TUE 0V TO 10V RANGE MIN TUE AVDD = +15V SR) 0.006 TA= 25°C 8 A±1V0SVS R=A –N1G5VE %F AVSS = –26.4V FOR AVDD > +26.4V TA = 25°C ROR ( 0.004 E (V) 4 OUTPUT UNLOADED R G E A D T TE 0.002 OL 0 S V L UNADJU 0 OUTPUT –4 A T O –0.008 –8 T –0.00410 15 S2U0PPLY (V) 25 30 09226-035 –12–5 0 TIME5 (µs) 10 15 09226-038 Figure 23. Total Unadjusted Error vs. AVDD/|AVSS| Figure 26. Full-Scale Negative Step Rev. G | Page 18 of 50

Data Sheet AD5755-1 15 25 0x7FFFTO 0x8000 AVDD = +15V 0x8000TO 0x7FFF AVSS = –15V 20 10 ±10V RANGE TA = 25°C 15 V) 5 mV) 10 E ( E ( G G 5 OUTPUT VOLTA –1–050 OUTPUT VOLTA –1–050 –15 –15 –20 AAVVDSSD == –+1155VV THE EXTERNAL RESISTOR IS A TA = 25°C VISHAY S102C, 0.6ppm RESISTOR –200 1 2 TIME (µs)3 4 5 09226-039 –250 25 50TIME (µs)75 100 125 09226-043 Figure 27. Digital-to-Analog Glitch Figure 30. VOUT_x vs. Time on Power-Up 15 60 AVDD = +15V AVSS = –15V 40 ±10V RANGE 10 TA = 25°C 20 OUTPUT UNLOADED E (µV) 5 E (mV) 0 G G –20 A A T T OL 0 OL –40 V V UT UT –60 POC = 1 P P T –5 T POC = 0 U U –80 O O AVDD = +15V –100 AVSS = –15V –10 ±10V RANGE –120 TA = 25°C INT_ENABLE = 1 –150 1 2 3 4 TIM5E (s) 6 7 8 9 10 09226-040 –1400 2 4TIME (µs)6 8 10 09226-044 Figure 28. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth) Figure 31. VOUT_x vs. Time on Output Enable 300 0 AVDD = +15V ±10V RANGE OUTPUT UNLOADED AVSS = –15V TA = 25°C AVDD = +15V VBOOST = +15V 200 –20 AVSS = –15V TA = 25°C V) E (µ 100 dB) –40 OLTAG 0 PSRR ( –60 UTPUT V –100 V OUT_x –80 O –200 –100 –3000 1 2 3 4 TIME5 (µs)6 7 8 9 10 09226-041 –12010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09226-045 Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth) Figure 32. VOUT_x PSRR vs. Frequency Rev. G | Page 19 of 50

AD5755-1 Data Sheet CURRENT OUTPUTS 0.0025 0.0010 AVDD = +15V AVSS = –15V 0.0008 TA = 25°C 0.0015 0.0006 OR (%FSR) 0.0005 OR (%FSR) 00..000000240 4000mmmmAAAA TTTTOOOO 22220040mmmmAAAA RRRRAAAANNNNGGGGEEEE MMMMAAAINXXX I NIIINNNLLLL AAVVDSSD == –+1155VV/0V INL ERR–0.0005 INL ERR––00..00000042 40mmAA TTOO 2204mmAA RRAANNGGEE MMAINX I NINLL –0.0015 4mATO 20mA, EXTERNAL RSET –0.0006 –0.0025 444mmmAAATTTOOO 222000mmmAAA,,, EIINNXTTTEEERRRNNNAAALLL RR RSSSEEETTT, ,W WITITHH D DCC-T-TOO--DDCC C COONNVVEERRTTEERR 09226-149 ––00..00000108 09226-152 0 10000 20000 30000 40000 50000 60000 –40 –20 0 20 40 60 80 100 CODE TEMPERATURE (°C) Figure 33. Integral Nonlinearity vs. Code Figure 36. Integral Nonlinearity vs. Temperature, Internal RSET 1.0 0.0020 AVDD = +15V 4mA TO 20mA RANGE MAX INL 0.8 AVSS = –15V 0.0015 0mA TO 24mA RANGE MAX INL TA = 25°C 0mA TO 20mA RANGE MIN INL 0.6 0.0010 SB) 0.4 FSR) 0.0005 L 0.2 % R ( R ( 0mA TO 20mA RANGE MAX INL RO 0 RO 0 40mmAA TTOO 2204mmAA RRAANNGGEE MMIINN IINNLL R R E E NL –0.2 NL –0.0005 D I –0.4 –0.0010 –––100...086 4444mmmmAAAATTTTOOOO 22220000mmmmAAAA,,,, EEIINNXXTTTTEEEERRRRNNNNAAAALLLL RR RRSSSSEEEETTTT, ,W WITITHH D DCC-T-TOO--DDCC C COONNVVEERRTTEERR 09226-150 ––00..00002105–40 –20 0 AAVVDSSD2 ==0 –+1155VV/04V0 60 80 100 09226-153 0 10000 20000 30000 40000 50000 60000 CODE TEMPERATURE (°C) Figure 37. Integral Nonlinearity vs. Temperature, External RSET Figure 34. Differential Nonlinearity vs. Code 1.0 0.035 0.8 AVDD = +15V R) 0.030 AAVLLSS R =A N–1G5EVS/0V %FS 0.025 0.6 INTERNAL AND EXTERNAL RSET D ERROR ( 00..001250 AATAALVV LDS=S D C2 ==5H ° A–+C11N55NVVELS ENABLED OR (LSB) 00..24 DNL ERROR MAX TE 0.010 RR 0 DNL ERROR MIN ADJUS 0.005 44mmAA TTOO 2200mmAA,, EEXXTTEERRNNAALL RRSSEETT, WITH DC-TO-DC CONVERTER DNL E–0.2 L UN 0 44mmAA TTOO 2200mmAA,, IINNTTEERRNNAALL RRSSEETT, WITH DC-TO-DC CONVERTER –0.4 A –0.6 T–0.005 O T––00..0011500 10000 20000 30000 40000 50000 60000 09226-151 ––10..08–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 09226-154 CODE Figure 38. Differential Nonlinearity vs. Temperature Figure 35. Total Unadjusted Error vs. Code Rev. G | Page 20 of 50

Data Sheet AD5755-1 0.03 0.02 0.02 R) 0.01 S 0.01 F TOTAL UNADJSUTED ERROR (%––––––––00000000........00000000876543210 440000mmmmmmAAAAAA TTTTTTAAOOOOOOVV DS222222SD000044 mmmmmm== AAAAAA–+1 1IEIEEI55NNNXXXVVTTTTTT/EEE0EEEVRRRRRRNNNNNNAAAAAALLLLLL RRR RRRSSSSSSEEEEEETTTTTT 09226-155 GAIN ERROR (%FSR)––––––000000......0000006543210 AAVV440000DSmmmmmmSDAAAAAA == TTTTTT –+OOOOOO115 5222222VV000044/mmmmmm0VAAAAAA IEIEEINNNXXXTTTTTTEEEEEERRRRRRNNNNNNAAAAAALLLLLL RRR RRRSSSSSSEEEEEETTTTTT 09226-159 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 39. Total Unadjusted Error vs. Temperature Figure 42. Gain Error vs. Temperature 0.03 0.0025 0.02 4mA TO 20mA RANGE MAX INL 0.0020 4mA TO 20mA RANGE MIN INL 0.01 TA= 25°C R) 0.0015 AVSS = –26.4V FOR AVDD > +26.4V FS 0 R (%–0.01 SR) 0.0010 SCALE ERRO–––000...000432 4mA TOAA 2VV0DSmSDA == I –N+11T55EVVR/0NVAL RSET L ERROR (%F 0.00050 ULL-–0.05 00mmAA TTOO 2204mmAA IINNTTEERRNNAALL RRSSEETT IN–0.0005 F–0.06 4mA TO 20mA EXTERNAL RSET –0.0010 0mA TO 20mA EXTERNAL RSET ––00..0087–40 –20 00mA TTEOM 22P04EmRAA TEUX4RT0EE R(°NCA)L6 0RSET 80 100 09226-157 ––00..0000210510 15 S2U0PPLY (V) 25 30 09226-056 Figure 40. Full Scale Error vs. Temperature Figure 43. Integral Nonlinearity Error vs. AVDD/|AVSS|, Over Supply, External RSET 0.020 0.0015 0.015 0.0010 R) 0.010 FS 0.0005 OR (% 0.005 FSR) 0 SET ERR–0.0050 AAVVDSSD == –+1155VV/0V RROR (%–0.0005 OFF–0.010 400mmmAAA TTTOOO 222004mmmAAA IIINNNTTTEEERRRNNNAAALLL RRRSSSEEETTT INL E–0.0010 4mA TO 20mA EXTERNAL RSET –0.0015 4mA TO 20mA RANGE MAX INL ––00..002105 00mmAA TTOO 2204mmAA EEXXTTEERRNNAALL RRSSEETT 09226-158 –0.0020 4TAmAVSA=S 2T =5O °–C 2206m.4AV RFOANRG AEV DMDI N> I+N2L6.4V –40 –20 0 20 40 60 80 100 Figure 41. OffsTeEt MErPrEoRr AvTs.U TReEm (°pCe)rature –0.002510 15 S2U0PPLY (V) 25 30 09226-057 Figure 44. Integral Nonlinearity Error vs. AVDD/|AVSS|, Over Supply, Internal RSET Rev. G | Page 21 of 50

AD5755-1 Data Sheet 1.0 6 0.8 AINLTLE RRANNAGL EASND EXTERNAL RSET AAVVDSSD == –+1155VV 0.6 ATAV S=S 2 =5 °–C26.4V FOR AVDD > +26.4V 5 TRAL O=A 2D5 =°C 300Ω 0.4 B) 4 RROR (LS 0.20 DDNNLL EERRRROORR MMAINX RENT (µA) 3 E R NL –0.2 CU D 2 –0.4 –0.6 1 –0.8 –1.010 15 S2U0PPLY (V) 25 30 09226-162 00 5 TIME10 (µs) 15 20 09226-062 Figure 45. Differential Nonlinearity Error vs. AVDD Figure 48. Output Current vs. Time on Power-Up 0.012 4 SR)0.010 2 F % R ( 0 O0.008 USTED ERR0.006 RRENT (µA) ––42 J U D C NA0.004 TOTAL U0.002 TA44mmAVSAA=S 2TT =5OO °–C 222006mm.4AAV RRFOAANNRGG AEEV DMMDAI N>X T +TU2U6EE.4V ––86 AATRINAVVLT ODS=_ASD E2D =N=5 = ° –+=C 131 1505V0VΩ 010 15 S2U0PPLY (V) 25 30 09226-060 –100 1 2 TIME3 (µs) 4 5 6 09226-063 Figure 46. Total Unadjusted Error vs. AVDD, External RSET Figure 49. Output Current vs. Time on Output Enable 0 30 –0.002 FSR) –0.004 25 % R ( –0.006 mA) RO 4mA TO 20mA RANGE MAX TUE T (20 ER –0.008 4mA TO 20mA RANGE MIN TUE EN USTED –0.010 TAAVS=S 2 =5 °–C26.4V FOR AVDD > +26.4V T CURR15 IVOBUOTOST UNADJ ––00..001142 OUTPU10 01mkΩA LTOOA 2D4mA RANGE AL fSW = 410kHz OT –0.016 5 INDUCTOR = 10µH (XAL4040-103) T ––00..00210810 15 S2U0PPLY (V) 25 30 09226-061 –00.50 –0.25 0 0.25 0.50TTAIMAV0 CE=.C7 2(5 m=5° s5C)1V.00 1.25 1.50 1.75 2.0009226-167 Figure 47. Total Unadjusted Error vs. AVDD, Internal RSET Figure 50. Output Current and VBOOST_x Settling Time with DC-to-DC Converter (See Figure 81) Rev. G | Page 22 of 50

Data Sheet AD5755-1 30 8 0mA TO 24mA RANGE 7 1kΩ LOAD 25 FSW = 410kHz INDUCTOR = 10µH (XAL4040-103) T (mA)20 AGE (V) 65 TA = 25°C N T E L R O UTPUT CUR1105 IIIOOOUUUTTT,,, TTTAAA === –++421050°°5CC°C ADROOM V 43 O 0mA TO 24mA RANGE HE 2 1kΩ LOAD –050.25 0 0.25 0.50 TIAf0NSI.VMW7DC5EU C= C( =4mT1 1O5s0.V)0kR0H =z 110.µ2H5 (XA1L.540040-11.0735) 09226-168 100 5 CU1R0RENT (mA) 15 20 09226-067 Figure 51. Output Current Settling with DC-to-DC Converter vs. Time and Figure 54. DC-to-DC Converter Headroom vs. Output Current (See Figure 81) Temperature (See Figure 81) 30 0 AVDD = +15V VBOOST = +15V 25 –20 AVSS = –15V TA = 25°C A) ENT (m20 R (dB) –40 R R UR15 IOUT, AVCC = 4.5V PS –60 UT C IIOOUUTT,, AAVVCCCC == 55..05VV UT_x TP10 IO –80 U O 0mA TO 24mA RANGE 1kΩ LOAD 5 fSW = 410kHz –100 –00.25 0 0.25 0.50 TIT0NIA.M7D =5EU 2C(m5T°1OsC.)0R0 = 110.µ2H5 (XA1L.540040-11.0735) 09226-169 –12010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09226-068 Figure 52. Output Current Settling with DC-to-DC Converter vs. Time and Figure 55. IOUT_x PSRR vs. Frequency AVCC (See Figure 81) 10 20mA OUTPUT 10mA OUTPUT 8 A) 6 µ D) ( 4 E L P 2 U O C-C 0 A T ( –2 N E R –4 R U C –6 0mA TO 24mA RANGE –1–08 AfINSVWDD U=DC =4T1 O50VRkH =z 10µH (XAL4040-103) EXTER1TNkAAΩ L =L RO25SA°EDCT 09226-170 0 2 4 6 8 10 12 14 TIME (µs) Figure 53. Output Current vs. Time with DC-to-DC Converter (See Figure 81) Rev. G | Page 23 of 50

AD5755-1 Data Sheet DC-TO-DC BLOCK 100 100 AVDD = 4.5V 90 AAVVDDDD == 55..05VV 90 80 80 %) %) Y ( 70 Y ( 70 20mA C C EN 60 EN 60 CI CI FI 50 FI 50 F F E E ST40 UT 40 VBOO30 0mA TO 24mA RANGE OUTP 30 0mA TO 24mA RANGE 20 1EkXΩT ELRONAADL RSET 20 1EkXΩT ELRONAADL RSET 10 fINSWDU =C 4T1O0kRH =z 10µH (XAL4040-103) 10 AfSVWD D= =41 50VkHz TA = 25°C INDUCTOR = 10µH (XAL4040-103) 00 0.005 OU0T.0P1U0T CURR0E.N01T5 (A) 0.020 0.025 09226-255 0–40 –20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 09226-258 Figure 56. Efficiency at VBOOST_x vs. Output Current (See Figure 81) Figure 59. Output Efficiency vs. Temperature (See Figure 81) 100 0.6 90 20mA 0.5 80 CIENCY (%) 6700 STANCE (Ω) 0.4 FI 50 SI 0.3 F E E R BOOST3400 WITCH 0.2 V 0mA TO 24mA RANGE S 20 1kΩ LOAD EXTERNAL RSET 0.1 AVDD = 5V 10 fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) 0-40 -20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 09226-256 0–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 09226-123 Figure 57. Efficiency at VBOOST_x vs. Temperature (See Figure 81) Figure 60. Switch Resistance vs. Temperature 100 AVDD = 4.5V 90 AVDD = 5.0V AVDD = 5.5V 80 %) Y ( 70 C EN 60 CI FI 50 F E UT 40 P T U 30 O 0mA TO 24mA RANGE 1kΩ LOAD 20 EXTERNAL RSET fSW = 410kHz 10 INDUCTOR = 10µH (XAL4040-103) TA = 25°C 00 0.005 OU0T.0P1U0T CURR0E.N01T5 (A) 0.020 0.025 09226-257 Figure 58. Output Efficiency vs. Output Current (See Figure 81) Rev. G | Page 24 of 50

Data Sheet AD5755-1 REFERENCE 16 5.0050 14 ARVEDFDOUT 5.0045 3A0V DDDE V= I1C5EVS SHOWN 12 TA = 25°C 5.0040 5.0035 10 VOLTAGE (V) 86 REFOUT (V) 555...000000223050 4 5.0015 2 5.0010 0 5.0005 –20 0.2 0.4 TIM0E. 6(ms) 0.8 1.0 1.2 09226-010 5.000–040 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 09226-163 Figure 61. REFOUT Turn-On Transient Figure 64. REFOUT vs. Temperature (When the AD5755-1 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is −4 mV. Measurement of these parts after seven days shows that the outputs typically shift back 2 mV toward their initial values. This second shift is due to the relaxations of stress incurred during soldering.) 4 5.002 µV) 3 TAAV D=D 2 =5 °1C5V 5.001 TAAV D=D 2 =5 °1C5V E ( G TA 2 5.000 L O E OUTPUT V 10 REFOUT (V)44..999998 C N RE –1 4.997 E F E R –2 4.996 –30 2 4 TIME (s) 6 8 10 09226-011 4.9950 2 LOA4D CURRENT 6(mA) 8 10 09226-014 Figure 62. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth) Figure 65. REFOUT vs. Load Current 150 5.00000 UT VOLTAGE (µV) 10500 TAAV D=D 2 =5 °1C5V T VOLTAGE (V) 444...999999999998505 TA = 25°C UTP 0 TPU 4.99980 O U E O NC –50 CE 4.99975 REFERE –100 REFEREN 4.99970 4.99965 –1500Figure 63. REF5OUT OutpTuItM N1Eo0 (imses )(100 kHz 1B5andwidth) 20 09226-012 4.9996010 15 2A0VDD (V) 25 30 09226-015 Figure 66. REFOUT vs. Supply Rev. G | Page 25 of 50

AD5755-1 Data Sheet GENERAL 450 13.4 400 TDAV D=D 2 =5° 5CV 13.3 350 13.2 300 MHz) 13.1 DI (µA)CC 225000 QUENCY ( 13.0 E 12.9 150 FR 12.8 100 50 12.7 DVDD = 5.5V 00 1 SD2IN VOLTAGE3 (V) 4 5 09226-007 12.6–40 –20 0 TE2M0PERAT4U0RE (°C6)0 80 100 09226-020 Figure 67. DICC vs. Logic Input Voltage Figure 70. Internal Oscillator Frequency vs. Temperature 10 14.4 8 14.2 6 4 AIDD 14.0 CURRENT (mA) ––4220 VOATAOIUS UT=ST P2 =U5 °T0C VUNLOADED REQUENCY (MHz) 1133..86 F –6 13.4 –8 –10 13.2 TDAV D=D 2 =5° 5C.5V –1210 15 VO20LTAGE (V) 25 30 09226-008 13.02.5 3.0 3.5 VOLT4A.0GE (V) 4.5 5.0 5.5 09226-021 Figure 68. AIDD/AISS vs. AVDD/|AVSS| Figure 71. Internal Oscillator Frequency vs. DVDD Supply Voltage 8 7 6 A) 5 m T ( N 4 E R R CU 3 2 AIDD 1 TA = 25°C IOUT = 0mA 010 15 VO20LTAGE (V) 25 30 09226-009 Figure 69. AIDD vs. AVDD Rev. G | Page 26 of 50

Data Sheet AD5755-1 TERMINOLOGY scale − 1 LSB. Full-scale error is expressed in percent of full- Relative Accuracy or Integral Nonlinearity (INL) scale range (% FSR). For the DAC, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation, in LSBs, from the best fit Full-Scale TC line through the DAC transfer function. A typical INL vs. code Full-scale TC is a measure of the change in full-scale error with plot is shown in Figure 9. changes in temperature and is expressed in ppm FSR/°C. Differential Nonlinearity (DNL) Total Unadjusted Error Differential nonlinearity (DNL) is the difference between the Total unadjusted error (TUE) is a measure of the output error measured change and the ideal 1 LSB change between any two taking all the various errors into account, including INL error, adjacent codes. A specified differential nonlinearity of ±1 LSB offset error, gain error, temperature, and time. TUE is expressed maximum ensures monotonicity. This DAC is guaranteed mono- in % FSR. tonic by design. A typical DNL vs. code plot is shown in Figure 10. DC Crosstalk Monotonicity This is the dc change in the output level of one DAC in response A DAC is monotonic if the output either increases or remains to a change in the output of another DAC. It is measured with a constant for increasing digital input code. The AD5755-1 is full-scale output change on one DAC while monitoring another monotonic over its full operating temperature range. DAC, which is at midscale. Negative Full-Scale Error/Zero-Scale Error Current Loop Compliance Voltage Negative full-scale error is the error in the DAC output voltage The maximum voltage at the I pin for which the output OUT_x when 0x0000 (straight binary coding) is loaded to the DAC register. current is equal to the programmed value. Zero-Scale TC Voltage Reference Thermal Hysteresis This is a measure of the change in zero-scale error with a change in Voltage reference thermal hysteresis is the difference in output temperature. Zero-scale error TC is expressed in ppm FSR/°C. voltage measured at +25°C compared to the output voltage measured at +25°C after cycling the temperature from +25°C to Bipolar Zero Error −40°C to +105°C and back to +25°C. The hysteresis is expressed Bipolar zero error is the deviation of the analog output from the in ppm. ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding). Output Voltage Settling Time Output voltage settling time is the amount of time it takes for Bipolar Zero TC the output to settle to a specified level for a full-scale input Bipolar zero TC is a measure of the change in the bipolar zero change. A plot of settling time is shown in Figure 25, Figure 51, error with a change in temperature. It is expressed in ppm FSR/°C. and Figure 52. Offset Error Slew Rate In voltage output mode, offset error is the deviation of the The slew rate of a device is a limitation in the rate of change of analog output from the ideal quarter-scale output when in the output voltage. The output slewing speed of a voltage-output bipolar output ranges and the DAC register is loaded with digital-to-analog converter is usually limited by the slew rate of 0x4000 (straight binary coding). the amplifier used at its output. Slew rate is measured from 10% In current output mode, offset error is the deviation of the to 90% of the output signal and is given in V/µs. analog output from the ideal zero-scale output when all DAC Power-On Glitch Energy registers are loaded with 0x0000. Power-on glitch energy is the impulse injected into the analog Gain Error output when the AD5755-1 is powered-on. It is specified as the This is a measure of the span error of the DAC. It is the devia- area of the glitch in nV-sec. See Figure 30 and Figure 48. tion in slope of the DAC transfer characteristic from the ideal, Digital-to-Analog Glitch Impulse expressed in % FSR. Digital-to-analog glitch impulse is the impulse injected into the Gain TC analog output when the input code in the DAC register changes This is a measure of the change in gain error with changes in state, but the output voltage remains constant. It is normally temperature. Gain TC is expressed in ppm FSR/°C. specified as the area of the glitch in nV-sec and is measured Full-Scale Error when the digital input code is changed by 1 LSB at the major Full-scale error is a measure of the output error when full-scale carry transition (~0x7FFF to 0x8000). See Figure 27. code is loaded to the DAC register. Ideally, the output is full- Rev. G | Page 27 of 50

AD5755-1 Data Sheet Glitch Impulse Peak Amplitude Line Regulation Glitch impulse peak amplitude is the peak amplitude of the Line regulation is the change in reference output voltage due to impulse injected into the analog output when the input code in a specified change in supply voltage. It is expressed in ppm/V. the DAC register changes state. It is specified as the amplitude Load Regulation of the glitch in mV and is measured when the digital input code Load regulation is the change in reference output voltage due to is changed by 1 LSB at the major carry transition (~0x7FFF to a specified change in load current. It is expressed in ppm/mA. 0x8000). See Figure 27. DC-to-DC Converter Headroom Digital Feedthrough This is the difference between the voltage required at the Digital feedthrough is a measure of the impulse injected into the current output and the voltage supplied by the dc-to-dc analog output of the DAC from the digital inputs of the DAC but is converter. See Figure 54. measured when the DAC output is not updated. It is specified Output Efficiency in nV-sec and measured with a full-scale code change on the data bus. I2OUT ×RLOAD AV ×AI DAC-to-DAC Crosstalk CC CC DAC-to-DAC crosstalk is the glitch impulse transferred to the This is defined as the power delivered to a channel’s load vs. the output of one DAC due to a digital code change and a subsequent power delivered to the channel’s dc-to-dc input. output change of another DAC. This includes both digital and Efficiency at V BOOST_x analog crosstalk. It is measured by loading one of the DACs I ×V with a full-scale code change (all 0s to all 1s and vice versa) with OUT BOOST_x AV ×AI LDAC low and monitoring the output of another DAC. The CC CC energy of the glitch is expressed in nV-sec. This is defined as the power delivered to a channel’s VBOOST_x supply vs. the power delivered to the dc-to-dc input of the channel. Power Supply Rejection Ratio (PSRR) The V quiescent current is considered part of the dc-to-dc PSRR indicates how the output of the DAC is affected by BOOST_x converter’s losses. changes in the power supply voltage. Reference TC Reference TC is a measure of the change in the reference output voltage with a change in temperature. It is expressed in ppm/°C. Rev. G | Page 28 of 50

Data Sheet AD5755-1 THEORY OF OPERATION The AD5755-1 is a quad, precision digital-to-current loop and VBOOST_x voltage output converter designed to meet the requirements of industrial process control applications. It provides a high precision, R2 R3 fully integrated, low cost, single-chip solution for generating T2 current loop and unipolar/bipolar voltage outputs. The current A2 ranges available are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA 16-BIT T1 to 20 mA. The voltage ranges available are 0 V to 5 V, ±5 V, 0 V DAC A1 IOUT_x to 10 V, and ±10 V. The current and voltage outputs are availa- ble on separate pins, and only one is active at any one time. The dcoensitrreodl roeugtipsutetr c. onfiguration is user selectable via the DAC RSET 09226-071 Figure 74. Voltage-to-Current Conversion Circuitry On-chip dynamic power control minimizes package power Voltage Output Amplifier dissipation in current mode. The voltage output amplifier is capable of generating both DAC ARCHITECTURE unipolar and bipolar output voltages. It is capable of driving a The DAC core architecture of the AD5755-1 consists of two load of 1 kΩ in parallel with 1 µF (with an external compen- matched DAC sections. A simplified circuit diagram is shown in sation capacitor) to AGND. The source and sink capabilities of Figure 72. The four MSBs of the 16-bit data-word are decoded to the output amplifier are shown in Figure 24. The slew rate is drive 15 switches, E1 to E15. Each of these switches connects 1.9 V/µs with a full-scale settling time of 16 µs (10 V step). If one of 15 matched resistors to either ground or the reference remote sensing of the load is not required, connect +V SENSE_x buffer output. The remaining 12 bits of the data-word drive directly to V . +V must stay within ±3.0 V of V OUT_x SENSE_x OUT_x Switch S0 to Switch S11 of a 12-bit voltage mode R-2R ladder for correct operation. network. Driving Large Capacitive Loads VOUT The voltage output amplifier is capable of driving capacitive 2R 2R 2R 2R 2R 2R 2R loads of up to 2 µF with the addition of a 220 pF nonpolarized S0 S1 S7/S11 E1 E2 E15 compensation capacitor on each channel. Take care to choose an appropriate value of compensation capacitor. This capacitor, while allowing the AD5755-1 to drive higher capacitive loads 12-BIT R-2R LADDER FOU15R EMQSUBAsL D SEECGOMDEENDT ISNTO 09226-069 aanndd, rtehdeurceefo orev,e rasfhfeocotst ,t ihnec rbeaansdesw tihdeth s eotft ltihneg styimsteem of. Wtheit hpoarutt Figure 72. DAC Ladder Structure the compensation capacitor, up to 10 nF capacitive loads can The voltage output from the DAC core is either converted to a be driven. See Table 5 for information on connecting compensa- current (see Figure 74), which is then mirrored to the supply rail tion capacitors. so that the application simply sees a current source output, or it Reference Buffers is buffered and scaled to output a software selectable unipolar or The AD5755-1 can operate with either an external or internal bipolar voltage range (see Figure 73). Both the voltage and current reference. The reference input requires a 5 V reference for outputs are supplied by V . The current and voltage are BOOST_x specified performance. This input voltage is then buffered output on separate pins and cannot be output simultaneously. before it is applied to the DAC. A channel’s current and voltage output pins can be tied together. POWER-ON STATE OF THE AD5755-1 +VSENSE_x On initial power-up of the AD5755-1, the power-on reset circuit DAC SRCAANLGINEG VOUT_x powers up in a state that is dependent on the power-on condition (POC) pin. VOUT_X SHORTFAULT 09226-070 If POC = 0, the voltage output and current output channels Figure 73. Voltage Output power up in tristate mode. If POC = 1, the voltage output channel powers up with a 30 kΩ pull-down resistor to ground, and the current output channel powers up to tristate. Rev. G | Page 29 of 50

AD5755-1 Data Sheet Even though the output ranges are not enabled, the default they are loaded into the DAC data register. All the DAC outputs output range is 0 V to 5 V, and the clear code register is loaded are updated by taking LDAC low after SYNC is taken high. with all zeros. This means that if the user clears the part after OUTPUT I/V AMPLIFIER power-up, the output is actively driven to 0 V (if the channel has been enabled for clear). VREFIN 1D6-ABCIT VOUT_x After a device power-on, or a device reset, it is recommended to wait 100 μs or more before writing to the device to allow time DAC LDAC REGISTER for internal calibrations to take place. SERIAL INTERFACE DAC INPUT REGISTER The AD5755-1 is controlled over a versatile 3-wire serial OFFSET interface that operates at clock rates of up to 30 MHz and is AND GAIN CALIBRATION compatible with SPI, QSPI, MICROWIRE, and DSP standards. DAC DATA REGISTER Data coding is always straight binary. Input Shift Register The input shift register is 24 bits wide. Data is loaded into the SSSYCDNLICNK INTLEORGFIACCE SDO 09226-072 device MSB first as a 24-bit word under the control of a serial Figure 75. Simplified Serial Interface of Input Loading Circuitry clock input, SCLK. Data is clocked in on the falling edge of SCLK. for One DAC Channel If packet error checking, or PEC (see the Device Features TRANSFER FUNCTION section), is enabled, an additional eight bits must be written to Table 6 shows the input code to ideal output voltage relationship the AD5755-1, creating a 32-bit serial interface. for the AD5755-1 for straight binary data coding of the ±10 V There are two ways in which the DAC outputs can be updated: output range. individual updating or simultaneous updating of all DACs. Table 6. Ideal Output Voltage to Input Code Relationship Individual DAC Updating Digital Input In this mode, LDAC is held low while data is being clocked into Straight Binary Data Coding Analog Output the DAC data register. The addressed DAC output is updated on MSB LSB VOUT the rising edge of SYNC. See Table 3 and Figure 3 for timing 1111 1111 1111 1111 +2 VREF × (32,767/32,768) information. 1111 1111 1111 1110 +2 VREF × (32,766/32,768) 1000 0000 0000 0000 0 V Simultaneous Updating of All DACs 0000 0000 0000 0001 −2 V × (32,767/32,768) REF In this mode, LDAC is held high while data is being clocked 0000 0000 0000 0000 −2 V REF into the DAC data register. Only the first write to each channel’s DAC data register is valid after LDAC is brought high. Any subse- quent writes while LDAC is still held high are ignored, though Rev. G | Page 30 of 50

Data Sheet AD5755-1 REGISTERS Table 7 shows an overview of the registers for the AD5755-1. Table 7. Data, Control, and Readback Registers for the AD5755-1 Register Description Data DAC Data Register (×4) Used to write a DAC code to each DAC channel. AD5755-1 data bits = D15 to D0. There are four DAC data registers, one per DAC channel. Gain Register (×4) Used to program gain trim, on a per channel basis. AD5755-1 data bits = D15 to D0. There are four gain registers, one per DAC channel. Offset Register (×4) Used to program offset trim, on a per channel basis. AD5755-1 data bits = D15 to D0. There are four offset registers, one per DAC channel. Clear Code Register (×4) Used to program clear code on a per channel basis. AD5755-1 data bits = D15 to D0. There are four clear code registers, one per DAC channel. Control Main Control Register Used to configure the part for main operation. Sets functions such as status readback during write, enables output on all channels simultaneously, powers on all dc-to-dc converter blocks simultaneously, and enables and sets conditions of the watchdog timer. See the Device Features section for more details. Software Register Has three functions. Used to perform a reset, enables the packet error checking feature, and verifies correct data communication operation as part of the watchdog timer feature. Slew Rate Control Register (×4) Used to program the slew rate of the output. There are four slew rate control registers, one per channel. DAC Control Register (×4) These registers are used to control the following: Set the output range, for example, 4 mA to 20 mA, 0 V to 10 V. Set whether an internal/external sense resistor is used. Enable/disable a channel for CLEAR. Enable/disable overrange. Enable/disable internal circuitry on a per channel basis. Enable/disable output on a per channel basis. Power on dc-to-dc converters on a per channel basis. There are four DAC control registers, one per DAC channel. DC-to-DC Control Register Use to set the dc-to-dc control parameters. Can control dc-to-dc maximum voltage, phase, and frequency. Readback Status Register This contains any fault information, as well as the status of the packet error checking feature. Rev. G | Page 31 of 50

AD5755-1 Data Sheet PROGRAMMING SEQUENCE TO WRITE/ENABLE CHANGING AND REPROGRAMMING THE RANGE THE OUTPUT CORRECTLY When changing between ranges, use the same sequence as To correctly write to and set up the part from a power-on described in the Programming Sequence to Write/Enable the condition, use the following sequence: Output Correctly section. It is recommended to set the range to its zero point (can be midscale or zero scale) prior to disabling 1. Perform a hardware or software reset after initial power-on. the output. Because the dc-to-dc switching frequency, maximum 2. The dc-to-dc converter supply block must be configured. voltage, and phase have already been selected, there is no need Set the dc-to-dc switching frequency, maximum output to reprogram these. A flowchart of this sequence is shown in voltage allowed, and the phase that the four dc-to-dc Figure 77. channels clock at. 3. Configure the DAC control register on a per channel basis. CHANNEL’S OUTPUT IS ENABLED. The output range is selected, and the dc-to-dc converter block is enabled (DC_DC bit). Other control bits can be STEP 1:WRITETO CHANNEL’S DAC DATA configured at this point. Set the INT_ENABLE bit; however, REGISTER. SET THE OUTPUT TO 0V (ZERO OR MIDSCALE). do not set the output enable bit (OUTEN). 4. Write the required code to the DAC data register. This STEP 2:WRITETO DAC CONTROL REGISTER. implements a full DAC calibration internally. Allow at least DISABLE THE OUTPUT (OUTEN = 0),AND SET THE NEW OUTPUT RANGE. KEEP THE 200 µs before Step 5 for reduced output glitch. DC_DC BITAND THE INT_ENABLE BIT SET. 5. Write to the DAC control register again to enable the output (set the OUTEN bit). STEP 3:WRITEVALUETO THE DAC DATA REGISTER. A flowchart of this sequence is shown in Figure 76. STEP 4:WRITETO DAC CONTROL REGISTER. POWER ON. RTEHNEILASOB TLAIEDM ETSH ESEQE ULOEEUCNTTCP EUTTHA.ES OINU STETENP B 2ITATBOOVE. 09226-074 Figure 77. Steps for Changing the Output Range STEP 1:PERFORM A SOFTWARE/HARDWARE RESET. STEP 2:WRITETO DC-TO-DC CONTROL REGISTERTO SET DC-TO-DC CLOCK FREQUENCY, PHASE, AND MAXIMUM VOLTAGE. STEP 3:WRITETO DAC CONTROL REGISTER. SELECT THE DAC CHANNELAND OUTPUT RANGE. SET THE DC_DC BITAND OTHER CONTROL BITSAS REQUIRED. SET THE INT_ENABLE BIT BUT DO NOT SELECT THE OUTEN BIT. STEP 4:WRITETO EACH/ALL DAC DATA REGISTERS. ALLOWAT LEAST 200µs BETWEEN STEP 3 AND STEP 5 FOR REDUCED OUTPUT GLITCH. STEP 5:WRITETO DAC CONTROL REGISTER. RELOAD SSTHEEQLEE UOCEUTNT CTPHEUETA .OS UINT ESNT EBPIT 3TAOB EONVAEB. TLHEIS TIME 09226-073 Figure 76. Programming Sequence for Enabling the Output Correctly Rev. G | Page 32 of 50

Data Sheet AD5755-1 DATA REGISTERS The input register is 24 bits wide. When PEC is enabled, the DAC Data Register input register is 32 bits wide, with the last eight bits correspond- When writing to the AD5755-1 DAC data registers, D15 to D0 ing to the PEC code (see the Packet Error Checking section for are used for DAC data bits. Table 10 shows the register format more information on PEC). When writing to a data register, the and Table 9 describes the function of Bit D23 to Bit D16. format in Table 8 must be used. Table 8. Writing to a Data Register MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0 R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 Data Table 9. Input Register Decode Bit Description R/W Indicates a read from or a write to the addressed register. DUT_AD1, DUT_AD0 Used in association with the external pins, AD1 and AD0, to determine which AD5755-1 device is being addressed by the system controller. It is not recommended to tie both AD1 and AD0 low when using PEC, see the Packet Error Checking section. DUT_AD1 DUT_AD0 Function 0 0 Addresses part with Pin AD1 = 0, Pin AD0 = 0 0 1 Addresses part with Pin AD1 = 0, Pin AD0 = 1 1 0 Addresses part with Pin AD1 = 1, Pin AD0 = 0 1 1 Addresses part with Pin AD1 = 1, Pin AD0 = 1 DREG2, DREG1, DREG0 Selects whether a data register or a control register is written to. If a control register is selected, a further decode of CREG bits (see Table 17) is required to select the particular control register, as follows. DREG2 DREG1 DREG0 Function 0 0 0 Write to DAC data register (individual channel write) 0 1 0 Write to gain register 0 1 1 Write to gain register (all DACs) 1 0 0 Write to offset register 1 0 1 Write to offset register (all DACs) 1 1 0 Write to clear code register 1 1 1 Write to a control register DAC_AD1, DAC_AD0 These bits are used to decode the DAC channel. DAC_AD1 DAC_AD0 DAC Channel/Register Address 0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D X X These are don’t cares if they are not relevant to the operation being performed. Table 10. Programming the DAC Data Registers MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0 R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 DAC data Rev. G | Page 33 of 50

AD5755-1 Data Sheet Gain Register in steps of 1 LSB. This is done by setting the DREG[2:0] bits to 100. It is possible to write the same offset code to all four DAC The 16-bit gain register, as shown in Table 11, allows the user to channels at the same time by setting the DREG[2:0] bits to 101. adjust the gain of each channel in steps of 1 LSB. This is done by The offset register coding is straight binary as shown in Table 14. setting the DREG[2:0] bits to 010. It is possible to write the same The default code in the offset register is 0x8000, which results in gain code to all four DAC channels at the same time by setting zero offset programmed to the output. See the Digital Offset the DREG[2:0] bits to 011. The gain register coding is straight and Gain Control section for more information. binary as shown in Table 12. The default code in the gain register is Clear Code Register 0xFFFF. In theory, the gain can be tuned across the full range of the output. In practice, the maximum recommended gain trim is The 16-bit clear code register allows the user to set the clear about 50% of programmed range to maintain accuracy. See the value of each channel as shown in Table 15. It is possible, via Digital Offset and Gain Control section for more information. software, to enable or disable on a per channel basis which Offset Register channels are cleared when the CLEAR pin is activated. The default clear code is 0x0000. See the Asynchronous Clear The 16-bit offset register, as shown in Table 13, allows the user to section for more information. adjust the offset of each channel by −32,768 LSBs to +32,768 LSBs Table 11. Programming the Gain Register R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D0 0 Device address 0 1 0 DAC channel address Gain adjustment Table 12. Gain Register Gain Adjustment G15 G14 G13 G12 to G4 G3 G2 G1 G0 +65,535 LSBs 1 1 1 1 1 1 1 1 +65,534 LSBs 1 1 1 1 1 1 1 0 … … … … … … … … … 1 LSB 0 0 0 0 0 0 0 1 0 LSBs 0 0 0 0 0 0 0 0 Table 13. Programming the Offset Register R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D0 0 Device address 1 0 0 DAC channel address Offset adjustment Table 14. Offset Register Options Offset Adjustment OF15 OF14 OF13 OF12 to OF4 OF3 OF2 OF1 OF0 +32,768 LSBs 1 1 1 1 1 1 1 1 +32,767 LSBs 1 1 1 1 1 1 1 0 +32,766 LSBs 1 1 1 1 1 1 0 0 … … … … … … … … … No Adjustment (Default) 1 0 0 0 0 0 0 0 … … … … … … … … … −32,767 LSBs 0 0 0 0 0 0 0 1 −32,768 LSBs 0 0 0 0 0 0 0 0 Table 15. Programming the Clear Code Register R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D0 0 Device address 1 1 0 DAC channel address Clear code Rev. G | Page 34 of 50

Data Sheet AD5755-1 CONTROL REGISTERS When writing to a control register, use the format shown in Table 16. Main Control Register See Table 9 for information on the configuration of Bit D23 to The main control register options are shown in Table 18 and Bit D16. The control registers are addressed by setting the DREG[2:0] Table 19. See the Device Features section for more information bits to 111 and then setting the CREG[2:0] bits to the appropriate on the features controlled by the main control register. decode address for that register, according to Table 17. These CREG bits select among the various control registers. Table 16. Writing to a Control Register MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 to D0 R/W DUT_AD1 DUT_AD0 1 1 1 DAC_AD1 DAC_AD0 CREG2 CREG1 CREG0 Data Table 17. Register Access Decode CREG2 (D15) CREG1 (D14) CREG0 (D13) Function 0 0 0 Slew rate control register (one per channel) 0 0 1 Main control register 0 1 0 DAC control register (one per channel) 0 1 1 DC-to-dc control register 1 0 0 Software register Table 18. Programming the Main Control Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 to D0 0 0 1 POC STATREAD EWD WD1 WD0 X1 SHTCCTLIM OUTEN_ALL DCDC_ALL X1 1 X = don’t care. Table 19. Main Control Register Functions Bit Description POC The POC bit determines the state of the voltage output channels during normal operation. Its default value is 0. POC = 0. The output goes to the value set by the POC hardware pin when the voltage output is not enabled (default). POC = 1. The output goes to the opposite value of the POC hardware pin if the voltage output is not enabled. STATREAD Enable status readback during a write. See the Device Features section. STATREAD = 1, enable. STATREAD = 0, disable (default). EWD Enable watchdog timer. See the Device Features section for more information. EWD = 1, enable watchdog. EWD = 0, disable watchdog (default). WD1, WD0 Timeout select bits. Used to select the timeout period for the watchdog timer. WD1 WD0 Timeout Period (ms) 0 0 5 0 1 10 1 0 100 1 1 200 SHTCCTLIM Programmable short-circuit limit on the V pin in the event of a short-circuit condition. OUT_x 0 = 16 mA (default). 1 = 8 mA. OUTEN_ALL Enables the output on all four DACs simultaneously. Do not use the OUTEN_ALL bit when using the OUTEN bit in the DAC control register. DCDC_ALL When set, powers up the dc-to-dc converter on all four channels simultaneously. To power down the dc-to-dc converters, all channel outputs must first be disabled. Do not use the DCDC_ALL bit when using the DC_DC bit in the DAC control register. Rev. G | Page 35 of 50

AD5755-1 Data Sheet DAC Control Register The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 20 and Table 21. Table 20. Programming DAC Control Register D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 X1 X1 X1 X1 INT_ENABLE CLR_EN OUTEN RSET DC_DC OVRNG R2 R1 R0 1 X = don’t care. Table 21. DAC Control Register Functions Bit Description INT_ENABLE Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel. Does not enable the output. Can only be done on a per channel basis. It is recommended to set this bit and allow a >200 µs delay before enabling the output because this results in a reduced output enable glitch. See Figure 31 and Figure 49 for plots of this glitch. CLR_EN Per channel clear enable bit. Selects if this channel clears when the CLEAR pin is activated. CLR_EN = 1, channel clears when the part is cleared. CLR_EN = 0, channel does not clear when the part is cleared (default). OUTEN Enables/disables the selected output channel. OUTEN = 1, enables the channel. OUTEN = 0, disables the channel (default). RSET Selects an internal or external current sense resistor for the selected DAC channel. RSET = 0, selects the external resistor (default). RSET = 1, selects the internal resistor. DC_DC Powers the dc-to-dc converter on the selected channel. DC_DC = 1, power up the dc-to-dc converter. DC_DC = 0, power down the dc-to-dc converter (default). This allows per channel dc-to-dc converter power-up/power-down. To power down the dc-to-dc converter, the OUTEN and INT_ENABLE bits must also be set to 0. All dc-to-dc converters can also be powered up simultaneously using the DCDC_ALL bit in the main control register. OVRNG Enables 20% overrange on voltage output channel only. No current output overrange available. OVRNG = 1, enabled. OVRNG = 0, disabled (default). R2, R1, R0 Selects the output range to be enabled. R2 R1 R0 Output Range Selected 0 0 0 0 V to 5 V voltage range (default). 0 0 1 0 V to 10 V voltage range. 0 1 0 ±5 V voltage range. 0 1 1 ±10 V voltage range. 1 0 0 4 mA to 20 mA current range. 1 0 1 0 mA to 20 mA current range. 1 1 0 0 mA to 24 mA current range. Rev. G | Page 36 of 50

Data Sheet AD5755-1 Software Register When the watchdog feature is enabled, the user must write 0x195 to the software register within the timeout period. If this command The software register has three functions. It allows the user to is not received within the timeout period, the ALERT pin signals perform a software reset to the device and enable the packet a fault condition. This is only required when the watchdog timer error checking feature (see the Packet Error Checking section) function is enabled. It is also used as part of the watchdog feature when it is enabled. This feature is useful to ensure that communication is not lost DC-to-DC Control Register between the MCU and the AD5755-1 and that the datapath The dc-to-dc control register allows the user control over lines are working properly (that is, SDIN, SCLK, and SYNC). the dc-to-dc switching frequency and phase, as well as the maximum allowable dc-to-dc output voltage. The dc-to-dc control register options are shown in Table 24 and Table 25. Table 22. Programming the Software Register MSB LSB D15 D14 D13 D12 D11 to D0 1 0 0 PEC enable Reset code/SPI code Table 23. Software Register Functions Bit Description PEC Enable This bit selects if the packet error checking feature is enabled (see the Packet Error Checking section). 0 = PEC disabled. 1 = PEC enabled. Reset Code/SPI Code Option Description Reset code Writing 0x555 to D[11:0] performs a reset of the AD5755-1. SPI code If the watchdog timer feature is enabled, 0x195 must be written to the software register (D11 to D0) within the programmed timeout period. Table 24. Programming the DC-to-DC Control Register MSB LSB D15 D14 D13 D12 to D7 D6 D5 to D4 D3 to D2 D1 to D0 0 1 1 X1 DC-DC Comp DC-DC phase DC-DC Freq DC-DC MaxV 1 X = don’t care. Table 25. DC-to-DC Control Register Options Bit Description DC-DC Comp Selects between an internal and external compensation resistor for the dc-to-dc converter. See the DC-to-DC Converter Compensation Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more information. 0 = selects the internal 150 kΩ compensation resistor (default). 1 = bypasses the internal compensation resistor for the dc-to-dc converter. In this mode, an external dc-to-dc compensation resistor must be used; this is placed at the COMP pin in series with the 10 nF dc-to-dc compensation capacitor to ground. DCDC_x Typically, a ~50 kΩ resistor is recommended. DC-DC Phase User programmable dc-to-dc converter phase (between channels). 00 = all dc-to-dc converters clock on the same edge (default). 01 = Channel A and Channel B clock on the same edge, Channel C and Channel D clock on opposite edges. 10 = Channel A and Channel C clock on the same edge, Channel B and Channel D clock on opposite edges. 11 = Channel A, Channel B, Channel C, and Channel D clock 90° out of phase from each other. DC-DC Freq DC-to-dc switching frequency; these are divided down from the internal 13 MHz oscillator (see Figure 70 and Figure 71). 00 = 250 ± 10% kHz. 01 = 410 ± 10% kHz (default). 10 = 650 ± 10% kHz. DC-DC MaxV Maximum allowed V voltage supplied by the dc-to-dc converter. BOOST_x 00 = 23 V + 1 V/−1.5 V (default). 01 = 24.5 V ± 1 V. 10 = 27 V ± 1 V. 11 = 29.5 V ± 1 V. Rev. G | Page 37 of 50

AD5755-1 Data Sheet Slew Rate Control Register Meanwhile, the SDO returns 24 bits, the 8 MSBs are don’t cares, and the 16 LSBs contain the data from the addressed register. If This register is used to program the slew rate control for the PEC is enabled, the SDO returns 32 bits (Figure 5), with 8 CRC bits selected DAC channel. This feature is available on both the current appended to the data readback. and voltage outputs. The slew rate control is enabled/disabled and programmed on a per channel basis. See Table 26 and the Readback Example Digital Slew Rate Control section for more information. To read back the gain register of Device 1, Channel A on the READBACK OPERATION AD5755-1, implement the following sequence: Readback mode is invoked by setting the R/W bit = 1 in the serial 1. Write 0xA80000 to the AD5755-1 input register. This config- input register write. See Table 27 and Table 28 for the bits asso- ures the AD5755-1 Device Address 1 for read mode with ciated with a readback operation. The DUT_AD1 and DUT_AD0 the gain register of Channel A selected. All the data bits, bits, in association with the RD[4:0] bits, select the register to be D15 to D0, are don’t cares. read. The remaining data bits in the write sequence are don’t cares. 2. Follow with another read command or a no operation com- mand (0x3CE000). During this command, the data from During the next SPI transfer (see Figure 4), either a no operation the Channel A gain register is clocked out on the SDO line. (NOP) or a request to read another register must be issued. Table 26. Programming the Slew Rate Control Register D15 D14 D13 D12 D11 to D7 D6 to D3 D2 to D0 0 0 0 SREN X1 SR_CLOCK SR_STEP 1 X = don’t care. Table 27. Input Shift Register Contents for a Read Operation D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0 R/W DUT_AD1 DUT_AD0 RD4 RD3 RD2 RD1 RD0 X1 1 X = don’t care. Table 28. Read Address Decoding RD4 RD3 RD2 RD1 RD0 Function 0 0 0 0 0 Read DAC A data register 0 0 0 0 1 Read DAC B data register 0 0 0 1 0 Read DAC C data register 0 0 0 1 1 Read DAC D data register 0 0 1 0 0 Read DAC A control register 0 0 1 0 1 Read DAC B control register 0 0 1 1 0 Read DAC C control register 0 0 1 1 1 Read DAC D control register 0 1 0 0 0 Read DAC A gain register 0 1 0 0 1 Read DAC B gain register 0 1 0 1 0 Read DAC C gain register 0 1 0 1 1 Read DAC D gain register 0 1 1 0 0 Read DACA offset register 0 1 1 0 1 Read DAC B offset register 0 1 1 1 0 Read DAC C offset register 0 1 1 1 1 Read DAC D offset register 1 0 0 0 0 Clear DAC A code register 1 0 0 0 1 Clear DAC B code register 1 0 0 1 0 Clear DAC C code register 1 0 0 1 1 Clear DAC D code register 1 0 1 0 0 DAC A slew rate control register 1 0 1 0 1 DAC B slew rate control register 1 0 1 1 0 DAC C slew rate control register 1 0 1 1 1 DAC D slew rate control register 1 1 0 0 0 Read status register 1 1 0 0 1 Read main control register 1 1 0 1 0 Read dc-to-dc control register Rev. G | Page 38 of 50

Data Sheet AD5755-1 Status Register The status register is a read only register. This register contains read back on the SDO pin during every write sequence. any fault information, the status of the packet error checking Alternatively, if the STATREAD bit is not set, the status register feature, and a ramp active bit. When the STATREAD bit in the can be read using the normal readback operation. main control register is set, the status register contents can be Table 29. Decoding the Status Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DC- DC- DC- DC- PEC PEC Ramp Over VOUT_D VOUT_C VOUT_B VOUT_A IOUT_D IOUT_C IOUT_B IOUT_A DCD DCC DCB DCA enabled error active TEMP fault fault fault fault fault fault fault fault Table 30. Status Register Options Bit Description DC-DCD In current output mode, this bit is set on Channel D if the dc-to-dc converter cannot maintain compliance (it may be reaching its V voltage). In this case, the I fault bit is also set. See the DC-to-DC Converter V Functionality section for more MAX OUT_D MAX information on the operation of this bit under this condition. In voltage output mode, this bit is set if, on Channel D, the dc-to-dc converter is unable to regulate to 15 V as expected. When this bit is set, it does not result in the FAULT pin going high. DC-DCC In current output mode, this bit is set on Channel C if the dc-to-dc converter cannot maintain compliance (it may be reaching its V voltage). In this case, the I fault bit is also set. See the DC-to-DC Converter V Functionality section for more MAX OUT_C MAX information on the operation of this bit under this condition. In voltage output mode, this bit is set if, on Channel C, the dc-to-dc converter is unable to regulate to 15 V as expected. When this bit is set, it does not result in the FAULT pin going high. DC-DCB In current output mode, this bit is set on Channel B if the dc-to-dc converter cannot maintain compliance (it may be reaching its V voltage). In this case, the I fault bit is also set. See the DC-to-DC Converter V Functionality section for more MAX OUT_B MAX information on the operation of this bit under this condition. In voltage output mode, this bit is set if, on Channel B, the dc-to-dc converter is unable to regulate to 15 V as expected. When this bit is set, it does not result in the FAULT pin going high. DC-DCA In current output mode, this bit is set on Channel A if the dc-to-dc converter cannot maintain compliance (it may be reaching its V voltage). In this case, the I fault bit is also set. See the DC-to-DC Converter V Functionality section for more MAX OUT_A MAX information on the operation of this bit under this condition. In voltage output mode, this bit is set if, on Channel A, the dc-to-dc converter is unable to regulate to 15 V as expected. When this bit is set, it does not result in the FAULT pin going high. PEC Enabled This is a read only bit. It allows the user to verify the status of the packet error checking feature. PEC Error Denotes a PEC error on the last data-word received over the SPI interface. Ramp Active This bit is set while any one of the output channels is slewing (slew rate control is enabled on at least one channel). Over TEMP This bit is set if the AD5755-1 core temperature exceeds approximately 150°C. V Fault This bit is set if a fault is detected on the V pin. OUT_D OUT_D V Fault This bit is set if a fault is detected on the V pin. OUT_C OUT_C V Fault This bit is set if a fault is detected on the V pin. OUT_B OUT_B V Fault This bit is set if a fault is detected on the V pin. OUT_A OUT_A I Fault This bit is set if a fault is detected on the I pin. OUT_D OUT_D I Fault This bit is set if a fault is detected on the I pin. OUT_C OUT_C I Fault This bit is set if a fault is detected on the I pin. OUT_B OUT_B I Fault This bit is set if a fault is detected on the I pin. OUT_A OUT_A Rev. G | Page 39 of 50

AD5755-1 Data Sheet DEVICE FEATURES OUTPUT FAULT implications for the update speed when several channels are updated at once (see Table 3). The AD5755-1 is equipped with a FAULT pin, an active low open-drain output allowing several AD5755-1 devices to be RDEAGC IDSTAETAR INDPAUCT DAC REGISTER connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by any one of the M REGISTER following fault scenarios: • The voltage at IOUT_x attempts to rise above the compliance REGICSTER 09226-075 range due to an open-loop circuit or insufficient power Figure 78. Digital Offset and Gain Control supply voltage. The internal circuitry that develops the Each time data is written to the M or C register, the output is fault output avoids using a comparator with windowed not automatically updated. Instead, the next write to the DAC limits because this requires an actual output error before channel uses these M and C values to perform a new calibration the FAULT output becomes active. Instead, the signal is and automatically updates the channel. generated when the internal amplifier in the output stage has less than approximately 1 V of remaining drive capability. The output data from the calibration is routed to the DAC input Thus, the FAULT output activates slightly before the register. This is then loaded to the DAC as described in the Theory of Operation section. Both the gain register and the compliance limit is reached. • A short is detected on a voltage output pin. The short- offset register have 16 bits of resolution. The correct method to calibrate the gain/offset is to first calibrate out the gain and then circuit current is limited to 16 mA or 8 mA, which is calibrate the offset. programmable by the user. If using the AD5755-1 in unipolar supply mode, a short-circuit fault may be The value (in decimal) that is written to the DAC input register generated if the output voltage is below 50 mV. can be calculated by • An interface error is detected due to a PEC failure. See (M+1) the Packet Error Checking section. Code =D× +C−215 (1) DACRegister 216 • If the core temperature of the AD5755-1 exceeds approximately 150°C. where: D is the code loaded to the DAC channel’s input register. The V fault, I fault, PEC error, and over TEMP bits OUT_x OUT_x M is the code in the gain register (default code = 216 – 1). of the status register are used in conjunction with the FAULT C is the code in the offset register (default code = 215). output to inform the user which one of the fault conditions STATUS READBACK DURING A WRITE caused the FAULT output to be activated. The AD5755-1 has the ability to read back the status register VOLTAGE OUTPUT SHORT-CIRCUIT PROTECTION contents during every write sequence. This feature is enabled Under normal operation, the voltage output sinks/sources up via the STATREAD bit in the main control register. This allows to 12 mA and maintains specified operation. The maximum the user to continuously monitor the status register and act output current or short-circuit current is programmable by quickly in the case of a fault. the user and can be set to 16 mA or 8 mA. If a short circuit is When status readback during a write is enabled, the contents of detected, the FAULT goes low and the relevant V fault bit OUT_x the 16-bit status register (see Table 30) are output on the SDO in the status register is set. pin, as shown in Figure 6. DIGITAL OFFSET AND GAIN CONTROL The AD5755-1 powers up with this feature disabled. When this Each DAC channel has a gain (M) and offset (C) register, which is enabled, the normal readback feature is not available, except allow trimming out of the gain and offset errors of the entire for the status register. To read back any other register, clear the signal chain. Data from the DAC data register is operated on by STATREAD bit first before following the readback sequence. a digital multiplier and adder controlled by the contents of the STATREAD can be set high again after the register read. M and C registers. The calibrated DAC data is then stored in the If there are multiple units on the same SDO bus which have the DAC input register. STATREAD feature enabled, ensure that each unit is provided a Although Figure 78 indicates a multiplier and adder for each unique physical address (AD1 and AD0) to prevent contention channel, there is only one multiplier and one adder in the device, on the bus. and they are shared among all four channels. This has Rev. G | Page 40 of 50

Data Sheet AD5755-1 ASYNCHRONOUS CLEAR WATCHDOG TIMER CLEAR is an active high, edge-sensitive input that allows the When enabled, an on-chip watchdog timer generates an alert output to be cleared to a preprogrammed 16-bit code. This code signal if 0x195 has not been written to the software register is user programmable via a per channel 16-bit clear code register. within the programmed timeout period. This feature is useful to ensure that communication is not lost between the MCU and For a channel to clear, that channel must be enabled to be cleared the AD5755-1 and that these datapath lines are working properly via the CLR_EN bit in the channel’s DAC control register. If the (that is, SDIN, SCLK, and SYNC). If 0x195 is not received by channel is not enabled to be cleared, then the output remains in its current state independent of the CLEAR pin level. When the the software register within the timeout period, the ALERT pin CLEAR signal is returned low, the relevant outputs remain signals a fault condition. The ALERT signal is active high and can be connected directly to the CLEAR pin to enable a clear in cleared until a new value is programmed. the event that communication from the MCU is lost. PACKET ERROR CHECKING The watchdog timer is enabled, and the timeout period (5 ms, To verify that data has been received correctly in noisy environ- 10 ms, 100 ms, or 200 ms) is set in the main control register (see ments, the AD5755-1 offers the option of packet error checking Table 18 and Table 19). based on an 8-bit cyclic redundancy check (CRC-8). The device OUTPUT ALERT controlling the AD5755-1 generates an 8-bit frame check sequence using the polynomial The AD5755-1 is equipped with an ALERT pin. This is an active high CMOS output. The AD5755-1 also has an internal watchdog C(x) = x + x + x + 1 8 2 1 timer. When enabled, it monitors SPI communications. If 0x195 This is added to the end of the data-word, and 32 bits are sent to is not received by the software register within the timeout period, the AD5755-1 before taking SYNC high. If the packet error the ALERT pin goes active. checking enable bit is set high (Bit 12 in the software register), INTERNAL REFERENCE the user must supply a 32-bit frame that contains the 24 data bits and 8-bit CRC. If the check is valid, the data is written to The AD5755-1 contains an integrated +5 V voltage reference the selected register. If the error check fails, the FAULT pin goes with initial accuracy of ±5 mV maximum and a temperature low and the PEC error bit in the status register is set. After drift coefficient of ±10 ppm maximum. The reference voltage reading the status register, FAULT returns high (assuming there is buffered and externally available for use elsewhere within are no other faults), and the PEC error bit is cleared automati- the system. REFOUT must be connected to REFIN to use the cally. It is not recommended to tie both AD1 and AD0 low internal reference. because a short low on SDIN, that is, a command of 16 zeroes, EXTERNAL CURRENT SETTING RESISTOR may possibly lead to a zero-scale update for DAC A. The PEC Referring to Figure 74, R is an internal sense resistor as part can be used for both transmit and receive of data packets. SET of the voltage-to-current conversion circuitry. The stability of UPDATE ON SYNC HIGH the output current value over temperature is dependent on the SYNC stability of the value of R . As a method of improving the stability SET of the output current over temperature, an external 15 kΩ low SCLK drift resistor can be connected to the R pin of the AD5755-1 SET_x MSB LSB D23 D0 to be used instead of the internal resistor, R1. The external resistor SDIN 24-BIT DATA is selected via the DAC control register (see Table 20). 24-BIT DATA TRANSFER—NO ERROR CHECKING Table 1 outlines the performance specifications of the AD5755-1 with both the internal R resistor and an external, 15 kΩ R SET SET UPDATE ON SYNC HIGH resistor. Using an external RSET resistor allows for improved SYNC ONLY IF ERROR CHECK PASSED performance over the internal R resistor option. The external SET R resistor specification assumes an ideal resistor; the actual SET SCLK performance depends on the absolute value and temperature MSB LSB coefficient of the resistor used. This directly affects the gain error D31 D8 D7 D0 of the output, and thus the total unadjusted error. To arrive at SDIN 24-BIT DATA 8-BIT CRC the gain/TUE error of the output with a particular external R SET resistor, add the percentage absolute error of the R resistor SET FAULT 32-BIT DATA TRANSFER WITH ERRIOFF REA RCURHLOETC RPK ICNINH GGEOCKES F ALOILWS 09226-180 dniarle RctSlEyT troes tihsteo gr,a sinh/oTwUnE in e rTraobrl eo f1 t (heex AprDes5s7e5d5 i-n1 %wi FthS Rth)e. exter- Figure 79. PEC Timing Rev. G | Page 41 of 50

AD5755-1 Data Sheet HART CONNECTIVITY Table 32. Slew Rate Update Clock Options SR_CLOCK Update Clock Frequency (Hz)1 The AD5755-1 has four CHART pins, one corresponding to 0000 64 k each output channels. A HART signal can be coupled into these 0001 32 k pins. The HART signal appears on the corresponding current 0010 16 k output, if the output is enabled. Table 31 shows the recommended 0011 8 k input voltages for the HART signal at the CHART pin. If these 0100 4 k voltages are used, the current output must meet the HART 0101 2 k amplitude specifications. Figure 80 shows the recommended 0110 1 k circuit for attenuating and coupling in the HART signal. 0111 500 Table 31. CHART Input Voltage to HART Output Current 1000 250 CHART Input Current Output 1001 125 RSET Voltage (HART) 1010 64 Internal RSET 150 mV p-p 1 mA p-p 1011 32 External RSET 170 mV p-p 1 mA p-p 1100 16 C1 1101 8 CHARTx 1110 4 HAORTU TMPOUDTEM C2 09226-076 1 111 0.5 Figure 80. Coupling HART Signal 1 These clock frequencies are divided down from the 13 MHz internal oscillator. See Table 1, Figure 70, and Figure 71. A minimum capacitance of C1 + C2 is required to ensure that the 1.2 kHz and 2.2 kHz HART frequencies are not significantly Table 33. Slew Rate Step Size Options attenuated at the output. The recommended values are C1 = 22 nF, SR_STEP Step Size (LSBs) C2 = 47 nF. 000 1 Digitally controlling the slew rate of the output is necessary to 001 2 meet the analog rate of change requirements for HART. 010 4 011 16 If the HART feature is not required, leave the CHART pins open 100 32 circuit. 101 64 DIGITAL SLEW RATE CONTROL 110 128 The slew rate control feature of the AD5755-1 allows the user to 111 256 control the rate at which the output value changes. This feature The following equation describes the slew rate as a function of is available on both the current and voltage outputs. With the the step size, the update clock frequency, and the LSB size: slew rate control feature disabled, the output value changes at a SlewTime= rate limited by the output drive circuitry and the attached load. To reduce the slew rate, this can be achieved by enabling the OutputChange slew rate control feature. With the feature enabled via the SREN StepSize×UpdateClockFrequency ×LSBSize bit of the slew rate control register (see Table 26), the output, where: instead of slewing directly between two values, steps digitally at Slew Time is expressed in seconds. a rate defined by two parameters accessible via the slew rate Output Change is expressed in amps for I or volts for V . OUT_x OUT_x control register, as shown in Table 26. When the slew rate control feature is enabled, all output changes The parameters are SR_CLOCK and SR_STEP. SR_CLOCK occur at the programmed slew rate (see the DC-to-DC Converter defines the rate at which the digital slew is updated, for example, Settling Time section for additional information). For example, if the selected update rate is 8 kHz, the output updates every 125 µs. if the CLEAR pin is asserted, the output slews to the clear value In conjunction with this, SR_STEP defines by how much the at the programmed slew rate (assuming that the clear channel is output value changes at each update. Together, both parameters enabled to be cleared). If a number of channels are enabled for define the rate of change of the output value. Table 32 and Table 33 slew, care must be taken when asserting the CLEAR pin. If one outline the range of values for both the SR_CLOCK and of the channels is slewing when CLEAR is asserted, other chan- SR_STEP parameters. nels may change directly to their clear values not under slew rate control. The update clock frequency for any given value is the same for all output ranges. The step size, however, varies Rev. G | Page 42 of 50

Data Sheet AD5755-1 across output ranges for a given value of step size because the DC-to-DC Converter Output Voltage LSB size is different for each output range. When a channel current output is enabled, the converter regulates POWER DISSIPATION CONTROL the V supply to 7.4 V (±5%) or (I × R + Headroom), BOOST_x OUT LOAD whichever is greater (see Figure 54 for a plot of headroom The AD5755-1 contains integrated dynamic power control supplied vs. output current). In voltage output mode with the using a dc-to-dc boost converter circuit, allowing reductions in output disabled, the converter regulates the V supply to power consumption from standard designs when using the part BOOST_x +15 V (±5%). In current output mode with the output disabled, in current output mode. the converter regulates the V supply to 7.4 V (±5%). BOOST_x In standard current input module designs, the load resistor Within a channel, the V and I stages share a common values can range from typically 50 Ω to 750 Ω. Output module OUT_x OUT_x V supply so that the outputs of the I and V stages systems must source enough voltage to meet the compliance BOOST_x OUT_x OUT_x can be tied together. voltage requirement across the full range of load resistor values. For example, in a 4 mA to 20 mA loop when driving 20 mA, a DC-to-DC Converter Settling Time compliance voltage of >15 V is required. When driving 20 mA When in current output mode, the settling time for a step greater into a 50 Ω load, only 1 V compliance is required. than ~1 V (I × R ) is dominated by the settling time of the OUT LOAD The AD5755-1 circuitry senses the output voltage and regulates dc-to-dc converter. The exception to this is when the required this voltage to meet compliance requirements plus a small voltage at the IOUT_x pin plus the compliance voltage is below headroom voltage. The AD5755-1 is capable of driving up to 7.4 V (±5%). A typical plot of the output settling time can be 24 mA through a 1 kΩ load. found in Figure 50. This plot is for a 1 kΩ load. The settling time for smaller loads is faster. The settling time for current steps less DC-TO-DC CONVERTERS than 24 mA is also faster. The AD5755-1 contains four independent dc-to-dc converters. DC-to-DC Converter V Functionality MAX These are used to provide dynamic control of the V supply BOOST voltage for each channel (see Figure 74). Figure 81 shows the The maximum VBOOST_x voltage is set in the dc-to-dc control discrete components needed for the dc-to-dc circuitry, and the register (23 V, 24.5 V, 27 V, or 29.5 V; see Table 25). On reaching following sections describe component selection and operation this maximum voltage, the dc-to-dc converter is disabled, and of this circuitry. the VBOOST_x voltage is allowed to decay by ~0.4 V. After the V voltage has decayed by ~0.4 V, the dc-to-dc converter LDCDC DDCDC RFILTER BOOST_x AVCC VBOOST_X is reenabled, and the voltage ramps up again to V , if still ≥10CµIFN 10µH SWx C4.D7CµDFC 10Ω C0.F1IµLFTER 09226-077 require29d.6. ThVisM AoXperation is show0nm Ai nTO F 24igmuA rReAN 8G2E,. 2 4mMA AOXUTPUT Figure 81. DC-to-DC Circuit DC_DC BIT OUTPUT UNLOADED 29.5 Table 34. Recommended DC-to-DC Components 29.4 Symbol Component Value Manufacturer V) 29.3 E ( LDCDC XAL4040-103 10 µH Coilcraft® AG 29.2 T CDCDC GRM32ER71H475KA88L 4.7 µF Murata OL 29.1 V DDCDC PD3S160-7 0.55 VF Diodes, Inc. OST 29.0 DCDCx BIT = 1 DC-DCMaxV = 11 (29.5V) O It is recommended to place a 10 Ω, 100 nF low-pass RC filter VB 28.9 fSW = 410kHz TA = 25°C after CDCDC. This consumes a small amount of power but 28.8 reduces the amount of ripple on the VBOOST_x supply. 28.7 DCDCx BIT = 0 DC-to-DC Converter Operation 28.6 The on-board dc-to-dc converters use a constant frequency, 0 0.5 1.0 1.5 TIM2E. 0(ms) 2.5 3.0 3.5 4.0 09226-183 peak current mode control scheme to step up an AVCC input of Figure 82. Operation on Reaching VMAX 4.5 V to 5.5 V to drive the AD5755-1 output channel. These are As can be seen in Figure 82, the DC-DCx bit in the status register designed to operate in discontinuous conduction mode (DCM) asserts when the AD5755-1 is ramping to the V value but MAX with a duty cycle of <90% typical. Discontinuous conduction deasserts when the voltage is decaying to V − ~0.4 V. MAX mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. The dc-to-dc converters are nonsynchronous; that is, they require an external Schottky diode. Rev. G | Page 43 of 50

AD5755-1 Data Sheet DC-to-DC Converter On-Board Switch the channel output current can rise. The ripple voltage is caused by a combination of the capacitance and equivalent series The AD5755-1 contains a 0.425 Ω internal switch. The switch resistance (ESR) of the capacitor. For the AD5755-1, a ceramic current is monitored on a pulse by pulse basis and is limited to capacitor of 4.7 µF is recommended for typical applications. 0.8 A peak current. DC-to-DC Converter Switching Frequency and Phase Larger capacitors or paralleled capacitors improve the ripple at the expense of reduced slew rate. Larger capacitors also impact The AD5755-1 dc-to-dc converter switching frequency can be the AV supplies current requirements while slewing (see the CC selected from the dc-to-dc control register. The phasing of the AI Supply Requirements—Slewing section). This capacitance CC channels can also be adjusted so that the dc-to-dc converter can at the output of the dc-to-dc converter must be >3 µF under all clock on different edges (see Table 25). For typical applications, operating conditions. a 410 kHz frequency is recommended. At light loads (low output The input capacitor provides much of the dynamic current current and small load resistor), the dc-to-dc converter enters a required for the dc-to-dc converter and must be a low ESR pulse-skipping mode to minimize switching power dissipation. component. For the AD5755-1, a low ESR tantalum or ceramic DC-to-DC Converter Inductor Selection capacitor of 10 µF is recommended for typical applications. For typical 4 mA to 20 mA applications, a 10 µH inductor (such Ceramic capacitors must be chosen carefully because they can as the XAL4040-103 from Coilcraft), combined with a switching exhibit a large sensitivity to dc bias voltages and temperature. frequency of 410 kHz, allows up to 24 mA to be driven into a load X5R or X7R dielectrics are preferred because these capacitors resistance of up to 1 kΩ with an AVCC supply of 4.5 V to 5.5 V. It remain stable over wider operating voltage and temperature is important to ensure that the inductor is able to handle the peak ranges. Care must be taken if selecting a tantalum capacitor to current without saturating, especially at the maximum ambient ensure a low ESR value. temperature. If the inductor enters into saturation mode, it results AI SUPPLY REQUIREMENTS—STATIC in a decrease in efficiency. The inductance value also drops CC during saturation and may result in the dc-to-dc converter The dc-to-dc converter is designed to supply a VBOOST_x voltage of circuit not being able to supply the required output power. V = I × R + Headroom (2) BOOST OUT LOAD DC-to-DC Converter External Schottky Selection See Figure 54 for a plot of headroom supplied vs. output The AD5755-1 requires an external Schottky for correct voltage. This means that, for a fixed load and output voltage, operation. Ensure that the Schottky is rated to handle the the dc-to-dc converter output current can be calculated by maximum reverse breakdown expected in operation and that the following formula: the rectifier maximum junction temperature is not exceeded. PowerOut I ×V AI = = OUT BOOST (3) The diode average current is approximately equal to the ILOAD CC Efficiency×AV η ×AV current. Diodes with larger forward voltage drops result in a CC VBOOST CC decrease in efficiency. where: I is the output current from I in amps. DC-to-DC Converter Compensation Capacitors OUT OUT_x η is the efficiency at V as a fraction (see Figure 56 As the dc-to-dc converter operates in DCM, the uncompensated VBOOST BOOST_x and Figure 57). transfer function is essentially a single-pole transfer function. The pole frequency of the transfer function is determined by AICC SUPPLY REQUIREMENTS—SLEWING the output capacitance of the dc-to-dc converter, input and output The AI current requirement while slewing is greater than in CC voltage, and output load. The AD5755-1 uses an external capacitor static operation because the output power increases to charge in conjunction with an internal 150 kΩ resistor to compensate the output capacitance of the dc-to-dc converter. This transient the regulator loop. Alternatively, an external compensation resistor current can be quite large (see Figure 83), although the methods can be used in series with the compensation capacitor, by setting described in the Reducing AI Current Requirements section CC the DC-DC Comp bit in the dc-to-dc control register. In this case, can reduce the requirements on the AV supply. If not enough CC a ~50 kΩ resistor is recommended. A description of the advantages AI current can be provided, the AV voltage drops. Due to CC CC of this can be found in the AI Supply Requirements—Slewing CC this AV drop, the AI current required to slew increases CC CC section. For typical applications, a 10 nF dc-to-dc compensation further. This means that the voltage at AV drops further (see CC capacitor is recommended. Equation 3) and the V voltage, and thus the output voltage, BOOST_x DC-to-DC Converter Input and Output Capacitor Selection may never reach its intended value. Because this AVCC voltage is common to all channels, this may also affect other channels. The output capacitor affects ripple voltage of the dc-to-dc converter and indirectly limits the maximum slew rate at which Rev. G | Page 44 of 50

Data Sheet AD5755-1 0.8 0.8 32 00..67 2350 OLTAGE (V) 00..67 AIVOBIUCOTCOST INDUCTOR 0=m 1A0 µTHO ( 2Xf4SA5mWL0A 40=0 Ω R44 0AL1-0ON1k0GAH3DEz) 2248 OLTAGE (V) AI CURRENT (A)CC 000...345 INDUCTOR 0=m 1A0 µTHO ( 2Xf4SAmWL1AT 4k=0A Ω R44 =0A1L -0ON21k50GAH°3DECz) 112050 ENT (mA)/V VBOOST_x AI CURRENT (A)CC 000...345 TA = 25°C 112260 ENT (mA)/V VBOOST_x R R 0.2 R 0.2 8 R U U 0.1 AIVOBIUCOTCOST 5 COUT_x 0.1 4 COUT_x I I 00 0.5 1.0TIME (ms)1.5 2.0 2.50 09226-184 00 0.5 1.0TIME (ms)1.5 2.0 2.50 09226-186 Figure 83. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load Figure 85. AICC Current vs. Time for 24 mA Step Through 500 Ω Load with Internal Compensation Resistor with External 51 kΩ Compensation Resistor Reducing AI Current Requirements CC Using slew rate control can greatly reduce the AV supplies CC There are two main methods that can be used to reduce the current requirements, as shown in Figure 86. When using slew AICC current requirements. One method is to add an external rate control, pay attention to the fact that the output cannot slew compensation resistor, and the other is to use slew rate control. faster than the dc-to-dc converter. The dc-to-dc converter slews Both of these methods can be used in conjunction. slowest at higher currents through large (for example, 1 kΩ) A compensation resistor can be placed at the COMP pin loads. This slew rate is also dependent on the configuration of the DCDC_x in series with the 10 nF compensation capacitor. A 51 kΩ exter- dc-to-dc converter. Two examples of the dc-to-dc converter nal compensation resistor is recommended. This compensation output slew are shown in Figure 84 and Figure 85 (VBOOST increases the slew time of the current output but eases the AI corresponds to the output voltage of the dc-to-dc converter). CC transient current requirements. Figure 84 shows a plot of AI 0.8 32 CC 0mA TO 24mA RANGE V) current for a 24 mA step through a 1 kΩ load when using a 0.7 1fSkWΩ =L O41A0DkHz 28 GE ( 51 kΩ compensation resistor. This method eases the current INDUCTOR = 10µH (XAL4040-103) TA requirements through smaller loads even further, as shown in 0.6 TA = 25°C 24 VOL FiAI CURRENT (A)gCCu000000r......e345678 85IT01fNSmk.A WDΩ A=U = L2CT O45OT1°AO C02DkR4Hm =zA 1 0RµAHN (GXEAL4040-103) 112223264082 NT (mA)/V VOLTAGE (V)BOOST_x AI CURRENT (A)CC 00000.....1234500 VAIOBI1UCOTCOST 2 TIME3 (ms) 4 5 6121804026 I CURRENT (mA)/V OUT_xBOOST_x09226-187 E 0.2 8 RR Figure 86. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load 0.1 AIVOBIUCOTCOST 4 CUOUT_x with Slew Rate Control I 00 0.5 1.0TIME (ms)1.5 2.0 2.50 09226-185 Figure 84. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load with External 51 kΩ Compensation Resistor Rev. G | Page 45 of 50

AD5755-1 Data Sheet APPLICATIONS INFORMATION VOLTAGE AND CURRENT OUTPUT RANGES ON the full-scale error increases due to the dc crosstalk. For example, with the measured channel at 0xFFFF and three channels at THE SAME TERMINAL zero scale, the full-scale error is 0.025%. Similarly, if only one When using a channel of the AD5755-1, the current and voltage channel is enabled in current output mode with the internal R , SET output pins can be connected to two separate terminals or tied the full-scale error is 0.025% FSR + 0.075% FSR = 0.1% FSR. together and connected to a single terminal. There is no conflict PRECISION VOLTAGE REFERENCE SELECTION with tying the two output pins together because only the voltage output or the current output can be enabled at any one time. When To achieve the optimum performance from the AD5755-1 over its the current output is enabled, the voltage output is in tristate full operating temperature range, a precision voltage reference must mode, and when the voltage output is enabled, the current output be used. Give thought to the selection of a precision voltage refer- is in tristate mode. For this operation, the POC pin must be tied ence. The voltage applied to the reference inputs is used to provide low and the POC bit in the main control register set to 0, or, if a buffered reference for the DAC cores. Therefore, any error in the POC pin is tied high, the POC bit in the main control register the voltage reference is reflected in the outputs of the device. must be set to 1 before the current output is enabled. There are four possible sources of error to consider when choosing As shown in the Absolute Maximum Ratings section, the output a voltage reference for high accuracy applications: initial accuracy, tolerances are the same for both the voltage and current output temperature coefficient of the output voltage, long term drift, pins. The +V connections are buffered so that current and output voltage noise. SENSE_x leakage into these pins is negligible when in current output mode. Initial accuracy error on the output voltage of an external reference CURRENT OUTPUT MODE WITH INTERNAL R can lead to a full-scale error in the DAC. Therefore, to minimize SET these errors, a reference with low initial accuracy error specification When using the internal R resistor in current output mode, the SET is preferred. Choosing a reference with an output trim adjustment, output is significantly affected by how many other channels using such as the ADR425, allows a system designer to trim system the internal R are enabled and by the dc crosstalk from these SET errors out by setting the reference voltage to a voltage other than channels. The internal R specifications in Table 1 are for all SET the nominal. The trim adjustment can be used at any temperature channels enabled with the internal R selected and outputting SET to trim out any error. the same code. Long-term drift is a measure of how much the reference output For every channel enabled with the internal R , the offset error SET voltage drifts over time. A reference with a tight long-term drift decreases. For example, with one current output enabled using specification ensures that the overall solution remains relatively the internal R , the offset error is 0.075% FSR. This value SET stable over its entire lifetime. decreases proportionally as more current channels are enabled; the offset error is 0.056% FSR on each of two channels, 0.029% The temperature coefficient of a reference’s output voltage affects on each of three channels, and 0.01% on each of four channels. INL, DNL, and TUE. Choose a reference with a tight temperature coefficient specification to reduce the dependence of the DAC Similarly, the dc crosstalk when using the internal R is propor- SET output voltage to ambient temperature. tional to the number of current output channels enabled with the internal R . For example, with the measured channel at In high accuracy applications, which have a relatively low noise SET 0x8000 and one channel going from zero to full scale, the dc budget, reference output voltage noise must be considered. crosstalk is −0.011% FSR. With two channels going from zero to Choosing a reference with as low an output noise voltage as full scale, it is −0.019% FSR, and with all three other channels practical for the system resolution required is important. going from zero to full scale, it is −0.025% FSR. Precision voltage references such as the ADR435 (XFET design) produce low output noise in the 0.1 Hz to 10 Hz region. However, For the full-scale error measurement in Table 1, all channels are as the circuit bandwidth increases, filtering the output of the at 0xFFFF. This means that, as any channel goes to zero scale, reference may be required to minimize the output noise. Table 35. Recommended Precision References Initial Accuracy Long-Term Drift 0.1 Hz to 10 Hz Noise Part No. (mV Maximum) (ppm Typical) Temperature Drift (ppm/°C Maximum) (µV p-p Typical) ADR445 ±2 50 3 2.25 ADR02 ±3 50 3 10 ADR435 ±2 40 3 8 ADR395 ±5 50 9 8 AD586 ±2.5 15 10 4 Rev. G | Page 46 of 50

Data Sheet AD5755-1 DRIVING INDUCTIVE LOADS MICROPROCESSOR INTERFACING When driving inductive or poorly defined loads, a capacitor Microprocessor interfacing to the AD5755-1 is via a serial bus may be required between I and AGND to ensure stability. that uses a protocol compatible with microcontrollers and DSP OUT_x A 0.01 µF capacitor between I and AGND ensures stability processors. The communications channel is a 3-wire minimum OUT_x of a load of 50 mH. The capacitive component of the load may interface consisting of a clock signal, a data signal, and a latch cause slower settling, although this may be masked by the set- signal. The AD5755-1 requires a 24-bit data-word with data tling time of the AD5755-1. There is no maximum capacitance valid on the falling edge of SCLK. limit for the current output of the AD5755-1. The DAC output update is initiated on either the rising edge of TRANSIENT VOLTAGE PROTECTION LDAC or, if LDAC is held low, on the rising edge of SYNC. The contents of the registers can be read using the readback function. The AD5755-1 contains ESD protection diodes that prevent damage from normal handling. The industrial control AD5755-1-to-ADSP-BF527 Interface environment can, however, subject I/O circuits to much higher The AD5755-1 can be connected directly to the SPORT interface transients. To protect the AD5755-1 from excessively high of the ADSP-BF527, an Analog Devices, Inc., Blackfin® DSP. voltage transients, external power diodes and a surge current Figure 88 shows how the SPORT interface can be connected to limiting resistor (R ) are required, as shown in Figure 87. A P control the AD5755-1. typical value for R is 10 Ω. The two protection diodes and the P AD5755-1 resistor (R) must have appropriate power ratings. P SPORT_TFS SYNC (FROM DC-TO-DC RFILTER SPORT_TSCK SCLK CONVERTER) SPORT_DTO SDIN CDCDC 10Ω CFILTER 4.7µF 0.1µF ADV5B7OI5OOS5UT-T_1_xx D2RP ADSP-BF527 GPIO0 LDAC 09226-080 AGND AVSSD1 RLOAD 09226-079 LAYOUTF igGuUre I8D8. EADL5IN75E5-S1- to-ADSP-BF527 SPORT Interface Figure 87. Output Transient Voltage Protection Grounding Further protection can be provided using transient voltage In any circuit where accuracy is important, careful consideration suppressors (TVSs), also referred to as transorbs. These com- of the power supply and ground return layout helps to ensure ponents are available as unidirectional suppressors, which the rated performance. The printed circuit board on which the protect against positive high voltage transients, and as AD5755-1 is mounted must be designed so that the analog and bidirectional suppressors, which protect against both positive digital sections are separated and confined to certain areas of the and negative high voltage transients. Transient voltage board. If the AD5755-1 is in a system where multiple devices suppressors are avail-able in a wide range of standoff and require an AGND-to-DGND connection, the connection must be breakdown voltage ratings. The TVS must be sized with the made at one point only. The star ground point must be lowest breakdown voltage possible while not conducting in the established as close as possible to the device. functional range of the current output. The GNDSW and ground connection for the AV supply are x CC It is recommended that all field connected nodes be protected. referred to as PGND. PGND must be confined to certain areas The voltage output node can be protected with a similar circuit, of the board, and the PGND-to-AGND connection must be where D2 and the transorb are connected to AV . For the volt- made at one point only. SS age output node, the +VSENSE_x pin must also be protected with a Supply Decoupling large value series resistance to the transorb, such as 5 kΩ. In this The AD5755-1 must have ample supply bypassing of 10 µF way, the I and V pins can also be tied together and OUT_x OUT_x in parallel with 0.1 µF on each supply located as close to the share the same protection circuitry. package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor must have low effective series resistance (ESR) and low effective series inductance (ESL), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Rev. G | Page 47 of 50

AD5755-1 Data Sheet Traces GALVANICALLY ISOLATED INTERFACE The power supply lines of the AD5755-1 must use as large a In many process control applications, it is necessary to provide trace as possible to provide low impedance paths and reduce an isolation barrier between the controller and the unit being the effects of glitches on the power supply line. Shield fast switching controlled to protect and isolate the controlling circuitry from signals, such as clocks, with digital ground to prevent radiating any hazardous common-mode voltages that may occur. The noise to other parts of the board and never run them near the Analog Devices iCoupler® products can provide voltage isolation reference inputs. A ground line routed between the SDIN and in excess of 2.5 kV. The serial loading structure of the AD5755-1 SCLK lines helps reduce crosstalk between them (not required makes it ideal for isolated interfaces because the number of on a multilayer board that has a separate ground plane, but interface lines is kept to a minimum. Figure 89 shows a 4-channel separating the lines helps). It is essential to minimize noise on isolated interface to the AD5755-1 using an ADuM1400. For the REFIN line because it couples through to the DAC output. more information, visit www.analog.com. Avoid crossover of digital and analog signals. Traces on oppo- MICROCONTROLLER ADuM1400* site sides of the board must run at right angles to each other. SERIAL CLOOCUKT VIA ENCODE DECODE VOA TO SCLK This reduces the effects of feedthrough on the board. A microstrip technique is by far the best but not always possible SERIAL DAOTUAT VIB ENCODE DECODE VOB TO SDIN with a double-sided board. In this technique, the component SYNC OUT VIC ENCODE DECODE VOC TO SYNC side of the board is dedicated to ground plane, whereas signal DtraCc-etso a-DreC p Claocendv eonrt ethres solder side. *ADDITICOONNATLR POINL SO OUTMITTEVDID FOR CLAERNICTOY.DE DECODE VOD TO LDAC 09226-081 Figure 89. Isolated Interface To achieve high efficiency, good regulation, and stability, a well- designed printed circuit board layout is required. Follow these guidelines when designing printed circuit boards (see Figure 81): • Keep the low ESR input capacitor, C , close to AV and IN CC PGND. • Keep the high current path from C through the inductor, IN L , to SW and PGND as short as possible. DCDC X • Keep the high current path from C through L and the IN DCDC rectifier, D , to the output capacitor, C , as short as DCDC DCDC possible. • Keep high current traces as short and as wide as possible. The path from C through the inductor, L , to SW and IN DCDC X PGND must be able to handle a minimum of 1 A. • Place the compensation components as close as possible to COMP . DCDC_x • Avoid routing high impedance traces near any node connected to SW or near the inductor to prevent radiated x noise injection. Rev. G | Page 48 of 50

Data Sheet AD5755-1 INDUSTRIAL HART CAPABLE ANALOG OUTPUT the AD5700 HART modem output modulating the 4 mA to APPLICATION—SHARED V AND I PIN 20 mA analog current without affecting the dc level of the OUT_X OUT_X current. This circuit adheres to the HART physical layer Many industrial control applications have requirements for specifications as defined by the HART Communication accurately controlled current output signals, and the AD5755-1 Foundation. is ideal for such applications. Figure 90 shows the AD5755-1 in a circuit design for a HART-enabled output module, specifically For transient overvoltage protection, a 24 V transient voltage for use in an industrial control application in which both the suppressor (TVS) is placed on the IOUT/VOUT connection. For voltage output and current output are available—one at a time—on added protection, clamping diodes are connected from the one pin, thus reducing the number of screw connections required. IOUT_x/VOUT_x pin to the AVDD and AVSS power supply pins. A There is no conflict with tying the two output pins together 5 kΩ current limiting resistor is also placed in series with the because only the voltage output or the current output can be +VSENSE_x input. This is to limit the current to an acceptable level enabled at any one time. during a transient event. The recommended external band-pass filter for the AD5700 HART modem includes a 150 kΩ resistor, The design provides for a HART-enabled current output, with which limits current to a sufficiently low level to adhere to the HART capability provided by the AD5700/AD5700-1 HART intrinsic safety requirements. In this case, the input has higher modem, the industry’s lowest power and smallest footprint HART- transient voltage protection and, therefore, does not require compliant IC modem. For additional space-savings, the AD5700-1 additional protection circuitry, even in the most demanding offers a 0.5% precision internal oscillator. The HART_OUT of industrial environments. signal from the AD5700 is attenuated and ac-coupled into the CHARTx pin of the AD5755-1. Such a configuration results in +15V +5V 10µF 0.1µF 2.7V TO 5.5V DVDDAVDD AVCC SW (×4) VBOOST (×4) 10µF 0.1µF 10kΩ VOUT B, C, D RESET IOUT B, C, D ALERT D2 CHART B, C, D FAULT RP IOUT A 4mA TO 20mA CLEAR CURRENT LOOP D1 D3 MCU SSCYNLKC AD5755-1 5kΩ R50L0Ω SDIN +VSENSE_A SDO UART AVSS INTERFACE LDAC VOUTA DGND REFOUT REFIN CHART A AVSS GND 0.1µF 0.1µF 22CnF1 4C72nF VCC TXD HART_OUT RXD RTS CD AD5700/AD5700-1 REF 1µF 1.2MΩ 300pF 150kΩ ADC_IP GND 1.2MΩ 150pF 09226-089 Figure 90. AD5755-1 in HART Configuration Rev. G | Page 49 of 50

AD5755-1 Data Sheet OUTLINE DIMENSIONS 9.10 0.60 9.00 SQ 0.60 0.42 8.90 0.42 0.24 PIN 1 0.24 INDICATOR 49 64 1 48 PIN 1 INDICATOR 8.85 0.50 EXPOSED 7.25 8.75 SQ BSC PAD 7.10 SQ 8.65 6.95 0.50 0.40 3332 1716 0.30 0.25 MIN TOP VIEW BOTTOM VIEW 7.50 REF 1.00 12° MAX 0.80 MAX 0.65 NOM 0.85 0.05 MAX FOR PROPER CONNECTION OF 0.80 0.02 NOM THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND SEATING 0.30 FUNCTION DESCRIPTIONS PLANE 0.23 0.20 REF SECTION OF THIS DATA SHEET. PKG-001152 0.18COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 01-22-2015-D Figure 91. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters ORDERING GUIDE Model1 Resolution (Bits) Temperature Range Package Description Package Option AD5755-1ACPZ 16 −40°C to +105°C 64-lead LFCSP_VQ CP-64-3 AD5755-1ACPZ-REEL7 16 −40°C to +105°C 64-lead LFCSP_VQ CP-64-3 EVAL-AD5755-1SDZ Evaluation Board 1 Z = RoHS Compliant Part. ©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09226-0-4/17(G) Rev. G | Page 50 of 50

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5755-1SDZ AD5755-1ACPZ AD5755-1ACPZ-REEL7