Complete, Quad, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DACs Data Sheet AD5724R/AD5734R/AD5754R FEATURES GENERAL DESCRIPTION Complete, quad, 12-/14-/16-bit DACs The AD5724R/AD5734R/AD5754R are quad, 12-/14-/16-bit Operates from single/dual supplies serial input, voltage output, digital-to-analog converters (DACs). Software programmable output range They operate from single supply voltages of +4.5 V up to +16.5 V +5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V or dual supply voltages from ±4.5 V up to ±16.5 V. Nominal INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum full-scale output range is software selectable from +5 V, +10 V, Total unadjusted error (TUE): 0.1% FSR maximum +10.8 V, ±5 V, ±10 V, or ±10.8 V. Integrated output amplifiers, Settling time: 10 µs typical reference buffers, and proprietary power-up/power-down Integrated reference: ±5 ppm/°C maximum control circuitry are also provided. Integrated reference buffers The devices offer guaranteed monotonicity, integral Output control during power-up/brownout nonlinearity (INL) of ±16 LSB maximum, low noise, 10 µs Simultaneous updating via LDAC typical settling time, and an on-chip +2.5 V reference. Asynchronous CLR to zero scale/midscale DSP/microcontroller-compatible serial interface The AD5724R/AD5734R/AD5754R use a serial interface that 24-lead TSSOP operates at clock rates up to 30 MHz and are compatible with Operating temperature range: −40°C to +85°C DSP and microcontroller interface standards. Double buffering iCMOS® process technology allows the simultaneous updating of all DACs. The input coding is user-selectable twos complement or offset binary for a bipolar APPLICATIONS output (depending on the state of Pin BIN/2sCOMP) and straight Industrial automation binary for a unipolar output. The asynchronous clear function Closed-loop servo control, process control clears all DAC registers to a user-selectable zero-scale or mid- Automotive test and measurement scale output. The devices are available in a 24-lead TSSOP and Programmable logic controllers offer guaranteed specifications over the −40°C to +85°C industrial temperature range. Table 1. Pin Compatible Devices Device Number Description AD5724/AD5734/AD5754 AD5724R/AD5734R/AD5754R without internal reference. AD5722/AD5732/AD5752 Complete, dual, 12-/14-/16-bit, serial input, unipolar/bipolar, voltage output DACs. AD5722R/AD5732R/AD5752R AD5722/AD5732/AD5752 with internal reference. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5724R/AD5734R/AD5754R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Transfer Function ....................................................................... 22 Applications ....................................................................................... 1 Input Register .............................................................................. 26 General Description ......................................................................... 1 DAC Register .............................................................................. 27 Revision History ............................................................................... 2 Output Range Select Register ................................................... 27 Functional Block Diagram .............................................................. 3 Control Register ......................................................................... 28 Specifications ..................................................................................... 4 Power Control Register ............................................................. 29 AC Performance Characteristics ................................................ 6 Design Features ............................................................................... 30 Timing Characteristics ................................................................ 6 Analog Output Control ............................................................. 30 Timing Diagrams .......................................................................... 7 Power-Down Mode .................................................................... 30 Absolute Maximum Ratings ............................................................ 9 Overcurrent Protection ............................................................. 30 ESD Caution .................................................................................. 9 Thermal Shutdown .................................................................... 30 Pin Configuration and Function Descriptions ........................... 10 Internal Reference ...................................................................... 30 Typical Performance Characteristics ........................................... 11 Applications Information .............................................................. 31 Terminology .................................................................................... 18 +5 V/±5 V Operation ................................................................ 31 Theory of Operation ...................................................................... 20 Alternative Power-Up Sequence Support ............................... 31 Architecture ................................................................................. 20 Layout Guidelines....................................................................... 31 Power-Up Sequence ................................................................... 20 Galvanically Isolated Interface ................................................. 32 Serial Interface ............................................................................ 20 Microprocessor Interfacing ....................................................... 32 Load DAC (LDAC) ..................................................................... 22 Outline Dimensions ....................................................................... 33 Asynchronous Clear (CLR) ....................................................... 22 Ordering Guide .......................................................................... 33 Configuring the AD5724R/AD5734R/AD5754R .................. 22 REVISION HISTORY 2/2017—Rev. F to Rev. G 5/2010—Rev. A to Rev. B Added Power-Up Sequence Section ............................................. 20 Changes to Table 5 ............................................................................. 9 Changes to Table 8 and Table 9 ..................................................... 23 Changes to Table 6 .......................................................................... 10 Changes to Table 11 and Table 12 ................................................ 24 Changes to Table 14 and Table 15 ................................................ 25 3/2009—Rev. 0 to Rev. A Changes to Analog Output Control Section ............................... 30 Added AD5724R Model ............................................... Throughout Added Alternative Power-Up Sequence Support Section, Added 12-Bit Resolution .............................................. Throughout Figure 49, and Figure 50; Renumbered Sequentially ................. 31 Changes to Resolution and Integral Nonlinearity (INL) Parameters (Table 2).......................................................................... 4 2/2016—Rev. E to Rev. F Changes to Endnote 2 (Table 2) ...................................................... 5 Changes to Table 2 ............................................................................ 4 Added Endnote 4 (Table 4) .............................................................. 6 Added Figure 8 and Figure 11 ...................................................... 11 7/2011—Rev. D to Rev. E Added Figure 39 ............................................................................. 16 Changes to t, t, and t Parameters, Table 4 ................................. 6 Added Ideal Output Voltage to Input Code 7 8 10 Relationship—AD5724R Section ................................................. 25 5/2011—Rev. C to Rev. D Added Table 21 ............................................................................... 27 Changes to Configuring the AD5724R/AD5734R/ Changes to Ordering Guide .......................................................... 32 AD5754R Section ........................................................................... 22 1/2009—Revision 0: Initial Version 7/2010—Rev. B to Rev. C Changes to Table 28 ........................................................................ 29 Rev. G | Page 2 of 33

Data Sheet AD5724R/AD5734R/AD5754R FUNCTIONAL BLOCK DIAGRAM AVSS AVDD REFIN/REFOUT AD5724R/AD5734R/AD5754R DVCC 2.5V REFERENCE REFERENCE BUFFERS n n INPUT DAC SDIN INPUTSHIFT REGISTER A REGISTER A DACA VOUTA REGISTER SCLK AND SYNC CONTROL INPUT DAC n LOGIC REGISTER B REGISTER B DACB VOUTB SDO INPUT DAC n REGISTER C REGISTER C DACC VOUTC CLR BIN/2sCOMP n REGINISPTUETR D REGDISATCER D DACD VOUTD AAADDD555777235444RRR::: nnn === 111246---BBBIIITTT GND LDAC DAC_GND (2) SIG_GND (2) 06465-001 Figure 1. Rev. G | Page 3 of 33

AD5724R/AD5734R/AD5754R Data Sheet SPECIFICATIONS AV = 4.5 V1 to 16.5 V, AV = −4.5 V1 to −16.5 V or AV = 0 V, GND = 0 V, REFIN= +2.5 V external, DV = 2.7 V to 5.5 V, DD SS SS CC R = 2 kΩ, C = 200 pF, all specifications T to T , unless otherwise noted. LOAD LOAD MIN MAX Table 2. Parameter Min Typ Max Unit Test Conditions/Comments ACCURACY Outputs unloaded Resolution AD5754R 16 Bits AD5734R 14 Bits AD5724R 12 Bits Total Unadjusted Error (TUE) −0.1 +0.1 % FSR ±10 V range Integral Nonlinearity (INL)2 AD5754R −16 +16 LSB AD5734R −4 +4 LSB AD5724R −1 +1 LSB Differential Nonlinearity (DNL) −1 +1 LSB All models, guaranteed monotonic Bipolar Zero Error −6 +6 mV ±10 V range , T = 25°C, error at other temperatures A obtained using bipolar zero TC Bipolar Zero TC3 ±4 ppm FSR/°C Zero-Scale Error −6 +6 mV ±10 V range , T = 25°C, error at other temperatures A obtained using zero-scale TC Zero-Scale TC3 ±4 ppm FSR/°C Offset Error −6 +6 mV ±10 V range , T = 25°C, error at other temperatures A obtained using offset error TC Offset Error TC3 ±4 ppm FSR/°C Gain Error −0.025 +0.025 % FSR ±10 V range, T = 25°C, error at other temperatures A obtained using gain TC Gain Error3 −0.065 0 +10 V and +5 V ranges, T = 25°C, error at other A temperatures obtained using gain TC Gain Error3 0 +0.08 ±5 V range, T = 25°C, error at other temperatures A obtained using gain TC Gain TC3 ±4 ppm FSR/°C DC Crosstalk3 120 µV REFERENCE INPUT/OUTPUT Reference Input3 Reference Input Voltage 2.5 V ±1% for specified performance DC Input Impedance 1 5 MΩ Input Current −2 ±0.5 +2 µA Reference Range 2 3 V Reference Output Output Voltage 2.497 2.501 V T = 25°C A Reference TC3, 4 1.8 5 ppm/°C T = 0°C to 85°C A 2.2 10 ppm/°C T = −40°C to +85°C A Output Noise (0.1 Hz to 10 Hz)3 5 µV p-p Noise Spectral Density3 75 nV/√Hz At 10 kHz OUTPUT CHARACTERISTICS3 Output Voltage Range −10.8 +10.8 V AV /AV = ±11.7 V min, REFIN = +2.5 V DD SS −12 +12 V AV /AV = ±12.9 V min, REFIN = +3 V DD SS Headroom 0.5 0.9 V Output Voltage TC ±4 ppm FSR/°C Output Voltage Drift vs. Time ±12 ppm FSR/500 hr ±15 ppm FSR/1000 hr Short-Circuit Current 20 mA Load 2 kΩ For specified performance Capacitive Load Stability 4000 pF DC Output Impedance 0.5 Ω Rev. G | Page 4 of 33

Data Sheet AD5724R/AD5734R/AD5754R Parameter Min Typ Max Unit Test Conditions/Comments DIGITAL INPUTS3 DVCC = 2.7 V to 5.5 V, JEDEC compliant Input High Voltage, V 2 V IH Input Low Voltage, V 0.8 V IL Input Current ±1 µA Per pin Pin Capacitance 5 pF Per pin DIGITAL OUTPUTS (SDO)3 Output Low Voltage, V 0.4 V DV = 5 V ± 10%, sinking 200 µA OL CC Output High Voltage, V DV − 1 V DV = 5 V ± 10%, sourcing 200 µA OH CC CC Output Low Voltage, V 0.4 V DV = 2.7 V to 3.6 V, sinking 200 µA OL CC Output High Voltage, V DV − 0.5 V DV = 2.7 V to 3.6 V, sourcing 200 µA OH CC CC High Impedance Leakage Current ±1 µA High Impedance Output 5 pF Capacitance POWER REQUIREMENTS AV 4.5 16.5 V DD AV −4.5 −16.5 V SS DV 2.7 5.5 V CC Power Supply Sensitivity3 ∆V /∆ΑV −65 dB 200 mV sine wave superimposed on AV /AV at OUT DD SS DD 50 Hz/60 Hz AI 2.5 mA/channel Outputs unloaded DD 1.75 mA/channel AV = 0 V, outputs unloaded SS AI 2.2 mA/channel Outputs unloaded SS DI 0.5 3 µA V = DV , V = GND, 0.5 µA typical CC IH CC IL Power Dissipation 310 mW ±16.5 V operation, outputs unloaded 115 mW +16.5 V operation, outputs unloaded Power-Down Currents All DAC channels and internal reference powered-down AI 40 µA DD AI 40 µA SS DI 300 nA CC 1 For specified performance, headroom requirement is 0.9 V. 2 INL is the relative accuracy. It is measured from Code 512, Code 128, and Code 32 for the AD5754R, AD5734R, and AD5724R respectively. 3 Guaranteed by characterization; not production tested. 4 The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +85°C. Rev. G | Page 5 of 33

AD5724R/AD5734R/AD5754R Data Sheet AC PERFORMANCE CHARACTERISTICS AV = 4.5 V1 to 16.5 V, AV = −4.5 V1 to −16.5 V or 0 V, GND = 0 V, REFIN= 2.5 V external, DV = 2.7 V to 5.5 V, R = 2 kΩ, DD SS CC LOAD C = 200 pF, all specifications T to T , unless otherwise noted. LOAD MIN MAX Table 3. Parameter2 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 10 12 µs 20 V step to ±0.03 % FSR 7.5 8.5 µs 10 V step to ±0.03 % FSR 5 µs 512 LSB step settling (16-bit resolution) Slew Rate 3.5 V/µs Digital-to-Analog Glitch Energy 13 nV-sec Glitch Impulse Peak Amplitude 35 mV Digital Crosstalk 10 nV-sec DAC-to-DAC Crosstalk 10 nV-sec Digital Feedthrough 0.6 nV-sec Output Noise 0.1 Hz to 10 Hz Bandwidth 15 µV p-p 0x8000 DAC code 100 kHz Bandwidth 80 µV rms Output Noise Spectral Density 320 nV/√Hz Measured at 10 kHz, 0x8000 DAC code 1 For specified performance, headroom requirement is 0.9 V. 2 Guaranteed by design and characterization; not production tested. TIMING CHARACTERISTICS AV = 4.5 V to 16.5 V, AV = −4.5 V to −16.5 V or 0 V, GND = 0 V, REFIN = 2.5 V external, DV = 2.7 V to 5.5 V, R = 2 kΩ, DD SS CC LOAD C = 200 pF, all specifications are T to T , unless otherwise noted. LOAD MIN MAX Table 4. Parameter1, 2, 3 Limit at T , T Unit Description MIN MAX t 4 33 ns min SCLK cycle time 1 t 13 ns min SCLK high time 2 t 13 ns min SCLK low time 3 t 13 ns min SYNC falling edge to SCLK falling edge setup time 4 t 13 ns min SCLK falling edge to SYNC rising edge 5 t 100 ns min Minimum SYNC high time (write mode) 6 t 7 ns min Data setup time 7 t 2 ns min Data hold time 8 t 20 ns min LDAC falling edge to SYNC falling edge 9 t 130 ns min SYNC rising edge to LDAC falling edge 10 t 20 ns min LDAC pulse width low 11 t 10 µs typ DAC output settling time 12 t 20 ns min CLR pulse width low 13 t 2.5 µs max CLR pulse activation time 14 t 5 13 ns min SYNC rising edge to SCLK falling edge 15 t 5 40 ns max SCLK rising edge to SDO valid (C 6 = 15 pF) 16 L SDO t 200 ns min Minimum SYNC high time (readback/daisy-chain mode) 17 1 Guaranteed by characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 To accommodate t16, in readback and daisy-chain modes the SCLK cycle time must be increased to 90 ns. 5 Daisy-chain and readback mode. 6 CL SDO = capacitive load on SDO output. Rev. G | Page 6 of 33

Data Sheet AD5724R/AD5734R/AD5754R TIMING DIAGRAMS t1 SCLK 1 2 24 t6 t3 t2 t4 t5 SYNC t8 t7 SDIN DB23 DB0 t9 t10 t11 LDAC t12 VOUTx t12 VOUTx CLR t13 t14 VOUTx 06465-002 Figure 2. Serial Interface Timing Diagram t1 SCLK 24 48 t17 t3 t2 t5 t4 t15 SYNC t8 t7 SDIN DB23 DB0 DB23 DB0 INPUTWORDFORDACN INPUTWORDFORDACN-1 t16 SDO DB23 DB0 UNDEFINED INPUTWORDFORDACN t10 t11 LDAC 06465-003 Figure 3. Daisy-Chain Timing Diagram Rev. G | Page 7 of 33

AD5724R/AD5734R/AD5754R Data Sheet SCLK 1 24 1 24 t17 SYNC SDIN DB23 DB0 DB23 DB0 INPUTWORDSPECIFIES NOPCONDITION REGISTERTOBEREAD SDO DB23 DB0 DB23 DB0 UNDEFINED SELECCTLEODCRKEEGDISOTUETRDATA 06465-004 Figure 4. Readback Timing Diagram Rev. G | Page 8 of 33

Data Sheet AD5724R/AD5734R/AD5754R ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents of up to Stresses at or above those listed under Absolute Maximum A 100 mA do not cause SCR latch-up. Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these Table 5. or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Operation beyond AV to GND −0.3 V to +17 V DD the maximum operating conditions for extended periods may AV to GND +0.3 V to −17 V SS affect product reliability. DV to GND −0.3 V to +7 V CC Digital Inputs to GND −0.3 V to DV + 0.3 V or 7 V ESD CAUTION CC (whichever is less) Digital Outputs to GND −0.3 V to DV + 0.3 V or 7 V CC (whichever is less) REFIN/REFOUT to GND −0.3 V to +5 V VOUTx to GND AVSS to AVDD DAC_GND to GND −0.3 V to +0.3 V SIG_GND to GND −0.3 V to +0.3 V Operating Temperature Range, T A Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature, T max 150°C J 24-Lead TSSOP θ Thermal Impedance 42°C/W JA θ Thermal Impedance 9°C/W JC Power Dissipation (T max − T )/θ J A JA Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 3.5 kV Rev. G | Page 9 of 33

AD5724R/AD5734R/AD5754R Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVSS 1 24 AVDD NC 2 23 VOUTC VOUTA 3 AD5724R/ 22 VOUTD VOUTB 4 AD5734R/ 21 SIG_GND BIN/2sCOMP 5 AD5754R 20 SIG_GND TOP VIEW NC 6 (Not to Scale) 19 DAC_GND SYNC 7 18 DAC_GND SCLK 8 17 REFIN/REFOUT SDIN 9 16 SDO LDAC 10 15 GND CLR 11 14 DVCC NC 12 13 NC NOTES 1.NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2.ITFTHO IERSR ERMNEAHCLAOLNMYC MCEEODNN TDNHEEEDCR TTMEHADAL TT POTEH ARE F CEOOXRPPMPOAESNREC DPE LP.AANDE BE 06465-005 Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 AV Negative Analog Supply Pin. Voltage range is from –4.5 V to –16.5 V. This pin can be connected to 0 V if SS output ranges are unipolar. 2, 6, 12, 13 NC No Connect. Do not connect to these pins. 3 V A Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. OUT 4 V B Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. OUT 5 BIN/2sCOMP This pin determines the DAC coding for a bipolar output range. This pin should be hardwired to either DV CC or GND. When hardwired to DV , input coding is offset binary. When hardwired to GND, input coding is twos CC complement. (For unipolar output ranges, coding is always straight binary.) 7 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC. 8 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 10 LDAC Load DAC, Logic Input. This is used to update the DAC registers and, consequently, the analog output. When tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin should not be left unconnected. 11 CLR Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user selectable). 14 DV Digital Supply Pin. Voltage range is from 2.7 V to 5.5 V. CC 15 GND Ground Reference Pin. 16 SDO Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. 17 REFIN/REFOUT External Reference Voltage Input and Internal Reference Voltage Output. Reference input range is 2 V to 3 V. REFIN = 2.5 V for specified performance. REFOUT = 2.5 V ± 2 mV at 25°C. 18, 19 DAC_GND Ground reference pins for the four digital-to-analog converters. 20, 21 SIG_GND Ground reference pins for the four output amplifiers. 22 V D Analog Output Voltage of DAC D. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. OUT 23 V C Analog Output Voltage of DAC C. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. OUT 24 AV Positive Analog Supply Pin. Voltage range is from 4.5 V to 16.5 V. DD EPAD Exposed Paddle. The exposed paddle should be connected to the potential of the AV pin or, alternatively, it SS can be left electrically unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance. Rev. G | Page 10 of 33

Data Sheet AD5724R/AD5734R/AD5754R TYPICAL PERFORMANCE CHARACTERISTICS 6 0.6 AVDD/AVSS = +12V/0V, RANGE = +10V AVDD/AVSS = ±12V, RANGE = ±10V 4 AVDD/AVSS = ±6.5V, RANGE = ±5V 0.4 AVDD/AVSS = +6.5V/0V, RANGE = +5V 2 0.2 OR (LSB) 0 OR (LSB) 0 INL ERR –2 DNL ERR–0.2 –4 –0.4 –6 –0.6 AAVVDDDD//AAVVSSSS == +±1122VV,/ 0RVA, NRGAEN G=E ± 1=0 +V10V AVDD/AVSS = ±6.5V, RANGE = ±5V AVDD/AVSS = +6.5V/0V, RANGE = +5V –8 –0.8 0 10,000 20,000 30,C00O0DE40,000 50,000 60,000 06465-013 0 10,000 20,000 30,C00O0DE40,000 50,000 60,000 06465-016 Figure 6. AD5754R Integral Nonlinearity Error vs. Code Figure 9. AD5754R Differential Nonlinearity Error vs. Code 1.5 0.15 AVDD/AVSS = +12V/0V, RANGE = +10V AVDD/AVSS = ±12V, RANGE = ±10V 1.0 AAVVDDDD//AAVVSSSS == ±+66..55VV,/ 0RVA, NRGAEN G= E± 5=V +5V 0.10 0.5 0.05 OR (LSB) 0 OR (LSB) 0 INL ERR–0.5 DNL ERR–0.05 –1.0 –0.10 –1.5 –0.15 AAVVDDDD//AAVVSSSS == +±1122VV,/ 0RVA, NRGAEN G=E ± 1=0 +V10V AVDD/AVSS = ±6.5V, RANGE = ±5V AVDD/AVSS = +6.5V/0V, RANGE = +5V –2.0 –0.20 0 2000 4000 6000 C80O0D0E10,000 12,000 14,000 16,000 06465-014 0 2000 4000 6000 8C0O0D0E10,000 12,000 14,000 16,000 06465-017 Figure 7. AD5734R Integral Nonlinearity Error vs. Code Figure 10. AD5734R Differential Nonlinearity Error vs. Code 0.3 0.04 AVDD/AVSS = +12V/0V, RANGE = +10V AVDD/AVSS = +12V/0V, RANGE = +10V 0.2 AAVVDDDD//AAVVSSSS == ±±162.5VV, , RRAANNGGEE == ±±150VV 0.03 AAVVDDDD//AAVVSSSS == ±±162.5VV, , RRAANNGGEE == ±±150VV AVDD/AVSS = +6.5V/0V, RANGE = +5V AVDD/AVSS = +6.5V/0V, RANGE = +5V 0.02 0.1 INL ERROR (LSB)––00..210 DNL ERROR (LSB) ––000...0002110 –0.3 –0.03 –0.4 –0.04 –0.5 –0.05 0 500 1000 1500 C20O0D0E 2500 3000 3500 4000 06465-015 0 500 1000 1500 C20O0D0E 2500 3000 3500 4000 06465-018 Figure 8. AD5724R Integral Nonlinearity Error vs. Code Figure 11. AD5724R Differential Nonlinearity Error vs. Code Rev. G | Page 11 of 33

AD5724R/AD5734R/AD5754R Data Sheet 8 10 8 6 6 4 4 L ERROR (LSB) –202 MMMMMMMMAAIIAIAINNNNXXXX IIII NNNNIIIINNNNLLLLLLLL ±±++ ±±++151515150V0V0V0VVVVV NL ERROR (LSB) –202 BUBUININPPIIOOPPOOLLAALLAARRRR 55 VV55 VVMM MMIANIAXNX IN I –4 –4 –6 –6 –8 –10 –8–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06465-044 5.5 6.5 7.5 8.5 S9U.P5PL1Y0 .V5OL11T.A5GE12 (.V5)13.5 14.5 15.5 16.5 06465-050 Figure 15. AD5754R Integral Nonlinearity Error vs. Supply Voltage Figure 12. AD5754R Integral Nonlinearity Error vs. Temperature 0.1 1.0 BIPOLAR 10V MIN 0.8 UNIPOLAR 10V MIN 0 BIPOLAR 10V MAX UNIPOLAR 10V MAX 0.6 –0.1 MAX DNL ±10V R (LSB)–0.2 MMMMAIIANNXX DD DDNNNNLLLL ±± ±+15510VV0VV R (LSB) 00..42 L ERRO–0.3 MMMIAINNX DD DNNNLLL ++ +1550VVV L ERRO–0.20 N N D D –0.4 –0.4 –0.6 –0.5 –0.8 –0.6–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06465-045 –1.011.5 12.0 12.5 13.0SUP13P.L5Y V14O.L0TA1G4E.5 (V1)5.0 15.5 16.0 16.5 06465-033 Figure 16. AD5754R Differential Nonlinearity Error vs. Supply Voltage Figure 13. AD5754R Differential Nonlinearity Error vs. Temperature 1.0 10 BIPOLAR 5V MIN 0.8 UNIPOLAR 5V MIN 8 BIPOLAR 5V MAX UNIPOLAR 5V MAX 0.6 6 0.4 4 B) INL ERROR (LSB) ––4202 BUBUININPPIIOOPPOOLLAALLAARRRR 11 0011VV00 VVMM MMIANIAXNX DNL ERROR (LS––000...4220 –0.6 –6 –0.8 –8 –1.0 –1011.5 12.0 12.5 13.0SUP13P.L5Y V14O.L0TA1G4E.5 (V1)5.0 15.5 16.0 16.5 06465-032 5.5 6.5 7.5 8.5 S9U.P5PL1Y0 .V5OL11T.A5GE12 (.V5)13.5 14.5 15.5 16.5 06465-034 Figure 17. AD5754R Differential Nonlinearity Error vs. Supply Voltage Figure 14. AD5754R Integral Nonlinearity Error vs. Supply Voltage Rev. G | Page 12 of 33

Data Sheet AD5724R/AD5734R/AD5754R 0.8 0.02 0.6 0.01 V) 0.4 m 0 BIPOLAR 10V MIN OR ( 0.2 ±5V RANGE UNIPOLAR 10V MIN R E (%) –0.01 BUINPIOPOLALARR 1 01V0 VM MAAXX RO ER 0 ±10V RANGE U E–0.2 T Z R –0.02 LA–0.4 O P BI–0.6 –0.03 –0.8 –0.0411.5 12.0 12.5 13.0 13.S5UP1P4L.0Y (V1)4.5 15.0 15.5 16.0 16.5 06465-036 –1.0–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06465-047 Figure 18. AD5754R Total Unadjusted Error vs. Supply Voltage Figure 21. Bipolar Zero Error vs. Temperature 0.04 0.06 0.03 ±5V 0.04 0.02 0.01 BUINPIOPOLALAR R5 V5 VM MININ FSR)0.02 TUE (%) –0.010 BUINPIOPOLALAR R5 V5 VM MAAXX RROR (% 0 ±10V E –0.02 AIN –0.02 G –0.03 +10V –0.04 –0.04 –0.055.5 6.5 7.5 8.5 9.5 S1U0P.5PL1Y1 .(5V)12.5 13.5 14.5 15.5 16.5 06465-037 –0.06–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06465-048 Figure 19. AD5754R Total Unadjusted Error vs. Supply Voltage Figure 22. Gain Error vs. Temperature 4 1000 +10V 3 900 800 V) R (m 2 700 O-SCALE ERRO 01 ±10V DI (µA)CC345600000000 DVCC = 5V ER –1 Z 200 –2 100 ±5V DVCC = 3V 0 –3 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06465-046 –1000 1 2 VLOG3IC (V) 4 5 6 06465-043 Figure 20. Zero-Scale Error vs. Temperature Figure 23. Digital Current vs. Logic Input Voltage Rev. G | Page 13 of 33

AD5724R/AD5734R/AD5754R Data Sheet 0.010 12 ±5V RANGE, CODE = 0xFFFF ±10V RANGE, CODE = 0xFFFF +10V RANGE, CODE = 0xFFFF 0.005 +5V RANGE, CODE = 0xFFFF 10 TA (V) ±±51V0V R RAANNGGEE, ,C COODDEE = = 0 x00x0000000 V) EL 0 E ( 8 D G OLTAGE –0.005 T VOLTA 6 V U TPUT –0.010 OUTP 4 U O –0.015 2 –0.020 0 –25 –20 –15 –1O0UTP–U5T CU0RRENT5 (mA1)0 15 20 25 06465-040 –3 –1 1 3 TIME (5µs) 7 9 11 06465-024 Figure 24. Output Source and Sink Capability Figure 27. Full-Scale Settling, +10 V Range 15 6 10 5 GE (V) 5 E (V) 4 A G T A L T O 0 L V O 3 UT T V P U OUT –5 UTP 2 O –10 1 –15 –3 –1 1 3 TIME (5µs) 7 9 11 06465-022 0–3 –1 1 3 TIME (5µs) 7 9 11 06465-025 Figure 25. Full-Scale Settling Time, ±10 V Range Figure 28. Full-Scale Settling, +5 V Range 7 0.020 ±10V RANGE, 0x7FF±F TO 0x8000 ±10V RANGE, 0x8000± TO 0x7FFF 5 0.015 ±±55VV RRAANNGGEE,, 00xx78F00F0F ±± TTOO 00xx78F0F0F0 +10V RANGE, 0x7FFF TO 0x8000 GE (V) 3 E (V) 0.010 +++1550VVV RR RAAANNNGGGEEE,, ,00 0xxx788F000F00F0 TT TOOO 00 0xxx787F0FF0FF0F LTA 1 TAG 0.005 O L V O UT –1 T V 0 P U T P U T O –3 OU–0.005 –5 –0.010 –7 –3 –1 1 3 TIME (5µs) 7 9 11 06465-023 –0.015–1 0 1 TIME2 (µs) 3 4 5 06465-039 Figure 26. Full-Scale Settling, ±5 V Range Figure 29. Digital-to-Analog Glitch Energy Rev. G | Page 14 of 33

Data Sheet AD5724R/AD5734R/AD5754R 1 2 CH1 5RRµAAVNNGGEE == +±55VV RRAANNGGMEE ==5 s+±1100VV LINE 73.8V 06465-026 1 06465-028 CH1 5V CH2 500mV M 200µs CH1 2.9V Figure 30. Peak-to-Peak Noise, 0.1 Hz to 10 Hz Bandwidth Figure 33. REFOUT Turn-On Transient 1 1 RRAANNGGEE == +±55VV RRAANNGGEE == ±+1100VV 06465-027 06465-029 CH1 5µV M5s LINE 73.8V CH1 10µV M 5s LINE 1.2V Figure 31. Peak-to-Peak Noise, 100 kHz Bandwidth Figure 34. REFOUT Output Noise (100 kHz Bandwidth) 0.10 AVDD/AVSS = ±16.5V AVDD = +16.5V, AVSS = 0V 0.08 0.06 V) GE ( 0.04 A T L O 0.02 V T 1 U P 0 T U O –0.02 –0.04 –0.06–50 –30 –10 10TIME 3(µ0s) 50 70 90 06465-041 CH1 1µV M 5s LINE 1.2V 06465-030 Figure 32. Output Glitch on Power-Up Figure 35. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth) Rev. G | Page 15 of 33

AD5724R/AD5734R/AD5754R Data Sheet 3.0 1.0 AVDD/AVSS = +12V/0V, RANGE = +10V 2.9 0.5 AAAVVVDDDDDD///AAAVVVSSSSSS === ±±+1662..55VVV, ,/ R0RVAA,N NRGGAEEN =G= E±±1 5=0V V+5V 2.8 V) 2.7 0 E ( VOLTAG 22..56 E (LSB)–0.5 T U–1.0 U 2.4 T O F RE 2.3 –1.5 2.2 –2.0 2.1 2.0–0.18 –0.13 –0.08LOA–0D. 0C3URRE0.N0T2 (mA0).07 0.12 0.17 06465-031 –2.50 500 1000 1500 C20O0D0E 2500 3000 3500 4000 06465-021 Figure 36. REFOUT Voltage vs. Load Current Figure 39. AD5724R Total Unadjusted Error vs. Code 15 40 AVDD/AVSS = +12V/0V, RANGE = +10V 10 AAVVDDDD//AAVVSSSS == ±±162.5VV, , RRAANNGGEE == ±±150VV 35 AVDD/AVSS = +6.5V/0V, RANGE = +5V 5 30 0 B) –5 N (%)25 S O TUE (L ––1150 PULATI20 O15 P –20 10 –25 –30 5 –350 1000 2000 30C00ODE 4000 5000 6000 06465-019 0 1.0 1.5 2.T0EM2P.5ER3A.T0UR3.E5 CO4.E0FF4I.C5IEN5.T0 (p5p.m5/°6C.)0 6.5 7.0 06465-051 Figure 37. AD5754R Total Unadjusted Error vs. Code Figure 40. Reference Output TC (−40°C to +85°C) 4 40 AVDD/AVSS = +12V/0V, RANGE = +10V AVDD/AVSS = ±12V, RANGE = ±10V 2 AAVVDDDD//AAVVSSSS == ±+66..55VV,/ 0RVA, NRGAEN G= E± 5=V +5V 35 30 0 B) –2 N (%)25 S O TUE (L –4 PULATI20 O15 P –6 10 –8 5 –100 2000 4000 6000 C80O0D0E10,000 12,000 14,000 16,000 06465-020 0 1.0 1.5TEM2P.E0RAT2U.5RE CO3.E0FFIC3I.E5NT (p4p.0m/°C4).5 5.0 06465-052 Figure 38. AD5734R Total Unadjusted Error vs. Code Figure 41. Reference Output TC (0°C to 85°C) Rev. G | Page 16 of 33

Data Sheet AD5724R/AD5734R/AD5754R 2.50120 2.50120 20 DEVICES SHOWN 20 DEVICES SHOWN V)2.50100 V)2.50100 E ( E ( G G A2.50080 A2.50080 T T L L O O V V T 2.50060 T 2.50060 U U P P T T U U O2.50040 O2.50040 E E C C N N E2.50020 E2.50020 R R E E F F E E R2.50000 R2.50000 2.49980–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06465-054 2.499800 10 20 3T0EMPE4R0ATUR5E0 (°C) 60 70 80 06465-053 Figure 42. Reference Output Voltage vs. Temperature (−40°C to+ 85°C) Figure 43. Reference Output Voltage vs. Temperature (0°C to 85°C) Rev. G | Page 17 of 33

AD5724R/AD5734R/AD5754R Data Sheet TERMINOLOGY Gain Error Relative Accuracy or Integral Nonlinearity (INL) Gain error is a measure of the span error of the DAC. It is the For the DAC, relative accuracy, or integral nonlinearity, is a deviation in slope of the DAC transfer characteristic from ideal measure of the maximum deviation in LSBs from a straight line expressed in % FSR. A plot of gain error vs. temperature can be passing through the endpoints of the DAC transfer function. A seen in Figure 22. typical INL vs. code plot can be seen in Figure 6. Gain TC Differential Nonlinearity (DNL) Gain TC is a measure of the change in gain error with changes Differential nonlinearity is the difference between the measured in temperature. It is expressed in ppm FSR/°C. change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum Total Unadjusted Error (TUE) ensures monotonicity. This DAC is guaranteed monotonic by Total unadjusted error is a measure of the output error taking design. A typical DNL vs. code plot can be seen in Figure 9. all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, Monotonicity and time. TUE is expressed in % FSR. A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5724R/ Digital-to-Analog Glitch Impulse AD5734R/AD5754R are monotonic over their full operating Digital-to-analog glitch impulse is the impulse injected into the temperature range. analog output when the input code in the DAC register changes state, but the output voltage remains constant. It is normally Bipolar Zero Error specified as the area of the glitch in nV-sec and is measured Bipolar zero error is the deviation of the analog output from the when the digital input code is changed by 1 LSB at the major ideal half-scale output of 0 V when the DAC register is loaded carry transition (0x7FFF to 0x8000). See Figure 29. with 0x8000 (straight binary coding) or 0x0000 (twos complement coding). A plot of bipolar zero error vs. temperature can be seen Glitch Impulse Peak Amplitude in Figure 21. Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in Bipolar Zero TC the DAC register changes state. It is specified as the amplitude of Bipolar zero TC is a measure of the change in the bipolar zero the glitch in millivolts and is measured when the digital input error with a change in temperature. It is expressed in ppm FSR/°C. code is changed by 1 LSB at the major carry transition (0x7FFF Zero-Scale Error/Negative Full-Scale Error to 0x8000). See Figure 29. Zero-scale error is the error in the DAC output voltage when Digital Feedthrough 0x0000 (straight binary coding) or 0x8000 (twos complement Digital feedthrough is a measure of the impulse injected into coding) is loaded to the DAC register. Ideally, the output voltage the analog output of the DAC from the digital inputs of the should be negative full-scale − 1 LSB. A plot of zero-scale error DAC but is measured when the DAC output is not updated. It is vs. temperature can be seen in Figure 20. specified in nV-sec and measured with a full-scale code change Zero-Scale TC on the data bus. Zero-scale TC is a measure of the change in zero-scale error with a Power Supply Sensitivity change in temperature. It is expressed in ppm FSR/°C. Power supply sensitivity indicates how the output of the DAC is Output Voltage Settling Time affected by changes in the power supply voltage. It is measured Output voltage settling time is the amount of time it takes for by superimposing a 50 Hz/60 Hz, 200 mV p-p sine wave on the the output to settle to a specified level for a full-scale input supply voltages and measuring the proportion of the sine wave change. A plot of full-scale settling time can be seen in Figure 25. that transfers to the outputs. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage output DAC is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/µs. Rev. G | Page 18 of 33

Data Sheet AD5724R/AD5734R/AD5754R DC Crosstalk Voltage Reference TC DC crosstalk is the dc change in the output level of one DAC in Voltage reference TC is a measure of the change in the reference response to a change in the output of another DAC. It is measured output voltage with a change in temperature. The reference TC with a full-scale output change on one DAC while monitoring is calculated using the box method, which defines the TC as the another DAC. It is expressed in LSBs. maximum change in the reference output over a given tempera- ture range expressed in ppm/°C as follows; Digital Crosstalk Digital crosstalk is a measure of the impulse injected into the  V −V  analog output of one DAC from the digital inputs of another TC= REFmax REFmin ×106 DAC but is measured when the DAC output is not updated. VREFnom×TempRange It is specified in nV-sec and measured with a full-scale code where: change on the data bus. V is the maximum reference output measured over the REFmax DAC-to-DAC Crosstalk total temperature range. DAC-to-DAC crosstalk is the glitch impulse transferred to the VREFmin is the minimum reference output measured over the total output of one DAC due to a digital code change and subsequent temperature range. output change of another DAC. This includes both digital and VREFnom is the nominal reference output voltage, 2.5 V. analog crosstalk. It is measured by loading one of the DACs TempRange is the specified temperature range, either 0°C to with a full-scale code change (all 0s to all 1s and vice versa) 85°C or −40°C to +85°C. with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-sec. Rev. G | Page 19 of 33

AD5724R/AD5734R/AD5754R Data Sheet THEORY OF OPERATION The AD5724R/AD5734R/AD5754R are quad, 12-/14-/16-bit, The resistor string structure is shown in Figure 45. It is a string serial input, unipolar/bipolar, voltage output DACs. They operate of resistors, each of value R. The code loaded to the DAC register from single supply voltages of +4.5 V to +16.5 V or dual supply determines the node on the string where the voltage is to be voltages of ±4.5 V to ±16.5 V. In addition, the devices have tapped off and fed into the output amplifier. The voltage is tapped software-selectable output ranges of +5 V, +10 V, +10.8 V, ±5 V, off by closing one of the switches connecting the string to the ±10 V, and ±10.8 V. Data is written to the AD5724R/AD5734R/ amplifier. Because it is a string of resistors, it is guaranteed AD5754R in a 24-bit word format via a 3-wire serial interface. monotonic. The devices also offer an SDO pin to facilitate daisy chaining or Output Amplifiers readback. The output amplifiers are capable of generating both unipolar The AD5724R/AD5734R/AD5754R incorporate a power-on and bipolar output voltages. They are capable of driving a load reset circuit to ensure that the DAC registers power up loaded of 2 kΩ in parallel with 4000 pF to GND. The source and sink with 0x0000. When powered on, the outputs are clamped to 0 V capabilities of the output amplifiers can be seen in Figure 24. via a low impedance path. The devices also feature on-chip The slew rate is 3.5 V/µs with a full-scale settling time of 10 µs. reference and reference buffers. Reference Buffers ARCHITECTURE The AD5724R/AD5734R/AD5754R can operate with either an The DAC architecture consists of a string DAC followed by an external or internal reference. The reference input has an input output amplifier. Figure 44 shows a block diagram of the DAC range of 2 V to 3 V with 2.5 V for specified performance. This architecture. The reference input is buffered before being applied input voltage is then buffered before it is applied to the DAC cores. to the DAC. POWER-UP SEQUENCE REFIN Because the DAC output voltage is controlled by the voltage monitor and control block (see Figure 48), it is important to REF (+) power the DV pin before applying any voltage to the AV CC DD DAC REGISTER RSETSRISINTOGR VOUTx and AVSS pins; otherwise, the G1 and G2 transmission gates are at REF (–) CONFIGURABLE an undefined state. The ideal power-up sequence is in the OUTPUT AMPLIFIER following order: GND, SIG_GND, DAC_GND, DVCC, AVDD, RANGEG NCDOONUTTRPOULT 06465-006 AAVVSDSD, aanndd tAhVenSS tihs en dotig iimtapl oinrtpauntts,. pTrhoev irdeeladt itvhea to rthdeeyr oarf ep poowwereirnegd up after DV . CC Figure 44. DAC Architecture Block Diagram SERIAL INTERFACE REFIN The AD5724R/AD5734R/AD5754R are controlled over a R versatile 3-wire serial interface that operates at clock rates up to 30 MHz. It is compatible with SPI, QSPI™, MICROWIRE, and DSP standards. R Input Shift Register R TO OUTPUT The input shift register is 24 bits wide. Data is loaded into the AMPLIFIER device MSB first as a 24-bit word under the control of a serial clock input, SCLK. The input register consists of a read/write bit, three register select bits, three DAC address bits, and 16 data bits. The timing diagram for this operation is shown in Figure 2. R R 06465-007 Figure 45. Resistor String Structure Rev. G | Page 20 of 33

Data Sheet AD5724R/AD5734R/AD5754R Standalone Operation Daisy-Chain Operation The serial interface works with both a continuous and a For systems that contain several devices, the SDO pin can be noncontinuous serial clock. A continuous SCLK source can used to daisy-chain several devices together. Daisy-chain mode only be used if SYNC is held low for the correct number of can be useful in system diagnostics and in reducing the number clock cycles. In gated clock mode, a burst clock containing the of serial interface lines. The first falling edge of SYNC starts the exact number of clock cycles must be used, and SYNC must be write cycle. SCLK is continuously applied to the input shift taken high after the final clock to latch the data. The first falling register when SYNC is low. If more than 24 clock pulses are edge of SYNC starts the write cycle. Exactly 24 falling clock applied, the data ripples out of the shift register and appears on edges must be applied to SCLK before SYNC is brought high the SDO line. This data is clocked out on the rising edge of again. If SYNC is brought high before the 24th falling SCLK SCLK and is valid on the falling edge. By connecting the SDO of the first device to the SDIN input of the next device in the edge, the data written is invalid. If more than 24 falling SCLK chain, a multidevice interface is constructed. Each device in the edges are applied before SYNC is brought high, the input data is system requires 24 clock pulses. Therefore, the total number of also invalid. The input register addressed is updated on the clock cycles must equal 24 × N, where N is the total number of rising edge of SYNC. For another serial transfer to take place, AD5724R/AD5734R/AD5754R devices in the chain. When the SYNC must be brought low again. After the end of the serial serial transfer to all devices is complete, SYNC is taken high. data transfer, data is automatically transferred from the input This latches the input data in each device in the daisy chain and shift register to the addressed register. prevents any further data from being clocked into the input shift When the data has been transferred into the chosen register of register. The serial clock can be a continuous or gated clock. the addressed DAC, all DAC registers and outputs can be A continuous SCLK source can only be used if SYNC is held updated by taking LDAC low while SYNC is high. low for the correct number of clock cycles. In gated clock mode, AD5724R/ a burst clock containing the exact number of clock cycles must 68HC11* AD5734R/ AD5754R* be used, and SYNC must be taken high after the final clock to MOSI SDIN latch the data. SCK SCLK Readback Operation PC7 SYNC Readback mode is invoked by setting the R/W bit to 1 in the PC6 LDAC MISO SDO write operation to the serial input shift register. (If the SDO output is disabled via the SDO disable bit in the control register, it is automatically enabled for the duration of the read operation, SDIN after which it is disabled again.) With R/W set to 1, Bit A2 to Bit AD5724R/ AD5734R/ A0 in association with Bit REG2 to Bit REG0 select the register AD5754R* to be read. The remaining data bits in the write sequence are don’t SCLK care bits. During the next SPI write, the data appearing on the SYNC SDO output contains the data from the previously addressed LDAC register. For a read of a single register, the NOP command can SDO be used in clocking out the data from the selected register on SDO. The readback diagram in Figure 4 shows the readback sequence. For example, to read back the DAC register of SDIN AD5724R/ Channel A, implement the following sequence: AD5734R/ AD5754R* 1. Write 0x800000 to the AD5724R/AD5734R/AD5754R SCLK input register. This configures the device for read mode SYNC with the DAC register of Channel A selected. Note that all LDAC the data bits, DB15 to DB0, are don’t care bits. SDO 2. Follow this with a second write, a NOP condition, 0x180000. *ADDITIONAL PINS OMITTED FOR CLARITY. 06465-008 Donu rthineg S tDhOis wlinriet.e , the data from the register is clocked out Figure 46. Daisy Chaining the AD5724R/AD5734R/AD5754R Rev. G | Page 21 of 33

AD5724R/AD5734R/AD5754R Data Sheet LOAD DAC (LDAC) CONFIGURING THE AD5724R/AD5734R/AD5754R After data has been transferred into the input register of the When the power supplies are applied to the AD5724R/AD5734R/ DACs, there are two ways to update the DAC registers and DAC AD5754R, the power-on reset circuit ensures that all registers outputs. Depending on the status of both SYNC and LDAC, one default to 0. This places all channels and the internal reference in of two update modes is selected: individual DAC updating or power-down mode. Bring the DVCC high before any of the simultaneous updating of all DACs. interface lines are powered. If this is not done, the first write to the device may be ignored. The first communication to the OUTPUT AMPLIFIER AD5724R/AD5734R/AD5754R should be to set the required VREFIN 12-/1D4-A/1C6-BIT VOUTx output range on all channels (the default range is the 5 V unipolar range) by writing to the output range select register. The user should then write to the power-control register to power- DAC LDAC REGISTER on the required channels and the internal reference, if required. If an external reference source is being used, the internal reference must remain in power-down mode. To program an INPUT REGISTER output value on a channel, that channel must first be powered up; any writes to a channel while it is in power-down mode are ignored. The AD5724R/AD5734R/AD5754R operate with a SSSYCDNLICKN INTLEORGFIACCE SDO 06465-009 wapipdleie pdo two etrh es udpepvilcye rsa pnrgoev.i dIte i as dimeqpuoartet ahneta tdhraoto tmhe t op osuwpepro srut pthpley Figure 47. Simplified Diagram of Input Loading Circuitry for One DAC chosen output ranges. Individual DAC Updating TRANSFER FUNCTION In this mode, LDAC is held low while data is clocked into the Table 8 to Table 16 show the relationships of the ideal input code input shift register. The addressed DAC output is updated on to output voltage for the AD5754R, AD5734R, and AD5724R for the rising edge of SYNC. all output voltage ranges. For unipolar output ranges, the data Simultaneous Updating of All DACs coding is straight binary. For bipolar output ranges, the data In this mode, LDAC is held high while data is clocked into the coding is user selectable via the BIN/2sCOMP pin and can be input shift register. All DAC outputs are asynchronously updated either offset binary or twos complement. by taking LDAC low after SYNC has been taken high. The For a unipolar output range, the output voltage expression is update now occurs on the falling edge of LDAC. given by ASYNCHRONOUS CLEAR (CLR)  D  CLR is an active low clear that allows the outputs to be cleared VOUT =VREFIN×Gain2N  to either zero-scale code or midscale code. The clear code value For a bipolar output range, the output voltage expression is given by is user selectable via the CLR select bit of the control register  D  Gain×V (see the Control Register section). It is necessary to keep CLR VOUT =VREFIN×Gain2N− 2 REFIN low for a minimum amount of time to complete the operation (see Figure 2). When the CLR signal is returned high, the output where: remains at the cleared value until a new value is programmed. D is the decimal equivalent of the code loaded to the DAC. The outputs cannot be updated with a new value while the CLR N is the bit resolution of the DAC. pin is low. A clear operation can also be performed via the clear VREFIN is the reference voltage applied at the REFIN pin. command in the control register. Gain is an internal gain the value of which depends on the output range selected by the user as shown in Table 7. Table 7. Internal Gain Values Output Range (V) Gain Value +5 2 +10 4 +10.8 4.32 ±5 4 ±10 8 ±10.8 8.64 Rev. G | Page 22 of 33

Data Sheet AD5724R/AD5734R/AD5754R Ideal Output Voltage to Input Code Relationship—AD5754R Table 8. Bipolar Output, Offset Binary Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 1111 1111 1111 1111 +2 × REFIN × (32,767/32,768) +4 × REFIN × (32,767/32,768) +4.32 × REFIN × (32,767/32,768) 1111 1111 1111 1110 +2 × REFIN × (32,766/32,768) +4 × REFIN × (32,766/32,768) +4.32 × REFIN × (32,766/32,768) … … … … … … … 1000 0000 0000 0001 +2 × REFIN × (1/32,768) +4 × REFIN × (1/32,768) +4.32 × REFIN × (1/32,768) 1000 0000 0000 0000 0 V 0 V 0 V 0111 1111 1111 1111 −2 × REFIN × (1/32,768) −4 × REFIN × (1/32,768) −4.32 × REFIN × (32,766/32,768) … … … … … … … 0000 0000 0000 0001 −2 × REFIN × (32,767/32,768) −4 × REFIN × (32,767/32,768) −4.32 × REFIN × (32,767/32,768) 0000 0000 0000 0000 −2 × REFIN × (32,768/32,768) −4 × REFIN × (32,768/32,768) −4.32 × REFIN × (32,768/32,768) Table 9. Bipolar Output, Twos Complement Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 0111 1111 1111 1111 +2 × REFIN × (32,767/32,768) +4 × REFIN × (32,767/32,768) +4.32 × REFIN × (32,767/32,768) 0111 1111 1111 1110 +2 × REFIN × (32,766/32,768) +4 × REFIN × (32,766/32,768) +4.32 × REFIN × (32,766/32,768) … … … … … … … 0000 0000 0000 0001 +2 × REFIN × (1/32,768) +4 × REFIN × (1/32,768) +4.32 × REFIN × (1/32,768) 0000 0000 0000 0000 0 V 0 V 0 V 1111 1111 1111 1111 −2 × REFIN × (1/32,768) −4 × REFIN × (1/32,768) −4.32 × REFIN × (1/32,768) … … … … … … … 1000 0000 0000 0001 −2 × REFIN × (32,767/32,768) −4 × REFIN × (32,767/32,768) −4.32 × REFIN × (32,767/32,768) 1000 0000 0000 0000 −2 × REFIN × (32,768/32,768) −4 × REFIN × (32,768/32,768) −4.32 × REFIN × (32,768/32,768) Table 10. Unipolar Output, Straight Binary Coding Digital Input Analog Output MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range 1111 1111 1111 1111 +2 × REFIN × (65,535/65,536) +4 × REFIN × (65,535/65,536) +4.32 × REFIN × (65,535/65,536) 1111 1111 1111 1110 +2 × REFIN × (65,534/65,536) +4 × REFIN × (65,534/65,536) +4.32 × REFIN × (65,534/65,536) … … … … … … … 1000 0000 0000 0001 +2 × REFIN × (32,769/65,536) +4 × REFIN × (32,769/65,536) +4.32 × REFIN × (32,769/65,536) 1000 0000 0000 0000 +2 × REFIN × (32,768/65,536) +4 × REFIN × (32,768/65,536) +4.32 × REFIN × (32,768/65,536) 0111 1111 1111 1111 +2 × REFIN × (32,767/65,536) +4 × REFIN × (32,767/65,536) +4.32 × REFIN × (32,767/65,536) … … … … … … … 0000 0000 0000 0001 +2 × REFIN × (1/65,536) +4 × REFIN × (1/65,536) +4.32 × REFIN × (1/65,536) 0000 0000 0000 0000 0 V 0 V 0 V Rev. G | Page 23 of 33

AD5724R/AD5734R/AD5754R Data Sheet Ideal Output Voltage to Input Code Relationship—AD5734R Table 11. Bipolar Output, Offset Binary Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 11 1111 1111 1111 +2 × REFIN × (8191/8192) +4 × REFIN × (8191/8192) +4.32× REFIN × (8191/8192) 11 1111 1111 1110 +2 × REFIN × (8190/8192) +4 × REFIN × (8190/8192) +4.32 × REFIN × (8190/8192) … … … … … … … 10 0000 0000 0001 +2 × REFIN × (1/8192) +4 × REFIN × (1/8192) +4.32 × REFIN × (1/8192) 10 0000 0000 0000 0 V 0 V 0 V 01 1111 1111 1111 −2 × REFIN × (1/8192) −4 × REFIN × (1/8192) −4.32 × REFIN × (1/8192) … … … … … … … 00 0000 0000 0001 −2 × REFIN × (8191/8192) −4 × REFIN × (8191/8192) −4.32 × REFIN × (8191/8192) 00 0000 0000 0000 −2 × REFIN × (8192/8192) −4 × REFIN × (8192/8192) −4.32 × REFIN × (8192/8192) Table 12. Bipolar Output, Twos Complement Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 01 1111 1111 1111 +2 × REFIN × (8191/8192) +4 × REFIN × (8191/8192) +4.32 × REFIN × (8191/8192) 01 1111 1111 1110 +2 × REFIN × (8190/8192) +4 × REFIN × (8190/8192) +4.32 × REFIN × (8190/8192) … … … … … … … 00 0000 0000 0001 +2 × REFIN × (1/8192) +4 × REFIN × (1/8192) +4.32 × REFIN × (1/8192) 00 0000 0000 0000 0 V 0 V 0 V 11 1111 1111 1111 −2 × REFIN × (1/8192) −4 × REFIN × (1/8192) −4.32 × REFIN × (1/8192) … … … … … … … 10 0000 0000 0001 −2 × REFIN × (8191/8192) −4 × REFIN × (8191/8192) −4.32 × REFIN × (8191/8192) 10 0000 0000 0000 −2 × REFIN × (8192/8192) −4 × REFIN × (8192/8192) −4.32 × REFIN × (8192/8192) Table 13. Unipolar Output, Straight Binary Coding Digital Input Analog Output MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range 11 1111 1111 1111 +2 × REFIN × (16,383/16,384) +4 × REFIN × (16,383/16,384) +4.32 × REFIN × (16,383/16,384) 11 1111 1111 1110 +2 × REFIN × (16,382/16,384) +4 × REFIN × (16,382/16,384) +4.32 × REFIN × (16,382/16,384) … … … … … … … 10 0000 0000 0001 +2 × REFIN × (8193/16,384) +4 × REFIN × (8193/16,384) +4.32 × REFIN × (8193/16,384) 10 0000 0000 0000 +2 × REFIN × (8192/16,384) +4 × REFIN × (8192/16,384) +4.32 × REFIN × (8192/16,384) 01 1111 1111 1111 +2 × REFIN × (8191/16,384) +4 × REFIN × (8191/16,384) +4.32 × REFIN × (8191/16,384) … … … … … … … 00 0000 0000 0001 +2 × REFIN × (1/16,384) +4 × REFIN × (1/16,384) +4.32 × REFIN × (1/16,384) 00 0000 0000 0000 0 V 0 V 0 V Rev. G | Page 24 of 33

Data Sheet AD5724R/AD5734R/AD5754R Ideal Output Voltage to Input Code Relationship—AD5724R Table 14. Bipolar Output, Offset Binary Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 1111 1111 1111 +2 × REFIN × (2047/2048) +4 × REFIN × (2047/2048) +4.32 × REFIN × (2047/2048) 1111 1111 1110 +2 × REFIN × (2046/2048) +4 × REFIN × (2046/2048) +4.32 × REFIN × (2046/2048) … … … … … … 1000 0000 0001 +2 × REFIN × (1/2048) +4 × REFIN × (1/2048) +4.32 × REFIN × (1/2048) 1000 0000 0000 0 V 0 V 0 V 0111 1111 1111 −2 × REFIN × (1/2048) −4 × REFIN × (1/2048) −4.32 × REFIN × (1/2048) … … … … … … 0000 0000 0001 −2 × REFIN × (2047/2048) −4 × REFIN × (2047/2048) −4.32 × REFIN × (2047/2048) 0000 0000 0000 −2 × REFIN × (2048/2048) −4 × REFIN × (2048/2048) −4.32 × REFIN × (2048/2048) Table 15. Bipolar Output, Twos Complement Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 0111 1111 1111 +2 × REFIN × (2047/2048) +4 × REFIN × (2047/2048) +4.32 × REFIN × (2047/2048) 0111 1111 1110 +2 × REFIN × (2046/2048) +4 × REFIN × (2046/2048) +4.32 × REFIN × (2046/2048) … … … … … … 0000 0000 0001 +2 × REFIN × (1/2048) +4 × REFIN × (1/2048) +4.32 × REFIN × (1/2048) 0000 0000 0000 0 V 0 V 0 V 1111 1111 1111 −2 × REFIN × (1/2048) −4 × REFIN × (1/2048) −4.32 × REFIN × (1/2048) … … … … … … 1000 0000 0001 −2 × REFIN × (2047/2048) −4 × REFIN × (2047/2048) −4.32 × REFIN × (2047/2048) 1000 0000 0000 −2 × REFIN × (2048/2048) −4 × REFIN × (2048/2048) −4.32 × REFIN × (2048/2048) Table 16. Unipolar Output, Straight Binary Coding Digital Input Analog Output MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range 1111 1111 1111 +2 × REFIN × (4095/4096) +4 × REFIN × (4095/4096) +4.32 × REFIN × (4095/4096) 1111 1111 1110 +2 × REFIN × (4094/4096) +4 × REFIN × (4094/4096) +4.32 × REFIN × (4094/4096) … … … … … … 1000 0000 0001 +2 × REFIN × (2049/4096) +4 × REFIN × (2049/4096) +4.32 × REFIN × (2049/4096) 1000 0000 0000 +2 × REFIN × (2048/4096) +4 × REFIN × (2048/4096) +4.32 × REFIN × (2048/4096) 0111 1111 1111 +2 × REFIN × (2047/4096) +4 × REFIN × (2047/4096) +4.32 × REFIN × (2047/4096) … … … … … … 0000 0000 0001 +2 × REFIN × (1/4096) +4 × REFIN × (1/4096) +4.32 × REFIN × (1/4096) 0000 0000 0000 0 V 0 V 0 V Rev. G | Page 25 of 33

AD5724R/AD5734R/AD5754R Data Sheet INPUT REGISTER The input register is 24 bits wide and consists of a read/write bit (R/W), a reserved bit (zero) which must always be set to 0, three register select bits (REG1, REG2, REG3), three DAC address bits (A2, A1, A0), and 16 data bits (data). The register data is clocked in MSB first on the SDIN pin. Table 17 shows the register format, while Table 18 describes the function of each bit in the register. All registers are read/ write registers. Table 17. AD5754R Input Register Format MSB LSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB0 R/W Zero REG2 REG1 REG0 A2 A1 A0 Data Table 18. Input Register Bit Functions Data Description R/W Indicates a read from or a write to the addressed register REG2, REG1, REG0 Used in association with the address bits to determine if a write operation is to the DAC register, output range select register, power control register, or control register REG2 REG1 REG0 Function 0 0 0 DAC register 0 0 1 Output range select register 0 1 0 Power control register 0 1 1 Control register A2, A1, A0 These bits are used to decode the DAC channels A2 A1 A0 Channel Address 0 0 0 DAC A 0 0 1 DAC B 0 1 0 DAC C 0 1 1 DAC D 1 0 0 All four DACs DB15 to DB0 Data bits Rev. G | Page 26 of 33

Data Sheet AD5724R/AD5734R/AD5754R DAC REGISTER The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel which the data transfer is to take place (see Table 18). The data bits are in positions DB15 to DB0 for the AD5754R (see Table 19), DB15 to DB2 for the AD5734R (see Table 20), and DB15 to DB4 for the AD5724R (see Table 21). Table 19. Programming the AD5754R DAC Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB0 0 0 0 0 0 DAC address 16-bit DAC data Table 20. Programming the AD5734R DAC Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB2 DB1 DB0 0 0 0 0 0 DAC address 14-bit DAC data X X Table 21. Programming the AD5724R DAC Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 DAC address 12-bit DAC data X X X X OUTPUT RANGE SELECT REGISTER The output range select register is addressed by setting the three REG bits to 001. The DAC address bits select the DAC channel, while the range bits (R2, R1, R0) select the required output range (see Table 22 and Table 23). Table 22. Programming the Required Output Range MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB3 DB2 DB1 DB0 1/0 0 0 0 1 DAC address Don’t care R2 R1 R0 Table 23. Output Range Options R2 R1 R0 Output Range (V) 0 0 0 +5 0 0 1 +10 0 1 0 +10.8 0 1 1 ±5 1 0 0 ±10 1 0 1 ±10.8 Rev. G | Page 27 of 33

AD5724R/AD5734R/AD5754R Data Sheet CONTROL REGISTER The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the control function selected. The control register options are shown in Table 24 and Table 25. Table 24. Programming the Control Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 0 0 0 NOP, data = don’t care 0 0 0 1 1 0 0 1 Don’t care TSD enable Clamp enable CLR select SDO disable 0 0 0 1 1 1 0 0 Clear, data = don’t care 0 0 0 1 1 1 0 1 Load, data = don’t care Table 25. Control Register Functions Option Description NOP No operation instruction used in readback operations. Clear Addressing this function sets the DAC registers to the clear code and updates the outputs. Load Addressing this function updates the DAC registers and, consequently, the DAC outputs. SDO disable Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). CLR select See Table 26 for a description of the CLR select operation. Clamp enable Set by the user to enable the current limit clamp (default). The channel does not power down on detection of overcurrent; the current is clamped at 20 mA. Cleared by the user to disable the current-limit clamp. The channel powers down on detection of overcurrent. TSD enable Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown feature (default). Table 26. CLR Select Options Output CLR Value CLR Select Setting Unipolar Output Range Bipolar Output Range 0 0 V 0 V 1 Midscale Negative full scale Rev. G | Page 28 of 33

Data Sheet AD5724R/AD5734R/AD5754R POWER CONTROL REGISTER The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power and thermal status of the AD5724R/AD5734R/AD5754R. The power control register options are shown in Table 27 and Table 28. Table 27. Programming the Power Control Register MSB LSB DB15 to R/W Zero REG2 REG1 REG0 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 0 0 0 X OCD OCC OCB OCA 0 TSD PUREF PUD PUC PUB PUA Table 28. Power Control Register Functions Option Description PU DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down A mode (default). After setting this bit to power DAC A, a power-up time of 10 µs is required. During this power-up time the DAC register should not be loaded to the DAC output (see the Load DAC (LDAC) section). If the clamp enable bit of the control register is cleared, DAC A powers down automatically on detection of an overcurrent, and PU is cleared to reflect this. A PU DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down B mode (default). After setting this bit to power DAC B, a power-up time of 10 µs is required. During this power-up time the DAC register should not be loaded to the DAC output (see the Load DAC(LDAC) section). If the clamp enable bit of the control register is cleared, DAC B powers down automatically on detection of an overcurrent, and PU is cleared to reflect this. B PU DAC C power-up. When set, this bit places DAC C in normal operating mode. When cleared, this bit places DAC C in power-down C mode (default). After setting this bit to power DAC C, a power-up time of 10 µs is required. During this power-up time the DAC register should not be loaded to the DAC output (see the Load DAC(LDAC) section). If the clamp enable bit of the control register is cleared, DAC C powers down automatically on detection of an overcurrent, and PU is cleared to reflect this. C PU DAC D power-up. When set, this bit places DAC D in normal operating mode. When cleared, this bit places DAC D in power-down D mode (default). After setting this bit to power DAC D, a power-up time of 10 µs is required. During this power-up time the DAC register should not be loaded to the DAC output (see the Load DAC(LDAC) section). If the clamp enable bit of the control register is cleared, DAC D powers down automatically on detection of an overcurrent, and PU is cleared to reflect this. D PU Reference power-up. When set, this bit places the internal reference in normal operating mode. When cleared, this bit places the REF internal reference in power-down mode (default). TSD Thermal shutdown alert. Read-only bit. In the event of an overtemperature situation, the four DACs are powered down and this bit is set. OC DAC A overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC A, this bit is set. A OC DAC B overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC B, this bit is set. B OC DAC C overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC C, this bit is set. C OC DAC D overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC D, this bit is set. D Rev. G | Page 29 of 33

AD5724R/AD5734R/AD5754R Data Sheet DESIGN FEATURES Constant Current Clamp (Clamp Enable = 1) ANALOG OUTPUT CONTROL If a short circuit occurs in this configuration, the current is In many industrial process control applications, it is vital that clamped at 20 mA. This event is signaled to the user by the the output voltage be controlled during power-up. When the setting of the appropriate overcurrent (OC ) bit in the power supply voltages change during power-up, the V x pins are X OUT control register. Upon removal of the short-circuit fault, the clamped to 0 V via a low impedance path (approximately 4 kΩ). OC bit is cleared. To prevent the output amplifiers from being shorted to 0 V X during this time, Transmission Gate G1 is also opened (see Automatic Channel Power-Down (Clamp Enable = 0) Figure 48). These conditions are maintained until the analog If a short circuit occurs in this configuration, the shorted power supplies have stabilized and a valid word is written to a channel powers down and its output is clamped to ground via DAC register. At this time, G2 opens and G1 closes. a resistance of approximately 4 kΩ. Also, at this time, the output of the amplifier is disconnected from the output pin. The short- VOLTAGE MONITOR circuit event is signaled to the user via the overcurrent bits (OC ), AND X CONTROL while the power-up bits (PU ) indicate which channels have X G1 powered down. After the fault is rectified, the channels can be VOUTA powered up again by setting the PUX bits. G2 THERMAL SHUTDOWN Figure 48. Analog Output Control Circuitry 06465-010 Tshhuet dAoDw5n7 f2e4aRtu/AreD th5a7t3 a4uRt/oAmDa5ti7c5a4llRy sinhcuotsr pdoorwatne tah teh deermvicael if the core temperature exceeds approximately 150°C. The thermal POWER-DOWN MODE shutdown feature is disabled by default and can be enabled Each DAC channel of the AD5724R/AD5734R/AD5754R can via the TSD enable bit of the control register. In the event of a be powered down individually. By default, all channels are in thermal shutdown, the TSD bit of the power control register is set. power-down mode. The power status is controlled by the power INTERNAL REFERENCE control register (see Table 27 and Table 28 for details). When a channel is in power-down mode its output pin is clamped to The on-chip voltage reference is powered down by default. If ground through a resistance of approximately 4 kΩ and the an external voltage reference source is to be used, the internal output of the amplifier is disconnected from the output pin. reference must remain powered down at all times. If the internal reference is to be used as the reference source, it must be powered OVERCURRENT PROTECTION up via the PU bit of the power control register. The internal REF Each DAC channel of the AD5724R/AD5734R/AD5754R reference voltage is accessible at the REFIN/REFOUT pin for use incorporates individual overcurrent protection. The user has as a reference source for other devices within the system. If the two options for the configuration of the overcurrent protection: internal reference is to be used external to the AD5724R/ constant current clamp or automatic channel power-down. The AD5734R/AD5754R, it must first be buffered. configuration of the overcurrent protection is selected via the clamp enable bit in the control register. Rev. G | Page 30 of 33

Data Sheet AD5724R/AD5734R/AD5754R APPLICATIONS INFORMATION +5 V/±5 V OPERATION VIN + Q2 AVDD C1 R3 When operating from a single +5 V supply or a dual ±5 V supply, LOAD SWITCH R2 an output range of +5 V or ±5 V is not achievable because sufficient SECTION headroom for the output amplifier is not available. In this situation, DVCC are rfeedreuncceed prreofedruecnecse avno lotuagtpeu cta rna nbge eu osef d+;4 f oVr oinrs ±ta4n Vce, ,t hife a 1 2 V V o f CSOENCTTRIOONL R1 Q1 06465-143 headroom is more than enough for full operation. A standard value Figure 49. Load Switch Control Circuit voltage reference of 2.048 V can be used to produce output ranges Figure 50 shows an example of the analog supplies powering up of +4.096 V and ±4.096 V. Refer to the Typical Performance before the digital supply. The circuit delays the AV power up DD Characteristics plots for performance data at a range of voltage until after DV , as shown by the AV (delayed) line. CC DD reference values. ALTERNATIVE POWER-UP SEQUENCE SUPPORT There may be cases where it is not possible to use the AVDD recommended power-up sequence, and in those instances an external circuit shown in Figure 49 is recommended to be used. AVSS The circuit shown in Figure 49 ensures that the digital block is t(sec) powered up first, prior to the analog block, by using a load switch circuit. This circuit targets applications for which either AVDD or AVSS or both supplies power up before DVCC. DVCC Consider the following design rules when choosing the component values for the AV delay circuit. DD • RD1V en sius riens a tnh aotp tehne sQta1t eg.a Rte1 taol ssoo uprrceev evnotlsta fgaels ies tzuerrno ownh oenf AVDD(DELAYED) 06465-144 CC Figure 50. Delayed Power Supplies Sequence Example Q1. However, if DV is permanently connected to the CC source, R1 can be removed to conserve power. LAYOUT GUIDELINES • Select Q1 (N-channel MOSFET) with a VGS threshold that In any circuit where accuracy is important, careful consideration of is much lower than the minimum operating DVCC and a the power supply and ground return layout helps to ensure the VDS rating much lower than the maximum operating AVDD. rated performance. Design the printed circuit board on which • C1, R2, and R3 are the main components that dictates the the AD5724R/AD5734R/AD5754R are mounted so that the delay from DVCC enable to AVDD. Adjust the values analog and digital sections are separated and confined to certain according for the desired delay. Choose R2 and R3 values areas of the board. If the AD5724R/AD5734R/AD5754R are in a that ensure Q2 turn on. system which multiple devices require an AGND-to-DGND connection, make the connection at one point only. Establish  V  t (sec)=−C (R ||R )×ln1− GS  the star ground point as close as possible to the device. DELAY 1 3 2  VEQ  Bypass the AD5724R/AD5734R/AD5754R with an ample supply  R  of a 10 µF capacitor in parallel with a 0.1 µF capacitor on each where VEQ =AVDDR3 +3R2 suupp apglyai lnoscta ttheed daes vcilcoes.e T thoe t h1e0 pµaFc ckaapgaec aitso prso sasrieb lteh,e i dtaenaltlayl urmigh t • Q2 (P-channel MOSFET) acts as a switch that allows the bead type. The 0.1 µF capacitor should have low effective series flow of current from V to AV ; therefore, choosing a resistance (ESR) and low effective series inductance (ESI) such IN DD MOSFET with very low R is necessary to minimize as the common ceramic types, which provide a low impedance DSON losses during operation. Other parameters such as path to ground at high frequencies to handle transient currents maximum V rating, maximum drain to source current due to internal logic switching. DS rating, VGS threshold voltage, and maximum gate to source The power supply lines of the AD5724R/AD5734R/AD5754R voltage rating must also be taken into consideration when should use as large a trace as possible to provide low impedance choosing Q2. paths and reduce the effects of glitches on the power supply line. Shield fast switching signals such as clocks with digital ground to avoid radiating noise to other parts of the board and never run them near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce crosstalk Rev. G | Page 31 of 33

AD5724R/AD5734R/AD5754R Data Sheet between them (this is not required on a multilayer board that MICROPROCESSOR INTERFACING has a separate ground plane, but separating the lines does help). Microprocessor interfacing to the AD5724R/AD5734R/AD5754R It is essential to minimize noise on the REFIN line because it is via a serial bus that uses a standard protocol compatible with couples through to the DAC output. microcontrollers and DSP processors. The communications Avoid crossover of digital and analog signals. Traces on channel is a 3-wire (minimum) interface consisting of a clock opposite sides of the board should run at right angles to each signal, a data signal, and a synchronization signal. The AD5724R/ other. This reduces the effects of feed through the board. A AD5734R/AD5754R require a 24-bit data-word with data valid microstrip technique is by far the best but not always possible on the falling edge of SCLK. with a double-sided board. In this technique, the component For all interfaces, the DAC output update can be initiated side of the board is dedicated to the ground plane, while signal automatically when all the data is clocked in, or it can be traces are placed on the solder side. performed under the control of LDAC. The contents of the GALVANICALLY ISOLATED INTERFACE registers can be read using the readback function. In many process control applications, it is necessary to provide AD5724R/AD5734R/AD5754R to Blackfin® DSP Interface an isolation barrier between the controller and the unit being Figure 52 shows how the AD5724R/AD5734R/AD5754R can be controlled to protect and isolate the controlling circuitry from interfaced to a Blackfin DSP from Analog Devices. The Blackfin any hazardous common-mode voltages that may occur. The has an integrated SPI port that can be connected directly to the iCoupler® family of products from Analog Devices, Inc., provides SPI pins of the AD5724R/AD5734R/AD5754R and the program- voltage isolation in excess of 2.5 kV. The serial loading structure mable input/output pins that can be used to set the state of a of the AD5724R/AD5734R/AD5754R makes them ideal for digital input such as the LDAC pin. isolated interfaces because the number of interface lines is kept to a minimum. Figure 51 shows a 4-channel isolated interface to the SPISELx SYNC AD5724R/AD5734R/AD5754R using an ADuM1400. For SCK SCLK further information, visit www.analog.com/icouplers. MOSI SDIN AD5724R/ MICROCONTROLLER ADuM1400* ADSP-BF531 AD5734R/ SERIAL CLOCK OUT VIA ENCODE DECODE VOA TO SCLK AD5754R SERIAL DATA OUT VIB ENCODE DECODE VOB TO SDIN PF10 LDAC SYNC OUT VIC ENCODE DECODE VOC TO SYNC 06465-012 CONTROL OUT VID ENCODE DECODE VOD TO LDAC Figure 52. AD5724R/AD5734R/AD5754R-to-Blackfin Interface *ADDITIONAL PINS OMITTED FOR CLARITY. 06465-011 Figure 51. Isolated Interface Rev. G | Page 32 of 33

Data Sheet AD5724R/AD5734R/AD5754R OUTLINE DIMENSIONS 7.90 5.02 7.80 5.00 7.70 4.95 24 13 4.50 EXPOSED 3.25 4.40 PAD 3.20 4.30 (Pins Up) 3.15 6.40 BSC 1 12 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF 1.05 THE EXPOSED PAD, REFER TO 1.20 MAX 1.00 THE PIN CONFIGURATION AND 8° FUNCTION DESCRIPTIONS 0.80 0° SECTION OF THIS DATA SHEET. 0.15 0.20 0.05 SPLEAATNIENG B0.S6C5 00..3109 0.09 00..7650 0.10 COPLANARITY 0.45 COMPLIANTTO JEDEC STANDARDS MO-153-ADT 061708-A Figure 53. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] (RE-24) Dimensions shown in millimeters ORDERING GUIDE Model1 Resolution Temperature Range INL Package Description Package Option AD5724RBREZ 12 −40°C to +85°C ±1 LSB 24-Lead TSSOP_EP RE-24 AD5724RBREZ-REEL7 12 −40°C to +85°C ±1 LSB 24-Lead TSSOP_EP RE-24 AD5734RBREZ 14 −40°C to +85°C ±4 LSB 24-Lead TSSOP_EP RE-24 AD5734RBREZ-REEL7 14 −40°C to +85°C ±4 LSB 24-Lead TSSOP_EP RE-24 AD5754RBREZ 16 −40°C to +85°C ±16 LSB 24-Lead TSSOP_EP RE-24 AD5754RBREZ-REEL7 16 −40°C to +85°C ±16 LSB 24-Lead TSSOP_EP RE-24 EVAL-AD5754REBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2009–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06465-0-2/17(G) Rev. G | Page 33 of 33

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5754REBZ AD5724RBREZ-REEL7 AD5734RBREZ-REEL7 AD5724RBREZ AD5754RBREZ-REEL7 AD5734RBREZ AD5754RBREZ