Industrial Current/Voltage Output Driver with Programmable Ranges Data Sheet AD5750/AD5750-1/AD5750-2 FEATURES The output current range is programmable across five current ranges: 4 mA to 20 mA, 0 mA to 20 mA, 0 mA to 24 mA, ±20 mA, Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, 0 mA and ±24 mA. An overrange of 2% is available on the unipolar to 24 mA, ±20 mA, and ±24 mA current ranges. ±0.03% full-scale range (FSR) total unadjusted error (TUE) ±5 ppm/°C typical output drift Voltage output is provided from a separate pin that can be Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, and ±10 V configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V with 20% overrange output ranges. An overrange of 20% is available on the voltage ±0.02% FSR TUE ranges. ±3 ppm/°C typical output drift Analog outputs are short-circuit and open-circuit protected and Flexible serial digital interface can drive capacitive loads of 1 µF and inductive loads of 0.1 H. On-chip output fault detection Packet error checking (PEC) The devices are specified to operate with a power supply range Asynchronous CLEAR function from ±12 V to ±24 V. Output loop compliance is 0 V to AVDD − Flexible power-up condition to 0 V or tristate 2.75 V. Power supply range The flexible serial interface is SPI and MICROWIRE compatible AVDD: +12 V (± 10%) to +24 V (± 10%) and can operate in 3-wire mode to minimize the digital isolation AVSS: −12 V (± 10%) to −24 V (± 10%) required in isolated applications. The interface also features an Output loop compliance to AVDD − 2.75 V optional PEC feature using CRC-8 error checking, useful in Temperature range: −40°C to +105°C industrial environments where data communication corruption 32-lead, 5 mm × 5 mm LFCSP package can occur. APPLICATIONS The devices also include a power-on-reset function, ensuring that Process controls the devices power up in a known state (0 V or tristate), and an Actuator controls asynchronous CLEAR pin that sets the outputs to a zero scale/mid- PLCs scale voltage output or the low end of the selected current range. The HW SELECT pin is used to configure the parts for hardware GENERAL DESCRIPTION or software mode on power-up. The AD5750/AD5750-1/AD5750-2 are single-channel, low cost, precision voltage/current output drivers with hardware- or Table 1. Related Devices software-programmable output ranges. The software ranges are Part Number Description configured via an SPI-/MICROWIRE™-compatible serial interface. AD5422 Single channel, 16-bit, serial input current The AD5750/AD5750-1/AD5750-2 target applications in PLC source and voltage output DAC and industrial process control. The analog input to the AD5750/ AD5751 Industrial I/V output driver, single supply, 55 V maximum supply, programmable ranges AD5750-1/AD5750-2 is provided from a low voltage, single-supply AD5420 Single channel, 16-bit, serial input, 4 mA to digital-to-analog converter (DAC) and is internally conditioned 20 mA current source DAC to provide the desired output current/voltage range. Analog input ranges available are 0 V to 2.5 V (AD5750-1/AD5750-2) or 0 V to 4.096 V (AD5750). Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5750/AD5750-1/AD5750-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 OUTEN ........................................................................................ 26 Applications ....................................................................................... 1 Software Control ........................................................................ 26 General Description ......................................................................... 1 Hardware Control ...................................................................... 28 Revision History ............................................................................... 2 Transfer Function ....................................................................... 28 Functional Block Diagram .............................................................. 3 Detailed Description of Features .................................................. 29 Specifications ..................................................................................... 4 Output Fault Alert—Software Mode ....................................... 29 Timing Characteristics ................................................................ 8 Output Fault Alert—Hardware Mode ..................................... 29 Absolute Maximum Ratings .......................................................... 10 Voltage Output Short-Circuit Protection ................................ 29 ESD Caution ................................................................................ 10 Asynchronous Clear (CLEAR) ................................................. 29 Pin Configuration and Function Descriptions ........................... 11 External Current Setting Resistor ............................................ 30 Typical Performance Characteristics ........................................... 13 Programmable Overrange Modes ............................................ 30 Voltage Output ............................................................................ 13 Packet Error Checking ............................................................... 30 Current Output ........................................................................... 17 Applications Information .............................................................. 31 Terminology .................................................................................... 22 Transient Voltage Protection .................................................... 31 Theory of Operation ...................................................................... 23 Thermal Considerations ............................................................ 31 Software Mode ............................................................................ 23 Layout Guidelines....................................................................... 31 Current Output Architecture .................................................... 25 Galvanically Isolated Interface ................................................. 32 Driving Inductive Loads ............................................................ 25 Microprocessor Interfacing ....................................................... 32 Power-On State of AD5750/AD5750-1/AD5750-2 ................... 25 Outline Dimensions ....................................................................... 33 Default Registers at Power-On ................................................. 26 Ordering Guide .......................................................................... 33 Reset Function ............................................................................ 26 REVISION HISTORY 9/14—Rev. E to Rev. F 7/10—Rev. B to Rev. C Changes to Accuracy, Internal R Parameter, Table 2 ............... 6 Added Leakage Current in Voltage Output Characteristics SET Changes to Table 4 .......................................................................... 10 Parameter (Table 2) ........................................................................... 5 Changes to Figure 4 ........................................................................ 11 Added Leakage Current in Current Output Characteristics Changes to Figure 46 ...................................................................... 20 Parameter (Table 2) ........................................................................... 6 Changes to Asynchronous Clear (CLEAR) Section ................... 29 6/10—Rev. A to Rev. B Changes to Thermal Consideration Section ............................... 31 Changes to Table 1 ............................................................................. 1 Updated Outline Dimensions ....................................................... 33 Changes to Table 2, Power Requirements ...................................... 7 Changes to Ordering Guide .......................................................... 33 8/09—Rev. 0 to Rev. A 6/12—Rev. D to Rev. E Added AD5750-1................................................................ Universal Changes to Figure 3 .......................................................................... 9 Changes to Features and General Description Sections .............. 1 Changes to Status Bit Read Operation Section ........................... 28 Changes to Table 2 ............................................................................. 4 Updated Outline Dimensions ....................................................... 33 Changes to Theory of Operation Section and Figure 51 .......... 23 4/12—Rev. C to Rev. D Change to Figure 52 and Table 6 Title ......................................... 24 Added AD5750-2 ................................................................ Universal Changes to Current Output Architecture Section and Power-On Changes to Table 2 ............................................................................ 4 State of AD5750/AD5750-1 .......................................................... 25 Updated Outline Dimensions ....................................................... 33 Changes to Transfer Function Section ........................................ 28 Changes to Ordering Guide .......................................................... 33 Changes to Programmable Overrange Modes Section ............. 30 Changes to Ordering Guide .......................................................... 33 7/09—Revision 0: Initial Version Rev. F | Page 2 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 FUNCTIONAL BLOCK DIAGRAM DVCC GND AVDD GND COMP1COMP2 CLEAR AD5750/AD5750-1/AD5750-2 CLRSEL VSENSE+ SCLK/OUTEN* INPUT SHIFT SDIN/R0* REGISTER VOUT RANGE SYNC/RSET* COANNTDROL SCALING VOUT SDO/VFAULT* LOGIC VOUT SHORTFAULT HW SELECT STATUS REGISTER VSENSE– VIN R2 VDD R3 VREF RESET IOUT RANGE REXT1 SCALING REXT2 RSET IOUT Vx** OVERTEMP VSS FAULT/TEMP* VOUT SHORTFAULT IOUT OPENFAULT NC/IFAULT* POWER- IOUT ON RESET OPENFAULT AD2/R1* AD1/R2* AD0/R3* AVSS *DENOTES SHARED PIN. SOFTWARE MODE DENOTED BY REGULAR TEXT, HARDWARE MODE DENOTED BYITALICTEXT. FOR EXAMPLE, FORFAULT/TEMP PIN, IN SOFTWARE MODE, THIS **PTVOIxN IGSTEAANKNEE IRSNA TOTENER FNTAHAUELL IBTN ITFAEUSRN VNCOATLLITO ASNGE. NEINS ( ECH AACNRU DRBWREAE GNRRTEOS MU NONEDDEE DO, ERTD HO IFSTOH PREIN RT HTVAEOK LCETUSAR GORENE)N TTTHE OAMTUP TISFP UUUNTSCSET.DION. 07268-001 Figure 1. Rev. F | Page 3 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet SPECIFICATIONS AV /AV = ±12 V (± 10%) to ±24 V (± 10%), DV = 2.7 V to 5.5 V, GND = 0 V. IOUT: R = 300 Ω. All specifications T to T , DD SS CC LOAD MIN MAX unless otherwise noted. Table 2. Parameter1 Min Typ Max Unit Test Conditions/Comments INPUT VOLTAGE RANGE Output unloaded 0 to 4.096 V AD5750 0 to 2.5 AD5750-1/AD5750-2 Input Leakage Current −1 +1 µA REFERENCE INPUT Reference Input Voltage 4.096 V AD5750; external reference must to be exactly as stated; otherwise, accuracy errors show up as error in output 2.5 V AD5750-2; external reference needs to be exactly as stated; otherwise, accuracy errors show up as error in output 1.25 V AD5750-1; external reference needs to be exactly as stated; otherwise, accuracy errors show up as error in output Input Leakage Current −1 +1 µA VOLTAGE OUTPUT Output Voltage Ranges 0 5 V 0 10 V AV needs to have minimum DD 1.3 V headroom or >11.3 V −5 +5 V −10 +10 V AV /AV needs to have minimum DD SS 1.3 V headroom or >±11.3 V Output Voltage Overranges 0 6 V Programmable overranges; see the Detailed Description of Features section 0 12 V −6 +6 V −12 +12 V −2.5 +2.5 V Accuracy Total Unadjusted Error (TUE) B Version2 −0.1 +0.1 % FSR −0.05 ±0.02 +0.05 % FSR T = 25°C A A Version2 −0.3 +0.3 % FSR −0.1 ±0.05 +0.1 % FSR T = 25°C A Relative Accuracy (INL) −0.02 ±0.005 +0.02 % FSR Bipolar Zero Error (Offset at Midscale) −10 +10 mV ±10 V range −8 ±0.5 +8 mV T = 25°C, ±10 V range A −5 +5 mV ±5 V range −4 ±0.3 +4 mV T = 25°C, ± 5 V range A Bipolar Zero Error Temperature ±1.5 ppm FSR/°C All bipolar ranges Coefficient3 Zero-Scale Error −10 +10 mV ±10 V range −8 ±0.5 +8 mV T = 25°C, ±10 V range A −5 +5 mV ± 5 V range −4 ±0.3 +4 mV T = 25°C, ±5 V range A Rev. F | Page 4 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 Parameter1 Min Typ Max Unit Test Conditions/Comments Zero-Scale Error Temperature ±1 ppm FSR/°C All bipolar ranges Coefficient3 Zero-Scale/Offset Error −5 +5 mV 0 V to 10 V range −4 ±0.5 +4 mV T = 25°C, 0 V to 10 V range A −3 +3 mV 0 V to 5 V range −2.2 ±0.3 +2.2 mV T = 25°C, 0 V to 5 V range A Offset Error Temperature Coefficient3 ±2 ppm FSR/°C All unipolar ranges Gain Error −0.05 +0.05 % FSR All bipolar/unipolar ranges, AD5750 and AD5750-1 −0.07 +0.07 % FSR AD5750-2 −0.04 ±0.015 +0.04 % FSR T = 25°C, AD5750, AD5750-1, and A AD5750-2 Gain Error Temperature Coefficient3 ±0.5 ppm FSR/°C Full-Scale Error −0.05 +0.05 % FSR All bipolar/unipolar ranges, AD5750 and AD5750-1 −0.04 ±0.015 +0.04 % FSR T = 25°C, AD5750 and AD5750-1 A −0.07 +0.07 % FSR AD5750-2 Full-Scale Error Temperature ±1.5 ppm FSR/°C Coefficient3 VOLTAGE OUTPUT CHARACTERISTICS3 Headroom 1.3 V Output unloaded Short-Circuit Current 15 mA Load 1 kΩ Capacitive Load Stability T = 25°C A R = ∞ 1 nF LOAD R = 2 kΩ 1 nF LOAD R = ∞ 2 µF External compensation capacitor LOAD required; see the Driving Inductive Loads section DC Output Impedance 0.12 Ω Leakage Current −110 +110 nA Output disabled; leakage to ground 0 V to 5 V Range, ¼ to ¾ Step 7 µs Specified with 2 kΩ || 220 pF, ±0.05% 0 V to 5 V Range, 40 mV Input Step 4.5 µs Specified with 2 kΩ || 220 pF, ±0.05% Slew Rate 2 V/µs Specified with 2 kΩ || 220 pF Output Noise 2.5 µV rms 0.1 Hz to 10 Hz bandwidth 45.5 µV rms 100 kHz bandwidth Output Noise Spectral Density 165 nV/√Hz Measured at 10 kHz; specified with 2 kΩ || 220 pF AC PSRR −65 dB 200 mV, 50 Hz/60 Hz sine wave super- imposed on power supply voltage DC PSRR 10 µV/V Outputs unloaded CURRENT OUTPUT Output Current Ranges 0 24 mA 0 20 mA 4 20 mA −20 +20 mA −24 +24 mA Output Current Overranges 0 24.5 mA See the Detailed Description of Features section 0 20.4 mA See the Detailed Description of Features section 4 20.4 mA See the Detailed Description of Features section Rev. F | Page 5 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet Parameter1 Min Typ Max Unit Test Conditions/Comments ACCURACY, INTERNAL R SET Total Unadjusted Error (TUE) B Version2 −0.2 +0.2 % FSR −0.1 ±0.03 +0.1 % FSR T = 25°C A A Version2 −0.5 +0.5 % FSR −0.3 ±0.15 +0.3 % FSR T = 25°C A Relative Accuracy (INL) −0.02 ±0.01 +0.02 % FSR Unipolar ranges −0.03 ±0.015 +0.03 % FSR Bipolar ranges Offset Error −16 +16 µA 4 mA to 20 mA, 0 mA to 20 mA, 0 mA to 24 mA ranges −10 +5 +10 µA T = 25°C A −50 +50 µA ±20 mA, ±24 mA ranges −26 +8 +26 µA T = 25°C A Offset Error Temperature Coefficient3 ±3 ppm FSR/°C All ranges Bipolar Zero Error −35 +35 µA ±20 mA, ±24 mA ranges −24 +15 +24 µA T = 25°C A Bipolar Zero Temperature Coefficient3 ±0.5 ppm FSR/°C Gain Error −0.2 +0.2 % FSR 4 mA to 20 mA, 0 mA to 20 mA, 0 mA to 24 mA ranges −0.25 +0.25 % FSR ±20 mA, ±24 mA ranges −0.03 ±0.006 +0.03 % FSR T = 25°C A Gain Temperature Coefficient3 ±8 ppm FSR/°C All ranges Full-Scale Error −0.2 +0.2 % FSR All ranges −0.125 ±0.02 +0.125 % FSR T = 25°C A Full-Scale Temperature Coefficient3 ±4 ppm FSR/°C All ranges ACCURACY, EXTERNAL R SET Total Unadjusted Error (TUE) B Version2 −0.1 +0.1 % FSR −0.08 ±0.03 +0.08 % FSR T = 25° A A Version2 −0.3 +0.3 % FSR −0.1 ±0.02 +0.1 % FSR T = 25°C A Relative Accuracy (INL) −0.02 ±0.01 +0.02 % FSR 4 mA to 20 mA, 0 mA to 20 mA, 0 mA to 24 mA ranges −0.03 ±0.015 +0.03 % FSR ±20 mA, ±24 mA ranges Offset Error −14 +14 µA 4 mA to 20 mA, 0 mA to 20 mA, 0 mA to 24 mA ranges −11 +5 +11 µA T = 25°C A −20 +20 µA ±20 mA, ±24 mA ranges +8 +15 µA T = 25°C A Offset Error Temperature Coefficient3 ±2 ppm FSR/°C All ranges Bipolar Zero Error −32 +32 µA All ranges −22 +12 +22 µA T = 25°C A Bipolar Zero Temperature Coefficient3 ±0.5 ppm FSR/°C Gain Error −0.08 +0.08 % FSR All ranges −0.07 ±0.02 +0.07 % FSR T = 25°C A Gain Temperature Coefficient ±1 ppm FSR/°C All ranges Full-Scale Error −0.1 +0.1 % FSR All ranges −0.07 ±0.02 +0.07 % FSR T = 25°C A Full-Scale Temperature Coefficient3 ±2 ppm FSR/°C All ranges Rev. F | Page 6 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 Parameter1 Min Typ Max Unit Test Conditions/Comments CURRENT OUTPUT CHARACTERISTICS3 Current Loop Compliance Voltage 0 AV − 2.75 V DD Resistive Load See test conditions/comments column Chosen such that compliance is not exceeded Inductive Load See test conditions/comments column Needs appropriate capacitor at higher inductance values; see the Driving Inductive Loads section Settling Time 4 mA to 20 mA, Full-Scale Step 8.5 µs 250 Ω load 4 mA to 20 mA, 120 µA Step 1.2 µs 250 Ω load DC PSRR 1 µA/V Output Impedance 130 MΩ Leakage Current −12 +12 nA Output disabled; leakage to ground VOUT/VSENSE− Error 0.9994 1.0006 Gain Error in VOUT voltage due to changes in VSENSE−; specified as gain, for example, if VSENSE− moves by 1 V, VOUT moves by 0.9994 V DIGITAL INPUT JEDEC compliant Input High Voltage, V 2 V IH Input Low Voltage, V 0.8 V IL Input Current −1 +1 µA Per pin Pin Capacitance 5 pF Per pin DIGITAL OUTPUTS3 FAULT, IFAULT, TEMP, VFAULT Output Low Voltage, V 0.4 V 10 kΩ pull-up resistor to DV OL CC 0.6 V At 2.5 mA Output High Voltage, V 3.6 V 10 kΩ pull-up resistor to DV OH CC SDO Output Low Voltage, V 0.5 0.5 V Sinking 200 µA OL Output High Voltage, V DV − 0.5 DV − 0.5 V Sourcing 200 µA OH CC CC High Impedance Output Capacitance 3 pF High Impedance Leakage Current −1 +1 µA POWER REQUIREMENTS AV 12 24 V ±10% DD AV −12 −24 V ±10% SS DV CC Input Voltage 2.7 5.5 V AI 4.4 5.6 mA Output unloaded, output disabled, DD R3, R2, R1, R0 = 0, 1, 0, 1; RSET = 0 5.2 6.2 mA Current output enabled 5.2 6.2 mA Voltage output enabled AI 2.0 2.5 mA Output unloaded, output disabled, SS R3, R2, R1, R0 = 0, 1, 0, 1; RSET = 0, AD5750 and AD5750-1 2.0 3.5 mA AD5750-2 2.5 3 mA Current output enabled 2.5 3 mA Voltage output enabled DI 0.3 1 mA V = DV , V = GND CC IH CC IL Power Dissipation 108 mW AV /AV = ±24 V, outputs unloaded DD SS 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 Specification includes gain and offset errors over temperature and drift after 1000 hours, TA = 125°C. 3 Guaranteed by characterization, but not production tested. Rev. F | Page 7 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet TIMING CHARACTERISTICS AV /AV = ±12 V (± 10%) to ±24 V (± 10%), DV = 2.7 V to 5.5 V, GND = 0 V. VOUT: R = 2 kΩ, C = 200 pF, IOUT: R = DD SS CC LOAD L LOAD 300 Ω. All specifications T to T , unless otherwise noted. MIN MAX Table 3. Parameter1, 2 Limit at T , T Unit Description MIN MAX t 20 ns min SCLK cycle time 1 t 8 ns min SCLK high time 2 t 8 ns min SCLK low time 3 t 5 ns min SYNC falling edge to SCLK falling edge setup time 4 t 10 ns min 16th SCLK falling edge to SYNC rising edge (on 24th SCLK falling edge if using PEC) 5 t 5 ns min Minimum SYNC high time (write mode) 6 t 5 ns min Data setup time 7 t 5 ns min Data hold time 8 t, t 1.5 µs max CLEAR pulse low/high activation time 9 10 t 5 ns min Minimum SYNC high time (read mode) 11 t 40 ns max SCLK rising edge to SDO valid (SDO C = 15 pF) 12 L t 10 ns min RESET pulse low time 13 1 Guaranteed by characterization, but not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. Rev. F | Page 8 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 Timing Diagrams t1 SCLK 1 2 16 t6 t3 t2 t4 t5 SYNC t8 t7 SDIN D15 D0 CLEAR t10 t9 VOUT RESET t13 07268-003 Figure 2. Write Mode Timing Diagram SCLK SYNC t11 SDIN A2 A1 A0 R=1 0 R3 R2 R1 R0 CLRSEL OUTEN CLEAR RSET RESET 0 0 t12 SDO X X X X X R3 R2 R1 R0 CLRSEL OUTEN RSET ERPREOCR OTEVMERP FIAOUULTT FVAOUULTT 07268-004 Figure 3. Readback Mode Timing Diagram Rev. F | Page 9 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents of up to A Stresses above those listed under Absolute Maximum Ratings 100 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 4. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute AV to GND −0.3 V to +30 V DD maximum rating conditions for extended periods may affect AV to GND +0.3 V to −28 V SS device reliability. AV to AV −0.3 V to +58 V DD SS DV to GND −0.3 V to +7 V CC VSENSE+ to GND AVSS to AVDD ESD CAUTION VSENSE− to GND ±5.0 V Digital Inputs to GND −0.3 V to DV + 0.3 V or CC +7 V (whichever is less) Digital Outputs to GND −0.3 V to DV + 0.3 V or CC +7 V (whichever is less) VREF to GND −0.3 V to +7 V VIN to GND −0.3 V to +7 V VOUT, IOUT to GND AV to AV SS DD Operating Temperature Range, −40°C to +105°C Industrial Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 125°C J 32-Lead LFCSP Package θ Thermal Impedance1 42°C/W JA Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 3 kV 1 Simulated data based on a JEDEC 2S2P board with thermal vias. Rev. F | Page 10 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TLUAPMETT/TTCELE FLES I/CUASE WCCCC NFRHNNNN 21098765 33322222 SDO/VFAULT 1 24 VSENSE+ CLRSEL 2 AD5750/ 23 VOUT CLEAR 3 AD5750-1/ 22 VSENSE– DVCC 4 AD5750-2 21 AVSS GND 5 20 COMP1 SYNC/RSET 6 TOP VIEW 19 COMP2 SCLK/OUTEN 7 (Not to Scale) 18 IOUT SDIN/R0 8 17 AVDD 90123456 1111111 N12..O NTTHCEE S= ENXOP OCOSENDN EPCA1R/2DATD.D2R/1DALE3R/0DA IS2TXER TI1TXEREDV FERTVONI ADNGVSS. 07268-005 Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 SDO/VFAULT Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin is a CMOS output. Short-Circuit Fault Alert (VFAULT). In hardware mode, this pin acts as a short-circuit fault alert pin and is asserted low when a short-circuit error is detected. This pin is an open-drain output and must be connected to a pull-up resistor. 2 CLRSEL In hardware or software mode, this pin selects the clear value, either zero-scale or midscale code. In software mode, this pin is implemented as a logic OR with the internal CLRSEL bit. 3 CLEAR Active High Input. Asserting this pin sets the output current/voltage to zero-scale code or midscale code of the range selected (user selectable). CLEAR is a logic OR with the internal clear bit. In software mode, during power-up, the CLEAR pin level determines the power-on condition of the voltage channel, which can be active 0 V or tristate. See the Asynchronous Clear (CLEAR) section for more details. 4 DV Digital Power Supply. CC 5 GND Ground Connection. 6 SYNC/RSET Positive Edge Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift register data into the AD5750/AD5750-1/AD5750-2, also updating the output. Resistor Select (RSET). In hardware mode, this pin selects whether the internal or the external current sense resistor is used. If RSET = 0, the external sense resistor is chosen, and if RSET = 1, the internal sense resistor is chosen. 7 SCLK/OUTEN Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling edge of SCLK. This pin operates at clock speeds up to 50 MHz. Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin. 8 SDIN/R0 Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK. Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output current/voltage range setting on the part. 9 AD2/R1 Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD1 and AD0, allows up to eight devices to be addressed on one bus. Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output current/voltage range setting on the part. 10 AD1/R2 Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD2 and AD0, allows up to eight devices to be addressed on one bus. Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output current/voltage range setting on the part. Rev. F | Page 11 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet Pin No. Mnemonic Description 11 AD0/R3 Device Addressing Bit (AD0). In software mode, this pin, in conjunction with AD1 and AD2, allows up to eight devices to be addressed on one bus. Range Decode Bit (R3). In hardware mode, this pin, in conjunction with R0, R1, and R2, selects the output current/voltage range setting on the part. 12, 13 REXT2, REXT1 A 15 kΩ external current setting resistor can be connected between the REXT1 and REXT2 pins to improve the IOUT temperature drift performance. 14 VREF Buffered Reference Input. 15 VIN Buffered Analog Input (0 V to 4.096 V). 16 GND Ground Connection. 17 AV Positive Analog Supply. DD 18 IOUT Current Output. 19, 20 COMP2, Optional Compensation Capacitor Connections for the Voltage Output Buffer. These pins are used to drive COMP1 higher capacitive loads on the output. They also reduce overshoot on the output. Care should be taken when choosing the value of the capacitor connected between the COMP1 and COMP2 pins because it has a direct influence on the settling time of the output. See the Driving Large Capacitive Loads section for further details. 21 AV Negative Analog Supply. SS 22 VSENSE− Sense Connection for the Negative Voltage Output Load Connection. This pin must stay within ±3.0 V of ground for correct operation. 23 VOUT Buffered Analog Output Voltage. 24 VSENSE+ Sense Connection for the Positive Voltage Output Load Connection. 25, 26, NC No Connect. Can be tied to GND. 27, 28 29 HW SELECT This pin is used to configure the part to hardware or software mode. HW SELECT = 0 selects software control, and HW SELECT = 1 selects hardware control. 30 RESET Resets the part to its power-on state. 31 FAULT/TEMP Fault Alert (FAULT). In software mode, this pin acts as a general fault alert pin. It is asserted low when an open- circuit error, short-circuit error, overtemperature error, or PEC interface error is detected. This pin is an open- drain output and must be connected to a pull-up resistor. Overtemperature Fault (TEMP). In hardware mode, this pin acts as an overtemperature fault pin. It is asserted low when an overtemperature error is detected. This pin is an open-drain output and must be connected to a pull-up resistor. 32 NC/IFAULT No Connect (NC). In software mode, this pin is a no connect. Instead, tie this pin to GND. Open-Circuit Fault Alert (IFAULT). In hardware mode, this pin acts as an open-circuit fault alert pin. It is asserted low when an open-circuit error is detected. This pin is an open-drain output and must be connected to a pull- up resistor. EPAD The exposed paddle is tied to AV . SS Rev. F | Page 12 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUT 0.0020 0.10 AVDD = +24V R) 0.0015 AVSS = –24V 0.08 S F % R ( 0.0010 0.06 O R 0.0005 0.04 R E Y 0 R) 0.02 T S ARI–0.0005 %F 0 NE E ( NLI–0.0010 TU –0.02 +5V POSITIVE TUE, NO LOAD L NO–0.0015 –0.04 +±51V0V P POOSSITITIVIVEE T TUUEE, ,N NOO L LOOAADD GRA–0.0020 +5V –0.06 ±+150VV N PEOGSAITTIIVVEE TTUUEE,, NNOO LLOOAADD INTE–0.0025 +±51V0V –0.08 +±51V0V N NEEGGAATTIVIVEE T TUUEE, ,N NOO L LOOAADD ±10V ±10V NEGATIVE TUE, NO LOAD –0.0030 –0.10 0 0.585 1.170 1.755VIN 2(V.3)41 2.926 3.511 4.096 07268-105 –40 TEMPERA25TURE (°C) 105 07268-108 Figure 5. Integral Nonlinearity Error vs. VIN Figure 8. Total Unadjusted Error (TUE) vs. Temperature 0.005 0.03 AVDD = +24V +5V LINEARITY, NO LOAD R) 0.004 AVSS = –24V +10V LINEARITY, NO LOAD FS ±5V LINEARITY, NO LOAD 0.02 % R ( 0.003 ±10V LINEARITY, NO LOAD R) RRO 0.002 %FS 0.01 RITY E 0.001 RROR ( 0 A 0 E LINE–0.001 ALE –0.01 N C O S AL N–0.002 ULL- –0.02 GR–0.003 F +5V RANGE, FULL-SCALE ERROR E –0.03 +10V RANGE, FULL-SCALE ERROR NT–0.004 ±5V RANGE, FULL-SCALE ERROR I ±10V RANGE, FULL-SCALE ERROR –0.005 –0.04 –40 TEMPERA25TURE (°C) 105 07268-106 –40 TEMPERA25TURE (°C) 105 07268-109 Figure 6. Integral Nonlinearity Error vs. Temperature Figure 9. Full-Scale Error vs. Temperature 0.006 2.5 AVDD = +24V AVDD = +24V 0.004 AVSS = –24V 2.0 AVSS = –24V 0.002 mV) 1.5 R ( 1.0 E (%FSR)–0.0020 ERO ERRO 0.05 ±10V ZERO ERROR TU–0.004 R Z –0.5 +5V A +10V OL –1.0 –0.006 ±±51V0V BIP –1.5 –0.008 ±5V ZERO ERROR –2.0 –0.010 –2.5 0 0.585 1.170 1.755VIN 2(V.3)41 2.926 3.511 4.096 07268-107 –40 TEMPERA25TURE (°C) 105 07268-110 Figure 7. Total Unadjusted Error (TUE) vs. VIN Figure 10. Bipolar Zero Error vs. Temperature Rev. F | Page 13 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet 0.020 0.10 AVDD = +24V +5V POSITIVE TUE, NO LOAD 0.015 AVSS = –24V 0.08 +10V POSITIVE TUE, NO LOAD ±5V POSITIVE TUE, NO LOAD 0.06 ±10V POSITIVE TUE, NO LOAD 0.010 +5V NEGATIVE TUE, NO LOAD SR) 0.005 0.04 ±+51V0V N NEEGGAATTIVIVEE T TUUEE, ,N NOO L LOOAADD %F R) 0.02 ±10V NEGATIVE TUE, NO LOAD R ( 0 FS O % 0 RR–0.005 E ( N E TU –0.02 AI–0.010 G –0.04 –0.015 +5V GAIN, NO LOAD –0.06 +10V GAIN, NO LOAD –0.020 ±5V GAIN, NO LOAD –0.08 ±10V GAIN, NO LOAD –0.025 –0.10 –40 TEMPERA25TURE (°C) 105 07268-111 +11.2/–10.8 SUPPL±Y1 5V.0OLTAGES (A±2V4D.D0/AVSS) ±26.4 07268-114 Figure 11. Gain Error vs. Temperature Figure 14. Total Unadjusted Error (TUE) vs. Supply Voltages 2.5 1.2 AVDD = +24V 2.0 AVSS = –24V OUTPUT UNLOADED 1.5 1.0 mV) 1.0 O-SCALE ERROR ( ––100...0505 HEADROOM (V) 000...864 ±10V VDD HEADROOM, LOAD OFF R E –1.5 Z –2.0 +5V RANGE 0.2 +10V RANGE –2.5 ±5V RANGE ±10V RANGE –3.0 0 –40 TEMPERA25TURE (°C) 105 07268-112 –40 TEMPERA25TURE (°C) 105 07268-115 Figure 12. Zero-Scale Error (Offset Error) vs. Temperature Figure 15. AVDD Headroom, ±10 V Range, Output Set to 10 V, Load Off 0.003 0.05 +5V LINEARITY, NO LOAD +5V RANGE R) +10V LINEARITY, NO LOAD 0.04 ±10V RANGE S OR (%F 0.002 ±±51V0V L LININEEAARRITITYY, ,N NOO L LOOAADD A (V) 0.03 R T 0.02 R 0.001 L TY E E DE 0.01 LINEARI 0 VOLTAG –0.010 AL NON–0.001 UTPUT –0.02 EGR–0.002 O –0.03 NT –0.04 I –0.003 –0.05 +11.2/–10.8 SUPPL±Y1 5V.0OLTAGES (A±2V4D.D0/AVSS) ±26.4 07268-113 –15–13–11 –9 –S7OU–R5CE–/3SIN–K1 CU1RR3ENT5 (mA7) 9 11 13 15 07268-116 Figure 13. Integral Nonlinearity Error vs. Supply Voltage Figure 16. Source and Sink Capability of Output Amplifier Rev. F | Page 14 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 12 10 1 8 V) E ( G A 6 T L O V 4 2 2 0–8 –3 2 7 TIM1E2 (µs) 17 22 27 07268-117 CH1 5.00V CH2 20.0mV BWM1.0µs A CH1 3.00V 07268-120 Figure 17. Full-Scale Positive Step Figure 20. VOUT Enable Glitch, Load = 2 kΩ || 1 nF 12 10 8 V) E ( G A 6 T L O V 4 2 0 5µV/DIV 1s/DIV 07268-121 –8 –3 2 7 TIM1E2 (µs) 17 22 27 07268-118 Figure 18. Full-Scale Negative Step Figure 21. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth) 40 35 30 25 mV) 20 (OUT 15 V 10 5 –50 100µV/DIV 1s/DIV 07268-122 –1.0 –0.5 0 0T.5IME (m1s.)0 1.5 2.0 2.5 07268-119 Figure 19. VOUT vs. Time on Power-Up, Load = 2 kΩ || 200 pF Figure 22. Peak-to-Peak Noise (100 kHz Bandwidth) Rev. F | Page 15 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet 4.0 1.0 3.5 0.8 3.0 VDD 0.6 2.5 V (V)DD2.0 0.4 V (V)OUT 1.5 0.2 1.0 VOUT 0 0.5 0 –0.2 –1.5 –1.0 –0.5 0TIME (m0s.)5 1.0 1.5 2.0 07268-123 Figure 23. VDD and VOUT vs. Time on Power-Up Rev. F | Page 16 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 CURRENT OUTPUT 0.004 0.010 AVDD = +24V +4mA TO +20mA INTERNAL RSET LINEARITY %FSR) 0.002 AVSS = –24V %FSR) 0.008 00mmAA TTOO ++2240mmAA IINNTTEERRNNAALL RRSSEETT LLIINNEEAARRIITTYY R ( R ( 0.006 ±20mA INTERNAL RSET LINEARITY RO 0 RO 0.004 ±24mA INTERNAL RSET LINEARITY R R E E Y Y 0.002 T–0.002 T RI RI A A 0 E E LIN–0.004 LIN–0.002 N N O O L N–0.006 L N–0.004 A A EGR–0.008 +0m4mAA T TOO + +202m0mAA EGR–0.006 NT 0mA TO +24mA NT–0.008 I ±20mA I –0.010 ±24mA –0.010 0 0.585 1.170 1.755VIN 2(V.3)41 2.926 3.511 4.096 07268-124 +11.2/–10.8 SUPPL±Y1 5V.0OLTAGES (A±2V4D.D0/AVSS) ±26.4 07268-127 Figure 24. Integral Nonlinearity Error vs. VIN, External RSET Resistor Figure 27. Integral Nonlinearity Error, Current Mode, Internal RSET Sense Resistor 0.004 0.010 AVDD = +24V AVDD = +24V +4mA TO +20mA SR) 0.002 AVSS = –24V 0.008 AVSS = –24V 00mmAA TTOO ++2204mmAA %F ±20mA R ( 0 0.006 ±24mA O R R 0.004 Y E–0.002 R) RIT FS 0.002 A–0.004 % NE E ( 0 NLI–0.006 TU NO –0.002 AL –0.008 GR +4mA TO +20mA –0.004 E 0mA TO +20mA NT–0.010 0mA TO +24mA –0.006 I ±20mA –0.012 ±24mA –0.008 0 0.585 1.170 1.755VIN 2(V.3)41 2.926 3.511 4.096 07268-125 0 0.585 1.170 1.755VIN 2(V.3)41 2.926 3.511 4.096 07268-128 Figure 25. Integral Nonlinearity Error vs. VIN, Internal RSET Resistor Figure 28. Total Unadjusted Error (TUE) vs. VIN, External RSET Resistor 0.010 0.015 +4mA TO +20mA EXTERNAL RSET LINEARITY AVDD = +24V +4mA TO +20mA SR) 0.008 0mA TO +20mA EXTERNAL RSET LINEARITY AVSS = –24V 00mmAA TTOO ++2204mmAA %F 0mA TO +24mA EXTERNAL RSET LINEARITY 0.010 ±20mA R ( 0.006 ±20mA EXTERNAL RSET LINEARITY ±24mA RO 0.004 ±24mA EXTERNAL RSET LINEARITY R 0.005 E Y 0.002 R) RIT FS A 0 % 0 NE E ( NLI–0.002 TU L NO–0.004 –0.005 A EGR–0.006 –0.010 NT–0.008 I –0.010 –0.015 +11.2/–10.8 SUPPL±Y1 5V.0OLTAGES (A±2V4D.D0/AVSS) ±26.4 07268-126 0 0.585 1.170 1.755VIN 2(V.3)41 2.926 3.511 4.096 07268-129 Figure 26. Integral Nonlinearity Error, Current Mode, Figure 29. Total Unadjusted Error vs. VIN, Internal RSET Resistor External RSET Sense Resistor Rev. F | Page 17 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet 0.10 0.010 +4mA TO +20mA EXTERNAL RSET POSITIVE TUE +4mA TO +20mA EXTERNAL RSET LINEARITY 0.08 0mA TO +20mA EXTERNAL RSET POSITIVE TUE 0.008 0mA TO +20mA EXTERNAL RSET LINEARITY 0.06 0±m20Am TAO E +X2T4EmRAN AELX TRESRENT APLO SRISTEITV EP OTUSIETIVE TUE 0.006 0±±22m40Amm TAAO EE +XX2TT4EEmRRANN AAELLX TRRESSREENTT ALLLIINN REESAAERRTII TTLYYINEARITY 0.04 ±24mA EXTERNAL RSET POSITIVE TUE 0.004 R) S SR) 0.02 %F 0.002 E (%F 0 RITY ( 0 TU –0.02 EA–0.002 N –0.04 LI–0.004 +4mA TO +20mA EXTERNAL RSET NEGATIVE TUE –0.06 0mA TO +20mA EXTERNAL RSET NEGATIVE TUE –0.006 0mA TO +24mA EXTERNAL RSET NEGATIVE TUE –0.08 ±20mA EXTERNAL RSET NEGATIVE TUE –0.008 AVDD = +24V –0.10 ±24mA EXTERNAL RSET NEGATIVE TUE –0.010 AVSS = –24V +11.2/–10.8 SUPPL±Y1 5V.0OLTAGES (A±2V4D.D0/AVSS) ±26.4 07268-130 –40 TEMPERA25TURE (°C) 105 07268-133 Figure 30. Total Unadjusted Error (TUE), Current Mode, Figure 33. INL vs. Temperature, External RSET Sense Resistor External RSET Sense Resistor 0.10 0.10 +4mA TO +20mA INTERNAL RSET POSITIVE TUE +4mA TO +20mA INTERNAL RSET POSITIVE TUE 0.08 0mA TO +20mA INTERNAL RSET POSITIVE TUE 0.08 0mA TO +20mA INTERNAL RSET POSITIVE TUE 0.06 0±m20Am TAO IN +T2E4mRNAA ILN TRESRENT APLO SRISTEITV EP OTUSIETIVE TUE 0.06 0±±22m04Amm TAAO II NN+TT2EE4RRmNNAAA ILLN TRRESSREENTTA PPLOO RSSSIITTEIITVV EEP OTTUUSEEITIVE TUE 0.04 ±24mA INTERNAL RSET POSITIVE TUE 0.04 R) 0.02 R) 0.02 S S F F % 0 % 0 E ( E ( TU –0.02 TU –0.02 –0.04 –0.04 +4mA TO +20mA INTERNAL RSET NEGATIVE TUE –0.06 0mA TO +20mA INTERNAL RSET NEGATIVE TUE –0.06 +4mA TO +20mA INTERNAL RSET NEGATIVE TUE –0.08 0±m20Am TAO IN +T2E4mRNAA ILN TRESRENT ANLE GRASETTIV NEE TGUAETIVE TUE –0.08 00±mm20AAm TTAOO IN ++T22E04RmmNAAA IILNN TTREESRRENNTAA NLLE RRGSSAEETTTIV NNEEE TGGUAAETTIIVVEE TTUUEE –0.10 ±24mA INTERNAL RSET NEGATIVE TUE –0.10 ±24mA INTERNAL RSET NEGATIVE TUE +11.2/–10.8 SUPPL±Y1 5V.0OLTAGES (A±2V4D.D0/AVSS) ±26.4 07268-131 –40 TEMPERA25TURE (°C) 105 07268-134 Figure 31. Total Unadjusted Error (TUE), Current Mode, Figure 34. Total Unadjusted Error (TUE) vs. Temperature, Internal RSET Sense Resistor Internal RSET Sense Resistor 0.010 0.10 +4mA TO +20mA INTERNAL RSET LINEARITY +4mA TO +20mA EXTERNAL RSET POSITIVE TUE 0.008 0mA TO +20mA INTERNAL RSET LINEARITY 0.08 0mA TO +20mA EXTERNAL RSET POSITIVE TUE 0mA TO +24mA INTERNAL RSET LINEARITY 0mA TO +24mA EXTERNAL RSET POSITIVE TUE 0.006 ±20mA INTERNAL RSET LINEARITY 0.06 ±20mA EXTERNAL RSET POSITIVE TUE ±24mA INTERNAL RSET LINEARITY ±24mA EXTERNAL RSET POSITIVE TUE 0.004 0.04 R) %FS 0.002 SR) 0.02 EARITY (–0.0020 TUE (%F –0.020 N LI–0.004 –0.04 –0.006 –0.06 +0m4mAA T TOO + +202m0mAA E EXXTETERRNNAALL R RSSEETT N NEEGGAATTIVIVEE T TUUEE –0.008 AVDD = +24V –0.08 ±0m20Am TAO E +X2T4EmRAN AELX TRESRENTA NLE RGSAETTIV NEE TGUAETIVE TUE –0.010 AVSS = ––2440V TEMPERA25TURE (°C) 105 07268-132 –0.10 ±24–m4A0 EXTERNALT RESMEPT ENREGA2A5TTUIVREE T (U°EC) 105 07268-135 Figure 32. INL vs. Temperature, Internal RSET Sense Resistor Figure 35. Total Unadjusted Error (TUE) vs. Temperature, External RSET Sense Resistor Rev. F | Page 18 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 6 2 AVDD = +24V +4mA TO +20mA EXTERNAL RSET AVSS = –24V 0mA TO +20mA EXTERNAL RSET 4 0mA TO +24mA EXTERNAL RSET A) 1 µ R (µA) 2 RROR ( 0 ±20mA, INTERNAL RSET RO E E –1 R L E A CALE 0 RO-SC –2 ±24mA, INTERNAL RSET S E –3 RO- –2 R Z E A Z L –4 O P –4 BI –5 ±20mA EXTERNAL RSET AVDD = +24V ±24mA EXTERNAL RSET AVSS = –24V –6 –6 –40 TEMPERA25TURE (°C) 105 07268-136 –40 TEMPERA25TURE (°C) 105 07268-139 Figure 36. Zero-Scale Error vs. Temperature, External RSET Sense Resistor Figure 39. Bipolar Zero-Scale Error vs. Temperature, Internal RSET Sense Resistor 25 0.04 +4mA TO +20mA INTERNAL RSET +4mA TO +20mA EXTERNAL RSET 20 00mmAA TTOO ++2204mmAA IINNTTEERRNNAALL RRSSEETT 0.03 00mmAA TTOO ++2204mmAA EEXXTTEERRNNAALL RRSSEETT A) 15 SR) 0.02 µ F OR ( 10 AAVVDSSD == –+2244VV R (% 0.01 AAVVDSSD == –+2244VV R O R 5 R E R E E 0 CAL 0 ALE RO-S –5 L-SC –0.01 E L Z U –0.02 –10 F –15 –0.03 ±20mA INTERNAL RSET ±20mA EXTERNAL RSET ±24mA INTERNAL RSET ±24mA EXTERNAL RSET –20 –0.04 –40 TEMPERA25TURE (°C) 105 07268-137 –40 TEMPERA25TURE (°C) 105 07268-140 Figure 37. Zero-Scale Error vs. Temperature, Internal RSET Sense Resistor Figure 40. Full-Scale Error vs. Temperature, External RSET Sense Resistor 3 0.04 +4mA TO +20mA INTERNAL RSET 0.03 0mA TO +20mA INTERNAL RSET E ERROR (µA) 012 ±24mA, EXTERNAL RSET OR (%FSR) 00..00120 ±±022m04mmA AAT OIINN +TT2EE4RRmNNAAA LLIN RRTESSEERTTNAL RSET O-SCAL –1 LE ERR –0.01 R A –0.02 E –2 C Z S AR ±20mA, EXTERNAL RSET LL- –0.03 L –3 U PO F –0.04 BI –4 AVDD = +24V –0.05 AVDD = +24V AVSS = –24V AVSS = –24V –5 –0.06 –40 TEMPERA25TURE (°C) 105 07268-138 –40 TEMPERA25TURE (°C) 105 07268-141 Figure 38. Bipolar Zero-Scale Error vs. Temperature, Figure 41. Full-Scale Error vs. Temperature, Internal RSET Sense Resistor External RSET Sense Resistor Rev. F | Page 19 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet 0.020 12 0.000010 +4mA TO +20mA EXTERNAL RSET 0mA TO +20mA EXTERNAL RSET 0.000008 0.015 0mA TO +24mA EXTERNAL RSET 10 0.000006 R) 0.010 8 0.000004 S ERROR (%F 0.0050 V (V)DD 64 IOUT –000.0.00000000022 I (A)OUT N GAI–0.005 2 –0.000004 –0.000006 0 –0.010 VDD –0.000008 AVDD = +24V ±20mA EXTERNAL RSET –0.015 AVSS = ––2440V TEMPERA25TURE ±(2°C4m)A EXTER10N5AL RSET 07268-142 –2–10 –8 –6 –4 –2TIME0 (ms)2 4 6 8 10–0.000010 07268-145 Figure 42. Gain Error vs. Temperature, External RSET Sense Resistor Figure 45. VDD and Output Current (IOUT) vs. Time-On Power-Up 0.08 0 +4mA TO +20mA INTERNAL RSET 0.06 00mmAA TTOO ++2204mmAA IINNTTEERRNNAALL RRSSEETT –2 ±20mA INTERNAL RSET 0.04 ±24mA INTERNAL RSET –4 SR) 0.02 –6 F % N ERROR ( –0.020 I (µA)OUT–1–08 GAI –0.04 –12 –0.06 –14 –0.08 AVDD = +24V –16 –0.10 AVSS = ––2440V TEMPERA25TURE (°C) 105 07268-143 –18–2 –1 0 1 2 TIME3 (µs)4 5 6 7 8 07268-146 Figure 43. Gain Error vs. Temperature, Internal RSET Sense Resistor Figure 46. Output Current (IOUT) vs. Time-On Output Enable 1.4 0.025 1.2 AVDD COMPLIANCE 0.020 1.0 V) NCE ( 0.8 T (A)0.015 COMPLIA 0.6 AVSS COMPLIANCE CURREN0.010 0.4 0.005 0.2 0 –40 TEMPERA25TURE (°C) 105 07268-144 0–12 –6 1 8 14 21TIM28E (µ3s4) 41 48 54 61 68 07268-147 Figure 44. Output Compliance vs. Temperature Figure 47. 4 mA to 20 mA Output Current Step Tested When IOUT = 10.8 mA, ±24 mA Range Selected Rev. F | Page 20 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 3000 6 5 2500 AIDD 4 2000 3 A) DI (µA)CC1500 DVCC = 5V /AI (mDDSS 21 AI 1000 0 –1 500 –2 DVCC = 3V AISS 0 –3 0 0.5 1.0 1.5 2L.O0GIC2 .L5EVE3.L0 (V)3.5 4.0 4.5 5.0 07268-148 ±10.8 ±15A.0VDD/AVSS (V±2)4.0 ±26.4 07268-150 Figure 48. DICC vs. Logic Input Voltage Figure 50. AIDD/AISS vs. AVDD/AVSS, IOUT = 0 mA 6 5 AIDD 4 3 A) m (S 2 S AI /D 1 D AI 0 –1 –2 AISS –3 ±10.8 ±15A.0VDD/AVSS (V±2)4.0 ±26.4 07268-149 Figure 49. AIDD/AISS vs. AVDD/AVSS, VOUT = 0 V Rev. F | Page 21 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet TERMINOLOGY Total Unadjusted Error (TUE) Zero-Scale Error TUE is a measure of the output error taking all the various Zero-scale error is the deviation of the actual zero-scale analog errors into account: INL error, offset error, gain error, and output from the ideal zero-scale output. Zero-scale error is output drift over supplies, temperature, and time. TUE is expressed in millivolts (mV). expressed as a percentage of full-scale range (% FSR). Zero-Scale TC Relative Accuracy or Integral Nonlinearity (INL) Zero-scale TC is a measure of the change in zero-scale error INL is a measure of the maximum deviation, in % FSR, from a with a change in temperature. Zero-scale error TC is expressed straight line passing through the endpoints of the output driver in ppm FSR/°C. transfer function. A typical INL vs. input voltage plot can be Offset Error seen in Figure 5. Offset error is a measurement of the difference between the Bipolar Zero Error actual VOUT and the ideal VOUT, expressed in millivolts (mV) Bipolar zero error is the deviation of the actual vs. ideal half-scale in the linear region of the transfer function. It can be negative output of 0 V/0 mA with a bipolar range selected. A plot of or positive. bipolar zero error vs. temperature can be seen in Figure 10. Output Voltage Settling Time Bipolar Zero Temperature Coefficient (TC) Output voltage settling time is the amount of time it takes for Bipolar zero TC is a measure of the change in the bipolar zero error the output to settle to a specified level for a half-scale input change. with a change in temperature. It is expressed in ppm FSR/°C. Slew Rate Full-Scale Error The slew rate of a device is a limitation in the rate of change of the Full-scale error is the deviation of the actual full-scale analog output voltage. The output slewing speed is usually limited by the output from the ideal full-scale output. Full-scale error is slew rate of the amplifier used at its output. Slew rate is measured expressed as a percentage of full-scale range (% FSR). from 10% to 90% of the output signal and is expressed in V/µs. Full-Scale Temperature Coefficient (TC) Current Loop Voltage Compliance Full-scale TC is a measure of the change in the full-scale error Current loop voltage compliance is the maximum voltage at with a change in temperature. It is expressed in ppm FSR/°C. the IOUT pin for which the output current is equal to the programmed value. Gain Error Gain error is a measure of the span error of the output. It is the Power-On Glitch Energy deviation in slope of the output transfer characteristic from the Power-on glitch energy is the impulse injected into the analog ideal expressed in % FSR. A plot of gain error vs. temperature output when the AD5750/AD5750-1/AD5750-2 are powered on. can be seen in Figure 11. It is specified as the area of the glitch in nV-sec. Gain Error Temperature Coefficient (TC) Power Supply Rejection Ratio (PSRR) Gain error TC is a measure of the change in gain error with PSRR indicates how the output is affected by changes in the changes in temperature. Gain error TC is expressed in ppm power supply voltage. FSR/°C. Rev. F | Page 22 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 THEORY OF OPERATION The AD5750/AD5750-1/AD5750-2 are single-channel, precision Figure 51 and Figure 52 show a typical configuration of the voltage/current output drivers with hardware- or software- AD5750/AD5750-1/AD5750-2 in software mode and in hardware programmable output ranges. The software ranges are configured mode, respectively, in an output module system. The HW SELECT via an SPI-/MICROWIRE-compatible serial interface. The analog pin selects whether the part is configured in software or hardware input to the AD5750/AD5750-1/AD5750-2 is provided from a mode. The analog input to the AD5750/AD5750-1/AD5750-2 is low voltage, single-supply DAC and is internally conditioned to provided from a low voltage, single-supply DAC, such as the provide the desired output current/voltage range. Analog input AD506x or AD566x, which provides an output range of 0 V to ranges available are 0 V to 2.5 V (AD5750-1/AD5750-2) or 0 V 4.096 V. The supply and reference for the DAC, as well as the to 4.096 V (AD5750). reference for the AD5750/AD5750-1/AD5750-2, can be supplied from a reference such as the ADR392. The AD5750/AD5750-1/ The output current range is programmable across five current AD5750-2 can operate from supplies up to ±26.4 V. ranges: +4 mA to +20 mA, 0 mA to +20 mA, 0 mA to +24 mA, ±20 mA, and ±24 mA. SOFTWARE MODE The voltage output is provided from a separate pin that can be In current mode, software-selectable output ranges include configured to provide 0 V to +5 V, 0 V to +10 V, ±5 V, or ±10 V ±20 mA, ±24 mA, 0 mA to +20 mA, +4 mA to +20 mA, and output ranges. An overrange of 20% is available on the voltage 0 mA to +24 mA. ranges. An overrange of 2% is available on the 4 mA to 20 mA, In voltage mode, software-selectable output ranges include 0 V 0 mA to 20 mA, and 0 mA to 24 mA current ranges. The current to +5 V, 0 V to +10 V, ±5 V, and ±10 V. and voltage outputs are available on separate pins. Only one output can be enabled at one time. The output range is selected by programming the R3 to R0 bits in the control register (see Table 7 and Table 8). VDD AGND VSS ADP1720 AD5750/ AVDD GND AVSS AD5750-1/ VSENSE+ AD5750-2 ADR392 VREF VSENSE– VDD REFIN VOUT SCLK RANGE VOUT SDI/DIN AD506x VIN SCALE 0±V5VT, O±1 +05VV, 0VTO +10V, MCU SDO AD566x SYNC1 IOUT RANGE IOUT SCALE 0mATO +20mA, 0mATO +24mA, SCLK +4mATO +20mA VOUT SHORTFAULT ±20mA, ±24mA SDIN IOUT OPENFAULT SERIAL OVERTEMPFAULT SDO INTERFACE SYNC STATUS REGISTER HW SELECT FAULT 07268-045 Figure 51. Typical System Configuration in Software Mode (Pull-Up Resistors Not Shown for Open-Drain Outputs) Rev. F | Page 23 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet VDD AGND VSS ADP1720 AADD55775500/-1/ AVDD GND AVSS VSENSE+ AD5750-2 ADR392 VREF VSENSE– VDD REFIN VOUT SCLK RANGE VOUT SDI/DIN SCALE 0VTO +5V, 0VTO +10V, AD506x VIN ±5V, ±10V SDO MCU AD566x SYNC1 IOUT RANGE IOUT SCALE 0mATO +20mA, DVCC HW SELECT 0mATO +24mA, +4mATO +20mA ±20mA, ±24mA OUTEN R3 R2 OUTPUT RANGE SELECT PINS R1 TEMP VFAULT IFAULT R0 07268-046 Figure 52. Typical System Configuration in Hardware Mode Using Internal DAC Reference (Pull-Up Resistors Not Shown for Open-Drain Outputs) Table 6. Suggested Parts for Use with AD5750, AD5750-1, and AD5750-2 DAC Reference Power Accuracy Description AD5660 Internal ADP17201 12-bit INL Midend system, single channel, internal reference AD5664R Internal Not applicable Not applicable Midend system, quad channel, internal reference AD5668 Internal Not applicable Not applicable Midend system, octal channel, internal reference AD5060 ADR434 ADP17201 16-bit INL High end system, single channel, external reference AD5064 ADR434 Not applicable Not applicable High end system, quad channel, external reference AD5662 ADR3922 ADR3922 12-bit INL Midend system, single channel, external reference AD5664 ADR3922 Not applicable Not applicable Midend system, quad channel, external reference 1 The input range of the ADP1720 is up to 28 V. 2 The input range of the ADR392 is up to 15 V. Rev. F | Page 24 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 CURRENT OUTPUT ARCHITECTURE The current and voltage are output on separate pins and cannot be output simultaneously. This allows the user to tie both the The voltage input from the analog input VIN pin (0 V to 4.096 V current and voltage output pins together and configure the end for AD5750 and 0 V to 2.5 V for the AD5750-1/AD5750-2) is system as a single channel output. either converted to a current (see Figure 53), which is then mirrored to the supply rail so that the application simply sees Driving Large Capacitive Loads a current source output with respect to an internal reference The voltage output amplifier is capable of driving capacitive loads voltage, or it is buffered and scaled to output a software-selectable of up to 1 μF with the addition of a nonpolarized compensation unipolar or bipolar voltage range (see Figure 54). The reference capacitor between the COMP1 and COMP2 pins. is used to provide internal offsets for range and gain scaling. Without the compensation capacitor, up to 20 nF capacitive loads The selectable output range is programmable through the can be driven. Care should be taken to choose an appropriate digital interface. value for the C capacitor. This capacitor, while allowing the COMP RANGE DECODE FROM INTERFACE R2 VDD R3 AD5750/AD5750-1/AD5750-2 to drive higher capacitive loads and reduce overshoot, increases the settling time of the part and, therefore, affects the bandwidth of the system. Considered VIN IOUT RANGE REXT1 values of this capacitor should be in the range 100 pF to 4 nF, VREF SCALING RSET IROEUXTT2 depending on the trade-off required between settling time, overshoot, and bandwidth. Vx POWER-ON STATE OF AD5750/AD5750-1/AD5750-2 R1 VSS R4 On power-up, the AD5750/AD5750-1/AD5750-2 sense whether hardware or software mode is loaded and set the power-up OPEINO UFATULT 07268-047 cIno nsodfittwioanrse aScPcIo rmdoindgel,y t.h e power-up state of the output is Figure 53. Current Output Configuration dependent on the state of the CLEAR pin. If the CLEAR pin is RANGE DECODE FROM INTERFACE pulled high, the part powers up, driving an active 0 V on the VSENSE+ output. If the CLEAR pin is pulled low, the part powers up with VIN (0V TO 4.096V) VOUT RANGE the voltage output channel in tristate mode. In both cases, the VREF SCALING VOUT current output channel powers up in the tristate condition (0 mA). VOUT SHORT FAULT This allows the voltage and current outputs to be connected VSENSE– 07268-048 together, if desired. Figure 54. Voltage Output To put the part into normal operation, the user must set the OUTEN bit in the control register to enable the output and, in DRIVING INDUCTIVE LOADS the same write, set the output range configuration using the R3 When driving inductive or poorly defined loads, connect a 0.01 μF to R0 range bits. If the CLEAR pin is still high (active) during capacitor between IOUT and GND. This ensures stability with this write, the part automatically clears to its normal clear state loads beyond 50 mH. There is no maximum capacitance limit. as defined by the programmed range and by the CLRSEL pin or The capacitive component of the load may cause slower settling. the CLRSEL bit (see the Asynchronous Clear (CLEAR) section Voltage Output Amplifier for more details). To operate the part in normal mode, take the CLEAR pin low. The voltage output amplifier is capable of generating both unipolar and bipolar output voltages. It is capable of driving a load of 1 kΩ The CLEAR pin is typically driven directly from a microcontroller. in parallel with 1.2 μF (with an external compensation capacitor In cases where the power supply for the AD5750/AD5750-1/ on the COMP1 and COMP2 pins). The source and sink capabilities AD5750-2 supply may be independent of the microcontroller of the output amplifier can be seen in Figure 16. The slew rate power supply, connect a weak pull-up resistor to DV or a pull- CC is 2 V/μs. down resistor to ground to ensure that the correct power-up condition is achieved independent of the microcontroller. A Internal to the device, there is a 2.5 MΩ resistor connected 10 kΩ pull-up/pull-down resistor on the CLEAR pin should be between the VOUT and VSENSE+ pins and, similarly, between sufficient for most applications. the VSENSE− pin and the internal device ground. If a fault condition occurs, these resistors act to protect the AD5750/ If hardware mode is selected, the part powers up to the conditions AD5750-1/AD5750-2 by ensuring that the amplifier loop is closed defined by the R3 to R0 range bits and the status of the OUTEN so that the part does not enter into an open-loop condition. or CLEAR pin. It is recommended to keep the output disabled when powering up the part in hardware mode. The VSENSE− pin can work in a common-mode range of ±3 V with respect to the remote load ground point. Rev. F | Page 25 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet DEFAULT REGISTERS AT POWER-ON OUTEN The AD5750/AD5750-1/AD5750-2 power-on-reset circuit In software mode, the output can be enabled or disabled using ensures that all registers are loaded with zero code. the OUTEN bit in the control register. When the output is disabled, both the current and voltage channels go into tristate. In software SPI mode, the part powers up with all outputs The user must set the OUTEN bit to enable the output and disabled (OUTEN bit = 0). The user must set the OUTEN bit in simultaneously set the output range configuration. the control register to enable the output and, in the same write, to set the output range configuration using the R3 to R0 bits. In hardware mode, the output can be enabled or disabled using the OUTEN pin. When the output is disabled, both the current If hardware mode is selected, the part powers up to the and voltage channels go into tristate. The user must write to the conditions defined by the R3 to R0 bits and the status of the OUTEN pin to enable the output. It is recommended that the OUTEN pin. It is recommended to keep the output disabled output be disabled when changing the ranges. when powering up the part in hardware mode. SOFTWARE CONTROL RESET FUNCTION Software control is enabled by connecting the HW SELECT pin In software mode, the part can be reset using the RESET pin to ground. In software mode, the AD5750/AD5750-1/AD5750-2 (active low) or the reset bit (reset = 1). A reset disables both the are controlled over a versatile 3-wire serial interface that operates at current and voltage outputs to their power-on condition. The clock rates up to 50 MHz. It is compatible with SPI, QSPI™, user must write to the OUTEN bit to enable the output and, in MICROWIRE, and DSP standards. the same write, to set the output range configuration. The RESET Input Shift Register pin is a level-sensitive input; the part stays in reset mode as long as the RESET pin is low. The reset bit clears to 0 following a The input shift register is 16 bits wide. Data is loaded into the reset command to the control register. device MSB first as a 16-bit word under the control of the serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. In hardware mode, there is no reset. If using the part in hardware The input shift register consists of 16 control bits, as shown in mode, tie the RESET pin high. Table 7. The timing diagram for this write operation is shown in Figure 2. The first three bits of the input shift register are used to set the hardware address of the AD5750/AD5750-1/AD5750-2 device on the printed circuit board (PCB). Up to eight devices can be addressed per board. Bit D11, Bit D1, and Bit D0 must always be set to 0 during any write sequence. Table 7. Input Shift Register Contents for a Write Operation—Control Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 R/W 0 R3 R2 R1 R0 CLRSEL OUTEN Clear RSET Reset 0 0 Table 8. Input Shift Register Descriptions Bit Description A2, A1, A0 Used in association with the AD2, AD1, and AD0 external pins to determine which part is being addressed by the system controller. A2 A1 A0 Function 0 0 0 Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 0. 0 0 1 Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 1. 0 1 0 Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 0. 0 1 1 Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 1. 1 0 0 Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 0. 1 0 1 Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 1. 1 1 0 Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 0. 1 1 1 Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 1. R/W Indicates a read from or a write to the addressed register. Rev. F | Page 26 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 Bit Description R3, R2, R1, R0 Selects the output configuration in conjunction with RSET. RSET R3 R2 R1 R0 Output Configuration 0 0 0 0 0 4 mA to 20 mA (external 15 kΩ current sense resistor). 0 0 0 0 1 0 mA to 20 mA (external 15 kΩ current sense resistor). 0 0 0 1 0 0 mA to 24 mA (external 15 kΩ current sense resistor). 0 0 0 1 1 ±20 mA (external 15 kΩ current sense resistor). 0 0 1 0 0 ±24 mA (external 15 kΩ current sense resistor). 0 0 1 0 1 0 V to 5 V. 0 0 1 1 0 0 V to 10 V. 0 0 1 1 1 ±5 V. 0 1 0 0 0 ±10 V. 0 1 0 0 1 0 V to 6.0 V (20% overrange). 0 1 0 1 0 0 V to 12.0 V (20% overrange). 0 1 0 1 1 ±6.0 V (20% overrange). 0 1 1 0 0 ±12.0 V (20% overrange). 0 1 1 0 1 ±2.5 V. 0 1 1 1 0 Not applicable; if selected, output drives between 0 V and −1 V. 0 1 1 1 1 Not applicable; if selected, output drives between 0 V and −1 V. 1 0 0 0 0 4 mA to 20 mA (internal current sense resistor). 1 0 0 0 1 0 mA to 20 mA (internal current sense resistor). 1 0 0 1 0 0 mA to 24 mA (internal current sense resistor). 1 0 0 1 1 ±20 mA (internal current sense resistor). 1 0 1 0 0 ±24 mA (internal current sense resistor). 1 0 1 0 1 0 V to 5 V. 1 0 1 1 0 0 V to 10 V. 1 0 1 1 1 ±5 V. 1 1 0 0 0 ±10 V. 1 1 0 0 1 0 V to 6.0 V (20% overrange). 1 1 0 1 0 0 V to 12.0 V (20% overrange). 1 1 0 1 1 ±6.0 V (20% overrange). 1 1 1 0 0 ±12.0 V (20% overrange). 1 1 1 0 1 3.92 mA to 20.4 mA (internal current sense resistor). 1 1 1 1 0 0 mA to 20.4 mA (internal current sense resistor). 1 1 1 1 1 0 mA to 24.5 mA (internal current sense resistor). CLRSEL Sets clear mode to zero scale or midscale. See the Asynchronous Clear (CLEAR) section. CLRSEL Function 0 Clear to 0 V. 1 Clear to midscale in unipolar mode; clear to zero scale in bipolar mode. OUTEN Output enable bit. This bit must be set to 1 to enable the outputs. Clear Software clear bit, active high. RSET Select internal/external current sense resistor. RSET Function 1 Select internal current sense resistor; used with R3 to R0 bits to select range. 0 Select external current sense resistor; used with R3 to R0 bits to select range. Reset Resets the part to its power-on state. Rev. F | Page 27 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet Status Bit Read Operation HARDWARE CONTROL A read of the status bits can be initiated as part of a normal write Hardware control is enabled by connecting the HW SELECT operation. The read is activated by selecting the correct device pin to DV . In this mode, the R3, R2, R1, and R0 pins, in CC address (A2, A1, A0) and then setting the R/W bit to 1. By conjunction with the RSET pin, are used to configure the default, the SDO pin is disabled. After having addressed the output range per Table 8. AD5750/AD5750-1/AD5750-2 and setting R/W to 1 the SDO In hardware mode, there is no status register. The fault conditions pin is enabled and data is clocked out on the 5th rising edge of (open circuit, short circuit, and overtemperature) are available SCLK. After all the data has been clocked out on SDO, a rising on the IFAULT, VFAULT, and TEMP pins. If any one of these edge on SYNC disables (tristates) the SDO pin again. Status fault conditions are set, a low is asserted on the specific fault pin. register data (see Table 9) and control register data are both IFAULT, VFAULT, and TEMP are open-drain outputs and, available during the same read cycle. Data contained in Bit D10 therefore, can be connected together to allow the user to generate to Bit D0 of the write operation are still valid and can be used to one interrupt to the system controller to communicate a fault. change the operating mode of the AD5750/AD5750-1/AD5750-2 If hardwired in this way, it is not possible to isolate which fault if required. occurred in the system. The status bits comprise three read-only bits. They are used to TRANSFER FUNCTION notify the user of specific fault conditions that occur, such as an The AD5750/AD5750-1/AD5750-2 consist of an internal signal open circuit or short circuit on the output, an overtemperature conditioning block that maps the analog input voltage to a error, or an interface error. If any of these fault conditions occur, programmed output range. The available analog input ranges are a hardware FAULT is also asserted low, which can be used as a 0 V to 4.096 V (AD5750) and 0 V to 2.5 V (AD5750-1/AD5750-2). hardware interrupt to the controller. For all ranges, both current and voltage, the AD5750, AD5750-1, See the Detailed Description of Features section for a full and AD5750-2 implement a straight linear mapping function, explanation of fault conditions. where 0 V maps to the lower end of the selected range and 4.096 V (or 2.5 V for AD5750-1/AD5750-2) maps to the upper end of the selected range. Table 9. Input Shift Register Contents for a Read Operation—Status Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1 0 R3 R2 R1 R0 CLRSEL OUTEN RSET PEC OVER IOUT VOUT Error TEMP Fault Fault Table 10. Status Bit Options Bit Description PEC Error This bit is set if there is an interface error detected by CRC-8 error checking. See the Detailed Description of Features section. OVER TEMP This bit is set if the AD5750/AD5750-1/AD5750-2 core temperature exceeds approximately 150°C. IOUT Fault This bit is set if there is an open circuit on the IOUT pin. VOUT Fault This bit is set if there is a short circuit on the VOUT pin. Rev. F | Page 28 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 DETAILED DESCRIPTION OF FEATURES OUTPUT FAULT ALERT—SOFTWARE MODE circuit or insufficient power supply voltage. The internal circuitry that develops the fault output avoids using a In software mode, the AD5750/AD5750-1/AD5750-2 are equipped comparator with window limits because this requires an with one FAULT pin; this is an open-drain output allowing several actual output error before the fault output becomes active. AD5750/AD5750-1/AD5750-2 devices to be connected together Instead, the signal is generated when the internal amplifier to one pull-up resistor for global fault detection. In software mode, in the output stage has less than approximately 1 V of the FAULT pin is forced active low by any one of the following remaining drive capability. Thus, the fault output activates fault scenarios: slightly before the compliance limit is reached. Because the • The voltage at IOUT attempts to rise above the compliance comparison is made within the feedback loop of the output range due to an open-loop circuit or insufficient power supply amplifier, the output accuracy is maintained by its open- voltage. The internal circuitry that develops the fault output loop gain, and an output error does not occur before the avoids using a comparator with window limits because this fault output becomes active. If this fault is detected, the requires an actual output error before the fault output becomes IFAULT pin is forced low. active. Instead, the signal is generated when the internal • A short is detected on the voltage output pin (VOUT). The amplifier in the output stage has less than approximately short-circuit current is limited to 15 mA. If this fault is 1 V of remaining drive capability. Thus, the fault output detected, the VFAULT pin is forced low. activates slightly before the compliance limit is reached. • The core temperature of the AD5750/AD5750-1/AD5750-2 Because the comparison is made within the feedback loop exceeds approximately 150°C. If this fault is detected, the of the output amplifier, the output accuracy is maintained TEMP pin is forced low. by its open-loop gain, and an output error does not occur VOLTAGE OUTPUT SHORT-CIRCUIT PROTECTION before the fault output becomes active. • A short is detected on the voltage output pin (VOUT). The Under normal operation, the voltage output sinks and sources short-circuit current is limited to 15 mA. up to 12 mA and maintains specified operation. The maximum • An interface error is detected due to PEC failure. See the current that the voltage output delivers is 15 mA; this is the Packet Error Checking section. short-circuit current. • The core temperature of the AD5750/AD5750-1/AD5750-2 ASYNCHRONOUS CLEAR (CLEAR) exceeds approximately 150°C. CLEAR is an active high clear that allows the output to be OUTPUT FAULT ALERT—HARDWARE MODE cleared to either zero-scale code or midscale code and is user- selectable via the CLRSEL pin or the CLRSEL bit of the input shift In hardware mode, the AD5750/AD5750-1/AD5750-2 are register, as described in Table 8. (The clear select feature is a equipped with three fault pins: VFAULT, IFAULT, and TEMP. logical OR function of the CLRSEL pin and the CLRSEL bit). These are open-drain outputs allowing several AD5750/AD5750-1/ The current loop output clears to the bottom of its programmed AD5750-2 devices to be connected together to one pull-up resistor range. When the CLEAR signal is returned low, the output returns for global fault detection. In hardware control mode, these fault to its programmed value or to a new programmed value. A clear pins are forced active by any one of the following fault scenarios: operation can also be performed via the clear command in the • An open circuit is detected. The voltage at IOUT attempts control register (see Table 11). to rise above the compliance range, due to an open-loop Table 11. CLRSEL Options Output Clear Value CLRSEL Unipolar Output Voltage Range Unipolar Current Output Range Bipolar Output Range Bipolar Current Output Range 0 0 V Zero scale; for example, Negative full scale Zero scale; for example, 4 mA on the 4 mA to 20 mA range, −24 mA on the ±24 mA range 0 mA on the 0 mA to 20 mA range 1 Midscale Midscale; for example, 0 V Midscale; for example, 12 mA on the 4 mA to 20 mA range, 0 mA on the ±24 mA range 10 mA on the 0 mA to 20 mA range Rev. F | Page 29 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet EXTERNAL CURRENT SETTING RESISTOR PACKET ERROR CHECKING Referring to Figure 1, R is an internal sense resistor and is To verify that data has been received correctly in noisy environ- SET part of the voltage-to-current conversion circuitry. The nominal ments, the AD5750/AD5750-1/AD5750-2 offer the option of error value of the internal current sense resistor is 15 kΩ. To allow for checking based on an 8-bit cyclic redundancy check (CRC-8). overrange capability in current mode, the user can also select The device controlling the AD5750/AD5750-1/AD5750-2 should the internal current sense resistor to be 14.7 kΩ, giving a nominal generate an 8-bit frame check sequence using the following polynomial: 2% overrange capability. This feature is available in the 0 mA to +20 mA, +4 mA to +20 mA, and ±20 mA current ranges. C(x) = x + x + x + 1 8 2 1 The stability of the output current value over temperature is This is added to the end of the data-word, and 24 data bits are dependent on the stability of the value of RSET. As a method of sent to the AD5750/AD5750-1/AD5750-2 before taking SYNC improving the stability of the output current over temperature, high. If the AD5750/AD5750-1/AD5750-2 receive a 24-bit data an external low drift resistor can be connected to the REXT1 frame, the parts perform the error check when SYNC goes high. and REXT2 pins of the AD5750/AD5750-1/AD5750-2, which If the check is valid, the data is written to the selected register. If can be used instead of the internal resistor. The external resistor the error check fails, the FAULT pin goes low, and Bit D3 of the is selected via the input shift register. If the external resistor option status register is set. After reading this register, this error flag is is not used, leave the REXT1 and REXT2 pins floating. cleared automatically, and the FAULT pin goes high again. PROGRAMMABLE OVERRANGE MODES UPDATE ON SYNC HIGH The AD5750/AD5750-1/AD5750-2 contain an overrange mode SYNC for most of the available ranges. The overranges are selected by configuring the R3, R2, R1, and R0 bits (or pins) accordingly. SCLK In voltage mode, the overranges are typically 20%, providing D15 D0 (MSB) (LSB) programmable output ranges of 0 V to +6 V, 0 V to +12 V, ±6 V, SDIN 16-BIT DATA and ±12 V. The analog input remains the same. 16-BIT DATA TRANSER—NO ERROR CHECKING In current mode, the overranges are typically 2%. In current mode, the overrange capability is available on only three ranges, UPDATE AFTER SYNC HIGH 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. For these ONLY IF ERROR CHECK PASSED SYNC ranges, the analog input also remains the same (0 V to 4.096 V for the AD5750, and 0 V to 2.5 V for the AD5750-1/AD5750-2). SCLK D23 D8 (MSB) (LSB) D7 D0 SDIN 16-BIT DATA 8-BIT FCS FAULT 16-BIT DATA TRANSER WITH ERROR ECFRHAREUOCLRKT ICGNHGOEECSK L FOAWIL ISF 07268-049 Figure 55. PEC Error Checking Timing Rev. F | Page 30 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 APPLICATIONS INFORMATION TRANSIENT VOLTAGE PROTECTION LAYOUT GUIDELINES The AD5750/AD5750-1/AD5750-2 contain ESD protection In any circuit where accuracy is important, careful consideration diodes that prevent damage from normal handling. The industrial of the power supply and ground return layout helps to ensure the control environment can, however, subject I/O circuits to much rated performance. The PCB on which the AD5750/AD5750-1/ higher transients. To protect the AD5750/AD5750-1/AD5750-2 AD5750-2 are mounted should be designed so that the AD5750/ AD5750-1/AD5750-2 lie on the analog plane. from excessively high voltage transients, external power diodes and a surge current limiting resistor may be required, as shown The AD5750/AD5750-1/AD5750-2 should have ample supply in Figure 56. The constraint on the resistor value is that during bypassing of 10 μF in parallel with 0.1 μF on each supply located normal operation the output level at IOUT must remain within as close to the package as possible, ideally right up against the its voltage compliance limit of AVDD − 2.75 V and the two device. The 10 μF capacitors are the tantalum bead type. The protection diodes and resistor must have appropriate power 0.1 μF capacitor should have low effective series resistance ratings. Further protection can be added with transient voltage (ESR) and low effective series inductance (ESI) such as the suppressors, if needed. common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to AVDD internal logic switching. In systems where there are many devices on one board, it is often AVDD useful to provide some heat sinking capability to allow the power AD5750/ AD5750-1/ RP to dissipate easily. AD5750-2 IOUT RLOAD The AD5750/AD5750-1/AD5750-2 have an exposed paddle AVSS 07268-050 btheen peaartht. Fthoer dopevtiimceu. mC opnenrfeocrtm thanisc ep,a udsdel sep teoc itahle c oAnVsiSdS esuraptpiolny so tfo Figure 56. Output Transient Voltage Protection design the motherboard and to mount the package. For enhanced thermal, electrical, and board level performance, solder the THERMAL CONSIDERATIONS exposed paddle on the bottom of the package to the corresponding It is important to understand the effects of power dissipation thermal land paddle on the PCB. Design thermal vias into the on the package and how it affects junction temperature. The PCB land paddle area to further improve heat dissipation. internal junction temperature should not exceed 125°C. The The AV plane on the device can be increased (as shown in AD5750/AD5750-1/AD5750-2 are packaged in a 32-lead, 5 mm × SS Figure 57) to provide a natural heat sinking effect. 5 mm LFCSP package. The thermal impedance, θ , is 42°C/W. It JA is important that the devices are not being operated under AD5750/ AD5750-1/ conditions that cause the junction temperature to exceed its AD5750-2 junction temperature. Worst-case conditions occur when the AD5750/AD5750-1/ AD5750-2 are operated from the maximum AV (26.4 V) and DD are driving the maximum current (24 mA) directly to ground. The quiescent current of the AD5750/AD5750-1/AD5750-2 AVSS PLANE should also be taken into account, nominally ~4 mA. The following calculations estimate maximum power dissipation under these worst-case conditions and determine the maximum BOARD 07268-051 ambient temperature: Figure 57. Paddle Connection to Board Power Dissipation = 26.4 V × 28 mA = 0.7392 W Temperature Increase = 42°C × 0.7392 W = 31°C Maximum Ambient Temperature = 125°C − 31°C = 94°C These figures assume that proper layout and grounding techniques are followed to minimize power dissipation, as outlined in the Layout Guidelines section. Rev. F | Page 31 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet GALVANICALLY ISOLATED INTERFACE MICROPROCESSOR INTERFACING In many process control applications, it is necessary to provide Microprocessor interfacing to the AD5750/AD5750-1/AD5750-2 an isolation barrier between the controller and the unit being is via a serial bus that uses a protocol that is compatible with controlled to protect and isolate the controlling circuitry from microcontrollers and DSP processors. The communication any hazardous common-mode voltages that may occur. The channel is a 3-wire (minimum) interface consisting of a clock iCoupler® family of products from Analog Devices, Inc., provides signal, a data signal, and a SYNC signal. The AD5750/AD5750-1/ voltage isolation in excess of 5.0 kV. The serial loading structure AD5750-2 require a 16-bit data-word with data valid on the of the AD5750/AD5750-1/AD5750-2 makes it ideal for isolated falling edge of SCLK. interfaces because the number of interface lines is kept to a minimum. Figure 58 shows a 4-channel isolated interface using an ADuM1400. For further information, visit http://www.analog.com/icouplers. CONTROLLER ADuM14001 E E SERIAL VIA OD OD VOA TO CLOCK OUT NC EC SCLK E E D E SERIAL VIB OD OD VOB TO DATA OUT NC EC SDIN E E E D SYNC OUT VIC COD COD VOC TSOYNC N E E E D E CONTROL OUT VID COD COD VOD TCOLEAR N E 1ADDITIONAL PINS OMITTED FOR CLAERITY. D 07268-052 Figure 58. Isolated Interface Rev. F | Page 32 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 OUTLINE DIMENSIONS 5.10 0.30 5.00 SQ 0.25 PIN 1 4.90 0.18 INDICATOR PIN 1 25 32 INDICATOR 24 1 0.50 BSC EXPOSED 3.25 PAD 3.10 SQ 2.95 17 8 0.50 16 9 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 THE PIN CONFIGURATION AND 0.05 MAX FUNCTION DESCRIPTIONS 0.70 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY 0.08 SEATING 0.20 REF PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A Figure 59. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Analog Input External Temperature Package Model1 TUE Accuracy (%) Range (V) Reference (V) Range Package Description Option AD5750ACPZ ±0.3 0 to 4.096 4.096 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-7 AD5750ACPZ-REEL7 ±0.3 0 to 4.096 4.096 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-7 AD5750BCPZ ±0.1 0 to 4.096 4.096 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-7 AD5750BCPZ-REEL7 ±0.1 0 to 4.096 4.096 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-7 EVAL-AD5750EBZ Evaluation Board AD5750-1ACPZ ±0.3 0 to 2.5 1.25 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-7 AD5750-1ACPZ-REEL ±0.3 0 to 2.5 1.25 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-7 AD5750-1ACPZ-REEL7 ±0.3 0 to 2.5 1.25 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-7 AD5750-1BCPZ ±0.1 0 to 2.5 1.25 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-7 AD5750-1BCPZ-REEL ±0.1 0 to 2.5 1.25 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-7 AD5750-1BCPZ-REEL7 ±0.1 0 to 2.5 1.25 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-7 AD5750-2BCPZ ±0.1 0 to 2.5 2.5 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-7 AD5750-2BCPZ-RL7 ±0.1 0 to 2.5 2.5 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-7 1 Z = RoHS Compliant Part. Rev. F | Page 33 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet NOTES Rev. F | Page 34 of 36

Data Sheet AD5750/AD5750-1/AD5750-2 NOTES Rev. F | Page 35 of 36

AD5750/AD5750-1/AD5750-2 Data Sheet NOTES ©2009–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07268-0-9/14(F) Rev. F | Page 36 of 36

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5750EBZ AD5750BCPZ AD5750-1ACPZ-REEL AD5750-2BCPZ AD5750ACPZ AD5750-1BCPZ-REEL AD5750ACPZ-REEL7 AD5750-2BCPZ-RL7 AD5750-1ACPZ-REEL7 AD5750-1BCPZ-REEL7 AD5750BCPZ-REEL7 AD5750-1BCPZ AD5750-1ACPZ