Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output DAC with Dynamic Power Control and HART Connectivity Data Sheet AD5737 FEATURES Each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output of the AD5737. 12-bit resolution and monotonicity Dynamic power control for thermal management The AD5737 uses a versatile 3-wire serial interface that operates or external PMOS mode at clock rates of up to 30 MHz and is compatible with standard Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA, SPI, QSPI™, MICROWIRE®, DSP, and microcontroller interface and 0 mA to 24 mA standards. The serial interface also features optional CRC-8 packet ±0.1% total unadjusted error (TUE) maximum error checking, as well as a watchdog timer that monitors activity User-programmable offset and gain on the interface. On-chip diagnostics PRODUCT HIGHLIGHTS On-chip reference: ±10 ppm/°C maximum −40°C to +105°C temperature range 1. Dynamic power control for thermal management. 2. 12-bit performance. APPLICATIONS 3. Quad channel. Process control 4. HART compliant. Actuator control COMPANION PRODUCTS PLCs HART network connectivity Product Family: AD5755, AD5755-1, AD5757, AD5735 HART Modem: AD5700, AD5700-1 GENERAL DESCRIPTION External References: ADR445, ADR02 The AD5737 is a quad-channel current output DAC that Digital Isolators: ADuM1410, ADuM1411 operates with a power supply range from 10.8 V to 33 V. Power: ADP2302, ADP2303 On-chip dynamic power control minimizes package power Additional companion products on the AD5737 product page dissipation by regulating the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation. FUNCTIONAL BLOCK DIAGRAM AVCC 5.0V AVDD AGND +15V SWx VBOOST_x DVDD 7.4VTO 29.5V DGND LDAC DC-TO-DC CONVERTER SCLK SDIN SYNC INDTIEGRITFAALCE IOUT_x SDO + DAC A RSET_x CLEAR CURRENT CHARTx FAULT OUTPUT RANGE ALERT GAIN REG A SCALING AD1 OFFSET REG A AD0 DAC CHANNEL A REFOUT REFERENCE REFIN DAC CHANNEL B DAC CHANNEL C AD5737 DAC CHANNEL D N1.O xT =EAS, B, C, OR D. 10067-101 Figure 1. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5737 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Readback Operation .................................................................. 31 Applications ....................................................................................... 1 Device Features ............................................................................... 33 General Description ......................................................................... 1 Fault Output ................................................................................ 33 Product Highlights ........................................................................... 1 Digital Offset and Gain Control ............................................... 33 Companion Products ....................................................................... 1 Status Readback During a Write .............................................. 33 Functional Block Diagram .............................................................. 1 Asynchronous Clear ................................................................... 33 Revision History ............................................................................... 3 Packet Error Checking ............................................................... 34 Detailed Functional Block Diagram .............................................. 4 Watchdog Timer ......................................................................... 34 Specifications ..................................................................................... 5 Alert Output ................................................................................ 34 AC Performance Characteristics ................................................ 7 Internal Reference ...................................................................... 34 Timing Characteristics ................................................................ 7 External Current Setting Resistor ............................................ 34 Absolute Maximum Ratings .......................................................... 10 HART Connectivity ................................................................... 35 Thermal Resistance .................................................................... 10 Digital Slew Rate Control .......................................................... 35 ESD Caution ................................................................................ 10 Dynamic Power Control ............................................................ 36 Pin Configuration and Function Descriptions ........................... 11 DC-to-DC Converters ............................................................... 36 Typical Performance Characteristics ........................................... 14 AI Supply Requirements—Static .......................................... 37 CC Current Outputs ......................................................................... 14 AI Supply Requirements—Slewing ...................................... 37 CC DC-to-DC Converter ................................................................. 18 External PMOS Mode ................................................................ 38 Reference ..................................................................................... 19 Applications Information .............................................................. 40 General ......................................................................................... 20 Current Output Mode with Internal R ................................ 40 SET Terminology .................................................................................... 21 Precision Voltage Reference Selection ..................................... 40 Theory of Operation ...................................................................... 22 Driving Inductive Loads ............................................................ 40 DAC Architecture ....................................................................... 22 Transient Voltage Protection .................................................... 41 Power-On State of the AD5737 ................................................ 22 Microprocessor Interfacing ....................................................... 41 Serial Interface ............................................................................ 22 Layout Guidelines....................................................................... 41 Transfer Function ....................................................................... 23 Galvanically Isolated Interface ................................................. 42 Registers ........................................................................................... 24 Industrial HART Capable Analog Output Application ........ 43 Enabling the Output ................................................................... 25 Outline Dimensions ....................................................................... 44 Reprogramming the Output Range ......................................... 25 Ordering Guide .......................................................................... 44 Data Registers ............................................................................. 26 Control Registers ........................................................................ 28 Rev. F | Page 2 of 44

Data Sheet AD5737 REVISION HISTORY 5/2017—Rev. E to Rev. F 11/2012—Rev. B to Rev. C Changes to Readback Operation Section ..................................... 31 Changed Thermal Impedance from 20°C/W to 28°C/W .......... 10 Removed Table 30 and Table 31; Renumbered Sequentially ..... 31 Changes to Pin 6 Description ........................................................ 11 Changes to Asynchronous Clear Section ..................................... 33 Changes to DUT_AD1, DUT_AD0 Description, Table 11 ....... 26 Changes to Changes to Packet Error Checking Section and 9/2014—Rev. D to Rev. E Internal Reference Section ............................................................. 34 Changes to Table 3 ............................................................................ 7 Changes to Figure 56 ...................................................................... 36 Changes to Software Register and Status Register Changes to Figure 62 ...................................................................... 41 Descriptions ..................................................................................... 24 Changes to Figure 65 ...................................................................... 43 Changes to Software Register Section, Table 24, and Table 25 ... 30 Updated Outline Dimensions ........................................................ 44 Changes to Status Register Section and Table 34 ........................ 33 Changes to Packet Error Checking Section ................................. 35 5/2012—Rev. A to Rev. B Changes to Companion Products Section ..................................... 1 6/2014—Rev. C to Rev. D Change to Table 5 ............................................................................ 12 Change to Thermal Hysteresis Parameter, Table 1 ....................... 6 Added Industrial HART Capable Analog Output Application Changes to Table 3 ............................................................................ 7 Section and Figure 65, Renumbered Sequentially ...................... 42 Changes to Figure 5 and Added Figure 6; Renumbered Updated Outline Dimensions ........................................................ 43 Sequentially ........................................................................................ 9 Changes to Table 5 .......................................................................... 10 11/2011—Rev. 0 to Rev. A Changes to Figure 33, Figure 34, Figure 35, and Figure 36 ....... 18 Change to Accuracy, External R Parameter in Table 1 ............ 4 SET Changes to Terminology Section .................................................. 21 Changes to Power-On State of the AD5737 Section .................. 21 Changes to Table 8 and Table 9 ..................................................... 24 Changes to Readback Operation Section and Readback Changes to Software Register Section, Table 24, and Table 25 ....... 30 Example Section .............................................................................. 30 Changes to Readback Operation Section and Table 34, Added Table 30 and Table 31; Renumbered Sequentially ...................... 31 7/2011—Revision 0: Initial Version Changes to Status Readback During a Write Section ................. 34 Changes to Packet Error Checking Section ................................. 35 Changes to Table 36 ........................................................................ 37 Changes to Figure 62 ...................................................................... 40 Rev. F | Page 3 of 44

AD5737 Data Sheet DETAILED FUNCTIONAL BLOCK DIAGRAM AVCC 5.0V AVDD AGND +15V SWA VBOOST_A DVDD POWER-ON DC-TO-DC DGND RESET CONVERTER DYNAMIC LDAC POWER 7.4VTO 29.5V VSEN1 VSEN2 CONTROL CLEAR INPUT SHIFT SCLK REGISTER 12 DAC DAC 12 R2 R3 SDIN AND DATA + INPUT DAC A SYNC CONTROL REG A REG A SDO FAULT GAIN REG A IOUT_A OFFSET REG A STATUS REGISTER ALERT WATCHDOG R1 RSET_A TIMER (SPIACTIVITY) CHARTA REFOUT VREF DAC CHANNEL A REFERENCE REFIN BUFFERS IOUT_B, IOUT_C, IOUT_D AD1 DAC CHANNEL B RSET_B, RSET_C, RSET_D AD5737 DAC CHANNEL C CHARTB, CHARTC, CHARTD AD0 DAC CHANNEL D SWB, SWC, SWD VBOOST_B,VBOOST_C,VBOOST_D 10067-001 Figure 2. Rev. F | Page 4 of 44

Data Sheet AD5737 SPECIFICATIONS AV = V = 15 V; DV = 2.7 V to 5.5 V; AV = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSW = 0 V; DD BOOST_x DD CC x REFIN = 5 V; R = 300 Ω; all specifications T to T , unless otherwise noted. L MIN MAX Table 1. Parameter1 Min Typ Max Unit Test Conditions/Comments CURRENT OUTPUT Output Current Ranges 0 24 mA 0 20 mA 4 20 mA Resolution 12 Bits ACCURACY, EXTERNAL R Assumes ideal resistor (see the External Current SET Setting Resistor section for more information) Total Unadjusted Error (TUE) −0.1 ±0.019 +0.1 % FSR TUE Long-Term Stability 100 ppm FSR Drift after 1000 hours, T = 150°C J Relative Accuracy (INL) −0.032 ±0.006 +0.032 % FSR Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.1 ±0.012 +0.1 % FSR Offset Error Drift2 ±4 ppm FSR/°C Gain Error −0.1 ±0.004 +0.1 % FSR Gain TC2 ±3 ppm FSR/°C Full-Scale Error −0.1 ±0.014 +0.1 % FSR Full-Scale TC2 ±5 ppm FSR/°C DC Crosstalk 0.0005 % FSR External R SET ACCURACY, INTERNAL R SET Total Unadjusted Error (TUE)3, 4 −0.14 ±0.022 +0.14 % FSR TUE Long-Term Stability 180 ppm FSR Drift after 1000 hours, T = 150°C J Relative Accuracy (INL) −0.032 ±0.006 +0.032 % FSR Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error3, 4 −0.1 ±0.017 +0.1 % FSR Offset Error Drift2 ±6 ppm FSR/°C Gain Error −0.12 ±0.004 +0.12 % FSR Gain TC2 ±9 ppm FSR/°C Full-Scale Error3, 4 −0.14 ±0.02 +0.14 % FSR Full-Scale TC2 ±14 ppm FSR/°C DC Crosstalk4 −0.011 % FSR Internal R SET OUTPUT CHARACTERISTICS2 Current Loop Compliance Voltage V − V − V BOOST_x BOOST_x 2.4 2.7 Output Current Drift vs. Time Drift after 1000 hours, ¾ scale output, T = 150°C J 90 ppm FSR External R SET 140 ppm FSR Internal R SET Resistive Load 1000 Ω The dc-to-dc converter has been characterized with a maximum load of 1 kΩ, chosen such that compliance is not exceeded; see Figure 31 and the DC-DC MaxV bits in Table 27 DC Output Impedance 100 MΩ DC PSRR 0.02 1 µA/V REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage 4.95 5 5.05 V For specified performance DC Input Impedance 45 150 MΩ Reference Output Output Voltage 4.995 5 5.005 V T = 25°C A Reference TC2 −10 ±5 +10 ppm/°C Rev. F | Page 5 of 44

AD5737 Data Sheet Parameter1 Min Typ Max Unit Test Conditions/Comments Output Noise (0.1 Hz to 10 Hz)2 7 µV p-p Noise Spectral Density2 100 nV/√Hz At 10 kHz Output Voltage Drift vs. Time2 180 ppm Drift after 1000 hours, T = 150°C J Capacitive Load2 1000 nF Load Current 9 mA See Figure 42 Short-Circuit Current 10 mA Line Regulation2 3 ppm/V See Figure 43 Load Regulation2 95 ppm/mA See Figure 42 Thermal Hysteresis2 200 ppm DC-TO-DC CONVERTER Switch Switch On Resistance 0.425 Ω Switch Leakage Current 10 nA Peak Current Limit 0.8 A Oscillator Oscillator Frequency 11.5 13 14.5 MHz This oscillator is divided down to provide the dc-to-dc converter switching frequency Maximum Duty Cycle 89.6 % At 410 kHz dc-to-dc switching frequency DIGITAL INPUTS2 JEDEC compliant Input High Voltage, V 2 V IH Input Low Voltage, V 0.8 V IL Input Current −1 +1 µA Per pin Pin Capacitance 2.6 pF Per pin DIGITAL OUTPUTS2 SDO, ALERT Pins Output Low Voltage, V 0.4 V Sinking 200 µA OL Output High Voltage, V DV − 0.5 V Sourcing 200 µA OH DD High Impedance Leakage −1 +1 µA Current High Impedance Output 2.5 pF Capacitance FAULT Pin Output Low Voltage, V 0.4 V 10 kΩ pull-up resistor to DV OL DD 0.6 V At 2.5 mA Output High Voltage, V 3.6 V 10 kΩ pull-up resistor to DV OH DD POWER REQUIREMENTS AV 9 33 V DD DV 2.7 5.5 V DD AV 4.5 5.5 V CC AI 7 7.5 mA DD DI 9.2 11 mA V = DV , V = DGND, internal oscillator CC IH DD IL running, over supplies AI 1 mA Outputs unloaded, over supplies CC I 5 1 mA Per channel, 0 mA output BOOST Power Dissipation 155 mW AV = 15 V, DV = 5 V, dc-to-dc converter DD DD enabled, outputs disabled 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 Guaranteed by design and characterization; not production tested. 3 For current outputs with internal RSET, the offset, full-scale, and TUE measurements exclude dc crosstalk. The measurements are made with all four channels enabled and loaded with the same code. 4 See the Current Output Mode with Internal RSET section for more information about dc crosstalk. 5 Efficiency plots in Figure 33 through Figure 36 include the IBOOST quiescent current. Rev. F | Page 6 of 44

Data Sheet AD5737 AC PERFORMANCE CHARACTERISTICS AV = V = 15 V; DV = 2.7 V to 5.5 V; AV = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSW = 0 V; DD BOOST_x DD CC x REFIN = 5 V; R = 300 Ω; all specifications T to T , unless otherwise noted. L MIN MAX Table 2. Parameter1 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE, CURRENT OUTPUT Output Current Settling Time 15 µs To 0.1% FSR, 0 mA to 24 mA range See Test Conditions/Comments ms For settling times when using the dc-to-dc con- verter, see Figure 26, Figure 27, and Figure 28 Output Noise (0.1 Hz to 10 Hz 0.15 LSB p-p 12-bit LSB, 0 mA to 24 mA range Bandwidth) Output Noise Spectral Density 0.5 nA/√Hz Measured at 10 kHz, midscale output, 0 mA to 24 mA range 1 Guaranteed by design and characterization; not production tested. TIMING CHARACTERISTICS AV = V = 15 V; DV = 2.7 V to 5.5 V; AV = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSW = 0 V; DD BOOST_x DD CC x REFIN = 5 V; R = 300 Ω; all specifications T to T , unless otherwise noted. L MIN MAX Table 3. Parameter1, 2, 3 Limit at T , T Unit Description MIN MAX t 33 ns min SCLK cycle time 1 t 13 ns min SCLK high time 2 t 13 ns min SCLK low time 3 t 13 ns min SYNC falling edge to SCLK falling edge setup time 4 t 13 ns min 24th/32nd SCLK falling edge to SYNC rising edge (see Figure 54) 5 t 198 ns min SYNC high time following a configuration write 6 5 µs min SYNC high time following a DAC update write t 5 ns min Data setup time 7 t 5 ns min Data hold time 8 t 20 µs min SYNC rising edge to LDAC falling edge (applies to any channel with digital slew 9 rate control enabled; single DAC updated) 5 µs min SYNC rising edge to LDAC falling edge (single DAC updated) t 10 ns min LDAC pulse width low 10 t 500 ns max LDAC falling edge to DAC output response time 11 t See Table 2 µs max DAC output settling time 12 t 10 ns min CLEAR high time 13 t 5 µs max CLEAR activation time 14 t 40 ns max SCLK rising edge to SDO valid 15 t 5 µs min SYNC rising edge to DAC output response time (LDAC = 0) (single DAC updated) 16 t 500 ns min LDAC falling edge to SYNC rising edge 17 t 800 ns min RESET pulse width 18 t 20 µs min SYNC rising edge to next SYNC low (falling edge (digital slew rate control enabled; 19 single DAC updated) 5 µs min SYNC rising edge to next SYNC low (falling edge (digital slew rate control disabled; single DAC updated) 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. 3 See Figure 3, Figure 4, Figure 5, and Figure 7. Rev. F | Page 7 of 44

AD5737 Data Sheet Timing Diagrams t1 SCLK 1 2 24 t6 t3 t2 t4 t5 SYNC t7 t8 t19 SDIN MSB LSB t10 t10 t9 LDAC t17 t12 t11 IOUT_x LDAC = 0 t12 t16 IOUT_x t13 CLEAR t14 IOUT_x RESET t18 10067-002 Figure 3. Serial Interface Timing Diagram SCLK 1 24 1 24 t6 SYNC SDIN MSB LSB MSB LSB INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ SDO MSB LSB UNDEFINED SELECTED REGISTER DATA t15 CLOCKED OUT SEE THE READBACK OPERATION SECTION FOR FURTHER INFORMATION. 10067-003 Figure 4. Readback Timing Diagram (Packet Error Checking Disabled) Rev. F | Page 8 of 44

Data Sheet AD5737 SCLK 1 24 32 1 24 32 t61 SYNC SDIN MSB LSB CRC7 CRC0 MSB LSB CRC7 CRC0 INPUT WORD SPECIFIES 8-BIT CRC NOP 8-BIT CRC REGISTER TO BE READ CONDITION SDO MSB LSB UNDEFINED t15 8-BIT CRC SELECTED REGISTER DATA CLOCKED OUT 1 SAEVEO ITDH SEC RLEKA ADCBTAICVKIT YO P DEURRAITNIGONt6 AANSD I TP AMCAKYE RTE ESRURLOT RIN C AH EPCEKCI NEGRR SOERC TOINO NRSE AFDOBRA FCUKR.THER INFORMATION. 10067-004 Figure 5. Readback Timing Diagram (Packet Error Checking Enabled) LSB MSB 1 2 24 SCLK SYNC SDIN R/W DUT_ DUT_ X X X D15 D14 D1 D0 AD1 AD0 SDO SDO DISABLED ESNDAOB_ STATUS STATUS STATUS STATUS 10067-104 Figure 6. Status Readback During a Write 200µA IOL TO OUTPUT VOH (MIN) OR PIN CL VOL (MAX) 50pF 200µA IOH 10067-005 Figure 7. Load Circuit for SDO Timing Diagrams Rev. F | Page 9 of 44

AD5737 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents of up to A Stresses at or above those listed under Absolute Maximum 100 mA do not cause SCR latch-up. Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these Table 4. or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Operation beyond AV , V to AGND, DGND −0.3 V to +33 V DD BOOST_x the maximum operating conditions for extended periods may AV to AGND −0.3 V to +7 V CC affect product reliability. DV to DGND −0.3 V to +7 V DD Digital Inputs to DGND −0.3 V to DV + 0.3 V or +7 V DD THERMAL RESISTANCE (whichever is less) Digital Outputs to DGND −0.3 V to DVDD + 0.3 V or +7 V Junction-to-air thermal resistance (θJA) is specified for a JEDEC (whichever is less) 4-layer test board. REFIN, REFOUT to AGND −0.3 V to AV + 0.3 V or +7 V DD (whichever is less) Table 5. Thermal Resistance IOUT_x to AGND AGND to VBOOST_x or 33 V if Package Type θJA Unit using the dc-to-dc converter 64-Lead LFCSP (CP-64-3) 28 °C/W SW to AGND −0.3 V to +33 V x AGND, GNDSW to DGND −0.3 V to +0.3 V x ESD CAUTION Operating Temperature Range (T) A Industrial1 −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 125°C J Power Dissipation (T max − T )/θ J A JA Lead Temperature JEDEC industry standard Soldering J-STD-020 1 Power dissipated on chip must be derated to keep the junction temperature below 125°C. Rev. F | Page 10 of 44

Data Sheet AD5737 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D C_ RSET_CRSET_DREFOUTREFINNCCHARTDIGATEDCOMPDCDVBOOST_DNCIOUT_DAGNDNCCHARTCNCIGATEC 4321098765432109 6666655555555554 PIN 1 INDICATOR RSET_B 1 48COMPDCDC_C RSET_A 2 47IOUT_C REFGND 3 46VBOOST_C REFGND 4 45AVCC AD0 5 44SWC AD1 6 43GNDSWC SYNC 7 AD5737 42GNDSWD SCLK 8 TOP VIEW 41SWD SDIN 9 40AGND (Not to Scale) SDO10 39SWA DVDD11 38GNDSWA DGND12 37GNDSWB LDAC13 36SWB CLEAR14 35AGND ALERT15 34VBOOST_B FAULT 16 33IOUT_B 7890123456789012 1112222222222333 DT DCAA AAC ADCBCB B DGNRESEAVDNHARTGATE DCDC_OOST_NIOUT_AGNNHARTNGATE DCDC_ CIP B C IP MV M O O C C NOTES 1. NC = NO CONNECT. DO NOT CONNECTTO THIS PIN. 2.THE EXPOSEDPADDLE SHOULD BE CONNECTEDTOAGND, OR,ALTERNATIVELY, ITTTHH CEEARPNMA ADBLDE L PLEEE RBFFTEO ETRLHMEECARTNMRCAIECL.ALYL LCYO UNNNCEOCNTNEEDCTTOE AD .C ITO PISP REREC POLMANMEE NFDOERD E TNHHAATNCED 10067-006 Figure 8. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 R An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the SET_B I temperature drift performance. For more information, see the External Current Setting Resistor section. OUT_B 2 R An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the SET_A I temperature drift performance. For more information, see the External Current Setting Resistor section. OUT_A 3 REFGND Ground Reference Point for Internal Reference. 4 REFGND Ground Reference Point for Internal Reference. 5 AD0 Address Decode for the Device Under Test (DUT) on the Board. 6 AD1 Address Decode for the DUT on the Board. It is not recommended to tie both AD1 and AD0 low when using PEC (see the Packet Error Checking section). 7 SYNC Frame Synchronization Signal for the Serial Interface. Active low input. When SYNC is low, data is clocked into the input shift register on the falling edge of SCLK. 8 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. The serial interface operates at clock speeds of up to 30 MHz. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 10 SDO Serial Data Output. Used to clock data from the serial register in readback mode (see Figure 4 and Figure 5). 11 DV Digital Supply Pin. The voltage range is from 2.7 V to 5.5 V. DD 12 DGND Digital Ground. 13 LDAC Load DAC. This active low input is used to update the DAC register and, consequently, the DAC outputs. When LDAC is tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the DAC output is updated only on the falling edge of LDAC (see Figure 3). Using this mode, all analog outputs can be updated simultaneously. Do not leave the LDAC pin unconnected. Rev. F | Page 11 of 44

AD5737 Data Sheet Pin No. Mnemonic Description 14 CLEAR Active High, Edge Sensitive Input. When this pin is asserted, the output current is set to the programmed clear code bit setting. Only channels enabled to be cleared are cleared. For more information, see the Asynchronous Clear section. When CLEAR is active, the DAC output register cannot be written to. 15 ALERT Active High Output. This pin is asserted when there is no SPI activity on the interface pins for a preset time. For more information, see the Alert Output section. 16 FAULT Active Low, Open-Drain Output. This pin is asserted low when any of the following conditions is detected: open circuit, PEC error, or an overtemperature condition (see the Fault Output section). 17 DGND Digital Ground. 18 RESET Hardware Reset, Active Low Input. 19 AV Positive Analog Supply Pin. The voltage range is from 9 V to 33 V. DD 20 NC No Connect. Do not connect to this pin. 21 CHARTA HART Input Connection for DAC Channel A. For more information, see the HART Connectivity section. 22 IGATEA Optional Connection for External Pass Transistor. Leave this pin unconnected when using the dc-to-dc converter. For more information, see the External PMOS Mode section. 23 COMP DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the DCDC_A feedback loop of the Channel A dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AI Supply Requirements—Slewing section. CC 24 V Supply for Channel A Current Output Stage (see Figure 49). To use the dc-to-dc converter, connect this pin BOOST_A as shown in Figure 56. 25 NC No Connect. Do not connect to this pin. 26 I Current Output Pin for DAC Channel A. OUT_A 27 AGND Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. 28 NC No Connect. Do not connect to this pin. 29 CHARTB HART Input Connection for DAC Channel B. For more information, see the HART Connectivity section. 30 NC No Connect. Do not connect to this pin. 31 IGATEB Optional Connection for External Pass Transistor. Leave this pin unconnected when using the dc-to-dc converter. For more information, see the External PMOS Mode section. 32 COMP DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the DCDC_B feedback loop of the Channel B dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AI Supply Requirements—Slewing section. CC 33 I Current Output Pin for DAC Channel B. OUT_B 34 V Supply for Channel B Current Output Stage (see Figure 49). To use the dc-to-dc converter, connect this pin BOOST_B as shown in Figure 56. 35 AGND Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. 36 SW Switching Output for Channel B DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as B shown in Figure 56. 37 GNDSW Ground Connection for DC-to-DC Switching Circuit. This pin must always be connected to ground. B 38 GNDSW Ground Connection for DC-to-DC Switching Circuit. This pin must always be connected to ground. A 39 SW Switching Output for Channel A DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as A shown in Figure 56. 40 AGND Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. 41 SW Switching Output for Channel D DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as D shown in Figure 56. 42 GNDSW Ground Connection for DC-to-DC Switching Circuit. This pin must always be connected to ground. D 43 GNDSW Ground Connection for DC-to-DC Switching Circuit. This pin must always be connected to ground. C 44 SW Switching Output for Channel C DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as C shown in Figure 56. 45 AV Supply for DC-to-DC Circuitry. The voltage range is from 4.5 V to 5.5 V. CC 46 V Supply for Channel C Current Output Stage (see Figure 49). To use the dc-to-dc converter, connect this pin BOOST_C as shown in Figure 56. 47 I Current Output Pin for DAC Channel C. OUT_C 48 COMP DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the DCDC_C feedback loop of the Channel C dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AI Supply Requirements—Slewing section. CC Rev. F | Page 12 of 44

Data Sheet AD5737 Pin No. Mnemonic Description 49 IGATEC Optional Connection for External Pass Transistor. Leave this pin unconnected when using the dc-to-dc converter. For more information, see the External PMOS Mode section. 50 NC No Connect. Do not connect to this pin. 51 CHARTC HART Input Connection for DAC Channel C. For more information, see the HART Connectivity section. 52 NC No Connect. Do not connect to this pin. 53 AGND Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. 54 I Current Output Pin for DAC Channel D. OUT_D 55 NC No Connect. Do not connect to this pin. 56 V Supply for Channel D Current Output Stage (see Figure 49). To use the dc-to-dc converter, connect this pin BOOST_D as shown in Figure 56. 57 COMP DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the DCDC_D feedback loop of the Channel D dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AI Supply Requirements—Slewing section. CC 58 IGATED Optional Connection for External Pass Transistor. Leave this pin unconnected when using the dc-to-dc converter. For more information, see the External PMOS Mode section. 59 CHARTD HART Input Connection for DAC Channel D. For more information, see the HART Connectivity section. 60 NC No Connect. Do not connect to this pin. 61 REFIN External Reference Voltage Input. 62 REFOUT Internal Reference Voltage Output. It is recommended that a 0.1 µF capacitor be placed between REFOUT and REFGND. REFOUT must be connected to REFIN to use the internal reference. 63 R An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the SET_D I temperature drift performance. For more information, see the External Current Setting Resistor section. OUT_D 64 R An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the SET_C I temperature drift performance. For more information, see the External Current Setting Resistor section. OUT_C EPAD Exposed Pad. The exposed paddle must be connected to AGND, or, alternatively, it can be left electrically unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance. Rev. F | Page 13 of 44

AD5737 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS CURRENT OUTPUTS 0.008 0.008 4mATO 20mA, INTERNAL RSET,WITH DC-TO-DC CONVERTER 4mATO 20mA,EXTERNAL RSET,WITHDC-TO-DCCONVERTER 0.006 0.006 4mATO 20mA, INTERNAL RSET 4mATO 20mA,EXTERNAL RSET 0.004 0.004 R) R) FS FS 0.002 4mATO20mA RANGEMAXINL AVDD=15V R (% 0.002 R (% 00mmAATTOO2204mmAA RRAANNGGEEMMAAXXIINNLL RO RO 0 4mATO20mA RANGEMININL ER 0 ER 0mATO24mA RANGEMININL NL NL –0.002 0mATO20mA RANGEMININL I I –0.002 –0.004 –0.004 AVDD=15V –0.006 TA=25°C –0.0060 1000 C20O0D0E 3000 4000 10067-231 –0.00–840 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 10067-234 Figure 9. Integral Nonlinearity Error vs. DAC Code Figure 12. Integral Nonlinearity Error vs. Temperature, Internal RSET 1.0 0.008 4mATO 20mA, INTERNAL RSET,WITH DC-TO-DC CONVERTER 0.8 4mATO 20mA,EXTERNAL RSET,WITHDC-TO-DCCONVERTER 0.006 4mATO 20mA, INTERNAL RSET 0.6 4mATO 20mA,EXTERNAL RSET 0.004 OR (LSB) 00..24 R (%FSR) 0.002 004mmmAAATTTOOO222040mmmAAA RRRAAANNNGGGEEEMMMAAAXXXIIINNNLLL AVDD=15V RR 0 RO 0 4mATO20mA RANGEMININL NL E–0.2 L ER–0.002 00mmAATTOO2240mmAA RRAANNGGEEMMIINNIINNLL D N –0.4 I –0.004 –0.6 AVDD=15V TA=25°C –0.006 –0.8 –1.00 1000 2C0O0D0E 3000 4000 10067-232 –0.00–840 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 10067-235 Figure 10. Differential Nonlinearity Error vs. DAC Code Figure 13. Integral Nonlinearity Error vs. Temperature, External RSET 0.06 1.0 4mATO 20mA, INTERNAL RSET 0.05 4mATO 20mA, INTERNAL RSET,WITH DC-TO-DC CONVERTER 0.8 R) S F 0.04 0.6 % USTED ERROR ( 000...000123 ATAVD=D2=5°1C5V ERROR (LSB) 00..240 MMAINX DDNNLL NADJ 0 DNL –0.2 U–0.01 –0.4 AL AVDD=15V OT–0.02 –0.6 ALL RANGES T INTERNALAND EXTERNAL RSET –0.03 4mATO 20mA, EXTERNAL RSET –0.8 4mATO 20mA,EXTERNAL RSET,WITHDC-TO-DCCONVERTER –0.040 1000 2C0O0D0E 3000 4000 10067-233 –1.0–40 –20 0 TEM20PERATU4R0E (°C)60 80 100 10067-236 Figure 11. Total Unadjusted Error vs. DAC Code Figure 14. Differential Nonlinearity Error vs. Temperature Rev. F | Page 14 of 44

Data Sheet AD5737 0.025 0.008 0.020 MAXINL R) 0.006 FS 0.015 % OR ( 0.010 R) 0.004 4mATO 20mA RANGE STED ERR 0.0050 ROR (%FS 0.002 TA = 25°C U R 0 J–0.005 E UNAD–0.010 AVDD = 15V INL –0.002 L TA–0.015 O T–0.020 4mATO 20mA RANGE, INTERNAL RSET –0.004 MININL 4mATO 20mA RANGE, EXTERNAL RSET –0.025–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 10067-155 –0.0065 10 15 SUPPL2Y0 (V) 25 30 10067-240 Figure 15. Total Unadjusted Error vs. Temperature Figure 18. Integral Nonlinearity Error vs. Supply, External RSET 0.020 0.008 MAXINL 0.015 0.006 SR) 0.010 F 0.004 % R) RROR ( 0.005 R (%FS 0.002 T4mA A= 2T5O° C20mA RANGE E 0 O E R AL ER 0 L-SC–0.005 INL UL–0.010 AVDD = 15V –0.002 F –0.015 44mmAATTOO 2200mmAA RRAANNGGEE,, EINXTTEERRNNAALL R RSSEETT –0.004 MININL –0.020–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 10067-157 –0.0065 10 15 SUPPL2Y0 (V) 25 30 10067-241 Figure 16. Full-Scale Error vs. Temperature Figure 19. Integral Nonlinearity Error vs. Supply, Internal RSET 0.005 1.0 ALL RANGES 0.8 TA = 25°C 0 0.6 SR)–0.005 B) 0.4 F S AIN ERROR (%––00..001150 DNL ERROR (L–00..202 MMAINX D DNNLL G –0.4 AVDD = 15V –0.6 –0.020 4mATO 20mA RANGE, INTERNAL RSET –0.8 4mATO 20mA RANGE, EXTERNAL RSET –0.025–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 10067-159 –1.05 10 15 SUPPL2Y0 (V) 25 30 10067-242 Figure 17. Gain Error vs. Temperature Figure 20. Differential Nonlinearity Error vs. Supply Rev. F | Page 15 of 44

AD5737 Data Sheet 0.005 6 AVDD = 15V SR) 0 MAX TUE 5 TRAL O=A 2D5 =°C 300Ω F %–0.005 R ( O 4 D ERR–0.010 4TmA A= 2T5O° C20mA RANGE T (µA) TE–0.015 EN 3 S R U R J U D–0.020 C UNA MIN TUE 2 L –0.025 A T O 1 T–0.030 –0.0355 10 15 SUPPLY20 (V) 25 30 10067-060 00 5 TIME10 (µs) 15 20 10067-062 Figure 21. Total Unadjusted Error vs. Supply, External RSET Figure 24. Current vs. Time on Power-Up 0.07 4 R) 0.06 MAX TUE 2 S %F 0.05 (R 0 O 0.04 D ERR 0.03 4TmA=A 2T5O° C20mA RANGE T (µA) –2 E N T E US 0.02 RR –4 NADJ 0.01 CU L U –6 AVDD = 15V TA 0 MIN TUE TA = 25°C TO –8 RLOAD = 300Ω –0.01 INT_ENABLE = 1 –0.02 5 10 15 SUPPLY20 (V) 25 30 10067-061 –100 1 2 TIME3 (µs) 4 5 6 10067-063 Figure 22. Total Unadjusted Error vs. Supply, Internal RSET Figure 25. Current vs. Time on Output Enable 0.006 V) E ( 30 0.004 MAX TUE G SR) LTA %F 0.002 VO 25 RROR ( 0 OOST_x20 E B ED –0.002 D V AL UNADJUST–––000...000000864 TE4RmAXL OTA=AE 2TDR5O N=° C A230L0m0 PΩAM ROASN (GNTELJS4149) RENT (mA)AN 1105 01mkΩA LTOOA 2D4mA RANIVOGBUOETO_xST_x OT UR fSW = 410kHz T–0.010 MIN TUE UT C 5 IANVDCUCC =T O5VR = 10µH (XAL4040-103) –0.01210 15 VBOOS2T0_x SUPPLY (2V5) 30 10067-188 OUTP –00.50 –0.25 0 0.25 0.50TTIMA0 E=.7 2(5m5°sC)1.00 1.25 1.50 1.75 2.00 10067-167 Figure 23. Total Unadjusted Error vs. VBOOST_x Supply Figure 26. Output Current and VBOOST_x Settling Time Using External PMOS Mode with DC-to-DC Converter (See Figure 56) Rev. F | Page 16 of 44

Data Sheet AD5737 30 10 20mA OUTPUT 10mA OUTPUT 8 25 A) 6 mA) D) (µ 4 T (20 LE N P 2 E U R O UT CUR15 TTTAAA === –++421050°°5CC°C T (AC-C –20 P N T10 E U R –4 O 0mATO 24mA RANGE UR 1kΩ LOAD C –6 5 IfNSWDU =C 4T1O0kRH =z 10µH (XAL4040-103) –8 AVCC = 5V 0mATO 24m1Ak ΩR ALNOGAED –00.25 0 0.25 0.50 TA0IV.M7C5EC ( =m 15s.V)00 1.25 1.50 1.75 10067-168 –100 2 fINSWD4 U=C 4T1O0kRH =z 610µTHIM (XEA (L8µ4s04)0-1031)0 E1X2TERTNAA =L1 2R45S°ECT 10067-170 Figure 27. Output Current Settling Time with DC-to-DC Converter Figure 30. Output Current, AC-Coupled vs. Time over Temperature (See Figure 56) with DC-to-DC Converter (See Figure 56) 30 8 0mATO 24mA RANGE 7 1kΩ LOAD 25 fSW = 410kHz ENT (mA)20 LTAGE (V) 65 ITNAD =U 2C5T°OCR = 10µH (XAL4040-103) R O UTPUT CUR1105 AAAVVVCCCCCC === 455...505VVV ADROOM V 43 O 0mATO 24mA RANGE HE 2 1kΩ LOAD 5 IfNSWDU =C 4T1O0kRH =z 10µH (XAL4040-103) 1 TA = 25°C –00.25 0 0.25 0.50 T0I.M75E (m1s.)00 1.25 1.50 1.75 10067-169 00 5 OUTPUT1 0CURRENT (m1A5) 20 10067-067 Figure 28. Output Current Settling Time with DC-to-DC Converter Figure 31. DC-to-DC Converter Headroom vs. Output Current (See Figure 56) over AVCC (See Figure 56) 25 0 AVDD = 15V 20 IOUT (4mA TO 20mA STEP) –20 VTAB O=O 2S5T°_Cx = 15V A) m UTPUT CURRENT ( 1105 TE4RVmAXBL OOTA=AOE 2TDSR5O TN=°_ C Ax23 0L0=m0 P2ΩA4M VROASN (GNTELJS4149) I PSRR (dB)OUT_x –––864000 O IOUT (20mA TO 4mA STEP) 5 –100 0–5 0 5TIME (µs)10 15 20 10067-189 –12010 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 10067-068 Figure 29. Output Current Settling Time with External PMOS Transistor Figure 32. IOUT_x PSRR vs. Frequency Rev. F | Page 17 of 44

AD5737 Data Sheet DC-TO-DC CONVERTER 100 100 AVCC = 4.5V 90 AAVVCCCC == 55..05VV 90 80 80 %) %) CY ( 70 CY ( 70 20mA CIEN 60 CIEN 60 EFFIST4500 UT EFFI 4500 O P O T B30 U 30 V 0mA TO 24mA RANGE O 0mA TO 24mA RANGE 20 1EkXΩT ELRONAADL RSET 20 1EkXΩT ELRONAADL RSET 10 IfNSWDU =C 4T1O0kRH =z 10µH (XAL4040-103) 10 AfSVWC C= =41 50VkHz TA = 25°C INDUCTOR = 10µH (XAL4040-103) 00 0.005 OU0T.0P1U0T CURR0E.N01T5 (A) 0.020 0.025 10067-055 0–40 –20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 10067-258 Figure 33. Efficiency at VBOOST_x vs. Output Current (See Figure 56) Figure 36. Output Efficiency vs. Temperature (See Figure 56) 100 0.6 90 20mA 0.5 80 CIENCY (%) 6700 STANCE (Ω) 0.4 FFI 50 ESI 0.3 E R BOOST3400 WITCH 0.2 V 0mA TO 24mA RANGE S 20 1kΩ LOAD EXTERNAL RSET 0.1 AVCC = 5V 10 fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) 0-40 -20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 10067-256 0–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 10067-123 Figure 34. Efficiency at VBOOST_x vs. Temperature (See Figure 56) Figure 37. Switch Resistance vs. Temperature 100 AVCC = 4.5V 90 AVCC = 5.0V AVCC = 5.5V 80 %) Y ( 70 C EN 60 CI FI 50 F E UT 40 P T U 30 O 0mA TO 24mA RANGE 1kΩ LOAD 20 EXTERNAL RSET fSW = 410kHz 10 INDUCTOR = 10µH (XAL4040-103) TA = 25°C 00 0.005 OU0T.0P1U0T CURR0E.N01T5 (A) 0.020 0.025 10067-257 Figure 35. Output Efficiency vs. Output Current (See Figure 56) Rev. F | Page 18 of 44

Data Sheet AD5737 REFERENCE 16 5.0050 1142 ARTAVE FD=DO 2U5°TC E (V) 55..00004405 3A0V DDDE V=I C15EVS SHOWN G 10 LTA 5.0035 V) VO 5.0030 VOLTAGE ( 86 E OUTPUT 55..00002205 4 NC E 5.0015 R 2 EFE 5.0010 R 0 5.0005 –20 0.2 0.4 TIM0E. 6(ms) 0.8 1.0 1.2 10067-010 5.000–040 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 10067-163 Figure 38. REFOUT Voltage Turn-On Transient Figure 41. REFOUT Voltage vs. Temperature (When the AD5737 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is −4 mV. Measurement of these parts after seven days shows that the outputs typically shift back 2 mV toward their initial values. This second shift is due to the relaxation of stress incurred during soldering.) 4 5.002 AVDD = 15V AVDD = 15V 3 TA = 25°C V)5.001 TA = 25°C E ( G 2 A5.000 T L E (µV) 1 UT VO4.999 G P LTA 0 OUT4.998 VO CE N –1 RE4.997 E F E –2 R4.996 –30 2 4 TIME (s) 6 8 10 10067-011 4.9950 2 LOA4D CURRENT 6(mA) 8 10 10067-014 Figure 39. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth) Figure 42. REFOUT Voltage vs. Load Current 150 5.00000 ATAV D=D 2 =5° 1C5V 4.99995 TA = 25°C 100 V) E ( G 4.99990 A T 50 L E (µV) UT VO 4.99985 TAG 0 UTP 4.99980 L O VO CE 4.99975 –50 N E ER 4.99970 F E –100 R 4.99965 –1500 5 TIM1E0 (ms) 15 20 10067-012 4.9996010 15 2A0VDD (V) 25 30 10067-015 Figure 40. REFOUT Output Noise (100 kHz Bandwidth) Figure 43. REFOUT Voltage vs. AVDD Rev. F | Page 19 of 44

AD5737 Data Sheet GENERAL 450 13.4 400 DTAV D=D 2 =5° 5CV 13.3 350 13.2 300 Hz) M 13.1 DI (µA)CC 225000 QUENCY ( 13.0 E 12.9 150 FR 12.8 100 50 12.7 DVDD = 5.5V 00 1 SD2IN VOLTAGE3 (V) 4 5 10067-007 12.6–40 –20 0 TE2M0PERAT4U0RE (°C6)0 80 100 10067-020 Figure 44. DICC vs. Logic Input Voltage Figure 46. Internal Oscillator Frequency vs. Temperature 8 14.4 7 14.2 6 14.0 CURRENT (mA) 345 REQUENCY (MHz) 1133..86 F 13.4 2 AIDD 1 TA = 25°C 13.2 IOUT = 0mA T = 25°C A 010 15 VO20LTAGE (V) 25 30 10067-009 13.02.5 3.0 3.5 VOLTA4.G0E (V) 4.5 5.0 5.5 10067-021 Figure 45. Supply Current (AIDD) vs. Supply Voltage (AVDD) Figure 47. Internal Oscillator Frequency vs. DVDD Supply Voltage Rev. F | Page 20 of 44

Data Sheet AD5737 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Current Loop Compliance Voltage Relative accuracy, or integral nonlinearity (INL), is a measure The current loop compliance voltage is the maximum voltage of the maximum deviation from the best fit line through the at the I pin for which the output current is equal to the OUT_x DAC transfer function. INL is expressed in percent of full-scale programmed value. range (% FSR). A typical INL vs. code plot is shown in Figure 9. Voltage Reference Thermal Hysteresis Differential Nonlinearity (DNL) Voltage reference thermal hysteresis is the difference in output Differential nonlinearity (DNL) is the difference between the voltage measured at +25°C compared to the output voltage measured change and the ideal 1 LSB change between any two measured at +25°C after cycling the temperature from +25°C to adjacent codes. A specified DNL of ±1 LSB maximum ensures −40°C to +105°C and back to +25°C. The hysteresis is expressed monotonicity. The AD5737 is guaranteed monotonic by design. in ppm. A typical DNL vs. code plot is shown in Figure 10. Power-On Glitch Energy Monotonicity Power-on glitch energy is the impulse injected into the analog A DAC is monotonic if the output either increases or remains output when the AD5737 is powered on. It is specified as the constant for increasing digital input code. The AD5737 is area of the glitch in nV-sec (see Figure 24). monotonic over its full operating temperature range. Power Supply Rejection Ratio (PSRR) Offset Error PSRR indicates how the output of the DAC is affected by changes Offset error is the deviation of the analog output from the ideal in the power supply voltage. zero-scale output when all DAC registers are loaded with 0x0000. Reference Temperature Coefficient (TC) It is expressed in % FSR. Reference TC is a measure of the change in the reference output Offset Error Drift or Offset TC voltage with changes in temperature. It is expressed in ppm/°C. Offset error drift, or offset TC, is a measure of the change in Line Regulation offset error with changes in temperature and is expressed in Line regulation is the change in the reference output voltage due ppm FSR/°C. to a specified change in supply voltage. It is expressed in ppm/V. Gain Error Load Regulation Gain error is a measure of the span error of the DAC. It is the Load regulation is the change in the reference output voltage due deviation in slope of the DAC transfer function from the ideal, to a specified change in load current. It is expressed in ppm/mA. expressed in % FSR. DC-to-DC Converter Headroom Gain Temperature Coefficient (TC) DC-to-DC converter headroom is the difference between the Gain TC is a measure of the change in gain error with changes voltage required at the current output and the voltage supplied in temperature and is expressed in ppm FSR/°C. by the dc-to-dc converter (see Figure 31). Full-Scale Error Output Efficiency Full-scale error is a measure of the output error when full-scale Output efficiency is defined as the ratio of the power delivered code is loaded to the DAC register. Ideally, the output is full- to a channel’s load and the power delivered to the channel’s scale − 1 LSB. Full-scale error is expressed in % FSR. dc-to-dc input. The V quiescent current is considered BOOST_x Full-Scale Temperature Coefficient (TC) part of the dc-to-dc converter’s losses. Full-scale TC is a measure of the change in full-scale error with I 2×R changes in temperature and is expressed in ppm FSR/°C. OUT LOAD AV ×AI Total Unadjusted Error (TUE) CC CC Total unadjusted error (TUE) is a measure of the output error Efficiency at V BOOST_x that includes all the error measurements: INL error, offset error, The efficiency at V is defined as the ratio of the power BOOST_x gain error, temperature, and time. TUE is expressed in % FSR. delivered to a channel’s V supply and the power delivered BOOST_x DC Crosstalk to the channel’s dc-to-dc input. The VBOOST_x quiescent current is DC crosstalk is the dc change in the output level of one DAC in considered part of the dc-to-dc converter’s losses. response to a change in the output of another DAC. It is measured I ×V with a full-scale output change on one DAC while monitoring OUT BOOST_x AV ×AI another DAC, which is at midscale. CC CC Rev. F | Page 21 of 44

AD5737 Data Sheet THEORY OF OPERATION The AD5737 is a quad, precision digital-to-current loop converter POWER-ON STATE OF THE AD5737 designed to meet the requirements of industrial process control When the AD5737 is first powered on, the I pins are in OUT_x applications. It provides a high precision, fully integrated, low cost, tristate mode. After a device power-on or a device reset, it is single-chip solution for generating current loop outputs. The recommended that the user wait at least 100 µs before writing to current ranges available are 0 mA to 20 mA, 4 mA to 20 mA, the device to allow time for internal calibrations to take place. and 0 mA to 24 mA. The output configuration is user-selectable SERIAL INTERFACE via the DAC control register. The AD5737 is controlled by a versatile 3-wire serial interface On-chip dynamic power control minimizes package power that operates at clock rates of up to 30 MHz and is compatible dissipation (see the Dynamic Power Control section). with SPI, QSPI, MICROWIRE, and DSP standards. Data coding DAC ARCHITECTURE is always straight binary. The DAC core architecture of the AD5737 consists of two Input Shift Register matched DAC sections. A simplified circuit diagram is shown The input shift register is 24 bits wide. Data is loaded into the in Figure 48. The four MSBs of the 12-bit data-word are decoded device MSB first as a 24-bit word under the control of the serial to drive 15 switches, E1 to E15. Each switch connects one of clock input, SCLK. Data is clocked in on the falling edge of SCLK. 15 matched resistors either to ground or to the reference buffer output. The remaining eight bits of the data-word drive Switch S0 If packet error checking (PEC) is enabled, an additional eight to Switch S7 of an 8-bit voltage mode R-2R ladder network. bits must be written to the AD5737, creating a 32-bit serial interface (see the Packet Error Checking section). VOUT 2R 2R 2R 2R 2R 2R 2R The DAC outputs can be updated in one of two ways: individual S0 S1 S7 E1 E2 E15 DAC updating or simultaneous updating of all DACs. Individual DAC Updating To update an individual DAC, LDAC is held low while data is 8-BIT R-2R LADDER FOU15R EMQSUBAsL D SEECGOMDEENDT ISNTO 10067-069 cisl oucpkdeadt eindt oon t hthe eD rAisCin dga etda gree goifs tSeYr.N TCh.e S aeded Traebsslee d3 DanAdC F oiguutpreu t3 Figure 48. DAC Ladder Structure for timing information. The voltage output from the DAC core is converted to a current, Simultaneous Updating of All DACs which is then mirrored to the supply rail so that the application To update all DACs simultaneously, LDAC is held high while sees only a current source output (see Figure 49). The current data is clocked into the DAC data register. After LDAC is taken outputs are supplied by V . BOOST_x high, only the first write to the DAC data register of each channel VBOOST_x is valid; subsequent writes to the DAC data register are ignored, although these subsequent writes are returned if a readback is R2 R3 initiated. All DAC outputs are updated by taking LDAC low after SYNC is taken high. T2 A2 OUTPUT 12-BIT T1 AMPLIFIERS DAC A1 IOUT_x VREFIN 1D2-ABCIT IOUT_x RSET 10067-071 LDAC REGDIASCTER Figure 49. Voltage-to-Current Conversion Circuitry DAC INPUT Reference Buffers REGISTER OFFSET The AD5737 can operate with either an external or internal AND GAIN CALIBRATION reference. The reference input requires a 5 V reference for DAC DATA specified performance. This input voltage is then buffered REGISTER before it is applied to the DAC. SSSYCDNLICNK INTLEORGFIACCE SDO 10067-072 Figure 50. Simplified Serial Interface of the Input Loading Circuitry for One DAC Channel Rev. F | Page 22 of 44

Data Sheet AD5737 TRANSFER FUNCTION For the 4 mA to 20 mA range, For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA 16mA current output ranges, the output current is expressed by the IOUT =  2N  ×D+4mA following equations: where: For the 0 mA to 20 mA range, D is the decimal equivalent of the code loaded to the DAC. 20mA N is the bit resolution of the DAC. I =   ×D OUT  2N  For the 0 mA to 24 mA range, 24mA IOUT =  2N  ×D Rev. F | Page 23 of 44

AD5737 Data Sheet REGISTERS Table 7, Table 8, and Table 9 provide an overview of the registers for the AD5737. Table 7. Data Registers for the AD5737 Register Description DAC Data Registers The four DAC data registers (one register per DAC channel) are used to write a DAC code to each DAC channel. The DAC data bits are D15 to D4. Gain Registers The four gain registers (one register per DAC channel) are used to program the gain trim on a per-channel basis. The gain data bits are D15 to D4. Offset Registers The four offset registers (one register per DAC channel) are used to program the offset trim on a per-channel basis. The offset data bits are D15 to D4. Clear Code Registers The four clear code registers (one register per DAC channel) are used to program the clear code on a per- channel basis. The clear code data bits are D15 to D4. Table 8. Control Registers for the AD5737 Register Description Main Control Register The main control register is used to configure functions for the entire part. These functions include the following: enabling status readback during a write; enabling the output on all four DAC channels simulta- neously; power-on of the dc-to-dc converter on all four DAC channels simultaneously; and enabling and configuring the watchdog timer. For more information, see the Main Control Register section. DAC Control Registers The four DAC control registers (one register per DAC channel) are used to configure the following functions on a per-channel basis: output range (for example, 4 mA to 20 mA); selection of the internal current sense resistor or an external current sense resistor; enabling/disabling the use of a clear code; enabling/disabling the internal circuitry (dc-to-dc converter, DAC, and internal amplifiers); power-on/power-off of the dc-to-dc converter; and enabling/disabling the output channel. Software Register The software register is used to perform a reset, to toggle the user bit in the status register, and, as part of the watchdog timer feature, to verify correct data communication operation. DC-to-DC Control Register The dc-to-dc control register is used to set the control parameters for the dc-to-dc converter: maximum output voltage, phase, and switching frequency. This register is also used to select the internal compensa- tion resistor or an external compensation resistor for the dc-to-dc converter. Slew Rate Control Registers The four slew rate control registers (one register per DAC channel) are used to program the slew rate of the DAC output. Table 9. Readback Register for the AD5737 Register Description Status Register The status register contains any fault information, as well as a user toggle bit. Rev. F | Page 24 of 44

Data Sheet AD5737 ENABLING THE OUTPUT REPROGRAMMING THE OUTPUT RANGE To correctly write to and set up the part from a power-on When changing the range of an output, use the same sequence condition, use the following sequence: described in the Enabling the Output section. Set the range to 0 V (zero scale or midscale) before the output is disabled. Because 1. Perform a hardware or software reset after initial power-on. the dc-to-dc switching frequency, maximum output voltage, 2. Configure the dc-to-dc converter supply block. Set the and phase are already selected, there is no need to reprogram dc-to-dc switching frequency, the maximum output voltage these values. Figure 52 provides a flowchart of this sequence. allowed, and the dc-to-dc converter phase between channels. 3. Configure the DAC control register on a per-channel basis. CHANNEL OUTPUT IS ENABLED. Select the output range, and enable the dc-to-dc converter block (DC_DC bit). Other control bits can also be config- ured. Set the INT_ENABLE bit, but do not set the OUTEN STEP 1:WRITETO CHANNEL’S DAC DATA REGISTER. SET THE OUTPUT (output enable) bit. TO 0V (ZERO OR MIDSCALE). 4. Write the required code to the DAC data register. This step implements a full internal DAC calibration. For reduced STEP 2:WRITETO DAC CONTROL REGISTER. DISABLE THE OUTPUT (OUTEN = 0)AND output glitch, allow at least 200 µs before performing Step 5. SET THE NEW OUTPUT RANGE. KEEP THE DC_DC BITAND THE INT_ENABLE BIT SET. 5. Write to the DAC control register again to enable the output (set the OUTEN bit). STEP 3:WRITEVALUETO THE DAC DATA REGISTER. Figure 51 provides a flowchart of this sequence. STEP 4:WRITETO DAC CONTROL REGISTER. POWER ON. RSOEEUTLT OPTAUHDTE. SOEUQTUEENN BCITETAOS EINN ASBTELPE 2T.HE 10067-074 Figure 52. Programming Sequence to Change the Output Range STEP 1:PERFORM A SOFTWARE/HARDWARE RESET. STEP 2:WRITE TO DC-TO-DC CONTROL REGISTER TO SET DC-TO-DC CLOCK FREQUENCY, PHASE, AND MAXIMUM VOLTAGE. STEP 3:WRITE TO DAC CONTROL REGISTER. SELECT THE DAC CHANNEL AND OUTPUT RANGE. SET THE DC_DC BIT AND OTHER CONTROL BITS AS REQUIRED. SET THE INT_ENABLE BIT BUT DO NOT SET THE OUTEN BIT. STEP 4:WRITE TO ONE OR MORE DAC DATA REGISTERS. ALLOW AT LEAST 200µs BETWEEN STEP 3 AND STEP 5 FOR REDUCED OUTPUT GLITCH. STEP 5:WRITE TO DAC CONTROL REGISTER. RELOAD SBEITQ TUOE NECNEA BALSE I NT HSET EOPU 3T.P SUETT. THE OUTEN 10067-073 Figure 51. Programming Sequence to Correctly Enable the Output Rev. F | Page 25 of 44

AD5737 Data Sheet DATA REGISTERS DAC Data Register The input shift register is 24 bits wide. When PEC is enabled, When writing to a DAC data register, Bit D15 to Bit D4 are the the input shift register is 32 bits wide, with the last eight bits DAC data bits. Table 12 shows the register format, and Table 11 corresponding to the PEC code (see the Packet Error Checking describes the functions of Bit D23 to Bit D16. section for more information about PEC). When writing to a data register, the format shown in Table 10 must be used. Table 10. Input Shift Register for a Write Operation to a Data Register MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0 R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 Data Table 11. Descriptions of Data Register Bits[D23:D16] Bit Name Description R/W This bit indicates whether the addressed register is written to or read from. 0 = write to the addressed register. 1 = read from the addressed register. DUT_AD1, DUT_AD0 Used in association with the external pins AD1 and AD0, these bits determine which AD5737 device is being addressed by the system controller. It is not recommended to tie both AD1 and AD0 low when using PEC (see the Packet Error Checking section). DUT_AD1 DUT_AD0 Part Addressed 0 0 Pin AD1 = 0, Pin AD0 = 0 0 1 Pin AD1 = 0, Pin AD0 = 1 1 0 Pin AD1 = 1, Pin AD0 = 0 1 1 Pin AD1 = 1, Pin AD0 = 1 DREG2, DREG1, DREG0 These bits select the register to be written to. If a control register is selected (DREG[2:0] = 111), the CREG bits in the control register select the specific control register to be written to (see Table 19). DREG2 DREG1 DREG0 Function 0 0 0 Write to DAC data register (one DAC channel) 0 0 1 Reserved 0 1 0 Write to gain register (one DAC channel) 0 1 1 Write to gain registers (all DAC channels) 1 0 0 Write to offset register (one DAC channel) 1 0 1 Write to offset registers (all DAC channels) 1 1 0 Write to clear code register (one DAC channel) 1 1 1 Write to a control register DAC_AD1, DAC_AD0 These bits are used to specify the DAC channel. If a write to the part does not apply to a specific DAC channel, these bits are don’t care bits. DAC_AD1 DAC_AD0 DAC Channel 0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D Table 12. Programming the DAC Data Register D23 D22 D21 D20 D19 D18 D17 D16 D15 to D4 D3 to D0 R/W DUT_AD1 DUT_AD0 0 0 0 DAC_AD1 DAC_AD0 DAC data X1 1 X = don’t care. Rev. F | Page 26 of 44

Data Sheet AD5737 Gain Register DREG[2:0] bits to 100 (see Table 15). To write the same offset code to all four DAC channels at the same time, set the DREG[2:0] The 12-bit gain register allows the user to adjust the gain of bits to 101. The offset register coding is straight binary, as shown in each channel in steps of 1 LSB. To write to the gain register of Table 16. The default code in the offset register is 0x8000, which one DAC channel, set the DREG[2:0] bits to 010 (see Table 13). results in zero offset programmed to the output (for more infor- To write the same gain code to all four DAC channels at the mation, see the Digital Offset and Gain Control section). same time, set the DREG[2:0] bits to 011. The gain register coding is straight binary, as shown in Table 14. The default code Clear Code Register in the gain register is 0xFFFF. The maximum recommended The 12-bit clear code register allows the user to set the clear gain trim is approximately 50% of the programmed range to value of each channel. To configure a channel to be cleared maintain accuracy (for more information, see the Digital Offset when the CLEAR pin is activated, set the CLR_EN bit in the and Gain Control section). DAC control register for that channel (see Table 23). To write Offset Register to the clear code register, set the DREG[2:0] bits to 110 (see Table 17). The default clear code is 0x0000 (for more informa- The 12-bit offset register allows the user to adjust the offset tion, see the Asynchronous Clear section). of each channel by −2048 LSB to +2047 LSB in steps of 1 LSB. To write to the offset register of one DAC channel, set the Table 13. Programming the Gain Register R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D4 D3 to D0 0 Device address 0 1 0 DAC channel address Gain adjustment 1111 Table 14. Gain Register Bit Descriptions Gain Adjustment G15 G14 G13 to G5 G4 G3 to G0 +4096 LSB 1 1 111111111 1 1111 +4095 LSB 1 1 111111111 0 1111 … … … … … 1111 1 LSB 0 0 000000000 1 1111 0 LSB 0 0 000000000 0 1111 Table 15. Programming the Offset Register R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D4 D3 to D0 0 Device address 1 0 0 DAC channel address Offset adjustment 0000 Table 16. Offset Register Bit Descriptions Offset Adjustment OF15 OF14 OF13 OF12 to OF5 OF4 OF3 to OF0 +2047 LSB 1 1 1 11111111 1 0000 +2046 LSB 1 1 1 11111111 0 0000 … … … … … … 0000 No Adjustment (Default) 1 0 0 00000000 0 0000 … … … … … … 0000 −2047 LSB 0 0 0 00000000 1 0000 −2048 LSB 0 0 0 00000000 0 0000 Table 17. Programming the Clear Code Register R/W DUT_AD1 DUT_AD0 DREG2 DREG1 DREG0 DAC_AD1 DAC_AD0 D15 to D4 D3 to D0 0 Device address 1 1 0 DAC channel address Clear code 0000 Rev. F | Page 27 of 44

AD5737 Data Sheet CONTROL REGISTERS Main Control Register When writing to a control register, the format shown in Table 18 The main control register options are shown in Table 20 and must be used. See Table 11 for information about the configura- Table 21. See the Device Features section for more information tion of Bit D23 to Bit D16. The control registers are addressed about the features controlled by the main control register. by setting the DREG[2:0] bits (Bits[D20:D18] in the input shift register) to 111 and then setting the CREG[2:0] bits to select the specific control register (see Table 19). Table 18. Input Shift Register for a Write Operation to a Control Register MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 to D0 R/W DUT_AD1 DUT_AD0 1 1 1 DAC_AD1 DAC_AD0 CREG2 CREG1 CREG0 Data Table 19. Control Register Addresses (CREG[2:0] Bits) CREG2 (D15) CREG1 (D14) CREG0 (D13) Control Register 0 0 0 Slew rate control register (one per channel) 0 0 1 Main control register 0 1 0 DAC control register (one per channel) 0 1 1 DC-to-DC control register 1 0 0 Software register Table 20. Programming the Main Control Register D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 to D0 0 0 1 0 STATREAD EWD WD1 WD0 X1 X1 OUTEN_ALL DCDC_ALL X1 1 X = don’t care. Table 21. Main Control Register Bit Descriptions Bit Name Description STATREAD Enable status readback during a write. See the Status Readback During a Write section. 0 = disable status readback (default). 1 = enable status readback. EWD Enable the watchdog timer. See the Watchdog Timer section. 0 = disable the watchdog timer (default). 1 = enable the watchdog timer. WD1, WD0 Timeout select bits. Used to select the timeout period for the watchdog timer. WD1 WD0 Timeout Period (ms) 0 0 5 0 1 10 1 0 100 1 1 200 OUTEN_ALL Setting this bit to 1 enables the output on all four DACs simultaneously. Do not use the OUTEN_ALL bit when using the OUTEN bit in the DAC control register. DCDC_ALL Setting this bit to 1 powers up the dc-to-dc converter on all four channels simultaneously. To power down the dc-to-dc converters, all channel outputs must first be disabled. Do not use the DCDC_ALL bit when using the DC_DC bit in the DAC control register. Rev. F | Page 28 of 44

Data Sheet AD5737 DAC Control Register The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 22 and Table 23. Table 22. Programming the DAC Control Register D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 X1 X1 X1 X1 INT_ENABLE CLR_EN OUTEN RSET DC_DC X1 R2 R1 R0 1 X = don’t care. Table 23. DAC Control Register Bit Descriptions Bit Name Description INT_ENABLE Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel. This bit applies to individual channels only; it does not enable the output. After setting this bit, it is recommended that a >200 µs delay be observed before enabling the output to reduce the output enable glitch. See Figure 25 for plots of this glitch. CLR_EN Per-channel clear enable bit. This bit specifies whether the selected channel is cleared when the CLEAR pin is activated. 0 = channel is not cleared when the part is cleared (default). 1 = channel is cleared when the part is cleared. OUTEN Enables or disables the selected output channel. 0 = channel disabled (default). 1 = channel enabled. RSET Selects the internal current sense resistor or an external current sense resistor for the selected DAC channel. 0 = external resistor selected (default). 1 = internal resistor selected. DC_DC Powers up or powers down the dc-to-dc converter on the selected channel. All dc-to-dc converters can be powered up simultaneously using the DCDC_ALL bit in the main control register. To power down the dc-to-dc converter, the OUTEN and INT_ENABLE bits must also be set to 0. 0 = dc-to-dc converter is powered down (default). 1 = dc-to-dc converter is powered up. R2, R1, R0 Selects the output range to be enabled. R2 R1 R0 Output Range Selected 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 4 mA to 20 mA current range 1 0 1 0 mA to 20 mA current range 1 1 0 0 mA to 24 mA current range Rev. F | Page 29 of 44

AD5737 Data Sheet Software Register When the watchdog timer feature is enabled, the user must write 0x195 to Bits[D11:D0] of the software register within the timeout The software register allows the user to perform a software reset of period. If this command is not received within the timeout period, the part. This register is also used to set the user toggle bit, D11, the ALERT pin signals a fault condition. This command is only in the status register and as part of the watchdog timer feature required when the watchdog timer feature is enabled. when that feature is enabled. DC-to-DC Control Register Bit D12 in the software register can be used to ensure that communication has not been lost between the MCU and the The dc-to-dc control register allows the user to configure the AD5737 and that the datapath lines are working properly (that dc-to-dc switching frequency and phase, as well as the maximum is, SDIN, SCLK, and SYNC). allowable dc-to-dc output voltage. The dc-to-dc control register options are shown in Table 26 and Table 27. Table 24. Programming the Software Register D15 D14 D13 D12 D11 to D0 1 0 0 User program Reset code/SPI code Table 25. Software Register Bit Descriptions Bit Name Description User Program This bit is mapped to Bit D11 of the status register. When this bit is set to 1, Bit D11 of the status register is set to 1. When this bit is set to 0, Bit D11 of the status register is also set to 0. This feature can be used to ensure that the SPI pins are working correctly by writing a known bit value to this register and then reading back Bit D11 from the status register. Reset Code/SPI Code Option Description Reset code Writing 0x555 to Bits[D11:D0] performs a software reset of the AD5737. SPI code If the watchdog timer feature is enabled, 0x195 must be written to the software register (Bits[D11:D0]) within the programmed timeout period (see Table 21). Table 26. Programming the DC-to-DC Control Register D15 D14 D13 D12 to D7 D6 D5 to D4 D3 to D2 D1 to D0 0 1 1 X1 DC-DC comp DC-DC phase DC-DC freq DC-DC MaxV 1 X = don’t care. Table 27. DC-to-DC Control Register Bit Descriptions Bit Name Description DC-DC Comp Selects the internal compensation resistor or an external compensation resistor for the dc-to-dc converter. See the DC-to-DC Converter Compensation Capacitors section and the AI Supply Requirements—Slewing section. CC 0 = selects the internal 150 kΩ compensation resistor (default). 1 = bypasses the internal compensation resistor. When this bit is set to 1, an external compensation resistor must be used; this resistor is placed at the COMP pin in series with the 10 nF dc-to-dc compensation capacitor to DCDC_x ground. Typically, a resistor of ~50 kΩ is recommended. DC-DC Phase User-programmable dc-to-dc converter phase (between channels). 00 = all dc-to-dc converters clock on the same edge (default). 01 = Channel A and Channel B clock on the same edge; Channel C and Channel D clock on the opposite edge. 10 = Channel A and Channel C clock on the same edge; Channel B and Channel D clock on the opposite edge. 11 = Channel A, Channel B, Channel C, and Channel D clock 90° out of phase from each other. DC-DC Freq Switching frequency for the dc-to-dc converter; this frequency is divided down from the internal 13 MHz oscillator (see Figure 46 and Figure 47). 00 = 250 kHz ± 10%. 01 = 410 kHz ± 10% (default). 10 = 650 kHz ± 10%. DC-DC MaxV Maximum allowed V voltage supplied by the dc-to-dc converter. BOOST_x 00 = 23 V + 1 V/−1.5 V (default). 01 = 24.5 V ± 1 V. 10 = 27 V ± 1 V. 11 = 29.5 V ± 1 V. Rev. F | Page 30 of 44

Data Sheet AD5737 Slew Rate Control Register loaded on each rising edge of SCLK and read on each falling This register is used to program the slew rate control for the edge of SCLK. selected DAC channel. The slew rate control is enabled/disabled If PEC is enabled, the SDO returns 32 bits (see Figure 5), with and programmed on a per-channel basis. See Table 28 and the 8 CRC bits appended to the data readback. There must be no Digital Slew Rate Control section for more information. activity on SCLK between read command and NOP command, READBACK OPERATION or an incorrect PEC may be read back. Readback Example Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. See Table 29 and Table 30 for the bits To read back the gain register of AD5737 Device 1, Channel A, associated with a readback operation. The DUT_AD1 and implement the following sequence: DUT_AD0 bits, in association with bits RD[4:0], select the 1. Write 0xA80000 to the input register to configure Device register to be read. The remaining data bits in the write Address 1 for read mode with the gain register of Channel A sequence are don’t cares. selected. The data bits, D15 to D0, are don’t care bits. During the next SPI transfer (see Figure 4), either a NOP or a 2. Execute another read command or a no operation command request to read another register must be issued. Meanwhile the (0x3CE000). During this command, the data from the SDO returns 24 bits, the 8 MSBs are don’t cares, and the 16 Channel A gain register is clocked out on the SDO line. LSBs contain the data from the addressed register. The SDO is Table 28. Programming the Slew Rate Control Register D15 D14 D13 D12 D11 to D7 D6 to D3 D2 to D0 0 0 0 SREN X1 SR_CLOCK SR_STEP 1 X = don’t care. Table 29. Input Shift Register for a Read Operation MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0 R/W DUT_AD1 DUT_AD0 RD4 RD3 RD2 RD1 RD0 X1 1 X = don’t care. Table 30. Read Addresses (Bits[RD4:RD0]) RD4 RD3 RD2 RD1 RD0 Function 0 0 0 0 0 Read DAC A data register 0 0 0 0 1 Read DAC B data register 0 0 0 1 0 Read DAC C data register 0 0 0 1 1 Read DAC D data register 0 0 1 0 0 Read DAC A control register 0 0 1 0 1 Read DAC B control register 0 0 1 1 0 Read DAC C control register 0 0 1 1 1 Read DAC D control register 0 1 0 0 0 Read DAC A gain register 0 1 0 0 1 Read DAC B gain register 0 1 0 1 0 Read DAC C gain register 0 1 0 1 1 Read DAC D gain register 0 1 1 0 0 Read DAC A offset register 0 1 1 0 1 Read DAC B offset register 0 1 1 1 0 Read DAC C offset register 0 1 1 1 1 Read DAC D offset register 1 0 0 0 0 Read DAC A clear code register 1 0 0 0 1 Read DAC B clear code register 1 0 0 1 0 Read DAC C clear code register 1 0 0 1 1 Read DAC D clear code register 1 0 1 0 0 Read DAC A slew rate control register 1 0 1 0 1 Read DAC B slew rate control register 1 0 1 1 0 Read DAC C slew rate control register 1 0 1 1 1 Read DAC D slew rate control register 1 1 0 0 0 Read status register 1 1 0 0 1 Read main control register 1 1 0 1 0 Read dc-to-dc control register Rev. F | Page 31 of 44

AD5737 Data Sheet Status Register register contents can be read back on the SDO pin during every write sequence. Alternatively, if the STATREAD bit is not set, The status register is a read-only register. This register contains the status register can be read using the normal readback any fault information, as a well as a ramp active bit (Bit D9) and operation (see the Readback Operation section). the status of the packet error checking feature (Bit D10). When the STATREAD bit in the main control register is set, the status Table 31. Decoding the Status Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DC-DCD DC-DCC DC-DCB DC-DCA User PEC Ramp Over X1 X1 X1 X1 I I I I OUT_D OUT_C OUT_B OUT_A toggle error active temp fault fault fault fault 1 X = don’t care. Table 32. Status Register Bit Descriptions Bit Name Description DC-DCD This bit is set if the dc-to-dc converter on Channel D cannot maintain compliance, for example, if the dc-to-dc converter is reaching its V voltage; in this case, the I fault bit is also set. See the DC-to-DC Converter V Functionality section for MAX OUT_D MAX more information about the operation of this bit under this condition. DC-DCC This bit is set if the dc-to-dc converter on Channel C cannot maintain compliance, for example, if the dc-to-dc converter is reaching its V voltage; in this case, the I fault bit is also set. See the DC-to-DC Converter V Functionality section for MAX OUT_C MAX more information about the operation of this bit under this condition. DC-DCB This bit is set if the dc-to-dc converter on Channel B cannot maintain compliance, for example, if the dc-to-dc converter is reaching its V voltage; in this case, the I fault bit is also set. See the DC-to-DC Converter V Functionality section for MAX OUT_B MAX more information about the operation of this bit under this condition. DC-DCA This bit is set if the dc-to-dc converter on Channel A cannot maintain compliance, for example, if the dc-to-dc converter is reaching its V voltage; in this case, the I fault bit is also set. See the DC-to-DC Converter V Functionality section for MAX OUT_A MAX more information about the operation of this bit under this condition. User Toggle User toggle bit. This bit is set or cleared via the software register and can be used to verify data communications, if needed. PEC Error Denotes a PEC error on the last data-word received over the SPI interface. Ramp Active This bit is set while any output channel is slewing (digital slew rate control is enabled on at least one channel). Over Temp This bit is set if the AD5737 core temperature exceeds approximately 150°C. I Fault This bit is set if a fault is detected on the I pin. OUT_D OUT_D I Fault This bit is set if a fault is detected on the I pin. OUT_C OUT_C I Fault This bit is set if a fault is detected on the I pin. OUT_B OUT_B I Fault This bit is set if a fault is detected on the I pin. OUT_A OUT_A Rev. F | Page 32 of 44

Data Sheet AD5737 DEVICE FEATURES FAULT OUTPUT The output data from the calibration is routed to the DAC input register. This data is then loaded to the DAC, as described in the The AD5737 is equipped with a FAULT pin, an active low, Serial Interface section. Both the gain register and the offset open-drain output that allows several AD5737 devices to be register have 12 bits of resolution. The correct order to calibrate connected together to one pull-up resistor for global fault the gain and offset is to first calibrate the gain and then calibrate detection. The FAULT pin is forced active by any one of the the offset. following fault conditions: The value (in decimal) that is written to the DAC input register • The voltage at I attempts to rise above the compliance OUT_x can be calculated as follows: range due to an open-loop circuit or insufficient power supply voltage. The internal circuitry that develops the (M+1) Code =D× +C−211 (1) fault output avoids using a comparator with windowed DACRegister 212 limits because this requires an actual output error before where: the FAULT output becomes active. Instead, the signal is D is the code loaded to the DAC data register of the generated when the internal amplifier in the output stage DAC channel. has less than approximately 1 V of remaining drive M is the code in the gain register (default code = 212 − 1). capability. Thus, the FAULT output is activated slightly C is the code in the offset register (default code = 211). before the compliance limit is reached. STATUS READBACK DURING A WRITE • An interface error is detected due to a PEC failure (see the Packet Error Checking section). The AD5737 can be configured to read back the contents of • The core temperature of the AD5737 exceeds approxi- the status register during every write sequence. This feature is enabled using the STATREAD bit in the main control register. mately 150°C. When this feature is enabled, the user can continuously monitor The IOUT_x fault, PEC error, and over temp bits of the status the status register and act quickly in the case of a fault. register are used in conjunction with the FAULT output to When status readback during a write is enabled, the contents inform the user which fault condition caused the FAULT of the 16-bit status register (see Table 32) are output on the SDO output to be activated. pin, as shown in Figure 5. DIGITAL OFFSET AND GAIN CONTROL When the AD5737 is powered up, the status readback during a Each DAC channel has a gain (M) register and an offset (C) write feature is disabled. When this feature is enabled, readback register, which allow trimming out of the gain and offset errors of registers other than the status register is not available. To read of the entire signal chain. Data from the DAC data register is back any other register, clear the STATREAD bit before following operated on by a digital multiplier and adder controlled by the the readback sequence (see the Readback Operation section). contents of the gain and offset registers; the calibrated DAC The STATREAD bit can be set high again after the register read. data is then stored in the DAC input register (see Figure 53). If multiple units on the same SDO bus have the STATREAD DAC DATA DAC feature enabled, ensure that each unit is provided a unique REGISTER INPUT DAC REGISTER physical address (AD1 and AD0) to prevent contention on the bus. GAIN (M) If packet error checking is enabled, ignore the PEC values returned REGISTER on a status readback during a write operation. See the Packet ORFEFGSISETTE (CR) 10067-075 AErSroYrN CChHecRkiOngN sOecUtioSn C. LEAR Figure 53. Digital Offset and Gain Control CLEAR is an active high, edge sensitive input that allows the Although Figure 53 indicates a multiplier and adder for each output to be cleared to a preprogrammed 12-bit code. This code channel, the device has only one multiplier and one adder, is user-programmable via a per-channel 12-bit clear code register. which are shared by all four channels. This design has impli- cations for the update speed when several channels are updated For a channel to be cleared, set the CLR_EN bit in the DAC at once (see Table 3). control register for that channel. If the clear function on a channel is not enabled, the output remains in its current state, When data is written to the gain (M) or offset (C) register, the independent of the level of the CLEAR pin. output is not automatically updated. Instead, the next write to the DAC channel uses the new gain and offset values to perform When the CLEAR signal returns low, the relevant outputs remain a new calibration and automatically updates the channel. cleared until a new value is programmed to them. The CLEAR pin must not be asserted between the first and second commands of a normal SPI read when SYNC is high Rev. F | Page 33 of 44

AD5737 Data Sheet (represented by t6 in Figure 4). Failure to comply with this will If PEC is enabled when receiving data packets, there must be no result in the DAC outputs not being cleared and may cause the activity on SCLK between the read command and the NOP AD5737 SPI port to become unresponsive requiring a hardware command, or an incorrect PEC may be read back. See Figure 5 reset to restore SPI communications. If automatic readback of and the Readback Operation section for further information. status registers is enabled then there are no restrictions to the WATCHDOG TIMER use of the CLEAR pin. When enabled, an on-chip watchdog timer generates an alert PACKET ERROR CHECKING signal if 0x195 is not written to the software register within the To verify that data has been received correctly in noisy environ- programmed timeout period. This feature is useful to ensure ments, the AD5737 offers the option of packet error checking that communication is not lost between the MCU and the based on an 8-bit cyclic redundancy check (CRC-8). The device AD5737 and that the datapath lines are working properly (that controlling the AD5737 generates an 8-bit frame check is, SDIN, SCLK, and SYNC). If 0x195 is not received by the sequence using the following polynomial: software register within the timeout period, the ALERT pin C(x) = x + x + x + 1 signals a fault condition. The ALERT pin is active high and can 8 2 1 be connected directly to the CLEAR pin to enable a clear in the This value is added to the end of the data-word, and 32 bits are event that communication from the MCU is lost. sent to the AD5737 before SYNC goes high. If the AD5737 sees a To enable the watchdog timer and set the timeout period (5 ms, 32-bit frame, it performs the error check when SYNC goes high. 10 ms, 100 ms, or 200 ms), program the main control register If the error check is valid, the data is written to the selected register. (see Table 20 and Table 21). If the error check fails, the FAULT pin goes low and the PEC error ALERT OUTPUT bit in the status register is set. After the status register is read, FAULT returns high (assuming that there are no other faults), The AD5737 is equipped with an ALERT pin. This pin is an and the PEC error bit is cleared automatically. It is not active high CMOS output. The AD5737 also has an internal recommended to tie both AD1 and AD0 low as a short low on watchdog timer. When enabled, the watchdog timer monitors SDIN could possibly lead to a zero-scale update for DAC A. SPI communications. If 0x195 is not received by the software register within the timeout period, the ALERT pin is activated. UPDATE ON SYNC HIGH SYNC INTERNAL REFERENCE The AD5737 contains an integrated 5 V voltage reference with SCLK initial accuracy of ±5 mV maximum and a temperature coefficient MSB LSB of ±10 ppm/°C maximum. The reference voltage is buffered and is D23 D0 externally available for use elsewhere within the system. REFOUT SDIN 24-BIT DATA must be connected to REFIN to use the internal reference. 24-BIT DATA TRANSFER—NO ERROR CHECKING EXTERNAL CURRENT SETTING RESISTOR R is an internal sense resistor that is part of the voltage-to- SET UPDATE ON SYNC HIGH SYNC ONLY IF ERROR CHECKPASSED current conversion circuitry (see Figure 49). The stability of the output current value over temperature is dependent on the stability of the R value. To improve the stability of the output current SET SCLK over temperature, the internal R resistor, R1, can be bypassed SET MSB LSB D31 D8 and an external, 15 kΩ, low drift resistor can be connected to D7 D0 the R pin of theAD5737. The external resistor is selected via SDIN 24-BIT DATA 8-BIT CRC SET_x the DAC control register (see Table 23). Table 1 provides the performance specifications for the AD5737 FAULT 32-BIT DATA TRANSFER WITH ERRIOFFR EA CRUHRLEOTC RPK ICNINH GGEOCEKSF LAOILWS 10067-180 rweistihst boor.t Th hthe eu isnet oerf naanl eRxStEeTr rneasli sRtoSErT a rnedsi satno re xatlelorwnasl f, o1r5 i kmΩp rRoSvEeTd Figure 54. PEC Timing performance over the internal R resistor option. The external SET R resistor specifications assume an ideal resistor; the actual Packet error checking can be used for transmitting and receiving SET performance depends on the absolute value and temperature data packets. If status readback during a write is enabled, ignore the coefficient of the resistor used. This directly affects the gain error PEC values returned during the status readback operation. If status of the output and, thus, the total unadjusted error. To arrive at readback during a write is disabled, the user can still use the the gain/TUE error of the output with a specific external R normal readback operation to monitor status register activity SET resistor, add the absolute error percentage of the R resistor with PEC. SET directly to the gain/TUE error of the AD5737 with the external R resistor, as shown in Table 1 (expressed in % FSR). SET Rev. F | Page 34 of 44

Data Sheet AD5737 HART CONNECTIVITY Table 34. Slew Rate Update Clock Options SR_CLOCK Update Clock Frequency1 The AD5737 has four CHART pins, one corresponding to each 0000 64 kHz output channel. A HART signal can be coupled into these pins. 0001 32 kHz The HART signal appears on the corresponding current output, 0010 16 kHz if the output is enabled. Table 33 shows the recommended input 0011 8 kHz voltages for the HART signal at the CHART pin. If these voltages 0100 4 kHz are used, the current output meets HART amplitude specifications. 0101 2 kHz Table 33. CHART Input Voltage to HART Output Current 0110 1 kHz RSET CHART Input Voltage Current Output (HART) 0111 500 Hz Internal R 150 mV p-p 1 mA p-p 1000 250 Hz SET External R 170 mV p-p 1 mA p-p 1001 125 Hz SET 1010 64 Hz Figure 55 shows the recommended circuit for attenuating and 1011 32 Hz coupling the HART signal. A minimum capacitance of C1 + C2 1100 16 Hz is required to ensure that the 1.2 kHz and 2.2 kHz HART 1101 8 Hz frequencies are not significantly attenuated at the output. The 1110 4 Hz recommended values are C1 = 22 nF and C2 = 47 nF. 1111 0.5 Hz C1 CHARTx 1 These clock frequencies are divided down from the 13 MHz internal HAORTU TMPOUDTEM C2 10067-076 oscillator (see Table 1, Figure 46, and Figure 47). Table 35. Slew Rate Step Size Options Figure 55. Coupling the HART Signal SR_STEP Step Size (LSB) Digitally controlling the slew rate of the output is necessary to 000 1 meet the analog rate of change requirements for HART. 001 2 If the HART feature is not required, leave the CHART pins 010 4 open circuit. 011 16 100 32 DIGITAL SLEW RATE CONTROL 101 64 The digital slew rate control feature of the AD5737 allows the 110 128 user to control the rate at which the output value changes. With 111 256 the slew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached The following equation describes the slew rate as a function of load. To reduce the slew rate, the user can enable the digital slew the step size, the update clock frequency, and the LSB size. rate control feature using the SREN bit of the slew rate control SlewRate= register (see Table 28). OutputChange When slew rate control is enabled, the output, instead of slewing StepSize×UpdateClockFrequency ×LSBSize directly between two values, steps digitally at a rate defined by the SR_CLOCK and SR_STEP parameters. These parameters where: are accessible via the slew rate control register (see Table 28). Slew Rate is expressed in seconds. Output Change is expressed in amperes. • SR_CLOCK defines the rate at which the digital slew is updated; for example, if the selected update rate is 8 kHz, The update clock frequency for any given value is the same for the output is updated every 125 µs. all output ranges. The step size, however, varies across output • SR_STEP defines by how much the output value changes ranges for a given value of step size because the LSB size is at each update. different for each output range. When the slew rate control feature is enabled, all output changes Together, these parameters define the rate of change of the occur at the programmed slew rate (see the DC-to-DC output value. Table 34 and Table 35 list the range of values for Converter Settling Time section for more information). For the SR_CLOCK and SR_STEP parameters, respectively. example, if the CLEAR pin is asserted, the output slews to the clear value at the programmed slew rate (assuming that the channel is enabled to be cleared). Rev. F | Page 35 of 44

AD5737 Data Sheet If more than one channel is enabled for digital slew rate control, DC-to-DC Converter Output Voltage care must be taken when asserting the CLEAR pin. If a channel When a channel current output is enabled, the converter regulates under slew rate control is slewing when the CLEAR pin is asserted, the V supply to 7.4 V (±5%) or (I × R + Headroom), BOOST_x OUT LOAD other channels under slew rate control may change directly to whichever is greater (see Figure 31 for a plot of headroom supplied their clear code not under slew rate control. vs. output current). When the output is disabled, the converter DYNAMIC POWER CONTROL regulates the V supply to 7.4 V (±5%). BOOST_x The AD5737 provides integrated dynamic power control using DC-to-DC Converter Settling Time a dc-to-dc boost converter circuit. This circuit reduces power The settling time for a step greater than ~1 V (I × R ) is OUT LOAD consumption compared with standard designs. dominated by the settling time of the dc-to-dc converter. The In standard current input module designs, the load resistor exception to this is when the required voltage at the IOUT_x pin values can range from typically 50 Ω to 750 Ω. Output module plus the compliance voltage is below 7.4 V (±5%). Figure 26 systems must source enough voltage to meet the compliance shows a typical plot of the output settling time. This plot is for voltage requirement across the full range of load resistor values. a 1 kΩ load. The settling time for smaller loads is faster. The For example, in a 4 mA to 20 mA loop when driving 20 mA, a settling time for current steps less than 24 mA is also faster. compliance voltage of >15 V is required. When driving 20 mA DC-to-DC Converter V Functionality MAX into a 50 Ω load, a compliance voltage of only 1 V is required. The maximum V voltage is set in the dc-to-dc control BOOST_x The AD5737 circuitry senses the output voltage and regulates register (23 V, 24.5 V, 27 V, or 29.5 V; see Table 27). When the this voltage to meet the compliance requirements plus a small maximum voltage is reached, the dc-to-dc converter is disabled, headroom voltage. The AD5737 is capable of driving up to and the V voltage is allowed to decay by ~0.4 V. After the BOOST_x 24 mA through a 1 kΩ load. V voltage decays by ~0.4 V, the dc-to-dc converter is BOOST_x DC-TO-DC CONVERTERS reenabled, and the voltage ramps up again to VMAX, if still required. This operation is shown in Figure 57. The AD5737 contains four independent dc-to-dc converters. 29.6 These are used to provide dynamic control of the VBOOST_x supply VDMCA-DXCx BIT O0mUATPTUOT 2U4NmLAO RAADNEGDE, 24mA OUTPUT voltage for each channel (see Figure 49). Figure 56 shows the 29.5 discrete components needed for the dc-to-dc circuitry, and the 29.4 following sections describe component selection and operation V) 29.3 of this circuitry. GE ( 29.2 A AVCC LDCDC DDCDC RFILTER VBOOST_x VOLT 29.1 ≥10CµIFN 10µH SWx C4.D7CµDFC 10Ω C0.F1IµLTFER 10067-077 V BOOST_x 2289..90 DC-DCx BIT = 1 DCfTSA-WD = C= 2 45M1°C0akxHVz BITS = 29.5V Figure 56. DC-to-DC Circuit 28.8 28.7 Table 36. Recommended Components for a DC-to-DC Converter DC-DCx BIT = 0 SLDyCmDCb ol CXAomL4p0o40n-e1n0t3 V10a lµuHe CMoailncuraffatc®t urer 28.60 0.5 1.0 1.5 TIM2E. 0(ms) 2.5 3.0 3.5 4.0 10067-183 CDCDC GRM32ER71H475KA88L 4.7 µF Murata Figure 57. Operation on Reaching VMAX D PD3S160-7 0.55 V Diodes, Inc. DCDC F As shown in Figure 57, the DC-DCx bit in the status register It is recommended that a 10 Ω, 100 nF low-pass RC filter be is asserted when the AD5737 ramps up to the VMAX value but placed after CDCDC. This filter consumes a small amount of power is deasserted when the voltage decays to VMAX − ~0.4 V. but reduces the amount of ripple on the VBOOST_x supply. DC-to-DC Converter On-Board Switch DC-to-DC Converter Operation The AD5737 contains a 0.425 Ω internal switch. The switch The on-board dc-to-dc converters use a constant frequency, peak current is monitored on a pulse-by-pulse basis and is limited current mode control scheme to step up an AV input of 4.5 V to 0.8 A peak current. CC to 5.5 V to drive the AD5737 output channel. These converters are designed to operate in discontinuous conduction mode with a duty cycle of <90% typical. Discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. The dc-to-dc converters are nonsynchronous; that is, they require an external Schottky diode. Rev. F | Page 36 of 44

Data Sheet AD5737 DC-to-DC Converter Switching Frequency and Phase requirements of the AV supply while slewing (see the AI CC CC Supply Requirements—Slewing section). The capacitance at The AD5737 dc-to-dc converter switching frequency can be the output of the dc-to-dc converter must be >3 µF under all selected from the dc-to-dc control register (see Table 27). The operating conditions. phasing of the channels can also be adjusted so that the dc-to-dc converters can clock on different edges. For typical applications, The input capacitor provides much of the dynamic current a 410 kHz frequency is recommended. At light loads (low output required for the dc-to-dc converter and must be a low ESR current and small load resistor), the dc-to-dc converter enters a component. For the AD5737, a low ESR tantalum or ceramic pulse-skipping mode to minimize switching power dissipation. capacitor of 10 µF is recommended for typical applications. DC-to-DC Converter Inductor Selection Ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature. For typical 4 mA to 20 mA applications, a 10 µH inductor (such X5R or X7R dielectrics are preferred because these capacitors as the XAL4040-103 from Coilcraft), combined with a switching remain stable over wider operating voltage and temperature frequency of 410 kHz, allows up to 24 mA to be driven into a ranges. Care must be taken if selecting a tantalum capacitor to load resistance of up to 1 kΩ with an AV supply of 4.5 V to CC ensure a low ESR value. 5.5 V. It is important to ensure that the inductor can handle the AI SUPPLY REQUIREMENTS—STATIC peak current without saturating, especially at the maximum CC ambient temperature. If the inductor enters saturation mode, The dc-to-dc converter is designed to supply a V voltage of BOOST_x efficiency decreases. The inductance value also drops during V = I × R + Headroom (2) BOOST_x OUT LOAD saturation and may result in the dc-to-dc converter circuit not being able to supply the required output power. See Figure 31 for a plot of headroom supplied vs. output current. Therefore, for a fixed load and output voltage, the DC-to-DC Converter External Schottky Diode Selection output current of the dc-to-dc converter can be calculated The AD5737 requires an external Schottky diode for correct by the following formula: operation. Ensure that the Schottky diode is rated to handle the PowerOut I ×V maximum reverse breakdown voltage expected in operation AI = = OUT BOOST (3) and that the maximum junction temperature of the diode is not CC Efficiency×AVCC ηVBOOST ×AVCC exceeded. The average current of the diode is approximately where: equal to the I current. Diodes with larger forward voltage LOAD I is the output current from I in amperes. OUT OUT_x drops result in a decrease in efficiency. η is the efficiency at V as a fraction (see Figure 33 VBOOST BOOST_x DC-to-DC Converter Compensation Capacitors and Figure 34). Because the dc-to-dc converter operates in discontinuous conduc- AI SUPPLY REQUIREMENTS—SLEWING CC tion mode, the uncompensated transfer function is essentially a The AI current requirement while slewing is greater than in single-pole transfer function. The pole frequency of the transfer CC static operation because the output power increases to charge function is determined by the output capacitance, input and output the output capacitance of the dc-to-dc converter. This transient voltage, and output load of the dc-to-dc converter. The AD5737 current can be quite large (see Figure 58), although the methods uses an external capacitor in conjunction with an internal 150 kΩ described in the Reducing AI Current Requirements section resistor to compensate the regulator loop. CC can reduce the requirements on the AV supply. CC Alternatively, an external compensation resistor can be used in If not enough AI current can be provided, the AV voltage series with the compensation capacitor by setting the DC-DC CC CC drops. Due to this AV drop, the AI current required for comp bit in the dc-to-dc control register (see Table 27). In this CC CC slewing increases further, causing the voltage at AV to drop case, a resistor of ~50 kΩ is recommended. The advantages of this CC further (see Equation 3). In this case, the V voltage and, configuration are described in the AI Supply Requirements— BOOST_x CC therefore, the output voltage, may never reach their intended Slewing section. For typical applications, a 10 nF dc-to-dc com- values. Because the AV voltage is common to all channels, pensation capacitor is recommended. CC this voltage drop may also affect other channels. DC-to-DC Converter Input and Output Capacitor Selection The output capacitor affects the ripple voltage of the dc-to-dc converter and indirectly limits the maximum slew rate at which the channel output current can rise. The ripple voltage is caused by a combination of the capacitance and the equivalent series resistance (ESR) of the capacitor. For typical applications, a ceramic capacitor of 4.7 µF is recommended. Larger capacitors or parallel capacitors improve the ripple at the expense of reduced slew rate. Larger capacitors also affect the current Rev. F | Page 37 of 44

AD5737 Data Sheet 0.8 0.8 32 00..67 2350 OLTAGE (V) 00..67 AIVOBIUCOTCOST INDUCTOR 0=m 1A0µTHO (2Xf4SAm5WL0A 40=0 Ω R44 A0L1-0NO1kG0AH3EDz) 2248 OLTAGE (V) AI CURRENT (A)CC 000...345 INDUCTOR 0=m 1A0µTHO (2Xf4SAmWL1AT 4k=0 AΩ R44 =A01L -0NO21k5G0AH°3EDCz) 112050 ENT (mA)/V VBOOST_x AI CURRENT (A)CC 000...345 TA = 25°C 112260 ENT (mA)/V VBOOST_x R R 0.2 R 0.2 8 R U U 0.1 AIVOBIUCOTCOST 5 COUT_x 0.1 4 COUT_x I I 00 0.5 1.0TIME (ms)1.5 2.0 2.50 10067-184 00 0.5 1.0TIME (ms)1.5 2.0 2.50 10067-186 Figure 58. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load Figure 60. AICC Current vs. Time for 24 mA Step Through 500 Ω Load with Internal Compensation Resistor with External 51 kΩ Compensation Resistor Reducing AICC Current Requirements Using Slew Rate Control Two main methods can be used to reduce the AICC current Using slew rate control can greatly reduce the current require- requirements. One method is to add an external compensation ments of the AV supply, as shown in Figure 61. CC resistor, and the other is to use slew rate control. These methods 0.8 32 can be used together. 0mATO 24mA RANGE V) Adding an External Compensation Resistor 0.7 I1fNSkWDΩU =LC O4T1AO0DkRH =z 10µH (XAL4040-103) 28 AGE ( 0.6 TA = 25°C 24 OLT tAininnraa c clsnr oecesrmoaiiemsepnesespt w netchsnuitaesrht arsi etotliehnnowet n r r1 teeri0smeqi ssnueitsFio rot reocf m roct ahmiesnen p rctbeesuecn. r oFsprmaeilgtanimucote rnoedeun c5atdap9tep u tdsahth.c e boTi tuCwohtrO sir.s ea MAcd po uP5lmco1Det Cpks Doe ΩCtnfh_ xsAee ap xIAtiCtineoCICr nC- AI CURRENT (A)CC 000...345 AIVOBIUCOTCOST 112260 NT (mA)/V VBOOST_x current for a 24 mA step through a 1 kΩ load when using a 51 kΩ RE 0.2 8 R compensation resistor. The compensation resistor reduces the CU current requirements through smaller loads even further, as 0.1 4 UT_x O shown in Figure 60. I 0.8 01mkΩA LTOOA 2D4mA RANGE 32 V) 00 1 2 TIME3 (ms) 4 5 60 10067-187 0.7 fINSWDU =C 4T1O0kRH =z 10µH (XAL4040-103) 28 AGE ( Figure 61. AICC Currentw vitsh. T Simlewe fRoar t2e4 C monAt Srotel p Through 1 kΩ Load 0.6 TA = 25°C 24 OLT V When using slew rate control, it is important to remember that NT (A) 0.5 20 OST_x the output cannot slew faster than the dc-to-dc converter. The AI CURRECC 00..34 1126 NT (mA)/VBO lodancr- gtteho -elod cacod cnsof (ingfvouerrr aettxeirao mnsl epowlfe st, h1sel ok dwΩce-)st. otT -ahdt ech sicgloehnwev rre acrtuteer rri.s eT nawtlssoo t hedxreoapmuegnphdle esn ot f RE the dc-to-dc converter output slew are shown in Figure 59 and 0.2 8 R 0.1 AIVOBIUCOTCOST 4 CUOUT_x Fdicg-utor-ed 6c0 c. o(VnvBeOrOtSeTr c.)o rresponds to the output voltage of the 00 0.5 1.0TIME (ms)1.5 2.0 2.50 I 10067-185 EThXeT AEDR5N7A37L c PanM aOlsoS bMe OusDedE w ith an external PMOS transistor Figure 59. AICC Current vs. Time for 24 mA Step Through 1 kΩ Load per channel, as shown in Figure 62. This mode can be used to with External 51 kΩ Compensation Resistor limit the on-chip power dissipation of the AD5737, although this mode does not reduce the power dissipation of the total system. The IGATEx functionality is not typically required when using the dynamic power control feature; therefore, Figure 62 shows the configuration of the device for a fixed V supply. BOOST_x In this configuration, the SW pin is left floating, and the GNDSW x x pin is grounded. The V pin is connected to a minimum BOOST_x Rev. F | Page 38 of 44

Data Sheet AD5737 supply of 7.4 V and a maximum supply of 33 V. This supply can dissipation required. Choose the V to accommodate for the GS be sized according to the maximum load required to be driven. I headroom. The external PMOS transistor typically has OUT minimal effect on the current output performance. The IGATEx functionality works by holding the gate of the external PMOS transistor at (V − 5 V). This means that BOOST_x the majority of the power dissipation of the channel takes place in the external PMOS transistor. Select the external PMOS transistor to tolerate a V voltage of DS at least the V voltage, as well as to handle the power BOOST_x AVCC 5.0V VBOOST_A SWA (OPEN CIRCUIT) R2 R3 DAC A IOUT_A (VBOOST_A – 5V) IGATEA R1 CURRENT OUTPUT RLOAD RSET_A CHARTA DAC CHANNEL A GNDSWA 10067-190 Figure 62. Configuration of Channel A Using IGATEx Rev. F | Page 39 of 44

AD5737 Data Sheet APPLICATIONS INFORMATION CURRENT OUTPUT MODE WITH INTERNAL R Four possible sources of error must be considered when choosing SET a voltage reference for high accuracy applications: initial accuracy, When using the internal R resistor, the current output is SET long-term drift, temperature coefficient of the output voltage, significantly affected by how many other channels using the and output voltage noise. internal R are enabled and by the dc crosstalk from these SET channels. The internal R specifications in Table 1 are for all Initial accuracy error on the output voltage of an external ref- SET four channels enabled with the internal R selected and erence can lead to a full-scale error in the DAC. Therefore, to SET outputting the same code. minimize these errors, a reference with a low initial accuracy error specification is preferred. Choosing a reference with an For every channel enabled with the internal R , the offset error SET output trim adjustment, such as the ADR435, allows a system decreases. For example, with one current output enabled using the designer to trim out system errors by setting the reference internal R , the offset error is 0.075% FSR. This value decreases SET voltage to a voltage other than the nominal. The trim adjust- proportionally as more current channels are enabled; the offset ment can be used at any temperature to trim out any error. error is 0.056% FSR on each of two channels, 0.029% FSR on each of three channels, and 0.01% FSR on each of four channels. Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight long-term drift Similarly, the dc crosstalk when using the internal R is propor- SET specification ensures that the overall solution remains relatively tional to the number of current output channels enabled with the stable over its entire lifetime. internal R . For example, with the measured channel at 0x8000 SET and another channel going from zero to full scale, the dc crosstalk The temperature coefficient of the reference output voltage affects is −0.011% FSR. With two other channels going from zero to full INL, DNL, and TUE. Choose a reference with a tight temperature scale, the dc crosstalk is −0.019% FSR, and with all three other coefficient specification to reduce the dependence of the DAC channels going from zero to full scale, it is −0.025% FSR. output voltage on ambient temperature. For the full-scale error measurement in Table 1, all channels are In high accuracy applications, which have a relatively low noise at 0xFFFF. This means that as any channel goes to zero scale, the budget, reference output voltage noise must be considered. Choos- full-scale error increases due to the dc crosstalk. For example, ing a reference with as low an output noise voltage as practical with the measured channel at 0xFFFF and three channels at for the system resolution required is important. Precision voltage zero scale, the full-scale error is 0.025% FSR. Similarly, if only references such as the ADR435 (XFET® design) produce low output one channel is enabled with the internal R , the full-scale error noise in the 0.1 Hz to 10 Hz bandwidth. However, as the circuit SET is 0.025% FSR + 0.075% FSR = 0.1% FSR. bandwidth increases, filtering the output of the reference may be required to minimize the output noise. PRECISION VOLTAGE REFERENCE SELECTION DRIVING INDUCTIVE LOADS To achieve the optimum performance from the AD5737 over its full operating temperature range, a precision voltage reference When driving inductive or poorly defined loads, a capacitor must be used. Take care with the selection of the precision voltage may be required between the IOUT_x pin and the AGND pin to reference. The voltage applied to the reference inputs is used to ensure stability. A 0.01 µF capacitor between IOUT_x and AGND provide a buffered reference for the DAC cores. Therefore, any ensures stability of a load of 50 mH. The capacitive component error in the voltage reference is reflected in the outputs of the of the load may cause slower settling, although this may be AD5737. masked by the settling time of the AD5737. There is no maxi- mum capacitance limit for the current output of the AD5737. Table 37. Recommended Precision Voltage References Initial Accuracy Long-Term Drift Temperature Coefficient 0.1 Hz to 10 Hz Noise Part No. (mV Maximum) (ppm Typical) (ppm/°C Maximum) (µV p-p Typical) ADR445 ±2 50 3 2.25 ADR02 ±3 50 3 10 ADR435 ±2 40 3 8 ADR395 ±5 50 9 8 AD586 ±2.5 15 10 4 Rev. F | Page 40 of 44

Data Sheet AD5737 TRANSIENT VOLTAGE PROTECTION AD5737-to-ADSP-BF527 Interface The AD5737 contains ESD protection diodes that prevent dam- The AD5737 can be connected directly to the SPORT interface age from normal handling. The industrial control environment of the ADSP-BF527, an Analog Devices, Inc., Blackfin® DSP. can, however, subject I/O circuits to much higher transients. To Figure 64 shows how the SPORT interface can be connected protect the AD5737 from excessively high voltage transients, to control the AD5737. external power diodes and a surge current limiting resistor (R ) P AD5737 are required, as shown in Figure 63. A typical value for R is 10 Ω. P SPORT_TFS SYNC The two protection diodes and the resistor (R) must have appro- P SPORT_TSCLK SCLK priate power ratings. SPORT_DT0 SDIN (FROM DC-TO-DC RFILTER CONVERTER) C4.D7CµDFC 10Ω C0.F1IµLFTER ADSP-BF527 GPIO0 LDAC 10067-080 VBOOST_x Figure 64. AD5737-to-ADSP-BF527 SPORT Interface D1 AD5737 IOUT_x RP LAYOUT GUIDELINES AGND D2 RLOAD 10067-079 GInr aonuyn cdirincugi t where accuracy is important, careful consider- Figure 63. Output Transient Voltage Protection ation of the power supply and ground return layout helps to Further protection can be provided using transient voltage ensure the rated performance. The printed circuit board on suppressors (TVSs), also referred to as transorbs. These compo- which the AD5737 is mounted must be designed so that the nents are available as unidirectional suppressors, which protect analog and digital sections are separated and confined to against positive high voltage transients, and as bidirectional certain areas of the board. If the AD5737 is in a system where suppressors, which protect against both positive and negative multiple devices require an AGND-to-DGND connection, the high voltage transients. Transient voltage suppressors are avail- connection must be made at one point only. The star ground able in a wide range of standoff and breakdown voltage ratings. point must be established as close as possible to the device. The TVS must be sized with the lowest breakdown voltage The GNDSW pin and the ground connection for the AV x CC possible while not conducting in the functional range of the supply are referred to as PGND. PGND must be confined to current output. certain areas of the board, and the PGND-to-AGND connection It is recommended that all field connected nodes be protected. must be made at one point only. MICROPROCESSOR INTERFACING Supply Decoupling Microprocessor interfacing to the AD5737 is via a serial bus The AD5737 must have ample supply bypassing of 10 μF that uses a protocol compatible with microcontrollers and DSP in parallel with 0.1 μF on each supply, located as close to the processors. The communication channel is a 3-wire minimum package as possible, ideally right up against the device. The interface consisting of a clock signal, a data signal, and a latch 10 μF capacitors are the tantalum bead type. The 0.1 μF cap- signal. The AD5737 requires a 24-bit data-word with data valid acitors must have low effective series resistance (ESR) and low on the falling edge of SCLK. effective series inductance (ESL), such as the common ceramic types, which provide a low impedance path to ground at high The DAC output update is initiated either on the rising edge of frequencies to handle transient currents due to internal logic LDAC or, if LDAC is held low, on the rising edge of SYNC. The switching. contents of the registers can be read using the readback function. Rev. F | Page 41 of 44

AD5737 Data Sheet Traces GALVANICALLY ISOLATED INTERFACE The power supply lines of the AD5737 must use as large a trace as In many process control applications, it is necessary to provide possible to provide low impedance paths and reduce the effects of an isolation barrier between the controller and the unit being glitches on the power supply line. Fast switching signals such as controlled to protect and isolate the controlling circuitry from clocks must be shielded with digital ground to prevent radi- any hazardous common-mode voltages that may occur. The ating noise to other parts of the board and must never be run Analog Devices iCoupler® products can provide voltage isolation near the reference inputs. A ground line routed between the in excess of 2.5 kV. The serial loading structure of the AD5737 SDIN and SCLK traces helps reduce crosstalk between them (not makes it ideal for isolated interfaces because the number of inter- required on a multilayer board that has a separate ground plane, face lines is kept to a minimum. Figure 65 shows a 4-channel but separating the lines helps). It is essential to minimize noise on isolated interface to the AD5737 using an ADuM1411. For the REFIN line because it couples through to the DAC output. more information, visit www.analog.com. Avoid crossover of digital and analog signals. Traces on oppo- MICROCONTROLLER ADuM1411 site sides of the board must run at right angles to each other to reduce the effects of feedthrough on the board. A microstrip SERIAL CLOOCUKT VIA ENCODE DECODE VOA TO SCLK technique is by far the best method, but it is not always possible SERIAL DOATUAT VIB ENCODE DECODE VOB TO SDIN with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, and signal traces SYNC OUT VIC ENCODE DECODE VOC TO SYNC DarCe -ptloa-cDedC o Cno tnhve esrotledresr side. CONTROL OUT VID ENCODE DECODE VOD TO LDAC 10067-081 Figure 65. 4-Channel Isolated Interface to the AD5737 To achieve high efficiency, good regulation, and stability, a well-designed printed circuit board layout is required. Follow these guidelines when designing printed circuit boards (see Figure 56): • Keep the low ESR input capacitor, C , close to AV and IN CC PGND. • Keep the high current path from C through the inductor IN (L ) to SW and PGND as short as possible. DCDC x • Keep the high current path from C through the inductor IN (L ), the diode (D ), and the output capacitor (C ) DCDC DCDC DCDC as short as possible. • Keep high current traces as short and as wide as possible. The path from C through the inductor (L ) to SW IN DCDC x and PGND must be able to handle a minimum of 1 A. • Place the compensation components as close as possible to the COMP pin. DCDC_x • Avoid routing high impedance traces near any node connected to SW or near the inductor to prevent radiated x noise injection. Rev. F | Page 42 of 44

Data Sheet AD5737 INDUSTRIAL HART CAPABLE ANALOG OUTPUT For transient overvoltage protection, a 24 V transient voltage APPLICATION suppressor (TVS) is placed on the I /V connection. For added OUT OUT protection, clamping diodes are connected from the I /V Many industrial control applications have requirements for OUT_x OUT_x pin to the AV and GND power supply pins. A 5 kΩ current accurately controlled current output signals, and the AD5737 DD limiting resistor is also placed in series with the +V input. is ideal for such applications. Figure 66 shows the AD5737 in SENSE_x This is to limit the current to an acceptable level during a transient a circuit design for a HART-enabled output module, specifically event. The recommended external band-pass filter for the AD5700 for use in an industrial control application. HART modem includes a 150 kΩ resistor, which limits current The design provides for a HART-enabled current output, with to a sufficiently low level to adhere to intrinsic safety requirements. the HART capability provided by the AD5700/AD5700-1 HART In this case, the input has higher transient voltage protection and, modem, the industry’s lowest power and smallest footprint HART- therefore, does not require additional protection circuitry, even compliant IC modem. For additional space-savings, the AD5700-1 in the most demanding of industrial environments. offers a 0.5% precision internal oscillator. The HART_OUT signal from the AD5700 is attenuated and ac-coupled into the CHARTx pin of the AD5737. Such a configuration results in the AD5700 HART modem output modulating the 4 mA to 20 mA analog current without affecting the dc level of the current. This circuit adheres to the HART physical layer specifications as defined by the HART Communication Foundation. 10µF +15V +5V 0.1µF 2.7V TO 5.5V DVDD AVDD AVCC SW(X4) VBOOST(X4) 10µF 10kΩ IOUT B,C,D 0.1µF RESET ALERT CHART B,C,D FAULT CLEAR SYNC AD5737 MCU SCLK D2 RP SDIN IOUTA SDO D3 4.20mA D1 CURRENTLOOP UART INTERFACE LDAC RL DGND REFOUT REFIN CHART A GND 0.1µF 0.1µF 22nF C1 47nF C2 VCC TXD HART_OUT RXD RTS CD AD5700/AD5700-1 REF 1µF 1.2MQ 150kΩ ADC_IP GND 1.2MQ 300pF 150pF 10067-065 Figure 66. AD5737 in HART Configuration Rev. F | Page 43 of 44

AD5737 Data Sheet OUTLINE DIMENSIONS 9.10 0.60 9.00 SQ 0.60 0.42 8.90 0.42 0.24 PIN 1 0.24 INDICATOR 49 64 1 48 PIN 1 INDICATOR 8.85 0.50 EXPOSED 7.25 8.75 SQ BSC PAD 7.10 SQ 8.65 6.95 0.50 0.40 3332 1716 0.30 0.25 MIN TOP VIEW BOTTOM VIEW 7.50 REF 1.00 12° MAX 0.80 MAX 0.65 NOM 0.85 0.05 MAX FOR PROPER CONNECTION OF 0.80 0.02 NOM THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND SEATING 0.30 FUNCTION DESCRIPTIONS PLANE 0.23 0.20 REF SECTION OF THIS DATA SHEET. PKG-001152 0.18COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 01-22-2015-D Figure 67. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters ORDERING GUIDE Model1 Resolution (Bits) Temperature Range Package Description Package Option AD5737ACPZ 12 −40°C to +105°C 64-Lead LFCSP_VQ CP-64-3 AD5737ACPZ-RL7 12 −40°C to +105°C 64-Lead LFCSP_VQ CP-64-3 1 Z = RoHS Compliant Part. ©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10067-0-5/17(F) Rev. F | Page 44 of 44