Complete, Quad, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DACs Data Sheet AD5724/AD5734/AD5754 FEATURES GENERAL DESCRIPTION Complete, quad, 12-/14-/16-bit digital-to-analog The AD5724/AD5734/AD5754 are quad, 12-/14-/16-bit, serial converter (DAC) input, voltage output DACs. The devices operate from single- Operates from single/dual supplies supply voltages from +4.5 V up to +16.5 V or dual-supply Software programmable output range voltages from ±4.5 V up to ±16.5 V. Nominal full-scale output +5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V range is software-selectable from +5 V, +10 V, +10.8 V, ±5 V, INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum ±10 V, or ±10.8 V. Integrated output amplifiers, reference buffers, Total unadjusted error (TUE): 0.1% FSR maximum and proprietary power-up/power-down control circuitry are also Settling time: 10 µs typical provided. Integrated reference buffers The devices offer guaranteed monotonicity, integral Output control during power-up/brownout nonlinearity (INL) of ±16 LSB maximum, low noise, and 10 µs Simultaneous updating via LDAC maximum settling time. Asynchronous CLR to zero scale or midscale DSP-/microcontroller-compatible serial interface The AD5724/AD5734/AD5754 use a serial interface that operates 24-lead TSSOP at clock rates up to 30 MHz and are compatible with DSP and Operating temperature range: −40°C to +85°C microcontroller interface standards. Double buffering allows iCMOS process technology1 the simultaneous updating of all DACs. The input coding is user-selectable twos complement or offset binary for a bipolar APPLICATIONS output (depending on the state of Pin BIN/2sComp), and straight Industrial automation binary for a unipolar output. The asynchronous clear function Closed-loop servo control, process control clears all DAC registers to a user-selectable zero-scale or midscale Automotive test and measurement output. The devices are available in a 24-lead TSSOP and offer Programmable logic controllers guaranteed specifications over the −40°C to +85°C industrial temperature range. FUNCTIONAL BLOCK DIAGRAM AVSS AVDD REFIN DVCC AD5724/AD5734/AD5754 REFERENCE BUFFERS n n INPUT DAC SDIN INPUTSHIFT REGISTER A REGISTER A DACA VOUTA REGISTER SCLK AND SYNC CONTROL INPUT DAC n LOGIC REGISTER B REGISTER B DACB VOUTB SDO INPUT DAC n REGISTER C REGISTER C DACC VOUTC CLR BIN/2sCOMP n REGINISPTUETR D REGDISATCER D DACD VOUTD AAADDD555777235444::: nnn === 111246---BBBIIITTT GND LDAC DAC_GND (2) SIG_GND (2) 06468-001 Figure 1. 1 For analog systems designers within industrial/instrumentation equipment OEMs that need high performance ICs at higher-voltage levels, iCMOS® is a technology platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and package size, as well as increased ac and dc performance. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5724/AD5734/AD5754 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Transfer Function ....................................................................... 20 Applications ....................................................................................... 1 Input Shift Register .................................................................... 24 General Description ......................................................................... 1 DAC Register .............................................................................. 24 Functional Block Diagram .............................................................. 1 Output Range Select Register ................................................... 25 Revision History ............................................................................... 2 Control Register ......................................................................... 25 Specifications ..................................................................................... 3 Power Control Register.............................................................. 26 AC Performance Characteristics ................................................ 5 Features ............................................................................................ 27 Timing Characteristics ................................................................ 5 Analog Output Control ............................................................. 27 Timing Diagrams .......................................................................... 6 Power-Down Mode .................................................................... 27 Absolute Maximum Ratings ............................................................ 8 Overcurrent Protection ............................................................. 27 ESD Caution .................................................................................. 8 Thermal Shutdown .................................................................... 27 Pin Configuration and Function Descriptions ............................. 9 Applications Information .............................................................. 28 Typical Performance Characteristics ........................................... 10 +5 V/±5 V Operation ................................................................ 28 Terminology .................................................................................... 16 Alternative Power-Up Sequence Support ............................... 28 Theory of Operation ...................................................................... 18 Layout Guidelines....................................................................... 28 Architecture ................................................................................. 18 Galvanically Isolated Interface ................................................. 29 Power-Up Sequence ................................................................... 18 Voltage Reference Selection ...................................................... 29 Serial Interface ............................................................................ 18 Microprocessor Interfacing ....................................................... 29 Load DAC (LDAC)..................................................................... 20 Outline Dimensions ....................................................................... 31 Asynchronous Clear (CLR) ....................................................... 20 Ordering Guide .......................................................................... 31 Configuring the AD5724/AD5734/AD5754 .......................... 20 REVISION HISTORY 2/2017—Rev. E to Rev. F Added Power-Up Sequence Section ............................................. 18 3/2011—Rev. B to Rev. C Changes to Table 7 and Table 8 ..................................................... 21 Changes to Configuring the AD5724/AD5734/AD5754 Changes to Table 10 and Table 11 ................................................ 22 Section .............................................................................................. 20 Changes to Table 13 and Table 14 ................................................ 23 Changes to Analog Output Control Section ............................... 27 8/2010—Rev. A to Rev. B Added Alternative Power-Up Sequence Support Section, Changes to Table 27 ....................................................................... 26 Figure 43, and Figure 44; Renumbered Sequentially ................. 28 4/2010—Rev. 0 to Rev. A 2/2016—Rev. D to Rev. E Changes to Junction Temperature, T max Parameter, Table 4 ... 8 J Changes to Table 1...................................................................................... 3 Changes to Exposed Pad Description, Table 5 .............................. 9 Change to Table 5 ......................................................................................... 9 Added Exposed Paddle Notation to Outline Dimensions ........ 30 7/2011—Rev. C to Rev. D 8/2008—Revision 0: Initial Version Changes to Table 3: t7, t8, t10 Limits ....................................................... 5 Rev. F | Page 2 of 31

Data Sheet AD5724/AD5734/AD5754 SPECIFICATIONS AV = 4.5 V1 to 16.5 V; AV = −4.5 V1 to −16.5 V, or 0 V; GND = 0 V; REFIN= 2.5 V; DV = 2.7 V to 5.5 V; R = 2 kΩ; DD SS CC LOAD C = 200 pF; all specifications T to T . LOAD MIN MAX Table 1. Parameter Min Typ Max Unit Test Conditions/Comments ACCURACY Outputs unloaded Resolution AD5754 16 Bits AD5734 14 Bits AD5724 12 Bits Total Unadjusted Error (TUE) A Version −0.3 +0.3 % FSR ±10 V range B Version −0.1 +0.1 % FSR ±10 V range Relative Accuracy (INL)2 AD5754 −16 +16 LSB AD5734 −4 +4 LSB AD5724 −1 +1 LSB Differential Nonlinearity (DNL) −1 +1 LSB All models, all versions, guaranteed monotonic Bipolar Zero Error −6 +6 mV ±10 V range, TA = 25°C, error at other temp- eratures obtained using bipolar zero error TC Bipolar Zero Error TC3 ±4 ppm FSR/°C Zero-Scale Error −6 +6 mV ±10 V range, TA = 25°C, error at other temp- eratures obtained using zero-scale error TC Zero-Scale Error TC3 ±4 ppm FSR/°C Offset Error −6 +6 mV +10 V range, TA = 25°C, error at other temperatures obtained using offset error TC Offset Error TC3 ±4 ppm FSR/°C Gain Error −0.025 +0.025 % FSR ±10 V range, T = 25°C, error at other A temperatures obtained using gain error TC Gain Error3 −0.065 0 % FSR +10 V and +5 V ranges, T = 25°C, error at other A temperatures obtained using gain error TC Gain Error3 0 +0.08 % FSR ±5 V range, T = 25°C, error at other A temperatures obtained using gain error TC Gain Error TC3 ±8 ppm FSR/°C DC Crosstalk3 120 µV REFERENCE INPUT3 Reference Input Voltage 2.5 V ±1% for specified performance DC Input Impedance 1 5 MΩ Input Current −2 ±0.5 +2 µA Reference Range 2 3 V OUTPUT CHARACTERISTICS3 Output Voltage Range −10.8 +10.8 V AV /AV = ±11.7 V min, REFIN = +2.5 V DD SS −12 +12 V AV /AV = ±12.9 V min, REFIN = +3 V DD SS Headroom Required 0.5 0.9 V Output Voltage TC ±4 ppm FSR/°C Short-Circuit Current 20 mA Load 2 kΩ For specified performance Capacitive Load Stability 4000 pF DC Output Impedance 0.5 Ω Rev. F | Page 3 of 31

AD5724/AD5734/AD5754 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments DIGITAL INPUTS3 DV = 2.7 V to 5.5 V, JEDEC compliant CC Input High Voltage, V 2 V IH Input Low Voltage, V 0.8 V IL Input Current ±1 µA Per pin Pin Capacitance 5 pF Per pin DIGITAL OUTPUTS (SDO)3 Output Low Voltage, V 0.4 V DV = 5 V ± 10%, sinking 200 µA OL CC Output High Voltage, V DV − 1 V DV = 5 V ± 10%, sourcing 200 µA OH CC CC Output Low Voltage, V 0.4 V DV = 2.7 V to 3.6 V, sinking 200 µA OL CC Output High Voltage, V DV − 0.5 V DV = 2.7 V to 3.6 V, sourcing 200 µA OH CC CC High Impedance Leakage Current −1 +1 µA High Impedance Output Capacitance 5 pF POWER REQUIREMENTS AV 4.5 16.5 V DD AV −4.5 −16.5 V SS DV 2.7 5.5 V CC Power Supply Sensitivity3 ∆V /∆ΑV −65 dB OUT DD AI 2.5 mA/channel Outputs unloaded DD 1.75 mA/channel AV = 0 V, outputs unloaded SS AI 2.2 mA/channel Outputs unloaded SS DI 0.5 3 µA V = DV , V = GND CC IH CC IL Power Dissipation 310 mW ±16.5 V operation, outputs unloaded 115 mW 16.5 V operation, AV = 0 V, outputs unloaded SS Power-Down Currents AI 40 µA DD AI 40 µA SS DI 300 nA CC 1 For specified performance, maximum headroom requirement is 0.9 V. 2 INL is measured from Code 512, Code 128, and Code 32 for the AD5754, the AD5734, and the AD5724, respectively. 3 Guaranteed by characterization; not production tested. Rev. F | Page 4 of 31

Data Sheet AD5724/AD5734/AD5754 AC PERFORMANCE CHARACTERISTICS AV = 4.5 V1 to 16.5 V; AV = −4.5 V1 to −16.5 V, or 0 V; GND = 0 V; REFIN= 2.5 V; DV = 2.7 V to 5.5 V; R = 2 kΩ; DD SS CC LOAD C = 200 pF; all specifications T to T . LOAD MIN MAX Table 2. A, B Version Parameter2 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 10 12 µs 20 V step to ±0.03% FSR 7.5 8.5 µs 10 V step to ±0.03% FSR 5 µs 512 LSB step settling (16-bit resolution) Slew Rate 3.5 V/µs Digital-to-Analog Glitch Energy 13 nV-sec Glitch Impulse Peak Amplitude 35 mV Digital Crosstalk 10 nV-sec DAC to DAC Crosstalk 10 nV-sec Digital Feedthrough 0.6 nV-sec Output Noise 0.1 Hz to 10 Hz Bandwidth 15 µV p-p 0x8000 DAC code 100 kHz Bandwidth 80 µV rms Output Noise Spectral Density 320 nV/√Hz Measured at 10 kHz, 0x8000 DAC code 1 For specified performance, maximum headroom requirement is 0.9 V. 2 Guaranteed by design and characterization. Not production tested. TIMING CHARACTERISTICS AV = 4.5 V to 16.5 V; AV = −4.5 V to −16.5 V, or 0 V; GND = 0 V; REFIN = 2.5 V; DV = 2.7 V to 5.5 V; R = 2 kΩ; C = 200 pF; DD SS CC LOAD LOAD all specifications T to T , unless otherwise noted. MIN MAX Table 3. Parameter1, 2, 3 Limit at t , t Unit Description MIN MAX t 33 ns min SCLK cycle time 1 t 13 ns min SCLK high time 2 t 13 ns min SCLK low time 3 t4 13 ns min SYNC falling edge to SCLK falling edge setup time t5 13 ns min SCLK falling edge to SYNC rising edge t6 100 ns min Minimum SYNC high time (write mode) t 7 ns min Data setup time 7 t 2 ns min Data hold time 8 t9 20 ns min LDAC falling edge to SYNC falling edge t10 130 ns min SYNC rising edge to LDAC falling edge t11 20 ns min LDAC pulse width low t 10 µs typ DAC output settling time 12 t13 20 ns min CLR pulse width low t14 2.5 µs max CLR pulse activation time t154 13 ns min SYNC rising edge to SCLK rising edge t 4 40 ns max SCLK rising edge to SDO valid (C 5 = 15 pF) 16 L SDO t17 200 ns min Minimum SYNC high time (readback/daisy-chain mode) 1 Guaranteed by characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 Daisy-chain and readback mode. 5 CL SDO = capacitive load on SDO output. Rev. F | Page 5 of 31

AD5724/AD5734/AD5754 Data Sheet TIMING DIAGRAMS t1 SCLK 1 2 24 t6 t3 t2 t4 t5 SYNC t8 t7 SDIN DB23 DB0 t9 t10 t11 LDAC t12 VOUTx t12 VOUTx CLR t13 t14 VOUTx 06468-002 Figure 2. Serial Interface Timing Diagram t1 SCLK 24 48 t17 t3 t2 t5 t4 t15 SYNC t8 t7 SDIN D32B D0B D32B D0B INPUT WORD FOR DAC N INPUT WORD FOR DAC N – 1 t16 SDO DB23 DB0 UNDEFINED INPUT WORD FOR DAC N t10 t11 LDAC 06468-003 Figure 3. Daisy-Chain Timing Diagram Rev. F | Page 6 of 31

Data Sheet AD5724/AD5734/AD5754 SCLK 1 24 1 24 t17 SYNC SDIN DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ SDO DB23 DB0 DB23 DB0 UNDEFINED SELECCTLEOD CRKEEGDIS OTUETR DATA 06468-004 Figure 4. Readback Timing Diagram Rev. F | Page 7 of 31

AD5724/AD5734/AD5754 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents of up to A Stresses at or above those listed under Absolute Maximum 100 mA do not cause SCR latch-up. Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these Table 4. or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Operation beyond AV to GND −0.3 V to +17 V DD the maximum operating conditions for extended periods may AV to GND +0.3 V to −17 V SS affect product reliability. DV to GND −0.3 V to +7 V CC Digital Inputs to GND −0.3 V to DV + 0.3 V or 7 V CC ESD CAUTION (whichever is less) Digital Outputs to GND −0.3 V to DV + 0.3 V or 7 V CC (whichever is less) REFIN to GND −0.3 V to +5 V V A, V B, V C, V D to GND AV to AV OUT OUT OUT OUT SS DD DAC_GND to GND −0.3 V to +0.3 V SIG_GND to GND −0.3 V to +0.3 V Operating Temperature Range, T A Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature, T max 150°C J 24-Lead TSSOP Package θ Thermal Impedance 42°C/W JA θ Thermal Impedance 9°C/W JC Power Dissipation (T max − T )/ θ J A JA Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 3.5 kV Rev. F | Page 8 of 31

Data Sheet AD5724/AD5734/AD5754 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVSS 1 24 AVDD NC 2 23 VOUTC VOUTA 3 AADD55772344// 22 VOUTD VOUTB 4 AD5754 21 SIG_GND BIN/2sCOMP 5 20 SIG_GND TOP VIEW NC 6 (Not to Scale) 19 DAC_GND SYNC 7 18 DAC_GND SCLK 8 17 REFIN SDIN 9 16 SDO LDAC 10 15 GND CLR 11 14 DVCC NC 12 13 NC NOTES 1.NC = NO CONNECT. 2.ITFTHO IERSR ERMNEAHCLAOLNMYC MCEEODNN TDNHEEEDCR TTMEHADAL TT POTEH ARE F CEOOXRPPMPOAESNREC DPE LP.AANDE BE 06468-005 Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 AV Negative Analog Supply. Voltage ranges from −4.5 V to −16.5 V. This pin can connect to 0 V if output ranges SS are unipolar. 2, 6, 12, 13 NC No connect. Do not connect to these pins. 3 V A Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. OUT 4 V B Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. OUT 5 BIN/2sCOMP Determines the DAC coding for a bipolar output range. This pin must be hardwired to either DVCC or GND. When hardwired to DV , input coding is offset binary. When hardwired to GND, input coding is twos CC complement. (For unipolar output ranges, coding is always straight binary). 7 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC. 8 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 10 LDAC Load DAC, Logic Input. This is used to update the DAC registers and consequently, the analog outputs. When this pin is tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected. 11 CLR Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user-selectable). 14 DV Digital Supply. Voltage ranges from 2.7 V to 5.5 V. CC 15 GND Ground Reference. 16 SDO Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. 17 REFIN External Reference Voltage Input. Reference input range is 2 V to 3 V. REFIN = 2.5 V for specified performance. 18, 19 DAC_GND Ground Reference for the Four Digital-to-Analog Converters. 20, 21 SIG_GND Ground Reference for the Four Output Amplifiers. 22 V D Analog Output Voltage of DAC D. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. OUT 23 V C Analog Output Voltage of DAC C. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. OUT 24 AV Positive Analog Supply. Voltage ranges from 4.5 V to 16.5 V. DD Exposed AV This exposed paddle can be connected to the potential of the AV pin, or alternatively, it can be left electrically SS SS Paddle unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance. Rev. F | Page 9 of 31

AD5724/AD5734/AD5754 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 6 0.6 AVDD/AVSS = +12V/0V, RANGE = +10V AVDD/AVSS = ±12V, RANGE = ±10V 4 AVDD/AVSS = ±6.5V, RANGE = ±5V 0.4 AVDD/AVSS = +6.5V/0V, RANGE = +5V 2 0.2 B) B) S S R (L 0 R (L 0 O O R R ER –2 ER–0.2 NL NL I D –4 –0.4 –6 –0.6 AAVVDDDD//AAVVSSSS == +±1122VV,/ 0RVA, NRGAEN G=E ± 1=0 +V10V AVDD/AVSS = ±6.5V, RANGE = ±5V AVDD/AVSS = +6.5V/0V, RANGE = +5V –8 0 10,000 20,000 30,C00O0DE40,000 50,000 60,000 06468-013 –0.80 10,000 20,000 30,C00O0DE40000 50,000 60,000 06468-016 Figure 6. AD5754 INL Error vs. Code Figure 9. AD5754 DNL Error vs. Code 1.5 0.15 AVDD/AVSS = +12V/0V, RANGE = +10V AVDD/AVSS = ±12V, RANGE = ±10V 1.0 AAVVDDDD//AAVVSSSS == ±+66..55VV,/ 0RVA, NRGAEN G= E± 5=V +5V 0.10 0.5 0.05 B) B) S S R (L 0 R (L 0 O O R R ER–0.5 ER–0.05 L L N N I D –1.0 –0.10 –1.5 –0.15 AAVVDDDD//AAVVSSSS == +±1122VV,/ 0RVA, NRGAEN G=E ± 1=0 +V10V AVDD/AVSS = ±6.5V, RANGE = ±5V AVDD/AVSS = +6.5V/0V, RANGE = +5V –2.00 2000 4000 6000 C80O0D0E10,000 12,000 14,000 16,000 06468-014 –0.200 2000 4000 6000 C80O0D0E 10000 12000 14000 16000 06468-017 Figure 7. AD5734 INL Error vs. Code Figure 10. AD5734 DNL Error vs. Code 00..23 AAAAVVVVDDDDDDDD////AAAAVVVVSSSSSSSS ==== +±±+16162.2.55VVVV,/ ,0/ R0VRVA,A ,N RNRGAGAENEN G =G=E E±± 1 =5=0 V +V+150VV 00..0034 AAAAVVVVDDDDDDDD////AAAAVVVVSSSSSSSS ==== ±±++16612.2.55VVVV,/, 0/ R0VRVA,A ,N RNRGAGAENEN G =G=E E±± 1 =5=0 V +V+150VV 0.1 0.02 SB) 0 SB) 0.01 L L R ( R ( 0 O–0.1 O R R ER ER –0.01 NL –0.2 NL I D –0.02 –0.3 –0.03 –0.4 –0.04 –0.50 500 1000 1500 C20O0D0E 2500 3000 3500 4000 06468-015 –0.050 500 1000 1500 C20O0D0E 2500 3000 3500 4000 06468-018 Figure 8. AD5724 INL Error vs. Code Figure 11. AD5724 DNL Error vs. Code Rev. F | Page 10 of 31

Data Sheet AD5724/AD5734/AD5754 8 10 8 6 6 4 4 LSB) 2 MMMAAINXX I NIINNLLL ± ±±11500VVV LSB) 2 ROR ( 0 MMMIAINNX II NNINLLL ±+ +511V00VV ROR ( 0 BUBINIPPIOOPOLLAALARRR 55 VV5 VMM MIANIXN L ER –2 MMAINX I NINLL + +55VV L ER –2 UNIPOLAR 5V MAX N N I I –4 –4 –6 –6 –8 –8–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06468-044 –105.5 6.5 7.5 8.5 S9U.P5PL1Y0 .V5OL11T.A5GE12 (.V5)13.5 14.5 15.5 16.5 06468-035 Figure 12. AD5754 INL Error vs. Temperature Figure 15. AD5754 INL Error vs. Supply Voltage 0.1 1.0 BIPOLAR 10V MIN 0.8 UNIPOLAR 10V MIN 0 BIPOLAR 10V MAX UNIPOLAR 10V MAX 0.6 –0.1 MAX DNL ±10V 0.4 B) MAX DNL ±5V B) S MIN DNL ±10V S R (L–0.2 MMIANX D DNNLL ± +51V0V R (L 0.2 RO MIN DNL +10V RO 0 R MAX DNL +5V R L E–0.3 MIN DNL +5V L E–0.2 N N D D –0.4 –0.4 –0.6 –0.5 –0.8 –0.6–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06468-045 –1.011.5 12.0 12.5 13.0SUP13P.L5Y V14O.L0TA1G4E.5 (V1)5.0 15.5 16.0 16.5 06468-032 Figure 13. AD5754 DNL Error vs. Temperature Figure 16. AD5754 DNL Error vs. Supply Voltage 10 1.0 BIPOLAR 5V MIN 8 0.8 UBNIPIOPOLALARR 5 V5 VM MAIXN UNIPOLAR 5V MAX 6 0.6 4 0.4 INL ERROR (LSB) ––4202 BUBUININPPIIOOPPOOLLAALLRARA R R11 0011VV00 VVMM MMIANIAXNX DNL ERROR (LSB)––000...4220 –6 –0.6 –8 –0.8 –1011.5 12.0 12.5 13.0 13.S5UP1P4L.0Y (V1)4.5 15.0 15.5 16.0 16.5 06468-034 –1.05.5 6.5 7.5 8.5 S9U.P5PL1Y0 .V5OL11T.A5GE12 (.V5)13.5 14.5 15.5 16.5 06468-033 Figure 14. AD5754 INL Error vs. Supply Voltage Figure 17. AD5754 DNL Error vs. Supply Voltage Rev. F | Page 11 of 31

AD5724/AD5734/AD5754 Data Sheet 0.02 10 0.01 9 0 BIPOLAR 10V MIN 8 UNIPOLAR 10V MIN BIPOLAR 10V MAX %) UNIPOLAR 10V MAX A) UE ( –0.01 (mD 7 T D AI –0.02 6 –0.03 5 –0.04 11.5 12F.0igu1r2e. 518.1 A3.D0S5U7P153P4.L5 TYU V1E4O .vL0sT.A S1Gu4E.p5 p(Vly1)5 V.0olta15g.5e 16.0 16.5 06468-036 44.5 6.5 8.5 AV1D0D.5 (V) 12.5 14.5 16.5 06468-042 Figure 21. Supply Current vs. Supply Voltage (Single Supply) 0.04 4 0.03 +10V 3 0.02 V) 0.01 BIPOLAR 5V MIN m 2 UNIPOLAR 5V MIN R ( E (%) 0 BUINPIOPOLALARR 5 V5 VM MAAXX ERRO 1 ±10V TU –0.01 LE A 0 C –0.02 S O- –0.03 ER –1 Z –0.04 –2 ±5V –0.05 5.5 6.5Figu7r.5e 198.. 5ADS59U7.P55P4L1 YT0U .V5EO vL11sT..A 5SGu1Ep2 p(.V5ly) 1V3o.5lta1g4e.5 15.5 16.5 06468-037 –3–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06468-046 Figure 22. Zero-Scale Error vs. Temperature 8 0.8 6 0.6 IDD (mA) 4 V) 0.4 m mA) 2 ROR ( 0.2 ±5V RANGE AI/AI (DDSS –20 R ZERO ER–0.20 ±10V RANGE ISS (mA) OLA–0.4 –4 P BI–0.6 –6 –0.8 –84.5 6.5 8.5 AVDD1/A0V.5SS (V) 12.5 14.5 16.5 06468-038 –1.0–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06468-047 Figure 20. Supply Current vs. Supply Voltage (Dual Supply) Figure 23. Bipolar Zero Error vs. Temperature Rev. F | Page 12 of 31

Data Sheet AD5724/AD5734/AD5754 0.06 15 ±5V 0.04 10 % FSR)0.02 AGE (V) 5 R ( LT O 0 O 0 R ±10V V ER UT N P AI–0.02 UT –5 G O +10V –0.04 –10 –0.06 –15 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06468-048 –3 –1 1 3 TIME (5µs) 7 9 11 06468-022 Figure 24. Gain Error vs. Temperature Figure 27. Full-Scale Settling Time, ±10 V Range 1000 7 900 5 800 700 V) 3 E ( 600 G (µA)C500 VOLTA 1 DIC400 DVCC = 5V PUT –1 300 UT O –3 200 100 –5 DVCC = 3V 0 –7 –1000 1 2 VLOG3IC (V) 4 5 6 06468-043 –3 Figu–r1e 28. Fu1ll-Scale3 STeItMtlEin (5gµs T)ime, 7±5 V Ra9nge 11 06468-023 Figure 25. Digital Current vs. Logic Input Voltage 12 0.010 ±5V RANGE, CODE = 0xFFFF ±10V RANGE, CODE = 0xFFFF +10V RANGE, CODE = 0xFFFF 10 0.005 +5V RANGE, CODE = 0xFFFF LTA (V) 0 ±±51V0V R RAANNGGEE, ,C COODDEE = = 0 x00x0000000 GE (V) 8 E A D T TAGE –0.005 T VOL 6 L U O P UT V –0.010 OUT 4 P T U O 2 –0.015 0 –0.020–25 –20 –15 –1O0UTP–U5T CU0RRENT5 (mA1)0 15 20 25 06468-040 –3 Figu–1re 29. F1ull-Scale3 STeItMtElin (5µgs T)ime,7 10 V Ra9nge 11 06468-024 Figure 26. Output Source and Sink Capability Rev. F | Page 13 of 31

AD5724/AD5734/AD5754 Data Sheet 6 5 V) E ( 4 G A T L O 3 1 V T U P UT 2 O 1 RANGE = ±5V RANGE = +10V 0–3 –1 1 3 TIME (5µs) 7 9 11 06468-025 CH1 R5AµVNGE = +5V RANGEM =5 s±10V LINE 73.8V 06468-027 Figure 30. Full-Scale Settling Time, +5 V Range Figure 33. Peak-to-Peak Noise, 100 kHz Bandwidth 0.020 0.10 ±10V RANGE, 0x7FF±F TO 0x8000 AVDD/AVSS = ±16.5V ±10V RANGE, 0x8000 TO 0x7FFF AVDD = +16.5V, AVSS = 0V 0.015 ±±55VV RRAANNGGEE,, 00xx78F00F0F ± TTOO 00xx78F0F0F0 0.08 +10V RANGE, 0x7FFF TO 0x8000 +10V RANGE, 0x8000 TO 0x7FFF 0.06 V) 0.010 +5V RANGE, 0x7FFF TO 0x8000 V) GE ( +5V RANGE, 0x8000 TO 0x7FFF GE ( 0.04 TA 0.005 TA L L O O 0.02 V V T 0 T U U P P 0 T T U U O–0.005 O –0.02 –0.010 –0.04 –0.015 –0.06 –1 0 1 TIME2 (µs) 3 4 5 06468-039 –50 –30 –10 10TIME 3(µ0s) 50 70 90 06468-041 Figure 31. Digital-to-Analog Glitch Energy Figure 34. Output Glitch on Power-Up 15 AVDD/AVSS = +12V/0V, RANGE = +10V 10 AAVVDDDD//AAVVSSSS == ±±162.5VV, ,R RAANNGGEE = = ± ±150VV AVDD/AVSS = +6.5V/0V, RANGE = +5V 5 0 B) –5 S 1 E (L –10 U T –15 –20 –25 RANGE = ±5V RANGE = +10V –30 CH1 5RµAVNGE = +5V RANGME =5 s±10V LINE 73.8V 06468-026 –350 1000 2000 30C00ODE 4000 5000 6000 06468-019 Figure 32. Peak-to-Peak Noise, 0.1 Hz to 10 Hz Bandwidth Figure 35. AD5754 TUE vs. Code Rev. F | Page 14 of 31

Data Sheet AD5724/AD5734/AD5754 4 1.0 AVDD/AVSS = +12V/0V, RANGE = +10V AVDD/AVSS = +12V/0V, RANGE = +10V AVDD/AVSS = ±12V, RANGE = ±10V AVDD/AVSS = ±12V, RANGE = ±10V 2 AAVVDDDD//AAVVSSSS == ±+66..55VV,/ 0RVA, NRGAEN G= E± 5=V +5V 0.5 AAVVDDDD//AAVVSSSS == ±+66..55VV,/ 0RVA, NRGAEN G= E± 5=V +5V 0 0 B) –2 B)–0.5 S S L L E ( E ( TU –4 TU–1.0 –6 –1.5 –8 –2.0 –100 2000 4000 6000 C80O0D0E10,000 12,000 14,000 16,000 06468-020 –2.50 500 1000 1500 C20O0D0E 2500 3000 3500 4000 06468-021 Figure 36. AD5734 TUE vs. Code Figure 37. AD5724 TUE vs. Code Rev. F | Page 15 of 31

AD5724/AD5734/AD5754 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Slew Rate For the DAC, relative accuracy, or integral nonlinearity, is a The slew rate of a device is a limitation in the rate of change of measure of the maximum deviation in LSBs from a straight line the output voltage. The output slewing speed of a voltage output passing through the endpoints of the DAC transfer function. A DAC is usually limited by the slew rate of the amplifier used at typical INL vs. code plot can be seen in Figure 6. the output. Slew rate is measured from 10% to 90% of the output signal and is given in V/µs. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured Gain Error change and the ideal 1 LSB change between any two adjacent Gain error is a measure of the span error of the DAC. It is the codes. A specified differential nonlinearity of ±1 LSB maximum deviation in slope of the DAC transfer characteristic from ensures monotonicity. This DAC is guaranteed monotonic by the ideal and is expressed in % FSR. A plot of gain error vs. design. A typical DNL vs. code plot can be seen in Figure 9. temperature can be seen in Figure 24. Monotonicity Gain TC A DAC is monotonic if the output either increases or remains Gain TC is a measure of the change in gain error with changes constant for increasing digital input code. The AD5724/AD5734/ in temperature. Gain TC is expressed in ppm FSR/°C. AD5754 are monotonic over the full operating temperature Total Unadjusted Error (TUE) range of the devices. Total unadjusted error is a measure of the output error taking Bipolar Zero Error all the various errors into account, namely INL error, offset Bipolar zero error is the deviation of the analog output from the error, gain error, and output drift over supplies, temperature, ideal half-scale output of 0 V when the DAC register is loaded and time. TUE is expressed in % FSR. with 0x8000 (straight binary coding) or 0x0000 (twos complement Digital-to-Analog Glitch Impulse coding). A plot of bipolar zero error vs. temperature can be seen Digital-to-analog glitch impulse is the impulse injected into the in Figure 23. analog output when the input code in the DAC register changes Bipolar Zero Temperature Coefficient (TC) state, but the output voltage remains constant. It is normally Bipolar zero TC is a measure of the change in the bipolar zero specified as the area of the glitch in nV-sec and is measured error with a change in temperature. It is expressed in ppm FSR/°C. when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 31. Zero-Scale Error or Negative Full-Scale Error Zero-scale error is the error in the DAC output voltage when Glitch Impulse Peak Amplitude 0x0000 (straight binary coding) or 0x8000 (twos complement Glitch impulse peak amplitude is the peak amplitude of the coding) is loaded to the DAC register. Ideally, the output voltage impulse injected into the analog output when the input code in must be negative full-scale −1 LSB. A plot of zero-scale error vs. the DAC register changes state. It is specified as the amplitude temperature can be seen in Figure 22. of the glitch in mV and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to Zero-Scale TC 0x8000). See Figure 31. Zero-scale TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale TC is expressed in ppm FSR/°C. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into Output Voltage Settling Time the analog output of the DAC from the digital inputs of the Output voltage settling time is the amount of time required for DAC, but is measured when the DAC output is not updated. the output to settle to a specified level for a full-scale input change. It is specified in nV-sec and measured with a full-scale code A plot for full-scale settling time can be seen in Figure 27. change on the data bus. Power Supply Sensitivity Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage. It is measured by superimposing a 50 Hz/60 Hz, 200 mV p-p sine wave on the supply voltages and measuring the proportion of the sine wave that transfers to the outputs. Rev. F | Page 16 of 31

Data Sheet AD5724/AD5734/AD5754 DC Crosstalk DAC-to-DAC Crosstalk This is the dc change in the output level of one DAC in response DAC-to-DAC crosstalk is the glitch impulse transferred to the to a change in the output of another DAC. It is measured with a output of one DAC due to a digital code change and a subsequent full-scale output change on one DAC while monitoring another output change of another DAC. This includes both digital and DAC. It is expressed in LSBs. analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with Digital Crosstalk LDAC low and monitoring the output of another DAC. The Digital crosstalk is a measure of the impulse injected into the energy of the glitch is expressed in nV-sec. analog output of one DAC from the digital inputs of another DAC, but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. Rev. F | Page 17 of 31

AD5724/AD5734/AD5754 Data Sheet THEORY OF OPERATION The AD5724/AD5734/AD5754 are quad, 12-/14-/16-bit, serial The resistor string structure is shown in Figure 39. It is a string input, unipolar/bipolar, voltage output DACs. They operate from of resistors, each of value R. The code loaded to the DAC unipolar supply voltages of +4.5 V to +16.5 V or bipolar supply register determines the node on the string where the voltage is voltages of ±4.5 V to ±16.5 V. In addition, the devices have to be tapped off and fed into the output amplifier. The voltage is software-selectable output ranges of +5 V, +10 V, +10.8 V, ±5 V, tapped off by closing one of the switches connecting the string ±10 V, and ±10.8 V. Data is written to the AD5724/AD5734/ to the amplifier. Because it is a string of resistors, it is AD5754 in a 24-bit word format via a 3-wire serial interface. guaranteed monotonic. The devices also offer an SDO pin to facilitate daisy-chaining Output Amplifiers or readback. The output amplifiers are capable of generating both unipolar The AD5724/AD5734/AD5754 incorporate a power-on reset and bipolar output voltages. They are capable of driving a load circuit to ensure that the DAC registers power up loaded with of 2 kΩ in parallel with 4000 pF to GND. The source and sink 0x0000. When powered on, the outputs are clamped to 0 V via capabilities of the output amplifiers can be seen in Figure 26. a low impedance path. The slew rate is 3.5 V/µs with a full-scale settling time of 10 µs. ARCHITECTURE Reference Buffers The DAC architecture consists of a string DAC followed by an The AD5724/AD5734/AD5754 require an external reference output amplifier. Figure 38 shows a block diagram of the DAC source. The reference input has an input range of 2 V to 3 V, architecture. The reference input is buffered before being with 2.5 V for specified performance. This input voltage is then applied to the DAC. buffered before it is applied to the DAC cores. REFIN POWER-UP SEQUENCE Because the DAC output voltage is controlled by the voltage REF (+) monitor and control block (see Figure 42), it is important to DAC REGISTER RSETSRISINTOGR VOUTx power the DVCC pin before applying any voltage to the AVDD REF (–) CONFIGURABLE and AVSS pins; otherwise, the G1 and G2 transmission gates are at OUTPUT AMPLIFIER an undefined state. The ideal power-up sequence is in the RANGEG NCDOONUTTRPOULT 06468-006 AfoVlloSSw, ainngd othrdener t:h Ge NdDig,i tSaIlG in_pGuNtsD. T, DheA rCel_aGtivNeD o,r DdeVr CoCf, pAoVwDeDr, ing AV and AV is not important, provided that they are powered DD SS Figure 38. DAC Architecture Block Diagram up after DV . CC REFIN SERIAL INTERFACE R The AD5724/AD5734/AD5754 are controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz. It is compatible with SPI, QSPI™, MICROWIRE™, and DSP R standards. Input Shift Register R TO OUTPUT AMPLIFIER The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. The input register consists of a read/write bit, three register select bits, three DAC address bits, and 16 data bits. The timing diagram for this operation is shown in Figure 2. R R 06468-007 Figure 39. Resistor String Structure Rev. F | Page 18 of 31

Data Sheet AD5724/AD5734/AD5754 Standalone Operation Daisy-Chain Operation The serial interface works with both a continuous and noncon- For systems that contain several devices, the SDO pin can be tinuous serial clock. A continuous SCLK source can be used used to daisy-chain several devices together. Daisy-chain mode only if SYNC is held low for the correct number of clock cycles. can be useful in system diagnostics and in reducing the number In gated clock mode, a burst clock containing the exact number of serial interface lines. The first falling edge of SYNC starts the of clock cycles must be used and SYNC must be taken high after write cycle. SCLK is continuously applied to the input shift the final clock to latch the data. The first falling edge of SYNC register when SYNC is low. If more than 24 clock pulses are starts the write cycle. Exactly 24 falling clock edges must be applied, the data ripples out of the shift register and appears on applied to SCLK before SYNC is brought high again. If SYNC is the SDO line. This data is clocked out on the rising edge of brought high before the 24th falling SCLK edge, the data written SCLK and is valid on the falling edge. By connecting the SDO is invalid. If more than 24 falling SCLK edges are applied before of the first device to the SDIN input of the next device in the SYNC is brought high, the input data is also invalid. The input chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of register addressed is updated on the rising edge of SYNC. For clock cycles must equal 24 × N, where N is the total number of another serial transfer to take place, SYNC must be brought low AD5724/AD5734/AD5754 devices in the chain. When the serial again. After the end of the serial data transfer, data is transfer to all devices is complete, SYNC is taken high. This automatically transferred from the input shift register to the latches the input data in each device in the daisy chain and addressed register. prevents any further data from being clocked into the input shift When the data has been transferred into the chosen register of register. The serial clock can be a continuous or a gated clock. the addressed DAC, all DAC registers and outputs can be A continuous SCLK source can only be used if SYNC is held updated by taking LDAC low while SYNC is high. low for the correct number of clock cycles. In gated clock mode, AD5724/ a burst clock containing the exact number of clock cycles must 68HC11* AD5734/ AD5754* be used, and SYNC must be taken high after the final clock to MOSI SDIN latch the data. SCK SCLK Readback Operation PC7 SYNC Readback mode is invoked by setting the R/W bit = 1 in the PC6 LDAC MISO SDO serial input shift register write. (If the SDO output is disabled via the SDO disable bit in the control register, it is automatically enabled for the duration of the read operation, after which it is SDIN AD5724/ disabled again). With R/W = 1, Bit A2 to Bit A0 in association AD5734/ with Bit REG2 to Bit REG0, select the register to be read. The AD5754* remaining data bits in the write sequence are don’t care bits. SCLK During the next SPI write, the data appearing on the SDO output SYNC contains the data from the previously addressed register. For a LDAC read of a single register, the NOP command can clock out the SDO data from the selected register on SDO. The readback diagram in Figure 4 shows the readback sequence. For example, to read back the DAC register of Channel A, the following sequence SDIN AD5724/ must be implemented: AD5734/ AD5754* 1. Write 0x800000 to the AD5724/AD5734/AD5754 input SCLK register. This configures the device for read mode with the SYNC DAC register of Channel A selected. Note that all the data LDAC bits, DB15 to DB0, are don’t care bits. SDO 2. Follow this with a second write, a NOP condition, 0x180000. *ADDITIONAL PINS OMITTED FOR CLARITY. 06468-008 Donu rthineg S tDhOis wlinriet.e , the data from the register is clocked out Figure 40. Daisy Chaining the AD5724/AD5734/AD5754 Rev. F | Page 19 of 31

AD5724/AD5734/AD5754 Data Sheet LOAD DAC (LDAC) The DV must be brought high before any of the interface lines CC are powered. If this is not done, the first write to the device may After data has been transferred into the input register of the be ignored. The first communication to the AD5724/AD5734/ DACs, there are two ways to update the DAC registers and DAC AD5754 must be to set the required output range on all channels outputs. Depending on the status of both SYNC and LDAC, one (the default range is the 5 V unipolar range) by writing to the of two update modes is selected: individual DAC updating or output range select register. The user must then write to the simultaneous updating of all DACs. power control register to power on the required channels. To OUTPUT AMPLIFIER program an output value on a channel, that channel must first REFIN 12-/1D4-A/1C6-BIT VOUT be powered up; any writes to a channel while it is in power-down mode are ignored. The AD5724/AD5734/AD5754 operate with a wide power supply range. It is important that the power supply DAC applied to the devices provides adequate headroom to support LDAC REGISTER the chosen output ranges. TRANSFER FUNCTION INPUT REGISTER Table 7 to Table 15 show the relationships of the ideal input code to output voltage for the AD5754, AD5734, and AD5724, respec- SSSYCDNLICNK INTLEORGFIACCE SDO 06468-009 ttihvee ldya, tfao rc oaldl ionugt pisu stt vraoilgtahgt eb rinanargye.s F. oFro rb iupnoilpaor loaur topuuttp ruatn rgaensg, eths,e Figure 41. Simplified Diagram of Input Loading Circuitry for One DAC data coding is user-selectable via the BIN/2sCOMP pin and can be either offset binary or twos complement. Individual DAC Updating For a unipolar output range, the output voltage expression is In this mode, LDAC is held low while data is being clocked into given by the input shift register. The addressed DAC output is updated on the rising edge of SYNC.  D  Simultaneous Updating of All DACs VOUT =VREFIN×Gain2N  In this mode, LDAC is held high while data is being clocked For a bipolar output range, the output voltage expression is given by into the input shift register. All DAC outputs are asynchronously  D  Gain×V updated by taking LDAC low after SYNC has been taken high. VOUT =VREFIN×Gain2N− 2 REFIN The update now occurs on the falling edge of LDAC. where: ASYNCHRONOUS CLEAR (CLR) D is the decimal equivalent of the code loaded to the DAC. CLR is an active low clear that allows the outputs to clear to N is the bit resolution of the DAC. V is the reference voltage applied at the REFIN pin. either zero-scale code or midscale code. The clear code value is REFIN Gain is an internal gain with a value that depends on the output user-selectable via the CLR select bit of the control register (see range selected by the user, as shown in Table 6. the Control Register section). It is necessary to maintain CLR low for a minimum amount of time to complete the operation (see Table 6. Internal Gain Values Figure 2). When the CLR signal is returned high, the output Output Range (V) Gain Value remains at the cleared value until a new value is programmed. +5 2 The outputs cannot update with a new value while the CLR pin +10 4 is low. A clear operation can also be performed via the clear +10.8 4.32 command in the control register. ±5 4 CONFIGURING THE AD5724/AD5734/AD5754 ±10 8 ±10.8 8.64 When the power supplies are applied to the AD5724/AD5734/ AD5754, the power-on reset circuit ensures that all registers default to 0. This places all channels in power-down mode. Rev. F | Page 20 of 31

Data Sheet AD5724/AD5734/AD5754 Ideal Output Voltage to Input Code Relationship—AD5754 Table 7. Bipolar Output, Offset Binary Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 1111 1111 1111 1111 +2 × REFIN × (32,767/32,768) +4 × REFIN × (32,767/32,768) +4.32 × REFIN × (32,767/32,768) 1111 1111 1111 1110 +2 × REFIN × (32,766/32,768) +4 × REFIN × (32,766/32,768) +4.32 × REFIN × (32,766/32,768) … … … … … … … 1000 0000 0000 0001 +2 × REFIN × (1/32,768) +4 × REFIN × (1/32,768) +4.32 × REFIN × (1/32,768) 1000 0000 0000 0000 0 V 0 V 0 V 0111 1111 1111 1111 −2 × REFIN × (1/32,768) −4 × REFIN × (1/32,768) −4.32 × REFIN × (32,766/32,768) … … … … … … … 0000 0000 0000 0001 −2 × REFIN × (32,767/32,768) −4 × REFIN × (32,767/32,768) −4.32 × REFIN × (32,767/32,768) 0000 0000 0000 0000 −2 × REFIN × (32,768/32,768) −4 × REFIN × (32,768/32,768) −4.32 × REFIN × (32,768/32,768) Table 8. Bipolar Output, Twos Complement Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 0111 1111 1111 1111 +2 × REFIN × (32,767/32,768) +4 × REFIN × (32,767/32,768) +4.32 × REFIN × (32,767/32,768) 0111 1111 1111 1110 +2 × REFIN × (32,766/32,768) +4 × REFIN × (32,766/32,768) +4.32 × REFIN × (32,766/32,768) … … … … … … … 0000 0000 0000 0001 +2 × REFIN × (1/32,768) +4 × REFIN × (1/32,768) +4.32 × REFIN × (1/32,768) 0000 0000 0000 0000 0 V 0 V 0 V 1111 1111 1111 1111 −2 × REFIN × (1/32,768) −4 × REFIN × (1/32,768) −4.32 × REFIN × (1/32,768) … … … … … … … 1000 0000 0000 0001 −2 × REFIN × (32,767/32,768) −4 × REFIN × (32,767/32,768) −4.32 × REFIN × (32,767/32,768) 1000 0000 0000 0000 −2 × REFIN × (32,768/32,768) −4 × REFIN × (32,768/32,768) −4.32 × REFIN × (32,768/32,768) Table 9. Unipolar Output, Straight Binary Coding Digital Input Analog Output MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range 1111 1111 1111 1111 +2 × REFIN × (65,535/65,536) +4 × REFIN × (65,535/65,536) +4.32 × REFIN × (65,535/65,536) 1111 1111 1111 1110 +2 × REFIN × (65,534/65,536) +4 × REFIN × (65,534/65,536) +4.32 × REFIN × (65,534/65,536) … … … … … … … 1000 0000 0000 0001 +2 × REFIN × (32,769/65,536) +4 × REFIN × (32,769/65,536) +4.32 × REFIN × (32,769/65,536) 1000 0000 0000 0000 +2 × REFIN × (32,768/65,536) +4 × REFIN × (32,768/65,536) +4.32 × REFIN × (32,768/65,536) 0111 1111 1111 1111 +2 × REFIN × (32,767/65,536) +4 × REFIN × (32,767/65,536) +4.32 × REFIN × (32,767/65,536) … … … … … … … 0000 0000 0000 0001 +2 × REFIN × (1/65,536) +4 × REFIN × (1/65,536) +4.32 × REFIN × (1/65,536) 0000 0000 0000 0000 0 V 0 V 0 V Rev. F | Page 21 of 31

AD5724/AD5734/AD5754 Data Sheet Ideal Output Voltage to Input Code Relationship—AD5734 Table 10. Bipolar Output, Offset Binary Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 11 1111 1111 1111 +2 × REFIN × (8191/8192) +4 × REFIN × (8191/8192) +4.32 × REFIN × (8191/8192) 11 1111 1111 1110 +2 × REFIN × (8190/8192) +4 × REFIN × (8190/8192) +4.32 × REFIN × (8190/8192) … … … … … … … 10 0000 0000 0001 +2 × REFIN × (1/8192) +4 × REFIN × (1/8192) +4.32 × REFIN × (1/8192) 10 0000 0000 0000 0 V 0 V 0 V 01 1111 1111 1111 −2 × REFIN × (1/8192) −4 × REFIN × (1/8192) −4.32 × REFIN × (1/8192) … … … … … … … 00 0000 0000 0001 −2 × REFIN × (8191/8192) −4 × REFIN × (8191/8192) −4.32 × REFIN × (8191/8192) 00 0000 0000 0000 −2 × REFIN × (8192/8192) −4 × REFIN × (8192/8192) −4.32 × REFIN × (8192/8192) Table 11. Bipolar Output, Twos Complement Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 01 1111 1111 1111 +2 × REFIN × (8191/8192) +4 × REFIN × (8191/8192) +4.32 × REFIN × (8191/8192) 01 1111 1111 1110 +2 × REFIN × (8190/8192) +4 × REFIN × (8190/8192) +4.32 × REFIN × (8190/8192) … … … … … … … 00 0000 0000 0001 +2 × REFIN × (1/8192) +4 × REFIN × (1/8192) +4.32 × REFIN × (1/8192) 00 0000 0000 0000 0 V 0 V 0 V 11 1111 1111 1111 −2 × REFIN × (1/8192) −4 × REFIN × (1/8192) −4.32 × REFIN × (1/8192) … … … … … … … 10 0000 0000 0001 −2 × REFIN × (8191/8192) −4 × REFIN × (8191/8192) −4.32 × REFIN × (8191/8192) 10 0000 0000 0000 −2 × REFIN × (8192/8192) −4 × REFIN × (8192/8192) −4.32 × REFIN × (8192/8192) Table 12. Unipolar Output, Straight Binary Coding Digital Input Analog Output MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range 11 1111 1111 1111 +2 × REFIN × (16,383/16,384) +4 × REFIN × (16,383/16,384) +4.32 × REFIN × (16,383/16,384) 11 1111 1111 1110 +2 × REFIN × (16,382/16,384) +4 × REFIN × (16,382/16,384) +4.32 × REFIN × (16,382/16,384) … … … … … … … 10 0000 0000 0001 +2 × REFIN × (8193/16,384) +4 × REFIN × (8193/16,384) +4.32 × REFIN × (8193/16,384) 10 0000 0000 0000 +2 × REFIN × (8192/16,384) +4 × REFIN × (8192/16,384) +4.32 × REFIN × (8192/16,384) 01 1111 1111 1111 +2 × REFIN × (8191/16,384) +4 × REFIN × (8191/16,384) +4.32 × REFIN × (8191/16,384) … … … … … … … 00 0000 0000 0001 +2 × REFIN × (1/16,384) +4 × REFIN × (1/16,384) +4.32 × REFIN × (1/16,384) 00 0000 0000 0000 0 V 0 V 0 V Rev. F | Page 22 of 31

Data Sheet AD5724/AD5734/AD5754 Ideal Output Voltage to Input Code Relationship—AD5724 Table 13. Bipolar Output, Offset Binary Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 1111 1111 1111 +2 × REFIN × (2047/2048) +4 × REFIN × (2047/2048) +4.32 × REFIN × (2047/2048) 1111 1111 1110 +2 × REFIN × (2046/2048) +4 × REFIN × (2046/2048) +4.32 × REFIN × (2046/2048) … … … … … … 1000 0000 0001 +2 × REFIN × (1/2048) +4 × REFIN × (1/2048) +4.32 × REFIN × (1/2048) 1000 0000 0000 0 V 0 V 0 V 0111 1111 1111 −2 × REFIN × (1/2048) −4 × REFIN × (1/2048) −4.32 × REFIN × (1/2048) … … … … … … 0000 0000 0001 −2 × REFIN × (2047/2048) −4 × REFIN × (2047/2048) −4.32 × REFIN × (2047/2048) 0000 0000 0000 −2 × REFIN × (2048/2048) −4 × REFIN × (2048/2048) −4.32 × REFIN × (2048/2048) Table 14. Bipolar Output, Twos Complement Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 0111 1111 1111 +2 × REFIN × (2047/2048) +4 × REFIN × (2047/2048) +4.32 × REFIN × (2047/2048) 0111 1111 1110 +2 × REFIN × (2046/2048) +4 × REFIN × (2046/2048) +4.32 × REFIN × (2046/2048) … … … … … … 0000 0000 0001 +2 × REFIN × (1/2048) +4 × REFIN × (1/2048) +4.32 × REFIN × (1/2048) 0000 0000 0000 0 V 0 V 0 V 1111 1111 1111 −2 × REFIN × (1/2048) −4 × REFIN × (1/2048) −4.32 × REFIN × (1/2048) … … … … … … 1000 0000 0001 −2 × REFIN × (2047/2048) −4 × REFIN × (2047/2048) −4.32 × REFIN × (2047/2048) 1000 0000 0000 −2 × REFIN × (2048/2048) −4 × REFIN × (2048/2048) −4.32 × REFIN × (2048/2048) Table 15. Unipolar Output, Straight Binary Coding Digital Input Analog Output MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range 1111 1111 1111 +2 × REFIN × (4095/4096) +4 × REFIN × (4095/4096) +4.32 × REFIN × (4095/4096) 1111 1111 1110 +2 × REFIN × (4094/4096) +4 × REFIN × (4094/4096) +4.32 × REFIN × (4094/4096) … … … … … … 1000 0000 0001 +2 × REFIN × (2049/4096) +4 × REFIN × (2049/4096) +4.32 × REFIN × (2049/4096) 1000 0000 0000 +2 × REFIN × (2048/4096) +4 × REFIN × (2048/4096) +4.32 × REFIN × (2048/4096) 0111 1111 1111 +2 × REFIN × (2047/4096) +4 × REFIN × (2047/4096) +4.32 × REFIN × (2047/4096) … … … … … … 0000 0000 0001 +2 × REFIN × (1/4096) +4 × REFIN × (1/4096) +4.32 × REFIN × (1/4096) 0000 0000 0000 0 V 0 V 0 V Rev. F | Page 23 of 31

AD5724/AD5734/AD5754 Data Sheet INPUT SHIFT REGISTER The input shift register is 24 bits wide and consists of a read/write bit (R/W), a reserved bit (zero) that must always be set to 0, three register select bits (REG0, REG1, REG2), three DAC address bits (A2, A1, A0), and 16 data bits (data). The register data is clocked in MSB first on the SDIN pin. Table 16 shows the register format and Table 17 describes the function of each bit in the register. All registers are read/write registers. Table 16. Input Register Format MSB LSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB0 R/W Zero REG2 REG1 REG0 A2 A1 A0 Data Table 17. Input Register Bit Functions Bit Mnemonic Description R/W Indicates a read from or a write to the addressed register. REG2, REG1, REG0 Used in association with the address bits to determine if a write operation is to the DAC register, the output range select register, the power control register, or the control register. REG2 REG1 REG0 Function 0 0 0 DAC register 0 0 1 Output range select register 0 1 0 Power control register 0 1 1 Control register A2, A1, A0 These DAC address bits are used to decode the DAC channels. A2 A1 A0 Channel Address 0 0 0 DAC A 0 0 1 DAC B 0 1 0 DAC C 0 1 1 DAC D 1 0 0 All four DACs DB15 to DB0 Data bits. DAC REGISTER The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel where the data transfer is to take place (see Table 17). The data bits are in positions DB15 to DB0 for the AD5754 (see Table 18), DB15 to DB2 for the AD5734 (see Table 19), and DB15 to DB4 for the AD5724 (see Table 20). Table 18. Programming the AD5754 DAC Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB0 0 0 0 0 0 DAC address 16-bit DAC data Table 19. Programming the AD5734 DAC Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB2 DB1 DB0 0 0 0 0 0 DAC address 14-bit DAC data X X Table 20. Programming the AD5724 DAC Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 DAC address 12-bit DAC data X X X X Rev. F | Page 24 of 31

Data Sheet AD5724/AD5734/AD5754 OUTPUT RANGE SELECT REGISTER The output range select register is addressed by setting the three REG bits to 001. The DAC address bits select the DAC channel and the range bits (R2, R1, R0) select the required output range (see Table 21 and Table 22). Table 21. Programming the Required Output Range MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB3 DB2 DB1 DB0 0 0 0 0 1 DAC address Don’t care R2 R1 R0 Table 22. Output Range Options R2 R1 R0 Output Range (V) 0 0 0 +5 0 0 1 +10 0 1 0 +10.8 0 1 1 ±5 1 0 0 ±10 1 0 1 ±10.8 CONTROL REGISTER The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the control function selected. The control register options are shown in Table 23 and Table 24. Table 23. Programming the Control Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 0 0 0 NOP, data = don’t care 0 0 0 1 1 0 0 1 Don’t care TSD enable Clamp enable CLR select SDO disable 0 0 0 1 1 1 0 0 Clear, data = don’t care 0 0 0 1 1 1 0 1 Load, data = don’t care Table 24. Explanation of Control Register Options Option Description NOP No operation instruction used in readback operations. Clear Addressing this function sets the DAC registers to the clear code and updates the outputs. Load Addressing this function updates the DAC registers and, consequently, the DAC outputs. SDO Disable Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). CLR Select See Table 25 for a description of the CLR select operation. Clamp Enable Set by the user to enable the current-limit clamp. The channel does not power down upon detection of an overcurrent; the current is clamped at 20 mA (default). Cleared by the user to disable the current-limit clamp. The channel powers down upon detection of an overcurrent. TSD Enable Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown feature (default). Table 25. CLR Select Options Output CLR Value CLR Select Setting Unipolar Output Range Bipolar Output Range 0 0 V 0 V 1 Midscale Negative full scale Rev. F | Page 25 of 31

AD5724/AD5734/AD5754 Data Sheet POWER CONTROL REGISTER The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power and thermal status of the AD5724/AD5734/AD5754. The power control register options are shown in Table 26 and Table 27. Table 26. Programming the Power Control Register MSB LSB DB15 to R/W Zero REG2 REG1 REG0 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 0 0 0 X OCD OCC OCB OCA 0 TSD 0 PUD PUC PUB PUA Table 27. Power Control Register Functions Option Description PU DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down A mode (default). After setting this bit to power DAC A, a power up time of 10 µs is required. During this power-up time, the DAC register must not be loaded to the DAC output (see the Load DAC/LDAC section). If the clamp enable bit of the control register is cleared, DAC A powers down automatically upon detection of an overcurrent, and PU is cleared to reflect this. A PU DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down B mode (default). After setting this bit to power DAC B, a power up time of 10 µs is required. During this power-up time, the DAC register must not be loaded to the DAC output (see the Load DAC/LDAC section). If the clamp enable bit of the control register is cleared, DAC B powers down automatically upon detection of an overcurrent, and PU is cleared to reflect this. B PU DAC C power-up. When set, this bit places DAC C in normal operating mode. When cleared, this bit places DAC C in power-down C mode (default). After setting this bit to power DAC C, a power up time of 10 µs is required. During this power-up time, the DAC register must not be loaded to the DAC output (see the Load DAC/LDAC section). If the clamp enable bit of the control register is cleared, DAC C powers down automatically upon detection of an overcurrent, and PU is cleared to reflect this. C PU DAC D power-up. When set, this bit places DAC D in normal operating mode. When cleared, this bit places DAC D in power-down D mode (default). After setting this bit to power DAC D, a power up time of 10 µs is required. During this power-up time, the DAC register must not be loaded to the DAC output (see the Load DAC/LDAC section). If the clamp enable bit of the control register is cleared, DAC D powers down automatically upon detection of an overcurrent, and PU is cleared to reflect this. D TSD Thermal shutdown alert. Read-only bit. In the event of an overtemperature situation, the four DACs are powered down and this bit is set. OC DAC A overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC A, this bit is set. A OC DAC B overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC B, this bit is set. B OC DAC C overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC C, this bit is set. C OC DAC D overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC D, this bit is set. D Rev. F | Page 26 of 31

Data Sheet AD5724/AD5734/AD5754 FEATURES ANALOG OUTPUT CONTROL OVERCURRENT PROTECTION In many industrial process control applications, it is vital to control Each DAC channel of the AD5724/AD5734/AD5754 incorporates the output voltage during power-up. When the supply voltages individual overcurrent protection. The user has two options for change during power-up, the V x pins are clamped to 0 V via the configuration of the overcurrent protection: constant current OUT a low impedance path (approximately 4 kΩ). To prevent the output clamp or automatic channel power-down. The configuration of amplifiers from being shorted to 0 V during this time, Trans- the overcurrent protection is selected via the clamp enable bit in mission Gate G1 is also opened (see Figure 42). These conditions the control register. are maintained until the analog power supplies have stabilized Constant Current Clamp (Clamp Enable = 1) and a valid word is written to a DAC register. At this time, G2 If a short circuit occurs in this configuration, the current is opens and G1 closes. clamped at 20 mA. This event is signaled to the user by the VOLTAGE setting of the appropriate overcurrent (OCX) bit in the power MONITOR AND control register. Upon removal of the short-circuit fault, the CONTROL OC bit is cleared. X G1 Automatic Channel Power-Down (Clamp Enable = 0) VOUTA G2 If a short circuit occurs in this configuration, the shorted 06468-010 crehsainstnaenlc pe oowf earpsp drooxwinm aantedly t h4e k oΩu.t pAut tt hisi sc ltaimmep,e tdh eto o gurtopuunt do fv tihae a Figure 42. Analog Output Control Circuitry amplifier is disconnected from the output pin. The short-circuit event is signaled to the user via the overcurrent (OC ) bits, and POWER-DOWN MODE X the power-up (PU ) bits indicate which DACs have powered X Each DAC channel of the AD5724/AD5734/AD5754 can be down. After the fault is rectified, the channels can be powered individually powered down. By default, all channels are in power- up again by setting the PU bits. X down mode. The power status is controlled by the power control THERMAL SHUTDOWN register (see Table 26 and Table 27 for details). When a channel is in power-down mode, the output pin is clamped to ground The AD5724/AD5734/AD5754 incorporate a thermal shutdown through a resistance of approximately 4 kΩ and the output of feature that automatically shuts down the device if the core temp- the amplifier is disconnected from the output pin. erature exceeds approximately 150°C. The thermal shutdown feature is disabled by default and can be enabled via the TSD enable bit of the control register. In the event of a thermal shutdown, the TSD bit of the power control register is set. Rev. F | Page 27 of 31

AD5724/AD5734/AD5754 Data Sheet APPLICATIONS INFORMATION +5 V/±5 V OPERATION Figure 44 shows an example of the analog supplies powering up before the digital supply. The circuit delays the AV power up When operating from a single +5 V supply or a dual ±5 V DD until after DV , as shown by the AV (delayed) line. supply, an output range of +5 V or ±5 V is not achievable because CC DD sufficient headroom for the output amplifier is not available. In this situation, a reduced reference voltage can be used. For example, a 2 V reference voltage produces an output range of +4 V or ±4 V, AVDD and the 1 V of headroom is more than enough for full operation. A standard value voltage reference of 2.048 V can be used to produce AVSS output ranges of +4.096 V and ±4.096 V. t(sec) ALTERNATIVE POWER-UP SEQUENCE SUPPORT There may be cases where it is not possible to use the DVCC recommended power-up sequence, and in those instances an external circuit shown in Figure 43 is recommended to be used. The circuit shown in Figure 43 ensures that the digital block is pswowitcehre cdi rucpu ifti.r Tsth, ipsr cioirrc tuoi tt htaer gaentasl oapg pblliocactki,o bnys ufosrin wgh ai cloha edi ther AVDD(DELAYED) 06468-144 Figure 44. Delayed Power Supplies Sequence Example AV or AV or both supplies power up before DV . DD SS CC LAYOUT GUIDELINES Consider the following design rules when choosing the component values for the AV delay circuit. In any circuit where accuracy is important, careful consideration of DD the power supply and ground return layout helps to ensure the  R1 ensures that the Q1 gate to source voltage is zero when rated performance. The printed circuit board on which the DV is in an open state. R1 also prevents false turn on of CC AD5724/AD5734/AD5754 are mounted must be designed so the Q1. However, if DV is permanently connected to the CC analog and digital sections are separated and confined to certain source, R1 can be removed to conserve power. areas of the board. If the AD5724/AD5734/AD5754 are in a system  Select Q1 (N-channel MOSFET) with a VGS threshold that where multiple devices require an AGND to DGND connection, is much lower than the minimum operating DV and a CC the connection must be made at one point only. The star ground V rating much lower than the maximum operating AV . DS DD point must be established as close as possible to the device.  C1, R2, and R3 are the main components that dictates the delay from DV enable to AV . Adjust the values The AD5724/AD5734/AD5754 must have ample supply bypassing CC DD according for the desired delay. Choose R2 and R3 values of a 10 μF capacitor in parallel with a 0.1 μF capacitor on each that ensure Q2 turn on. supply located as close to the package as possible, ideally right up against the device. The 10 μF capacitor is the tantalum bead type.  V  The 0.1 μF capacitor must have low effective series resistance (ESR) t (sec)C (R ||R )ln1 GS  DELAY 1 3 2  VEQ  and low effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground  R  at high frequencies to handle transient currents due to internal where V AV  3  EQ DDR R  logic switching.  3 2 The power supply lines of the AD5724/AD5734/AD5754 must  Q2 (P-channel MOSFET) acts as a switch that allows the flow use as large a trace as possible to provide low impedance paths of current from V to AV ; therefore, choosing a MOSFET IN DD and reduce the effects of glitches on the power supply line. Fast with very low R is necessary to minimize losses during DSON switching signals, such as a data clock, must be shielded with operation. Other parameters such as maximum V rating, DS digital ground to avoid radiating noise to other devices of the maximum drain to source current rating, V threshold GS board, and must never run near the reference inputs. A ground voltage, and maximum gate to source voltage rating must line routed between the SDIN and SCLK lines helps reduce also be taken into consideration when choosing Q2. crosstalk between them (this is not required on a multilayer VIN + Q2 AVDD board that has a separate ground plane, but separating the lines C1 R3 does help). It is essential to minimize noise on the REFIN line LOAD SWITCH R2 because any unwanted signals couple through to the DAC SECTION outputs. DVCC CSOENCTTRIOONL R1 Q1 06468-143 Asivdoeisd o cfr tohses obvoearr odf mdiugsitta rlu ann da ta rniaglhotg a sniggnleasl st.o T eraacches o otnh eorp. pTohsiist e Figure 43. Load Switch Control Circuit reduces the effects of feedthrough on the board. A microstrip Rev. F | Page 28 of 31

Data Sheet AD5724/AD5734/AD5754 technique is by far the best method, but it is not always possible  The temperature coefficient of a reference output voltage with a double-sided board. In this technique, the component affects INL, DNL, and TUE. A reference with a tight side of the board is dedicated to a ground plane and signal temperature coefficient specification must be chosen to traces are placed on the solder side. reduce the dependence of the DAC output voltage on GALVANICALLY ISOLATED INTERFACE ambient conditions.  Long-term drift is a measure of how much the reference In many process control applications, it is necessary to provide output voltage drifts over time. A reference with a tight an isolation barrier between the controller and the unit being long-term drift specification ensures that the overall controlled to protect and isolate the controlling circuitry from solution remains relatively stable over the entire lifetime. any hazardous common-mode voltages that may occur. The  Consider reference output voltage noise in high accuracy iCoupler® family of products from Analog Devices, Inc., provides applications that have relatively low noise budgets. It is voltage isolation in excess of 2.5 kV. The serial loading structure important to choose a reference with as low an output of the AD5724/AD5734/AD5754 makes them ideal for isolated noise voltage as practical for the required system resolution. interfaces because the number of interface lines is kept to a Precision voltage references such as the ADR431 (XFET® minimum. Figure 45 shows a 4-channel isolated interface to the design) produce low output noise in the 0.1 Hz to 10 Hz AD5724/AD5734/AD5754 using an ADuM1400. For further range. However, as the circuit bandwidth increases, information, visit http://www.analog.com/icouplers. filtering the output of the reference may be required to MICROCONTROLLER ADuM1400* minimize the output noise. SERIAL CLOCK OUT VIA ENCODE DECODE VOA TO SCLK MICROPROCESSOR INTERFACING SERIAL DATA OUT VIB ENCODE DECODE VOB TO SDIN Microprocessor interfacing to the AD5724/AD5734/AD5754 is SYNC OUT VIC ENCODE DECODE VOC TO SYNC via a serial bus that uses standard protocol compatible with micro- CONTROL OUT VID ENCODE DECODE VOD TO LDAC controllers and DSP processors. The communications channel *ADDITIONAL PINS OMITTED FOR CLARITY. 06468-011 idsa ata 3 s-iwgnirael, (amndin ai msyunmch)r oinntiezraftaiocne csiognnsails.t Tinhge oAf Da 5c7lo2c4k/ AsiDgn5a7l3, 4a/ Figure 45. Isolated Interface AD5754 require a 24-bit data-word with data valid on the VOLTAGE REFERENCE SELECTION falling edge of SCLK. To achieve optimum performance from the AD5724/AD5734/ For all interfaces, the DAC output update can be initiated AD5754 over the full operating temperature range of the devices, a automatically when all the data is clocked in, or it can be precision voltage reference must be used. Thought must be given to performed under the control of LDAC. The contents of the the selection of a precision voltage reference. The voltage applied to registers can be read using the readback function. the reference inputs are used to provide a buffered positive and AD5724/AD5734/AD5754 to Blackfin® DSP Interface negative reference for the DAC cores. Therefore, any error in Figure 46 shows how the AD5724/AD5734/AD5754 can be inter- the voltage reference is reflected in the outputs of the device. faced to the Analog Devices Blackfin DSP. The Blackfin has an There are four possible sources of error to consider when integrated SPI port that can be connected directly to the SPI pins of choosing a voltage reference for high accuracy applications: the AD5724/AD5734/AD5754 and the programmable I/O pins initial accuracy, temperature coefficient of the output voltage, that can be used to set the state of a digital input such as the long-term drift, and output voltage noise. LDAC pin.  Initial accuracy error on the output voltage of an external reference can lead to a full-scale error in the DAC. Therefore, SPISELx SYNC to minimize these errors, a reference with low initial accuracy SCK SCLK MOSI SDIN error specification is preferred. Choosing a reference with AD5724/ an output trim adjustment, such as the ADR421, allows a ADSP-BF531 AD5734/ system designer to trim out system errors by setting the AD5754 reference voltage to a voltage other than the nominal. The trim PF10 LDAC adjustment can also trim out temperature-induced errors. 06468-012 Figure 46. AD5724/AD5734/AD5754 to Blackfin Interface Rev. F | Page 29 of 31

AD5724/AD5734/AD5754 Data Sheet Table 28. Some Precision References Recommended for Use with the AD5724/AD5734/AD5754 Part No. Initial Accuracy (mV Max) Long-Term Drift (ppm Typ) Temp Drift (ppm/°C Max) 0.1 Hz to 10 Hz Noise (µV p-p Typ) ADR431 ±1 40 3 3.5 ADR421 ±1 50 3 1.75 ADR03 ±2.5 50 3 6 ADR291 ±2 50 8 8 AD780 ±1 20 3 4 Rev. F | Page 30 of 31

Data Sheet AD5724/AD5734/AD5754 OUTLINE DIMENSIONS 7.90 5.02 7.80 5.00 7.70 4.95 24 13 4.50 EXPOSED 3.25 4.40 PAD 3.20 4.30 (Pins Up) 3.15 6.40 BSC 1 12 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF 1.05 THE EXPOSED PAD, REFER TO 1.20 MAX 1.00 THE PIN CONFIGURATION AND 8° FUNCTION DESCRIPTIONS 0.80 0° SECTION OF THIS DATA SHEET. 0.15 0.20 0.05 SPLEAATNIENG B0.S6C5 00..3109 0.09 00..7650 0.10 COPLANARITY 0.45 COMPLIANTTO JEDEC STANDARDS MO-153-ADT 061708-A Figure 47. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] (RE-24) Dimensions shown in millimeters ORDERING GUIDE Model1 Resolution (Bits) Temperature Range TUE INL Package Description Package Option AD5724AREZ 12 −40°C to +85°C 0.3% FSR ±1 LSB 24-Lead TSSOP_EP RE-24 AD5724AREZ-REEL7 12 −40°C to +85°C 0.3% FSR ±1 LSB 24-Lead TSSOP_EP RE-24 AD5734AREZ 14 −40°C to +85°C 0.3% FSR ±4 LSB 24-Lead TSSOP_EP RE-24 AD5734AREZ-REEL7 14 −40°C to +85°C 0.3% FSR ±4 LSB 24-Lead TSSOP_EP RE-24 AD5754AREZ 16 −40°C to +85°C 0.3% FSR ±16 LSB 24-Lead TSSOP_EP RE-24 AD5754AREZ-REEL7 16 −40°C to +85°C 0.3% FSR ±16 LSB 24-Lead TSSOP_EP RE-24 AD5754BREZ 16 −40°C to +85°C 0.1% FSR ±16 LSB 24-Lead TSSOP_EP RE-24 AD5754BREZ-REEL7 16 −40°C to +85°C 0.1% FSR ±16 LSB 24-Lead TSSOP_EP RE-24 1 Z = RoHS Compliant Part. ©2008–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06468-0-2/17(F) Rev. F | Page 31 of 31