Quad, 12-Bit, Parallel Input, Unipolar/Bipolar, Voltage Output DAC Data Sheet AD5725 FEATURES FUNCTIONAL BLOCK DIAGRAM +5 V to ±15 V operation AVSS AVDD VREFP Unipolar or bipolar operation VL ±0.5 LSB max INL error, ±1 LSB max DNL error 12 INPUT DAC 12 Settling time: 10 µs max (10 V step) A0 I/O REG A REG A DAC A VOUTA A1 REGISTER Double-buffered inputs AND Simultaneous updating via LDAC RC/WS COLNOTGRICOL RINEPGU TB RDEAGC B 12 DAC B VOUTB Asynchronous CLR to zero/mid scale Readback 12 RINEPGU TC RDEAGC C 12 DAC C VOUTC DB0 OiCpMeOraSt®i npgro tceemssp teercahtunroel oragnyg e: −40°C to +85°C DBT1O1 RINEPGU TD RDEAGC D 12 DAC D VOUTD AD5725 AInPduPsLtIrCiaAl aTuItOoNmSat ion DGND CLR LDAC VREFN 06442-001 Figure 1. Closed-loop servo control, process control Automotive test and measurement Programmable logic controllers GENERAL DESCRIPTION The AD5725 is a quad, 12-bit, parallel input, voltage output Digital controls allow the user to load or read back data from digital-to-analog converter that offers guaranteed monotonicity, any DAC, load any DAC, and transfer data to all DACs at integral nonlinearity (INL) of ±0.5 LSB maximum and 10 µs one time. maximum settling time. The AD5725 is available in a 28-lead SSOP package. It can be Output voltage swing is set by two reference inputs, V and operated from a wide variety of supply and reference voltages, REFP V . By setting the V input to 0 V and the V to a with supplies ranging from single +5 V to ±15 V, and references REFN REFN REFP positive voltage, the DAC provides a unipolar positive output from +2.5 V to ±10 V. Power dissipation is less than 270 mW range. A similar configuration with V at 0 V and V at a with ±15 V supplies and only 40 mW with a +5 V supply. REFP REFN negative voltage provides a unipolar negative output range. Operation is specified over the temperature range of −40°C Bipolar outputs are configured by connecting both V and to +85°C. REFP V to nonzero voltages. This method of setting output voltage REFN ranges has advantages over the bipolar offsetting methods because it is not dependent on internal and external resistors with different temperature coefficients. iCMOS® Process Technology For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and package size, and increased ac and dc performance. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5725 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 15 Applications ....................................................................................... 1 DAC Architecture....................................................................... 15 Functional Block Diagram .............................................................. 1 Output Amplifiers ...................................................................... 15 General Description ......................................................................... 1 Reference Inputs ......................................................................... 15 Revision History ............................................................................... 2 Parallel Interface ......................................................................... 15 Specifications ..................................................................................... 3 Data Coding ................................................................................ 15 AC Performance Characteristics ................................................ 5 CLR............................................................................................... 15 Timing Characteristics, ............................................................... 6 Power Supplies ............................................................................ 17 Absolute Maximum Ratings ............................................................ 8 Reference Configuration ........................................................... 17 ESD Caution .................................................................................. 8 Single +5 V Supply Operation .................................................. 18 Pin Configuration and Function Descriptions ............................. 9 Outline Dimensions ....................................................................... 19 Typical Performance Characteristics ........................................... 10 Ordering Guide .......................................................................... 19 Terminology .................................................................................... 14 REVISION HISTORY 8/13—Rev. B to Rev. C Change Junction Temperature from 105°C to 150°C; Changed Power Dissipation Package Condition from Derate 10 mW/°C Above 70°C to Derate 10 mW/°C Above 60°C; Table 5 .............. 8 4/13—Rev. A to Rev. B Changes to V Input Current Parameter, Table 1 .................... 3 REFN Changes to Figure 27 and Figure 28 ............................................. 17 Changes to Figure 29 and Figure 30 ............................................. 18 12/08—Rev. 0 to Rev. A Changes to Figure 26 ...................................................................... 13 7/07—Revision 0: Initial Version Power Dissipation Package (Derate 10 mW/°C Above 60°C) Rev. C | Page 2 of 20

Data Sheet AD5725 SPECIFICATIONS AV = +15 V, AV = −15 V, DGND = 0 V; V = +10 V; V = −10 V, V = 5 V. All specifications T to T , unless otherwise noted.1 DD SS REFP REFN L MIN MAX Table 1. Parameter Value Unit Test Conditions/Comments ACCURACY Outputs unloaded Resolution 12 Bits Relative Accuracy (INL) ±0.5 LSB max B grade ±1 LSB max A grade Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic Zero-Scale Error ±2 LSB max R = 2 kΩ L Zero-Scale TC2 ±15 ppm FSR/°C typ R = 2 kΩ L Full-Scale Error ±2 LSB max R = 2 kΩ L Full-Scale TC2 ±20 ppm FSR/°C typ R = 2 kΩ L REFERENCE INPUT V REFP Reference Input Range3 V + 2.5 V min REFN AV − 2.5 V max DD Input Current ±2.75 mA max Typically 1.5 mA V REFN Reference Input Range3 −10 V min V − 2.5 V max REFP Input Current2 0 mA max Typically −2 mA −2.75 mA min Large Signal Bandwidth2 160 kHz typ −3 dB, V = 0 V to 10 V p-p REFP OUTPUT CHARACTERISTICS2 Output Current ±5 mA max R = 2 kΩ, C = 100 pF L L DIGITAL INPUTS V = 2.7 V to 5.5 V, JEDEC compliant L V , Input High Voltage 2.4 V min T = 25°C IH A V , Input Low Voltage 0.8 V max T = 25°C IL A Input Current2 1 µA max Input Capacitance2 8 pF typ DIGITAL OUTPUTS (SDO) V , Output High Voltage 4 V min I = 0.4 mA OH OH V , Output Low Voltage 0.4 V max I = −1.6 mA OL OL POWER SUPPLY CHARACTERISTICS Power Supply Sensitivity2 30 ppm FSR/V max 14.25 V ≤ AVDD ≤ 15.75 V AI 3 mA/channel max Outputs unloaded, V = 2.5 V, typically 2.125 mA DD REFP AI 2.5 mA/channel max Outputs unloaded, typically 1.625 mA SS Power Dissipation 270 mW max 1 All supplies can be varied ±5%, and operation is guaranteed. Device is tested with nominal supplies. 2 Guaranteed by design and characterization, not production tested. 3 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. Rev. C | Page 3 of 20

AD5725 Data Sheet AV = +5 V, AV = −5 V/0 V, DGND = 0 V; V = +2.5 V; V = −2.5 V/0 V, V = 5 V. All specifications T to T , unless DD SS REFP REFN L MIN MAX otherwise noted. Table 2. Parameter Value Unit Test Conditions/Comments ACCURACY Outputs unloaded Resolution 12 Bits Relative Accuracy (INL) ±0.5 LSB max B grade ±1 LSB max A grade ±1 LSB max B grade, AV = 0 V1 SS ±2 LSB max A grade, AV = 0 V1 SS Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic Zero-Scale Error ±5 LSB max AV = −5 V SS ±10 LSB max AV = 0 V SS Zero-Scale TC2 100 ppm FSR/°C typ Full-Scale Error ±5 LSB max AV = −5 V SS ±10 LSB max AV = 0 V SS Full-Scale TC2 100 ppm FSR/°C typ REFERENCE INPUT V REFP Reference Input Range3 V + 2.5 V min REFN AV − 2.5 V max DD Input Current2 ±0.5 mA max Code 0x0000 V REFN Reference Input Range3 −2.5 V min AV = −5 V SS 0 V min AV = 0 V SS V − 2.5 V max REFP Large Signal Bandwidth2 450 kHz typ −3 dB, V = 0 V to 2.5 V p-p REFP OUTPUT CHARACTERISTICS2 Output Current ±1.25 mA max R = 2 kΩ, C = 100 pF L L DIGITAL INPUTS V = 2.7 V to 5.5 V, JEDEC compliant L V , Input High Voltage 2.4 V min T = 25°C IH A V , Input Low Voltage 0.8 V max T = 25°C IL A Input Current2 1 µA max Input Capacitance2 8 pF typ DIGITAL OUTPUTS (SDO) V , Output High Voltage 4 V min I = 0.4 mA OH OH V , Output Low Voltage 0.4 V max I = −1.6 mA OL OL POWER SUPPLY CHARACTERISTICS Power Supply Sensitivity2 100 ppm FSR/V typ AI 2 mA/channel max Outputs unloaded. DD AI 1.5 mA/channel max Outputs unloaded, A = −5 V SS VSS Power Dissipation 70 mW max AV = −5 V SS 40 mW max AV = 0 V SS 1 For single supply operation only (VREFN = 0 V, AVSS = 0 V): Due to internal offset errors, INL and DNL are measured beginning at code 0x005. 2 Guaranteed by design and characterization, not production tested. 3 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. Rev. C | Page 4 of 20

Data Sheet AD5725 AC PERFORMANCE CHARACTERISTICS1 AV = +15 V/+5 V, AV = −15 V/−5 V/0 V, DGND = 0 V; V = +10 V/+2.5 V; V = −10 V/−2.5 V/0 V, V = 5 V. All specifications DD SS REFP REFN L T to T , unless otherwise noted. MIN MAX Table 3. Parameter A Grade B Grade Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 10 10 µs typ To 0.01%, 10 V step, R = 1 kΩ L 7 7 µs typ To 0.01%, 2.5 V step, R = 1 kΩ L Slew Rate 2.2 2.2 V/µs typ 10% to 90% Analog Crosstalk 72 72 dB typ Digital Feedthrough 5 5 nV-s typ 1 Guaranteed by design and characterization, not production tested. Rev. C | Page 5 of 20

AD5725 Data Sheet TIMING CHARACTERISTICS1, 2 AV = +5 V/+15 V, AV = −5 V/0 V/−15 V, DGND = 0 V; V = +2.5 V/+10 V; V = −2.5 V/0 V/−10 V, V = 5 V. All specifications DD SS REFP REFN L T to T , unless otherwise noted. MIN MAX Table 4. Parameter Limit at T , T Unit Description MIN MAX t 10 ns min Chip Select Write Pulse Width WCS t 0 ns min Write Setup, t = 10 ns WS WCS t 0 ns min Write Hold, t = 10 ns WH WCS t 0 ns min Address Setup AS t 0 ns min Address Hold AH t 5 ns min Load Setup LS t 5 ns min Load Hold LH t 5 ns min Write Data Setup, t = 10 ns WDS WCS t 0 ns min Write Data Hold, t = 10 ns WDH WCS t 10 ns min Load Data Pulse Width LDW t 10 ns min Reset Pulse Width RESET t 30 ns min Chip Select Read Pulse Width RCS t 0 ns min Read Data Hold, t = 30 ns RDH RCS t 0 ns min Read Data Setup, t = 30 ns RDS RCS t 15 ns max Data to High-Z, C = 10 pF DZ L t 35 ns max Chip Select to Data, C = 100 pF CSD L 1 All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 2 Guaranteed by design and characterization, not production tested. Rev. C | Page 6 of 20

Data Sheet AD5725 Timing Diagrams 10ns CS tRCS CS tWS tWH tRDS tRDH R/W R/W tAS tAS tAH ADDRESS ADODRNEESS ADTDWREOSS ADTHDRREEESS ADFDORUERSS A0/A1 tLS tLH tDZ LDAC DATA HIGH-Z HIGH-Z OUT tCSD DATA VALID 06442-002 DATA IN DVAATLtAWID1DS DVAATLAID2 DVAATLAID3 DVAATLAID4 tWDH 06442-004 Figure 2. Data Read Timing Figure 4. Single Buffer Mode Timing tWCS 10ns CS CS tWS tWH tWS tWH R/W R/W tAS tAH A0/A1 tAS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ONE TWO THREE FOUR tLS tLH tLDW tLS tLH LDAC LDAC tWDS tWDH tWDS tLDWtWDH DRAETASE INT tRESET 06442-003 DATAIN DVAATLAID1 DVAATLAID2 DVAATLAID3 DVAATLAID4 06442-005 Figure 3. Data Write Timing Figure 5. Double Buffer Mode Timing Rev. C | Page 7 of 20

AD5725 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C unless otherwise noted. Transient currents of up to A Stresses above those listed under Absolute Maximum Ratings 100 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 5. other conditions above those listed in the operational sections Parameter Rating of this specification is not implied. Exposure to absolute AV to DGND +0.3 V to −16.5 V SS maximum rating conditions for extended periods may affect AV to DGND −0.3 V to +16.5 V DD device reliability. AV to AV +0.3 V to −33 V SS DD V to DGND −0.3 V to +7 V L Current into Any Pin ±15 mA ESD CAUTION Digital Pin Voltage to DGND −0.3 V to +7 V Operating Temperature Range Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 150°C J 28-Lead SSOP Package θ Thermal Impedance 100°C/W JA θ Thermal Impedance 39°C/W JC Power Dissipation Package 900 mW (Derate 10 mW/°C Above 60°C) Reflow Soldering Time at Peak Temperature 10 sec to 40 sec Lead Temperature (Soldering, 60 sec) 300°C Rev. C | Page 8 of 20

Data Sheet AD5725 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VREFP 1 28 VREFN VOUTB 2 27 VOUTC VOUTA 3 26 VOUTD AVSS 4 25 AVDD DGND 5 24 VL CLR 6 AD5725 23 CS TOP VIEW LDAC 7 (Not to Scale) 22 A0 DB0 (LSB) 8 21 A1 DB1 9 20 R/W DB2 10 19 DB11 (MSB) DB3 11 18 DB10 DB4 12 17 DB9 DDBB56 1134 1165 DDBB87 06442-006 Figure 6. Pin Configuration Diagram Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 V Positive DAC Reference Input. The voltage applied to this pin defines the full-scale output voltage. REFP Allowable range is AV − 2.5 V to V + 2.5 V. DD REFN 2 V Buffered Analog Output Voltage of DAC B. OUTB 3 V Buffered Analog Output Voltage of DAC A. OUTA 4 AV Negative Analog Supply Pin. Voltage ranges from 0 V to −15 V. SS 5 DGND Digital Ground Pin. 6 CLR Active Low Input. Sets input registers and DAC registers to zero scale (0x000) for the AD5725-1 or midscale (0x800) for the AD5725. 7 LDAC Active Low Load DAC Input. 8 DB0 Data Bit 0 (LSB). 9 DB1 Data Bit 1. 10 DB2 Data Bit 2. 11 DB3 Data Bit 3. 12 DB4 Data Bit 4. 13 DB5 Data Bit 5. 14 DB6 Data Bit 6. 15 DB7 Data Bit 7. 16 DB8 Data Bit 8. 17 DB9 Data Bit 9. 18 DB10 Data Bit 10. 19 DB11 Data Bit 11 (MSB). 20 R/W Read/Write Pin. Active low to write data to DAC; Active high to read back previous data at data bit pins with V connected to +5 V. L 21 A1 Address Bit 1. 22 A0 Address Bit 0. 23 CS Active Low Chip Select Pin. 24 V Voltage Supply for Readback Function. Can be left open circuit if not used. L 25 AV Positive Analog Supply Pin. Voltage ranges from +5 V to +15 V. DD 26 V Buffered Analog Output Voltage of DAC D. OUTD 27 V Buffered Analog Output Voltage of DAC C. OUTC 28 V Negative DAC Reference Input. The voltage applied to this pin defines the zero-scale output voltage. REFN Allowable range is AV to V − 2.5 V. SS REFP Rev. C | Page 9 of 20

AD5725 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.5 AVDD = +15V AVDD = 5V 0.8 AVSS = –15V 0.4 AVSS = 0V VREFN = –10V VREFN = 0V 0.6 TA = 25°C 0.3 TA = 25°C R (LSB) 00..42 R (LSB) 0.2 RO RO 0.1 MAX DNL ER––00..240 MAX INL ER–0.10 –0.2 –0.6 –0.8 –0.3 –1.0 –0.4 6 7 8 VREF9P (V) 10 11 12 06442-017 1.0 1.2 1.4 1.6 1.8VRE2F.P0 (V)2.2 2.4 2.6 2.8 3.0 06442-020 Figure 7. DNL vs. VREFP (VSUPPLY = ±15 V) Figure 10. INL vs. VREFP (VSUPPLY = +5 V) 0.05 0 AVDD = +15V AVSS = –15V 0 –0.1 VREFP = +10V VREFN = –10V B) 2kΩ LOAD B) S–0.2 OR (LS–0.05 ROR (L–0.3 DAC D R R ER–0.10 E E DNL CAL–0.4 MAX –0.15 ULL-S–0.5 F DAC B DAC C –0.20 AAVVDSSD == 05VV –0.6 VREFN = 0V DAC A TA = 25°C –0.25 –0.7 1.0 1.2 1.4 1.6 1.8VRE2F.P0 (V)2.2 2.4 2.6 2.8 3.0 06442-018 –40 –20 0TEMPERA20TURE (°C4)0 60 80 06442-023 Figure 8. DNL vs. VREFP (VSUPPLY = +5 V) Figure 11. Full-Scale Error vs. Temperature 1.0 0.3 AVDD = +15V AVDD = +15V 0.8 AVSS = –15V AVSS = –15V VREFN = –10V 0.2 VREFP = +10V 0.6 TA = 25°C VREFN = –10V B) 2kΩ LOAD LSB) 0.4 R (LS 0.1 ERROR ( 0.20 E ERRO 0 AX INL –0.2 O-SCAL–0.1 DAC A M–0.4 R DAC D E Z DAC C –0.6 –0.2 –0.8 DAC B –1.0 –0.3 6 7 8 VREF9P (V) 10 11 12 06442-019 –40 –20 0TEMPERA20TURE (°C4)0 60 80 06442-024 Figure 9. INL vs. VREFP (VSUPPLY = ±15 V) Figure 12. Zero-Scale Error vs. Temperature Rev. C | Page 10 of 20

Data Sheet AD5725 0.3 0.4 0.3 0.2 DAC A +85°C DDAACC BC 0.2 +–4205°°CC DAC D B) 0.1 B) S S 0.1 L L R ( R ( RO 0 RO 0 R R E E NL NL –0.1 I–0.1 I AVDD = +15V –0.2 –0.2 AVRVESFSP = = – +1150VV –0.3 AAVVDSSD == –+1155VV VREFN = –10V VREFP = +10V TA = 25°C VREFN = –10V –0.3 –0.4 0 500 1000 1500DA2C0 (0C0ode2)500 3000 3500 4000 06442-025 0 500 1000 1500DA2C0 0(C0ode2)500 3000 3500 4000 06442-028 Figure 13. Channel-to-Channel Matching (VSUPPLY = ±15 V) Figure 16. INL vs. DAC Code 0.3 0.20 +85°C +25°C 0.2 DAC A 0.15 –40°C DAC B 0.1 DDAACC CD 0.10 B) B) R (LS 0 R (LS 0.05 RO RO 0 R R NL E–0.1 NL E–0.05 I D –0.2 AVDD = 5V –0.10 AVSS = 0V AVDD = +15V –0.3 VREFP = 2.5V –0.15 AVSS = –15V VREFN = 0V VREFP = +10V TA = 25°C VREFN = –10V –0.4 –0.20 0 500 1000 1500DA2C0 (0C0ode2)500 3000 3500 4000 06442-026 0 500 1000 1500DA2C0 0(C0ode2)500 3000 3500 4000 06442-042 Figure 14. Channel-to-Channel Matching (VSUPPLY = +5 V) Figure 17. DNL vs. DAC Code 16 1.7995 AVDD = +15V VREFP = +10V VREFN = –10V TA = 25°C 14 1.5995 AVSS = –15V 1.3995 12 1.1995 10 A) A) m0.9995 I (mDD 8 V (REFP0.7995 6 I 0.5995 4 AVDD = +15V 0.3995 AVSS = –15V 2 VDRIGEFITNA =L –IN10PVUTS HIGH 0.1995 TA = 25°C 0 –0.0005 –7 –5 –3 –1 1VREF3P (V)5 7 9 11 13 06442-027 0 500 1000 1500DA2C0 (0C0ode2)500 3000 3500 4000 06442-029 Figure 15. IDD vs. VREFP Figure 18. IVREFP vs. DAC Code Rev. C | Page 11 of 20

AD5725 Data Sheet 12 1.0 AVDD = +15V AVDD = +15V AVSS = –15V 0.9 AVSS = –15V 10 VVRREEFFPN == +–1100VV 0.8 VVRREEFFPN == +–1100VV V) TA = 25°C TA = 25°C E ( V) 0.7 G 8 m E VOLTA 6 ENSITY ( 00..65 L D 0.4 LL-SCA 4 NOISE 0.3 U 0.2 F 2 0.1 0 0 –0.1 0.01 0.1 LOAD RESIS1TANCE (kΩ) 10 100 06442-035 1 10 NOIS1E0 0FREQUENC1kY (Hz) 10k 100k 06442-044 Figure 19. Output Voltage Swing vs. Resistive Load Figure 22. Output Noise Spectral Density vs. Frequency 2 20 AVDD = +15V 0 15 AVSS = –15V VREFP = +10V –2 10 VTAR E=F N25 =° C–10V DATA = 0x000 –4 5 GAIN (dB) ––68 I (µA)OUT 0 –5 –10 AVDD = +15V –12 AVSS = –15V –10 VREFP = 0V ± 100mV –14 VDRAETFAN B=I T–1S0 =V +5V –15 TA = 25°C –16 –20 10 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 06442-036 –15 –10 –5 VOU0T (V) 5 10 15 06442-040 Figure 20. Small Signal Response Figure 23. IOUT vs. VOUT (VSUPPLY = ±15 V) 8 25 6 IDD 20 AAVRVVEDSFSDP == = 01 1V50VV T (mA) 4 AAVVDSSD == –+1155VV 15 VTDARA ET=FA N2 5 ==° C00xV800 N E R 2 R U A) 10 C µ PPLY 0 I (OUT 5 SU –2 R E 0 W –4 PO ISS –6 –5 –8 –10 –35 –15 5TEMPERA25TURE (°C4)5 65 85 06442-045 0 1 2 3 4 VOU5T (V) 6 7 8 9 10 06442-041 Figure 21. Power Supply Current vs. Temperature Figure 24. IOUT vs. VOUT (VSUPPLY = +15 V) Rev. C | Page 12 of 20

Data Sheet AD5725 1.0 0x800 → 0x7FF (±15V SUPPLY) AVDD = +15V VREFP = +10V TA = 25°C 0x7FF → 0x800 (±15V SUPPLY) AVSS = –15V VREFN = –10V BW = 100kHz 0.8 0x800 → 0x7FF (±5V SUPPLY) 0x7FF → 0x800 (±5V SUPPLY) V) 0.6 E ( D U T 0.4 LI 1 MP H A 0.2 C T GLI 0 –0.2 CH1 50µV M 2s A CH1 0V 06442-046 –0.40 100 200 300 400TIM5E0 0(ns)600 700 800 900 1000 06442-043 Figure 25. Broadband Noise Figure 26. Output Glitch Rev. C | Page 13 of 20

AD5725 Data Sheet TERMINOLOGY Zero-Scale Error TC Relative Accuracy or Integral Nonlinearity (INL) Zero-scale error TC is a measure of the change in zero-scale For the DAC, relative accuracy or integral nonlinearity is a error with a change in temperature. Zero-scale error TC is measure of the maximum deviation, in LSBs, from a straight expressed in ppm FSR/°C. line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 16. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for Differential Nonlinearity (DNL) the output to settle to a specified level for a full-scale input Differential nonlinearity is the difference between the measured change. change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum Slew Rate ensures monotonicity. This DAC is guaranteed monotonic by The slew rate of a device is a limitation in the rate of change of design. A typical DNL vs. code plot can be seen in Figure 17. the output voltage. The output slewing speed of a voltage- output DAC is usually limited by the slew rate of the amplifier Monotonicity used at its output. Slew rate is measured from 10% to 90% of the A DAC is monotonic if the output either increases or remains output signal and is given in V/µs. constant for increasing digital input code. The AD5725 is monotonic over its full operating temperature range. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into Full-Scale Error the analog output of the DAC from the digital inputs of the Full-scale error is a measure of the output error when full-scale DAC, but it is measured when the DAC output is not updated. code is loaded to the DAC register. Ideally, the output should be It is specified in nV-sec and measured with a full-scale code V − 1 LSB. Full-scale error is expressed in LSBs. A plot of REFP change on the data bus. full-scale error vs. temperature can be seen in Figure 11. Power Supply Sensitivity Full-Scale Error TC Power supply sensitivity indicates how the output of the DAC is Full-scale error TC is a measure of the change in full-scale error affected by changes in the power supply voltage. with a change in temperature. Full-scale error TC is expressed in ppm FSR/°C. Analog Crosstalk Analog crosstalk is the dc change in the output level of one Zero-Scale Error DAC in response to a change in the output of another DAC. It is Zero-scale error is the error in the DAC output voltage when measured with a full-scale output change on one DAC while 0x0000 (straight binary coding) is loaded to the DAC register. monitoring another DAC. It is expressed in dB. Ideally, the output voltage should be V . A plot of zero-scale REFN error vs. temperature can be seen in Figure 12. Rev. C | Page 14 of 20

Data Sheet AD5725 THEORY OF OPERATION PARALLEL INTERFACE The AD5725 is a quad voltage output, 12-bit parallel input DAC featuring a 12-bit data bus with readback capability. The AD5725 See Table 7 for the digital control logic truth table. The parallel operates from single or dual supplies ranging from +5 V up to interface consists of a 12-bit bidirectional data bus, two register ±15 V. The output voltage range is set by the reference voltages select inputs, A0 and A1, a R/W input, a chip select (CS), and a applied at the V and V pins. REFP REFN load DAC (LDAC) input. Control of the DACs and bus DAC ARCHITECTURE direction is determined by these inputs as shown in Table 7. Digital data bits are labeled with the MSB defined as Data Bit 11 Each of the four DACs is a voltage switched, high impedance and the LSB as Data Bit 0. All digital pins are TTL/CMOS (50 kΩ), R-2R ladder configuration. Each 2R resistor is driven compatible. by a pair of switches that connect the resistor to either V REFH or V . The register select inputs A0 and A1 select individual DAC REFL OUTPUT AMPLIFIERS Register A (Binary Code 00) through Register D (Binary Code 11). Decoding of the registers is enabled by the CS input. When CS The output amplifiers are capable of generating both unipolar is high, no decoding takes place, and neither the writing nor the and bipolar output voltages. They are capable of driving a load reading of the input registers is enabled. The loading of the of 2 kΩ in parallel with 500 pF to DGND. The source and sink second bank of registers is controlled by the asynchronous capabilities of the output amplifiers can be seen in Figure 23 LDAC input. By taking LDAC low while CS is high, all output and Figure 24. The slew rate is 2.2 V/µs with a full-scale settling registers can be updated simultaneously. Note that the t LDW time of 10 µs. The amplifiers are short-circuit protected. required pulse width for updating all DACs is a minimum of Careful attention to grounding is important for accurate 10 ns. The R/W input, when enabled by CS, controls the writing operation of the AD5725. With four outputs and two references to and reading from the input register. there is potential for ground loops. Since the AD5725 has no DATA CODING analog ground, the ground must be specified with respect to the reference. The AD5725 uses binary coding. The output voltage can be calculated as follows: REFERENCE INPUTS (V −V )×D All four DACs share common positive reference (VREFP) and V =V + REFP REFN OUT REFN negative reference (V ) inputs. The voltages applied to these 4096 REFN reference inputs set the output high and low voltage limits on all where D is the digital code in decimal. four of the DACs. Each reference input has voltage restrictions CLR with respect to the other reference and to the power supplies. V can be any voltage between AV and V − 2.5 V and The CLR function can be used either at power-up or at any time REFN SS REFP VREFP can be any value between AVDD – 2.5 V and during the DACs operation. The CLR function is independent VREFN + 2.5 V. Note that because of these restrictions, the of CS. This pin is active low and sets the DAC registers to either AD5725 references cannot be inverted (VREFN cannot be midscale code (0x800) for the AD5725 or zero code (0x000) for greater than VREFP). the AD5725-1. The CLR to midscale code is most useful when It is important to note that the AD5725 V input both sinks the DAC is configured for bipolar references and an output of REFP and sources current. Also, the input current of both V and 0 V is desired. REFP V are code dependent. Many references have limited current REFN sinking capability and must be buffered with an amplifier to drive V . The V reference input has no such special REFP REFN requirements. It is recommended that the reference inputs be bypassed with 0.2 µF capacitors when operating with ±10 V references. This limits the reference bandwidth. Rev. C | Page 15 of 20

AD5725 Data Sheet Table 7. AD5725 Logic Truth Table A1 A0 R/W CS CLR LDAC INPUT REG DAC REG MODE DAC Low Low Low Low High Low Write Write Transparent A Low High Low Low High Low Write Write Transparent B High Low Low Low High Low Write Write Transparent C High High Low Low High Low Write Write Transparent D Low Low Low Low High High Write Hold Write Input A Low High Low Low High High Write Hold Write Input B High Low Low Low High High Write Hold Write Input C High High Low Low High High Write Hold Write Input D Low Low High Low High High Read Hold Read Input A Low High High Low High High Read Hold Read Input B High Low High Low High High Read Hold Read Input C High High High Low High High Read Hold Read Input D X X X High High Low Hold Update all DAC registers All X X X High High High Hold Hold Hold All X X X X Low X All Registers set to mid/zero scale All X X X High  X All Registers latched to mid/zero scale All Rev. C | Page 16 of 20

Data Sheet AD5725 POWER SUPPLIES Figure 28 (Symmetrical Bipolar Operation) shows the AD5725 configured for ±10 V operation. See the AD688 data sheet for a Power supplies required are AV , AV , and V . The AV SS DD L SS full explanation of reference operation. Adjustments may not be supply can be set between −15 V and 0 V. AV is the positive DD required for many applications since the AD688 is a very high supply; its operating range is between +5 V and +15 V. accuracy reference. However, if additional adjustments are V is the digital output supply voltage for the readback function. L required, adjust the AD5725 full scale first. Begin by loading the It is normally connected to +5 V. This pin is a logic reference digital full-scale code (0xFFF). Then, adjust the gain adjust input only. It does not supply current to the device. If the readback potentiometer to attain a DAC output voltage of 9.9976 V. function is not used, V can be left open-circuit. While V does L L Then, adjust the balance adjust to set the mid-scale output not supply current to the AD5725, it does supply current to the voltage to 0.000 V. digital outputs when the readback function is used. The 0.2 µF bypass capacitors shown at the reference inputs in REFERENCE CONFIGURATION Figure 28 should be used whenever ±10 V references are used. Output voltage ranges can be configured as either unipolar or Applications with single references or references to ±5 V may bipolar, and within these choices, a wide variety of options not require the 0.2 µF bypassing. The 6.2 Ω resistor in series exists. The unipolar configuration can be either a positive or a with the output of the reference amplifier is to keep the amplifier negative voltage output, and the bipolar configuration can be from oscillating with the capacitive load. We have found that either symmetrical or nonsymmetrical. this is large enough to stabilize this circuit. Larger resistor values are acceptable, provided that the drop across the resistor does not exceed a V . Assuming a minimum V of 0.6 V and a +15V BE BE +15V maximum current of 2.75 mA, the resistor should be under + 200 Ω for the loading of a single AD5725. 0.1µF INPUT OP1177 VREFP AVDD 10µF Using two separate references is not recommended. Having two OUTPUT 0.2µF references can cause different drifts with time and temperature, AD5725 ADR01 whereas with a single reference, most drifts will track. TRIM 10kΩ Unipolar positive full-scale operation can usually be set with a VREFN AVSS reference with the correct output voltage. This is preferable to +10V OPERATION using a reference and dividing down to the required value. For a 0.1µF 10 V full-scale output, the circuit can be configured as shown in –15V 10µF 06442-007 aFdigjuusrtei n2g9 .t hIne t1h0i sk cΩo nrefisgisutroart ifoonr ,a t hfuel lf-uslcl-aslec aoleu tvpaulut eo fi s9 s.9e9t 7fi6r sVt .b y Figure 27. Unipolar +10 V Operation +15V 39kΩ +15V 6 4 3 0.1µF AVDD 6.2Ω 10µF BALANCE 12 1 VREFP 100kΩ 0.2µF AD688 FOR ±10V AD5725 AD588 FOR ±5V 5 14 GAIN 100kΩ 6.2Ω 15 VREFN 0.2µF AVSS 8 13 7 1µF 0.1µF –15V ±5 OR ±10V OPERATION 10µF 06442-008 Figure 28. Symmetrical Bipolar Operation Rev. C | Page 17 of 20

AD5725 Data Sheet Figure 29 shows the AD5725 configured for −10 V to 0 V SINGLE +5 V SUPPLY OPERATION operation. An ADR01 and OP1177 are configured to produce a For operation with a +5 V supply, the reference voltage should −10 V output, which is connected directly to V for the REFP be set between +1.0 V and +2.5 V for optimum linearity. Figure 30 reference voltage. shows an ADR03 used to supply a +2.5 V reference voltage. The +15V U1 headroom of the reference and DAC are both sufficient to support +15V VIN VOUT a +5 V supply with ±5 V tolerance. AVDD and VL should be 0.1µF ADR01 connected to the same supply. Separate bypassing to each pin 10µF AVDD VREFP TEMP TRIM should be used. GND +15V +5V AD5725 U2 V+ 10µF 0.01µF +15V VREFN OP1177 AVSS 0.2µF V– INPUT 0.1µF OUTPUT VREFP AVDD 10µF 0.1µF 10µF –15V 0V TO –10V OPERATION –15V 06442-009 ADR03 TRIM 10kΩ 0.2µF AD5725 Figure 29. Unipolar −10 V Operation GND VREFN AVSS 0V TO 2.5V OPERATION SINGLE 5V SUPPLY 0.1µF –15V 10µF 06442-010 Figure 30. +5 V Single-Supply Operation Rev. C | Page 18 of 20

Data Sheet AD5725 OUTLINE DIMENSIONS 10.50 10.20 9.90 28 15 5.60 5.30 5.00 8.20 7.80 1 7.40 14 1.85 0.25 2.00 MAX 1.75 0.09 1.65 COPLA0N.0A5R MITIYN 0.65 BSC 00..3282 SPLEAATNIENG 840°°° 000...975555 0.10 COMPLIANTTO JEDEC STANDARDS MO-150-AH 060106-A Figure 31. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters ORDERING GUIDE INL Package Model1 Temperature Range (LSB) Clear Action Package Description Option AD5725ARSZ-1500RL7 −40°C to +85°C 1 Clear to zero scale 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD5725ARSZ-1REEL −40°C to +85°C 1 Clear to zero scale 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD5725ARSZ-500RL7 −40°C to +85°C 1 Clear to midscale 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD5725ARSZ-REEL −40°C to +85°C 1 Clear to midscale 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD5725BRSZ-1500RL7 −40°C to +85°C 0.5 Clear to zero scale 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD5725BRSZ-1REEL −40°C to +85°C 0.5 Clear to zero scale 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD5725BRSZ-500RL7 −40°C to +85°C 0.5 Clear to midscale 28-Lead Shrink Small Outline Package [SSOP] RS-28 AD5725BRSZ-REEL −40°C to +85°C 0.5 Clear to midscale 28-Lead Shrink Small Outline Package [SSOP] RS-28 1 Z = RoHS Compliant Part. Rev. C | Page 19 of 20

AD5725 Data Sheet NOTES ©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06442-0-8/13(C) Rev. C | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5725BRSZ-500RL7 AD5725ARSZ-1500RL7 AD5725ARSZ-REEL AD5725ARSZ-500RL7 AD5725ARSZ-1REEL AD5725BRSZ-1500RL7 AD5725BRSZ-REEL