Complete, Dual, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DACs Data Sheet AD5722R/AD5732R/AD5752R FEATURES Nominal full-scale output range is software selectable from Complete, dual, 12-/14-/16-bit digital-to-analog converter (DAC) +5 V, +10 V, +10.8 V, ±5 V, ±10 V, or ±10.8 V. Integrated output Operates from single/dual supplies amplifiers, reference buffers, and proprietary power-up/power- Software programmable output range down control circuitry are also provided. +5 V, +10 V, +10.8 V, ±5 V, ±10 V, ±10.8 V The devices offer guaranteed monotonicity, integral INL error: ±16 LSB maximum, DNL error: ±1 LSB maximum nonlinearity (INL) of ±16 LSB maximum, low noise, 10 μs Total unadjusted error (TUE): 0.1% FSR maximum maximum settling time, and an on-chip +2.5 V reference. Settling time: 10 μs typical The AD5722R/AD5732R/AD5752R use a serial interface that Integrated reference: 5 ppm/°C maximum operates at clock rates up to 30 MHz and are compatible with Integrated reference buffers DSP and microcontroller interface standards. Double buffering Output control during power-up/brownout allows the simultaneous updating of all DACs. The input coding Simultaneous updating via LDAC is user-selectable twos complement or offset binary for a bipolar Asynchronous CLR to zero scale or midscale output (depending on the state of Pin BIN/2sComp), and DSP-/microcontroller-compatible serial interface 24-lead TSSOP straight binary for a unipolar output. The asynchronous clear Operating temperature range: −40°C to +85°C function clears all DAC registers to a user-selectable zero-scale iCMOS process technology1 or midscale output. The devices are available in a 24-lead TSSOP and offer guaranteed specifications over the −40°C to APPLICATIONS +85°C industrial temperature range. Industrial automation Closed-loop servo control, process control Table 1. Pin Compatible Devices Automotive test and measurement Device Number Description Programmable logic controllers AD5722/AD5732/AD5752 AD5722R/AD5732R/AD5752R GENERAL DESCRIPTION without internal reference. AD5724/AD5734/AD5754 Complete, quad, 12-/14-/16-bit, The AD5722R/AD5732R/AD5752R are dual, 12-/14-/16-bit, serial input, unipolar/bipolar, serial input, voltage output digital-to-analog converters. They voltage output DACs. operate from single supply voltages of +4.5 V up to +16.5 V or AD5724R/AD5734R/AD5754R AD5724/AD5734/AD5754 with dual supply voltages from ±4.5 V up to ±16.5 V. internal reference. . FUNCTIONAL BLOCK DIAGRAM AVSS AVDD REFIN/REFOUT AD5722R/AD5732R/AD5752R DVCC 2.5V REFERENCE CLR REFERENCE BUFFERS BIN/2sCOMP n n INPUT DAC SDIN INPUTSHIFT REGISTER A REGISTER A DACA VOUTA REGISTER SCLK AND SYNC CONTROL INPUT DAC n LOGIC REGISTER B REGISTER B DACB VOUTB SDO AD5722: n = 12-BIT GND LDAC DAC_GND (2) SIG_GND (2) 06466-001 AD5732: n = 14-BIT AD5752: n = 16-BIT Figure 1. 1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS® is a technology platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and package size, as well as increased ac and dc performance. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5722R/AD5732R/AD5752R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Shift Register .................................................................... 26 Applications ....................................................................................... 1 DAC Register .............................................................................. 27 General Description ......................................................................... 1 Output Range Select Register ................................................... 27 Functional Block Diagram .............................................................. 1 Control Register ......................................................................... 28 Revision History ............................................................................... 2 Power Control Register.............................................................. 28 Specifications ..................................................................................... 3 Design Features ............................................................................... 29 AC Performance Characteristics ................................................ 5 Analog Output Control ............................................................. 29 Timing Characteristics ................................................................ 6 Power-Up Sequence ................................................................... 20 Timing Diagrams .......................................................................... 7 Power-Down Mode .................................................................... 29 Absolute Maximum Ratings ............................................................ 9 Overcurrent Protection ............................................................. 29 ESD Caution .................................................................................. 9 Thermal Shutdown .................................................................... 29 Pin Configuration and Function Descriptions ........................... 10 Internal Reference ...................................................................... 29 Typical Performance Characteristics ........................................... 11 Applications Information .............................................................. 30 Terminology .................................................................................... 18 +5 V/±5 V Operation ................................................................ 30 Theory of Operation ...................................................................... 20 Layout Guidelines....................................................................... 30 Architecture ................................................................................. 20 Galvanically Isolated Interface ................................................. 31 Serial Interface ............................................................................ 20 Microprocessor Interfacing ....................................................... 31 Load DAC (LDAC)..................................................................... 22 Outline Dimensions ....................................................................... 32 Asynchronous Clear (CLR) ....................................................... 22 Ordering Guide .......................................................................... 32 Configuring the AD5722R/AD5732R/AD5752R .................. 22 Transfer Function ....................................................................... 22 REVISION HISTORY 2/2017—Rev. E to Rev. F 3/2011—Rev. B to Rev. C Added Power-Up Sequence Section ............................................. 20 Changes to Configuring the AD5722R/AD5732R/ Changes to Table 8 and Table 9 ..................................................... 23 AD5752R Section ........................................................................... 22 Changes to Table 11 and Table 12 ................................................ 24 Changes to Table 14 and Table 15 ................................................ 25 8/2010—Rev. A to Rev. B Change to Analog Output Section ............................................... 29 Changes to Table 28 ....................................................................... 28 Added Alternative Power-Up Sequence Support Section ......... 30 4/2010—Rev. 0 to Rev. A 2/2016—Rev. D to Rev. E Changes to Junction Temperature, T max Parameter, Table 5 ... 9 J Changes to Table 1 ............................................................................ 3 Changes to Exposed Paddle Description, Table 6 ...................... 10 7/2011—Rev. C to Rev. D 11/2008—Revision 0: Initial Version Changes to Table 4: t7, t8, t10 Limits ....................................................... 6 Rev. F | Page 2 of 32

Data Sheet AD5722R/AD5732R/AD5752R SPECIFICATIONS AV = 4.5 V1 to 16.5 V; AV = −4.5 V1 to −16.5 V, or AV = 0 V; GND = 0 V; REFIN= 2.5 V external; DV = 2.7 V to 5.5 V; R = 2 kΩ; DD SS SS CC LOAD C = 200 pF; all specifications T to T unless otherwise noted. LOAD MIN MAX Table 2. Parameter Min Typ Max Unit Test Conditions/Comments ACCURACY Outputs unloaded Resolution AD5752R 16 Bits AD5732R 14 Bits AD5722R 12 Bits Total Unadjusted Error (TUE) −0.1 +0.1 % FSR ±10 V range Integral Nonlinearity (INL)2 AD5752R −16 +16 LSB AD5732R −4 +4 LSB AD5722R −1 +1 LSB Differential Nonlinearity (DNL) −1 +1 LSB All models, guaranteed monotonic Bipolar Zero Error −6 +6 mV ±10 V range, T = 25 C, error at other temperatures A obtained using bipolar zero TC Bipolar Zero TC3 ±4 ppm FSR/°C Zero-Scale Error −6 +6 mV ±10 V range, T = 25°C, error at other temperatures A obtained using zero-scale TC Zero-Scale TC3 ±4 ppm FSR/°C Offset Error −6 +6 mV 10 V range, T = 25°C, error at other temperatures A obtained using offset error TC Offset Error TC3 ±4 ppm FSR/°C Gain Error −0.025 +0.025 % FSR ±10 V range, T = 25°C, error at other temperatures A obtained using gain TC Gain Error3 −0.065 0 % FSR +10 V and +5 V ranges, T = 25°C, error at other A temperatures obtained using gain TC Gain Error3 0 0.08 % FSR ±5 V range, T = 25°C, error at other temperatures A obtained using gain TC Gain TC3 ±4 ppm FSR/°C DC Crosstalk3 120 µV REFERENCE INPUT/OUTPUT Reference Input3 Reference Input Voltage 2.5 V ±1% for specified performance DC Input Impedance 1 5 MΩ Input Current −2 ±0.5 +2 µA Reference Range +2 +3 V Reference Output Output Voltage +2.497 +2.501 V T = 25°C A Reference TC3 −5 ±1.8 +5 ppm/°C 0°C to +85°C −10 ±2.2 +10 ppm/°C −40°C to +85°C Output Noise (0.1 Hz to 10 Hz)3 5 µV p-p Noise Spectral Density3 75 nV/√Hz 10 kHz OUTPUT CHARACTERISTICS3 Output Voltage Range −10.8 +10.8 V AV /AV = ±11.7 V min, REFIN = 2.5 V DD SS −12 +12 V AV /AV = ±12.9 V min, REFIN = 3 V DD SS Headroom 0.5 0.9 V Output Voltage TC ±4 ppm FSR/°C Short-Circuit Current 20 mA Load 2 kΩ For specified performance Capacitive Load Stability 4000 pF DC Output Impedance 0.5 Ω Rev. F | Page 3 of 32

AD5722R/AD5732R/AD5752R Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments DIGITAL INPUTS3 DV = 2.7 V to 5.5 V, JEDEC compliant CC Input High Voltage, V 2 V IH Input Low Voltage, V 0.8 V IL Input Current ±1 µA Per pin Pin Capacitance 5 pF Per pin DIGITAL OUTPUTS (SDO) 3 Output Low Voltage, V 0.4 V DV = 5 V ± 10%, sinking 200 µA OL CC Output High Voltage, V DV − 1 V DV = 5 V ± 10%, sourcing 200 µA OH CC CC Output Low Voltage, V 0.4 V DV = 2.7 V to 3.6 V, sinking 200 µA OL CC Output High Voltage, V DV − 0.5 V DV = 2.7 V to 3.6 V, sourcing 200 µA OH CC CC High Impedance Leakage Current ±1 µA High Impedance Output 5 pF Capacitance POWER REQUIREMENTS AV 4.5 16.5 V DD AV −4.5 −16.5 V SS DV 2.7 5.5 V CC Power Supply Sensitivity3 ∆V /∆ΑV −65 dB OUT DD AI 3.25 mA/channel Outputs unloaded DD 2.4 mA/channel AV = 0 V, outputs unloaded SS AI 2.5 mA/channel Outputs unloaded SS DI 0.5 3 µA V = DV , V = GND CC IH CC IL Power Dissipation 190 mW ±16.5 V operation, outputs unloaded 79 mW +16.5 V operation, AV = 0 V, outputs unloaded SS Power-Down Currents AI 40 µA DD AI 40 µA SS DI 300 nA CC 1 For specified performance, the headroom requirement is 0.9 V. 2 INL is the relative accuracy. It is measured from Code 512, Code 128, and Code 32 for the AD5752R, AD5732R, and AD5722R, respectively. 3 Guaranteed by characterization; not production tested. Rev. F | Page 4 of 32

Data Sheet AD5722R/AD5732R/AD5752R AC PERFORMANCE CHARACTERISTICS AV = 4.5 V1 to 16.5 V; AV = −4.5 V to −16.5 V, or AV = 0 V; GND = 0 V; REFIN = 2.5 V external; DV = 2.7 V to 5.5 V; R = 2 kΩ; DD SS SS CC LOAD C = 200 pF; all specifications T to T unless otherwise noted. LOAD MIN MAX Table 3. B Version Parameter2 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 10 12 µs 20 V step to ±0.03% FSR 7.5 8.5 µs 10 V step to ±0.03% FSR 5 µs 512 LSB step settling (16-bit resolution) Slew Rate 3.5 V/µs Digital-to-Analog Glitch Energy 13 nV-sec Glitch Impulse Peak Amplitude 35 mV Digital Crosstalk 10 nV-sec DAC-to-DAC Crosstalk 10 nV-sec Digital Feedthrough 0.6 nV-sec Output Noise 0.1 Hz to 10 Hz Bandwidth 15 µV p-p 0x8000 DAC code 100 kHz Bandwidth 80 µV rms Output Noise Spectral Density 320 nV/√Hz Measured at 10 kHz, 0x8000 DAC code 1 For specified performance, the headroom requirement is 0.9 V. 2 Guaranteed by design and characterization; not production tested. Rev. F | Page 5 of 32

AD5722R/AD5732R/AD5752R Data Sheet TIMING CHARACTERISTICS AV = 4.5 V to 16.5 V; AV = −4.5 V to −16.5 V, or AV = 0 V; GND = 0 V; REFIN = 2.5 V external; DV = 2.7 V to 5.5 V; R = 2 kΩ; DD SS SS CC LOAD C = 200 pF; all specifications T to T , unless otherwise noted. LOAD MIN MAX Table 4. Parameter1, 2, 3 Limit at t , t Unit Description MIN MAX t 33 ns min SCLK cycle time 1 t 13 ns min SCLK high time 2 t 13 ns min SCLK low time 3 t4 13 ns min SYNC falling edge to SCLK falling edge setup time t5 13 ns min SCLK falling edge to SYNC rising edge t6 100 ns min Minimum SYNC high time (write mode) t 7 ns min Data setup time 7 t 2 ns min Data hold time 8 t9 20 ns min LDAC falling edge to SYNC falling edge t10 130 ns min SYNC rising edge to LDAC falling edge t11 20 ns min LDAC pulse width low t 10 µs typ DAC output settling time 12 t13 20 ns min CLR pulse width low t14 2.5 µs max CLR pulse activation time t154 13 ns min SYNC rising edge to SCLK rising edge t 4 40 ns max SCLK rising edge to SDO valid (C 5 = 15 pF) 16 L SDO t17 200 ns min Minimum SYNC high time (readback/daisy-chain mode) 1 Guaranteed by characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 Daisy-chain and readback mode. 5 CL SDO = capacitive load on SDO output. Rev. F | Page 6 of 32

Data Sheet AD5722R/AD5732R/AD5752R TIMING DIAGRAMS t1 SCLK 1 2 24 t6 t3 t2 t4 t5 SYNC t8 t7 SDIN DB23 DB0 t9 t10 t11 LDAC t12 VOUTx t12 VOUTx CLR t13 t14 VOUTx 06466-002 Figure 2. Serial Interface Timing Diagram t1 SCLK 24 48 t17 t3 t2 t5 t4 t15 SYNC t8 t7 SDIN D32B D0B D32B D0B INPUT WORD FOR DAC N INPUT WORD FOR DAC N – 1 t16 SDO DB23 DB0 UNDEFINED INPUT WORD FOR DAC N t10 t11 LDAC 06466-003 Figure 3. Daisy-Chain Timing Diagram Rev. F | Page 7 of 32

AD5722R/AD5732R/AD5752R Data Sheet SCLK 1 24 1 24 t17 SYNC SDIN DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ SDO DB23 DB0 DB23 DB0 UNDEFINED SELECCTLEOD CRKEEGDIS OTUETR DATA 06466-004 Figure 4. Readback Timing Diagram Rev. F | Page 8 of 32

Data Sheet AD5722R/AD5732R/AD5752R ABSOLUTE MAXIMUM RATINGS T = 25°C unless otherwise noted. Transient currents of up to A Stresses at or above those listed under Absolute Maximum 100 mA do not cause SCR latch-up. Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these Table 5. or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Operation beyond AV to GND −0.3 V to +17 V DD the maximum operating conditions for extended periods may AV to GND +0.3 V to −17 V SS affect product reliability. DV to GND −0.3 V to +7 V CC Digital Inputs to GND −0.3 V to DV + 0.3 V or to CC ESD CAUTION 7 V (whichever is less) Digital Outputs to GND −0.3 V to DV + 0.3 V or to CC 7 V (whichever is less) REFIN/REFOUT to GND −0.3 V to +5 V V A or V B to GND AV to AV OUT OUT SS DD DAC_GND to GND −0.3 V to +0.3 V SIG_GND to GND −0.3 V to +0.3 V Operating Temperature Range, T A Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature, T max 150°C J 24-Lead TSSOP Package θ Thermal Impedance 42°C/W JA θ Thermal Impedance 9°C/W JC Power Dissipation (T max − T )/θ J A JA Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 3.5 kV Rev. F | Page 9 of 32

AD5722R/AD5732R/AD5752R Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVSS 1 24 AVDD NC 2 23 VOUTB VOUTA 3 22 NC NC 4 21 SIG_GND BIN/2sCOMP 5 AD5722R/ 20 SIG_GND AD5732R/ NC 6 19 DAC_GND AD5752R SYNC 7 18 DAC_GND TOP VIEW SCLK 8 (Not to Scale) 17 REFIN/REFOUT SDIN 9 16 SDO LDAC 10 15 GND CLR 11 14 DVCC NC 12 13 NC NOTES 1. NC = NO CONNECT 2 . ITFTHO IERSR REMNEACHLOALNMYCM CEEODNN TDNHEEEDCR TTMHEADAL TT POTEH ARE F CEOOXRPPMPOAESNREC DPE LP.AANDE BE 06466-005 Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 AV Negative Analog Supply. Voltage ranges from −4.5 V to −16.5 V. This pin can be connected to 0 V if output SS ranges are unipolar. 2, 4, 6, 12, NC Do not connect to these pins. 13, 22 3 V A Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. OUT 5 BIN/2sCOMP Determines the DAC coding for a bipolar output range. This pin must be hardwired to either DVCC or GND. When hardwired to DV , input coding is offset binary. When hardwired to GND, input coding is twos CC complement. (For unipolar output ranges, coding is always straight binary.) 7 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC. 8 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 10 LDAC Load DAC, Logic Input. This is used to update the DAC registers and, consequently, the analog output. When this pin is tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected. 11 CLR Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user selectable). 14 DV Digital Supply. Voltage ranges from 2.7 V to 5.5 V. CC 15 GND Ground Reference. 16 SDO Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. 17 REFIN/REFOUT External Reference Voltage Input and Internal Reference Voltage Output. Reference input range is 2 V to 3 V. REFIN = 2.5 V for specified performance. REFOUT = 2.5 V ± 2 mV. 18, 19 DAC_GND Ground Reference for the Four Digital-to-Analog Converters. 20, 21 SIG_GND Ground Reference for the Four Output Amplifiers. 23 V B Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load. OUT 24 AV Positive Analog Supply. Voltage ranges from 4.5 V to 16.5 V. DD Exposed This exposed paddle must be connected to the potential of the AV pin, or alternatively, it can be left electrically SS Paddle unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance. Rev. F | Page 10 of 32

Data Sheet AD5722R/AD5732R/AD5752R TYPICAL PERFORMANCE CHARACTERISTICS 6 0.6 AVDD/AVSS = +12V/0V, RANGE = +10V AVDD/AVSS = ±12V, RANGE = ±10V 4 AVDD/AVSS = ±6.5V, RANGE = ±5V 0.4 AVDD/AVSS = +6.5V/0V, RANGE = +5V 2 0.2 B) B) R (LS 0 R (LS 0 O O R R NL ER –2 NL ER–0.2 I D –4 –0.4 –6 –0.6 AAVVDDDD//AAVVSSSS == +±1122VV,/ 0RVA, NRGAEN G=E ± 1=0 +V10V AVDD/AVSS = ±6.5V, RANGE = ±5V AVDD/AVSS = +6.5V/0V, RANGE = +5V –8 –0.8 0 10,000 20,000 30,C00O0DE40,000 50,000 60,000 06466-013 0 10,000 20,000 30,C00O0DE40,000 50,000 60,000 06466-016 Figure 6. AD5752R Integral Nonlinearity Error vs. Code Figure 9. AD5752R Differential Nonlinearity Error vs. Code 1.5 0.15 AVDD/AVSS = +12V/0V, RANGE = +10V AVDD/AVSS = ±12V, RANGE = ±10V 1.0 AAVVDDDD//AAVVSSSS == ±+66..55VV,/ 0RVA, NRGAEN G= E± 5=V +5V 0.10 0.5 0.05 B) B) S S R (L 0 R (L 0 O O R R ER–0.5 ER–0.05 L L N N I D –1.0 –0.10 –1.5 –0.15 AAVVDDDD//AAVVSSSS == +±1122VV,/ 0RVA, NRGAEN G=E ± 1=0 +V10V AVDD/AVSS = ±6.5V, RANGE = ±5V AVDD/AVSS = +6.5V/0V, RANGE = +5V –2.00 2000 4000 6000 C80O0D0E10,000 12,000 14,000 16,000 06466-014 –0.200 2000 4000 6000 C80O0D0E10,000 12,000 14,000 16,000 06466-017 Figure 7. AD5732R Integral Nonlinearity Error vs. Code Figure 10. AD5732R Differential Nonlinearity Error vs. Code 0.3 0.04 AVDD/AVSS = +12V/0V, RANGE = +10V AVDD/AVSS = +12V/0V, RANGE = +10V AVDD/AVSS = ±12V, RANGE = ±10V AVDD/AVSS = ±12V, RANGE = ±10V 0.2 AVDD/AVSS = ±6.5V, RANGE = ±5V 0.03 AVDD/AVSS = ±6.5V, RANGE = ±5V AVDD/AVSS = +6.5V/0V, RANGE = +5V AVDD/AVSS = +6.5V/0V, RANGE = +5V 0.02 0.1 B) B) 0.01 R (LS 0 R (LS 0 INL ERRO––00..21 DNL ERRO ––00..0021 –0.3 –0.03 –0.4 –0.04 –0.5 –0.05 0 500 1000 1500 C20O0D0E 2500 3000 3500 4000 06466-015 0 500 1000 1500 C20O0D0E 2500 3000 3500 4000 06466-018 Figure 8. AD5722R Integral Nonlinearity Error vs. Code Figure 11. AD5722R Differential Nonlinearity Error vs. Code Rev. F | Page 11 of 32

AD5722R/AD5732R/AD5752R Data Sheet 8 1.0 BIPOLAR 10V MIN 6 0.8 UBNIPIOPOLALARR 1 01V0 VM MAIXN UNIPOLAR 10V MAX 0.6 4 SB) 2 MMAAXX IINNLL ±±150VV SB) 0.4 L MIN INL ±10V L 0.2 R ( MIN INL ±5V R ( RO 0 MMAINX I NINLL + +1100VV RO 0 ER MAX INL +5V ER L –2 MIN INL +5V L –0.2 N N I D –0.4 –4 –0.6 –6 –0.8 –8–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06466-044 –1.011.5 12.0 12.5 13.0SUP13P.L5Y V14O.L0TA1G4E.5 (V1)5.0 15.5 16.0 16.5 06466-032 Figure 12. AD5752R Integral Nonlinearity Error vs. Temperature Figure 15. AD5752R Differential Nonlinearity Error vs. Supply Voltage 0.1 10 8 0 6 DNL ERROR (LSB)––––0000....4321 MMMMMMMMAAIIAIAINNNNXXXX DDDD DDDDNNNNNNNNLLLLLLLL ±±++ ±±++151515150V0V0V0VVVVV INL ERROR (LSB) ––42024 BUBUININPPIIOOPPOOLLAALLAARRRR 55 VV55 VVMM MMIANIAXNX –6 –0.5 –8 –0.6–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06466-045 –105.5 6.5 7.5 8.5 S9U.P5PL1Y0 .V5OL11T.A5GE12 (.V5)13.5 14.5 15.5 16.5 06466-035 Figure 13. AD5752R Differential Nonlinearity Error vs. Temperature Figure 16. AD5752R Integral Nonlinearity Error vs. Supply Voltage 10 1.0 BIPOLAR 5V MIN 8 0.8 UNIPOLAR 5V MIN BIPOLAR 5V MAX UNIPOLAR 5V MAX 6 0.6 4 0.4 B) B) LS 2 LS 0.2 ROR ( 0 BUBINIPPIOOPOLLAALARRR 11 001VV0 VMM MAINIXN ROR ( 0 L ER –2 UNIPOLAR 10V MAX L ER–0.2 N N I –4 D–0.4 –6 –0.6 –8 –0.8 –1011.5 12.0 12.5 13.0SUP13P.L5Y V14O.L0TA1G4E.5 (V1)5.0 15.5 16.0 16.5 06466-034 –1.05.5 6.5 7.5 8.5 S9U.P5PL1Y0 .V5OL11T.A5GE12 (.V5)13.5 14.5 15.5 16.5 06466-033 Figure 14. AD5752R Integral Nonlinearity Error vs. Supply Voltage Figure 17. AD5752R Differential Nonlinearity Error vs. Supply Voltage Rev. F | Page 12 of 32

Data Sheet AD5722R/AD5732R/AD5752R 0.02 0.8 0.6 0.01 mV) R ( 0.4 O ±5V RANGE 0 BIPOLAR 10V MIN RR 0.2 UNIPOLAR 10V MIN E BIPOLAR 10V MAX E %) UNIPOLAR 10V MAX AL 0 TUE ( –0.01 O-SC–0.2 ±10V RANGE R E –0.02 R Z–0.4 A L O–0.6 P –0.03 BI –0.8 –0.04 –1.0 11.5 12.0 12.5 13.0SUP13P.L5Y V14O.L0TA1G4E.5 (V1)5.0 15.5 16.0 16.5 06466-036 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06466-047 Figure 18. AD5752R Total Unadjusted Error vs. Supply Voltage Figure 21. Bipolar Zero-Scale Error vs. Temperature 0.04 0.06 ±5V 0.03 0.04 0.02 R) 0.01 BIPOLAR 5V MIN S0.02 %) 0 UBUNINPIIOPPOOLALLARAR R5 V55 VVM MMAIAXNX R (% F TUE ( –0.01 ERRO 0 ±10V N –0.02 AI–0.02 G +10V –0.03 –0.04 –0.04 –0.05 –0.06 5.5 6.5 7.5 8.5 S9U.P5PL1Y0 .V5OL11T.A5G1E2 (.V5)13.5 14.5 15.5 16.5 06466-037 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06466-048 Figure 19. AD5752R Total Unadjusted Error vs. Supply Voltage Figure 22. Gain Error vs. Temperature 4 1000 +10V 900 3 800 mV) 2 700 R ( 600 O CALE ERR 01 ±10V DI (µA)CC450000 DVCC = 5V S 300 O- ER –1 200 Z 100 –2 DVCC = 3V ±5V 0 –3–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06466-046 –1000 1 2 VLOG3IC (V) 4 5 6 06466-043 Figure 20. Zero-Scale Error vs. Temperature Figure 23. Digital Current vs. Logic Input Voltage Rev. F | Page 13 of 32

AD5722R/AD5732R/AD5752R Data Sheet 0.010 12 ±5V RANGE, CODE = 0xFFFF ±10V RANGE, CODE = 0xFFFF +10V RANGE, CODE = 0xFFFF 0.005 +5V RANGE, CODE = 0xFFFF 10 ELTA (V) 0 ±±51V0V R RAANNGGEE, ,C COODDEE = = 0 x00x0000000 E (V) 8 D G OLTAGE –0.005 T VOLTA 6 UT V –0.010 UTPU 4 P O T U O –0.015 2 –0.020 0 –25 –20 –15 –1O0UTP–U5T CU0RRENT5 (mA1)0 15 20 25 06466-040 –3 –1 1 3 TIME (5µs) 7 9 11 06466-024 Figure 24. Output Source and Sink Capability Figure 27. Full-Scale Settling Time, +10 V Range 15 6 10 5 V) V) E ( 5 E ( 4 G G A A T T L L O 0 O 3 V V T T U U P P UT –5 UT 2 O O –10 1 –15 0 –3 –1 1 3 TIME (5µs) 7 9 11 06466-022 –3 –1 1 3 TIME (5µs) 7 9 11 06466-025 Figure 25. Full-Scale Settling Time, ±10 V Range Figure 28. Full-Scale Settling Time, +5 V Range 7 0.020 ±10V RANGE, 0x7FF±F TO 0x8000 ±10V RANGE, 0x8000± TO 0x7FFF 5 0.015 ±±55VV RRAANNGGEE,, 00xx78F00F0F ±± TTOO 00xx78F0F0F0 +10V RANGE, 0x7FFF TO 0x8000 +10V RANGE, 0x8000 TO 0x7FFF V) 3 V) 0.010 +5V RANGE, 0x7FFF TO 0x8000 E ( E ( +5V RANGE, 0x8000 TO 0x7FFF G G TA 1 TA 0.005 L L O O V V T –1 T 0 U U P P T T U U O –3 O–0.005 –5 –0.010 –7 –0.015 –3 –1 1 3 TIME (5µs) 7 9 11 06466-023 –1 0 1 TIME2 (µs) 3 4 5 06466-039 Figure 26. Full-Scale Settling Time, ±5 V Range Figure 29. Digital-to-Analog Glitch Energy Rev. F | Page 14 of 32

Data Sheet AD5722R/AD5732R/AD5752R 1 2 CH1 5RRµAAVNNGGEE == ±+55VV RRAANNGGMEE ==5 s+±1100VV LINE 73.8V 06466-026 1 CH1 5V CH2 500mV M 200µs CH1 2.9V 06466-028 Figure 30. Peak-to-Peak Noise, 0.1 Hz to 10 Hz Bandwidth Figure 33. REFOUT Turn-On Transient 1 1 CH1 RR5AAµVNNGGEE == ±+55VV RRAANNGGEEM ==5 s±+1100VV LINE 73.8V 06466-027 CH1 100mV M 5s LINE 1.2V 06466-029 Figure 31. Peak-to-Peak Noise, 100 kHz Bandwidth Figure 34. REFOUT Output Noise (100 kHz Bandwidth) 0.10 AVDD/AVSS = ±16.5V AVDD = +16.5V, AVSS = 0V 0.08 0.06 V) GE ( 0.04 A T OL 0.02 1 V T U P 0 T U O –0.02 ––00..0064–50 –30 –10 10TIME 3(µ0s) 50 70 90 06466-041 CH1 10mV M 5s LINE 1.2V 06466-030 Figure 32. Output Glitch on Power-Up Figure 35. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth) Rev. F | Page 15 of 32

AD5722R/AD5732R/AD5752R Data Sheet 3.0 1.0 AVDD/AVSS = +12V/0V, RANGE = +10V 2.9 0.5 AAAVVVDDDDDD///AAAVVVSSSSSS === ±±+1662..55VVV, ,/ R0RVAA,N NRGGAEEN =G= E±±1 5=0V V+5V 2.8 V) 2.7 0 E ( VOLTAG 22..56 E (LSB)–0.5 UT 2.4 TU–1.0 O F E R 2.3 –1.5 2.2 –2.0 2.1 2.0–0.18 –0.13 –0.08LOA–0D. 0C3URRE0.N0T2 (mA0).07 0.12 0.17 06466-031 –2.50 500 1000 1500 C20O0D0E 2500 3000 3500 4000 06466-021 Figure 36. REFOUT Voltage vs. Load Current Figure 39. AD5722R Total Unadjusted Error vs. Code 15 40 AVDD/AVSS = +12V/0V, RANGE = +10V 10 AAVVDDDD//AAVVSSSS == ±±162.5VV, , RRAANNGGEE == ±±150VV 35 AVDD/AVSS = +6.5V/0V, RANGE = +5V 5 30 0 SB) –5 ON (%)25 UE (L –10 ULATI20 T –15 P O15 P –20 10 –25 5 –30 –350 1000 2000 30C00ODE 4000 5000 6000 06466-019 0 1.0 1.5 2.T0EM2P.5ER3A.T0UR3.E5 CO4.E0FF4I.C5IEN5.T0 (p5p.m5/°6C.)0 6.5 7.0 06466-049 Figure 37. AD5752R Total Unadjusted Error vs. Code Figure 40. Reference Output TC (−40°C to +85°C) 4 40 AVDD/AVSS = +12V/0V, RANGE = +10V AVDD/AVSS = ±12V, RANGE = ±10V 2 AAVVDDDD//AAVVSSSS == ±+66..55VV,/ 0RVA, NRGAEN G= E± 5=V +5V 35 30 0 %) E (LSB) –2 LATION (2250 U –4 U T P O15 P –6 10 –8 5 –100 2000 4000 6000 C80O0D0E10,000 12,000 14,000 16,000 06466-020 0 1.0 1.5TEM2P.E0RAT2U.5RE CO3.E0FFIC3I.E5NT (p4p.0m/°C4).5 5.0 06466-052 Figure 38. AD5732R Total Unadjusted Error vs. Code Figure 41. Reference Output TC (0°C to 85°C) Rev. F | Page 16 of 32

Data Sheet AD5722R/AD5732R/AD5752R 2.50120 2.50120 20 DEVICES SHOWN 20 DEVICES SHOWN V)2.50100 V)2.50100 E ( E ( G G A2.50080 A2.50080 T T L L O O V V T 2.50060 T 2.50060 U U P P T T U U O2.50040 O2.50040 E E C C N N E2.50020 E2.50020 R R E E F F E E R2.50000 R2.50000 2.49980–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06466-051 2.499800 10 20 3T0EMPE4R0ATUR5E0 (°C) 60 70 80 06466-050 Figure 42. Reference Output Voltage vs. Temperature (−40°C to+ 85°C) Figure 43. Reference Output Voltage vs. Temperature (0°C to 85°C) Rev. F | Page 17 of 32

AD5722R/AD5732R/AD5752R Data Sheet TERMINOLOGY Gain TC Relative Accuracy or Integral Nonlinearity (INL) Gain TC is a measure of the change in gain error with changes For the DAC, relative accuracy, or integral nonlinearity, is a in temperature. Gain TC is expressed in ppm FSR/°C. measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. A Total Unadjusted Error (TUE) typical INL vs. code plot can be seen in Figure 6. Total unadjusted error is a measure of the output error taking all the various errors into account, namely, INL error, offset Differential Nonlinearity (DNL) error, gain error, and output drift over supplies, temperature, Differential nonlinearity is the difference between the measured and time. TUE is expressed in % FSR. change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum Power-On Glitch Energy ensures monotonicity. Therefore, the AD5722R/AD5732R/ Power-on glitch energy is the impulse injected into the analog AD5752R DACs are guaranteed monotonic by design. A typical output when the AD5722R/AD5732R/AD5752R power on. It is DNL vs. code plot can be seen in Figure 9. normally specified as the area of the glitch in nV-sec (see Figure 32). Monotonicity Digital-to-Analog Glitch Impulse A DAC is monotonic if the output either increases or remains Digital-to-analog glitch impulse is the impulse injected into the constant for increasing digital input code. The AD5722R/ analog output when the input code in the DAC register changes AD5732R/AD5752R are monotonic over the full operating state but the output voltage remains constant. It is normally temperature range. specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major Bipolar Zero Error carry transition (0x7FFF to 0x8000). See Figure 29. Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded Glitch Impulse Peak Amplitude with 0x8000 (straight binary coding) or 0x0000 (twos complement Glitch impulse peak amplitude is the peak amplitude of the coding). A plot of bipolar zero error vs. temperature can be seen impulse injected into the analog output when the input code in in Figure 21. the DAC register changes state. It is specified as the amplitude of the glitch in mV and is measured when the digital input code Bipolar Zero Temperature Change (TC) is changed by 1 LSB at the major carry transition (0x7FFF to Bipolar zero TC is a measure of the change in the bipolar zero 0x8000). See Figure 29. error with a change in temperature. It is expressed in ppm FSR/°C. Digital Feedthrough Zero-Scale Error or Negative Full-Scale Error Digital feedthrough is a measure of the impulse injected into Zero-scale error is the error in the DAC output voltage when the analog output of the DAC from the digital inputs of the 0x0000 (straight binary coding) or 0x8000 (twos complement DAC and is measured when the DAC output is not updated. It coding) is loaded to the DAC register. Ideally, the output voltage is specified in nV-sec and measured with a full-scale code must be negative full-scale − 1 LSB. A plot of zero-scale error vs. change on the data bus. temperature can be seen in Figure 20. Power Supply Sensitivity Zero-Scale TC Power supply sensitivity indicates how the output of the DAC is Zero-scale TC is a measure of the change in zero-scale error with a affected by changes in the power supply voltage. change in temperature. Zero-scale TC is expressed in ppm FSR/°C. DC Crosstalk Output Voltage Settling Time DC crosstalk is the dc change in the output level of one DAC in Output voltage settling time is the amount of time required for response to a change in the output of another DAC. It is measured the output to settle to a specified level for a full-scale input change. with a full-scale output change on one DAC while monitoring A plot of full-scale settling time can be seen in Figure 25. another DAC. It is expressed in LSBs. Slew Rate Digital Crosstalk The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage output Digital crosstalk is a measure of the impulse injected into the DAC is usually limited by the slew rate of the amplifier used at analog output of one DAC from the digital inputs of another its output. Slew rate is measured from 10% to 90% of the output DAC and is measured when the DAC output is not updated. It signal and is given in V/µs. is specified in nV-sec and measured with a full-scale code change on the data bus. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation of the DAC transfer characteristic from the ideal slope and is expressed in % FSR. A plot of gain error vs. temperature can be seen in Figure 22. Rev. F | Page 18 of 32

Data Sheet AD5722R/AD5732R/AD5752R DAC-to-DAC Crosstalk Voltage Reference TC DAC-to-DAC crosstalk is the glitch impulse transferred to the Voltage reference TC is a measure of the change in the refer output of one DAC due to a digital code change and a subsequent ence output voltage with a change in temperature. This value output change of another DAC. This includes both digital and is expressed in ppm/°C. analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 1s to all 0s, and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-sec. Rev. F | Page 19 of 32

AD5722R/AD5732R/AD5752R Data Sheet THEORY OF OPERATION The AD5722R/AD5732R/AD5752R are dual, 12-/14-/16-bit, REFIN serial input, unipolar/bipolar, voltage output DACs. They R operate from unipolar supply voltages of +4.5 V to +16.5 V or bipolar supply voltages of ±4.5 V to ±16.5 V. In addition, the R devices have software-selectable output ranges of +5 V, +10 V, +10.8 V, ±5 V, ±10 V, and ±10.8 V. Data is written to the R TO OUTPUT AMPLIFIER AD5722R/AD5732R/AD5752R in a 24-bit word format via a 3-wire serial interface. The devices also offer an SDO pin to facilitate daisy chaining or readback. The AD5722R/AD5732R/AD5752R incorporate a power-on reset circuit to ensure that the DAC registers power up loaded R with 0x0000. When powered on, the outputs are clamped to 0 V vreiafe are lnocwe iamnpde rdeafenrceen pcea tbhu. fTfehres .d evices also feature on-chip R 06466-007 ARCHITECTURE Figure 45. Resistor String Structure The DAC architecture consists of a string DAC followed by an Output Amplifiers output amplifier. Figure 44 shows a block diagram of the DAC The output amplifiers are capable of generating both unipolar architecture. The reference input is buffered before being and bipolar output voltages. They are capable of driving a load applied to the DAC. of 2 kΩ in parallel with 4000 pF to GND. The source and sink REFIN capabilities of the output amplifiers can be seen in Figure 24. The slew rate is 4.5 V/µs with a full-scale settling time of 10 µs. REF (+) POWER-UP SEQUENCE RESISTOR DAC REGISTER STRING VOUTx Because the DAC output voltage is controlled by the voltage REF (–) CONFIGURABLE monitor and control block (see Figure 48), it is important to OUTPUT AMPLIFIER power the DV pin before applying any voltage to the AV CC DD RANGEG NCDOONUTTRPOULT 06466-006 aant dan A uVnSdS epfiinnse; do tshtaetrew. iTshe,e t ihdee Gal1 p aonwde rG-u2p t rsaenqsumeniscseio ins igna tthese are following order: GND, SIG_GND, DAC_GND, DV , AV , Figure 44. DAC Architecture Block Diagram CC DD AV , and then the digital inputs. The relative order of SS The resistor string structure is shown in Figure 45. It is a string powering AV and AV is not important, provided that they DD SS of resistors, each of value R. The code loaded to the DAC register are powered up after DV . CC determines the node on the string where the voltage is to be Reference Buffers tapped off and fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string The AD5722R/AD5732R/AD5752R can operate with either an to the amplifier. Because it is a string of resistors, it is guaranteed external or internal reference. The reference input has an input monotonic. range of 2 V to 3 V, with 2.5 V for specified performance. This input voltage is then buffered before it is applied to the DAC cores. SERIAL INTERFACE The AD5722R/AD5732R/AD5752R are controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz. It is compatible with SPI, QSPI™, MICROWIRE™, and DSP standards. Input Shift Register The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. The input register consists of a read/write bit, three register select bits, three DAC address bits, and 16 data bits. The timing diagram for this operation is shown in Figure 2. Rev. F | Page 20 of 32

Data Sheet AD5722R/AD5732R/AD5752R Standalone Operation Daisy-Chain Operation The serial interface works with both a continuous and noncon- For systems that contain several devices, the SDO pin can be tinuous serial clock. A continuous SCLK source can be used used to daisy-chain several devices together. Daisy-chain mode only if SYNC is held low for the correct number of clock cycles. can be useful in system diagnostics and in reducing the number In gated clock mode, a burst clock containing the exact number of serial interface lines. The first falling edge of SYNC starts the of clock cycles must be used, and SYNC must be taken high write cycle. SCLK is continuously applied to the input shift after the final clock to latch the data. The first falling edge of register when SYNC is low. If more than 24 clock pulses are SYNC starts the write cycle. Exactly 24 falling clock edges must applied, the data ripples out of the shift register and appears on be applied to SCLK before SYNC is brought high again. If the SDO line. This data is clocked out on the rising edge of SYNC is brought high before the 24th falling SCLK edge, the SCLK and is valid on the falling edge. By connecting the SDO of the first device to the SDIN input of the next device in the data written is invalid. If more than 24 falling SCLK edges are chain, a multidevice interface is constructed. Each device in the applied before SYNC is brought high, the input data is also system requires 24 clock pulses. Therefore, the total number of invalid. The input register addressed is updated on the rising clock cycles must equal 24 × N, where N is the total number of edge of SYNC. For another serial transfer to take place, SYNC AD5722R/AD5732R/AD5752R devices in the chain. When the must be brought low again. After the end of the serial data serial transfer to all devices is complete, SYNC is taken high. transfer, data is automatically transferred from the input shift This latches the input data in each device in the daisy chain and register to the addressed register. prevents any further data from being clocked into the input shift When the data has been transferred into the chosen register of register. The serial clock can be a continuous or gated clock. the addressed DAC, all DAC registers and outputs can be A continuous SCLK source can only be used if SYNC is held updated by taking LDAC low while SYNC is high. low for the correct number of clock cycles. In gated clock mode, AD5722R/ a burst clock containing the exact number of clock cycles must 68HC11* AD5732R/ AD5752R* be used, and SYNC must be taken high after the final clock to MOSI SDIN latch the data. SCK SCLK Readback Operation PC7 SYNC Readback mode is invoked by setting the R/W bit = 1 in the write PC6 LDAC MISO SDO operation to the serial input shift register. (If the SDO output is disabled via the SDO disable bit in the control register, it is auto- matically enabled for the duration of the read operation, after SDIN which it is disabled again). With R/W = 1, Bit A2 to Bit A0 in AD5722R/ AD5732R/ association with Bit REG2 to Bit REG0 select the register to be AD5752R* read. The remaining data bits in the write sequence are don’t SCLK care bits. During the next SPI write, the data appearing on the SYNC SDO output contains the data from the previously addressed LDAC register. For a read of a single register, the NOP command can SDO be used in clocking out the data from the selected register on SDO. The readback diagram in Figure 4 shows the readback sequence. For example, to read back the DAC register of SDIN AD5722R/ Channel A, the following sequence must be implemented: AD5732R/ AD5752R* 1. Write 0x800000 to the AD5722R/AD5732R/AD5752R SCLK input register. This configures the device for read mode SYNC with the DAC register of Channel A selected. Note that all LDAC the data bits, DB15 to DB0, are don’t care bits. SDO 2. Follow this with a second write, a NOP condition, 0x180000. *ADDITIONAL PINS OMITTED FOR CLARITY. 06466-008 Donu rthineg S tDhOis wlinriet.e , the data from the register is clocked out Figure 46. Daisy Chaining the AD5722R/AD5732R/AD5752R Rev. F | Page 21 of 32

AD5722R/AD5732R/AD5752R Data Sheet LOAD DAC (LDAC) CONFIGURING THE AD5722R/AD5732R/AD5752R After data has been transferred into the input register of the When the power supplies are applied to the AD5722R/AD5732R/ DACs, there are two ways to update the DAC registers and DAC AD5752R, the power-on reset circuit ensures that all registers outputs. Depending on the status of both SYNC and LDAC, one default to 0. This places all channels and the internal reference of two update modes is selected: individual DAC updating or in power-down mode. The DVCC must be brought high before simultaneous updating of all DACs. any of the interface lines are powered. If this is not done the first write to the device may be ignored. The first communication to OUTPUT AMPLIFIER the AD5722R/AD5732R/AD5752R should be to set the required REFIN 12-/1D4-A/1C6-BIT VOUTx output range on all channels (the default range is the 5 V unipolar range) by writing to the output range select register. The user should then write to the power control register to power on the DAC LDAC REGISTER required channels and the internal reference, if required. If an external reference source is being used, the internal reference must remain in power-down mode. To program an INPUT REGISTER output value on a channel, that channel must first be powered up; any writes to a channel while it is in power-down mode are SSSYCDNLICNK INTLEORGFIACCE SDO 06466-009 wigindoer epdo.w Tehr es uApDpl5y7 r2a2nRg/eA. DIt 5is7 3im2Rp/oArtDan5t7 5th2aRt othpee rpaotew weri tshu pap ly Figure 47. Simplified Diagram of Input Loading Circuitry for One DAC applied to the devices provides adequate headroom to support the chosen output ranges. Individual DAC Updating TRANSFER FUNCTION In this mode, LDAC is held low while data is being clocked into Table 8 to Table 16 show the relationships of the ideal input code the input shift register. The addressed DAC output is updated to output voltage for the AD5752R, AD5732R, and AD5722R, on the rising edge of SYNC. respectively, for all output voltage ranges. For unipolar output Simultaneous Updating of All DACs ranges, the data coding is straight binary. For bipolar output In this mode, LDAC is held high while data is being clocked ranges, the data coding is user selectable via the BIN/2sCOMP into the input shift register. All DAC outputs are asynchronously pin and can be either offset binary or twos complement. updated by taking LDAC low after SYNC has been taken high. For a unipolar output range, the output voltage expression is The update now occurs on the falling edge of LDAC. given by ASYNCHRONOUS CLEAR (CLR)  D  V =V ×Gain CLR is an active low clear that allows the outputs to be cleared OUT REFIN 2N  to either zero-scale code or midscale code. The clear code value For a bipolar output range, the output voltage expression is given by is user selectable via the CLR select bit of the control register  D  Gain×V (see the Control Register section). It is necessary to maintain V =V ×Gain − REFIN CLR low for a minimum amount of time to complete the operation OUT REFIN 2N 2 (see Figure 2). When the CLR signal is returned high, the output where: remains at the cleared value until a new value is programmed. The D is the decimal equivalent of the code loaded to the DAC. outputs cannot be updated with a new value while the CLR pin N is the bit resolution of the DAC. is low. A clear operation can also be performed via the clear VREFIN is the reference voltage applied at the REFIN pin. command in the control register. Gain is an internal gain whose value depends on the output range selected by the user, as shown in Table 7. Table 7. Output Range (V) Gain Value +5 2 +10 4 +10.8 4.32 ±5 4 ±10 8 ±10.8 8.64 Rev. F | Page 22 of 32

Data Sheet AD5722R/AD5732R/AD5752R Ideal Output Voltage to Input Code Relationship—AD5752R Table 8. Bipolar Output, Offset Binary Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 1111 1111 1111 1111 +2 × REFIN × (32,767/32,768) +4 × REFIN × (32,767/32,768) +4.32 × REFIN × (32,767/32,768) 1111 1111 1111 1110 +2 × REFIN × (32,766/32,768) +4 × REFIN × (32,766/32,768) +4.32 × REFIN × (32,766/32,768) … … … … … … … 1000 0000 0000 0001 +2 × REFIN × (1/32,768) +4 × REFIN × (1/32,768) +4.32 × REFIN × (1/32,768) 1000 0000 0000 0000 0 V 0 V 0 V 0111 1111 1111 1111 −2 × REFIN × (1/32,768) −4 × REFIN × (1/32,768) −4.32 × REFIN × (32,766/32,768) … … … … … … … 0000 0000 0000 0001 −2 × REFIN × (32,767/32,768) −4 × REFIN × (32,767/32,768) −4.32 × REFIN × (32,767/32,768) 0000 0000 0000 0000 −2 × REFIN × (32,768/32,768) −4 × REFIN × (32,768/32,768) −4.32 × REFIN × (32,768/32,768) Table 9. Bipolar Output, Twos Complement Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 0111 1111 1111 1111 +2 × REFIN × (32,767/32,768) +4 × REFIN × (32,767/32,768) +4.32 × REFIN × (32,767/32,768) 0111 1111 1111 1110 +2 × REFIN × (32,766/32,768) +4 × REFIN × (32,766/32,768) +4.32 × REFIN × (32,766/32,768) … … … … … … … 0000 0000 0000 0001 +2 × REFIN × (1/32,768) +4 × REFIN × (1/32,768) +4.32 × REFIN × (1/32,768) 0000 0000 0000 0000 0 V 0 V 0 V 1111 1111 1111 1111 −2 × REFIN × (1/32,768) −4 × REFIN × (1/32,768) −4.32 × REFIN × (1/32,768) … … … … … … … 1000 0000 0000 0001 −2 × REFIN × (32,767/32,768) −4 × REFIN × (32,767/32,768) −4.32 × REFIN × (32,767/32,768) 1000 0000 0000 0000 −2 × REFIN × (32,768/32,768) −4 × REFIN × (32,768/32,768) −4.32 × REFIN × (32,768/32,768) Table 10. Unipolar Output, Straight Binary Coding Digital Input Analog Output MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range 1111 1111 1111 1111 +2 × REFIN × (65,535/65,536) +4 × REFIN × (65,535/65,536) +4.32 × REFIN × (65,535/65,536) 1111 1111 1111 1110 +2 × REFIN × (65,534/65,536) +4 × REFIN × (65,534/65,536) +4.32 × REFIN × (65,534/65,536) … … … … … … … 1000 0000 0000 0001 +2 × REFIN × (32,769/65,536) +4 × REFIN × (32,769/65,536) +4.32 × REFIN × (32,769/65,536) 1000 0000 0000 0000 +2 × REFIN × (32,768/65,536) +4 × REFIN × (32,768/65,536) +4.32 × REFIN × (32,768/65,536) 0111 1111 1111 1111 +2 × REFIN × (32,767/65,536) +4 × REFIN × (32,767/65,536) +4.32 × REFIN × (32,767/65,536) … … … … … … … 0000 0000 0000 0001 +2 × REFIN × (1/65,536) +4 × REFIN × (1/65,536) +4.32 × REFIN × (1/65,536) 0000 0000 0000 0000 0 V 0 V 0 V Rev. F | Page 23 of 32

AD5722R/AD5732R/AD5752R Data Sheet Ideal Output Voltage to Input Code Relationship—AD5732R Table 11. Bipolar Output, Offset Binary Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 11 1111 1111 1111 +2 × REFIN × (8191/8192) +4 × REFIN × (8191/8192) +4.32 × REFIN × (8191/8192) 11 1111 1111 1110 +2 × REFIN × (8190/8192) +4 × REFIN × (8190/8192) +4.32 × REFIN × (8190/8192) … … … … … … … 10 0000 0000 0001 +2 × REFIN × (1/8192) +4 × REFIN × (1/8192) +4 × REFIN × (1/8192) 10 0000 0000 0000 0 V 0 V 0 V 01 1111 1111 1111 −2 × REFIN × (1/8192) −4 × REFIN × (1/8192) −4.32 × REFIN × (1/8192) … … … … … … … 00 0000 0000 0001 −2 × REFIN × (8191/8192) −4 × REFIN × (8191/8192) −4.32 × REFIN × (8191/8192) 00 0000 0000 0000 −2 × REFIN × (8192/8191) −4 × REFIN × (8192/8192) −4.32 × REFIN × (8192/8192) Table 12. Bipolar Output, Twos Complement Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 01 1111 1111 1111 +2 × REFIN × (8191/8192) +4 × REFIN × (8191/8192) +4.32 × REFIN × (8191/8192) 01 1111 1111 1110 +2 × REFIN × (8190/8192) +4 × REFIN × (8190/8192) +4.32 × REFIN × (8190/8192) … … … … … … … 00 0000 0000 0001 +2 × REFIN × (1/8192) +4 × REFIN × (1/8192) +4 × REFIN × (1/8192) 00 0000 0000 0000 0 V 0 V 0 V 11 1111 1111 1111 −2 × REFIN × (1/8192) −4 × REFIN × (1/8192) −4.32 × REFIN × (1/8192) … … … … … … … 10 0000 0000 0001 −2 × REFIN × (8191/8192) −4 × REFIN × (8191/8192) −4.32 × REFIN × (8191/8192) 10 0000 0000 0000 −2 × REFIN × (8192/8192) −4 × REFIN × (8192/8192) −4.32 × REFIN × (8192/8192) Table 13. Unipolar Output, Straight Binary Coding Digital Input Analog Output MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range 11 1111 1111 1111 +2 × REFIN × (16,383/16,384) +4 × REFIN × (16,383/16,384) +4.32 × REFIN × (16,383/16,384) 11 1111 1111 1110 +2 × REFIN × (16,382/16,384) +4 × REFIN × (16,382/16,384) +4.32 × REFIN × (16,382/16,384) … … … … … … … 10 0000 0000 0001 +2 × REFIN × (8193/16,384) +4 × REFIN × (8193/16,384) +4.32 × REFIN × (8193/16,384) 10 0000 0000 0000 +2 × REFIN × (8192/16,384) +4 × REFIN × (8192/16,384) +4.32 × REFIN × (8192/16,384) 01 1111 1111 1111 +2 × REFIN × (8191/16,384) +4 × REFIN × (8191/16,384) +4.32 × REFIN × (8191/16,384) … … … … … … … 00 0000 0000 0001 +2 × REFIN × (1/16,384) +4 × REFIN × (1/16,384) +4.32 × REFIN × (1/16,384) 00 0000 0000 0000 0 V 0 V 0 V Rev. F | Page 24 of 32

Data Sheet AD5722R/AD5732R/AD5752R Ideal Output Voltage to Input Code Relationship—AD5722R Table 14. Bipolar Output, Offset Binary Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 1111 1111 1111 +2 × REFIN × (2047/2048) +4 × REFIN × (2047/2048) +4.32 × REFIN × (2047/2048) 1111 1111 1110 +2 × REFIN × (2046/2048) +4 × REFIN × (2046/2048) +4.32 × REFIN × (2046/2048) … … … … … … 1000 0000 0001 +2 × REFIN × (1/2048) +4 × REFIN × (1/2048) +4 × REFIN × (1/2048) 1000 0000 0000 0 V 0 V 0 V 0111 1111 1111 −2 × REFIN × (1/2048) −4 × REFIN × (1/2048) −4.32 × REFIN × (1/2048) … … … … … … 0000 0000 0001 −2 × REFIN × (2047/2048) −4 × REFIN × (2047/2048) −4.32 × REFIN × (2047/2048) 0000 0000 0000 −2 × REFIN × (2048/2048) −4 × REFIN × (2048/2048) −4.32 × REFIN × (2048/2048) Table 15. Bipolar Output, Twos Complement Coding Digital Input Analog Output MSB LSB ±5 V Output Range ±10 V Output Range ±10.8 V Output Range 0111 1111 1111 +2 × REFIN × (2047/2048) +4 × REFIN × (2047/2048) +4.32 × REFIN × (2047/2048) 0111 1111 1110 +2 × REFIN × (2046/2048) +4 × REFIN × (2046/2048) +4.32 × REFIN × (2046/2048) … … … … … … 0000 0000 0001 +2 × REFIN × (1/2048) +4 × REFIN × (1/2048) +4 × REFIN × (1/2048) 0000 0000 0000 0 V 0 V 0 V 1111 1111 1111 −2 × REFIN × (1/2048) −4 × REFIN × (1/2048) −4.32 × REFIN × (1/2048) … … … … … … 1000 0000 0001 −2 × REFIN × (2047/2048) −4 × REFIN × (2047/2048) −4.32 × REFIN × (2047/2048) 1000 0000 0000 −2 × REFIN × (2048/2048) −4 × REFIN × (2048/2048) −4.32 × REFIN × (2048/2048) Table 16. Unipolar Output, Straight Binary Coding Digital Input Analog Output MSB LSB +5 V Output Range +10 V Output Range +10.8 V Output Range 1111 1111 1111 +2 × REFIN × (4095/4096) +4 × REFIN × (4095/4096) +4.32 × REFIN × (4095/4096) 1111 1111 1110 +2 × REFIN × (4094/4096) +4 × REFIN × (4094/4096) +4.32 × REFIN × (4094/4096) … … … … … … 1000 0000 0001 +2 × REFIN × (2049/4096) +4 × REFIN × (2049/4096) +4.32 × REFIN × (2049/4096) 1000 0000 0000 +2 × REFIN × (2048/4096) +4 × REFIN × (2048/4096) +4.32 × REFIN × (2048/4096) 0111 1111 1111 +2 × REFIN × (2047/4096) +4 × REFIN × (2047/4096) +4.32 × REFIN × (2047/4096) … … … … … … 0000 0000 0001 +2 × REFIN × (1/4096) +4 × REFIN × (1/4096) 4.32 × REFIN × (1/4096) 0000 0000 0000 0 V 0 V 0 V Rev. F | Page 25 of 32

AD5722R/AD5732R/AD5752R Data Sheet INPUT SHIFT REGISTER The input shift register is 24 bits wide and consists of a read/write bit (R/W); a reserved bit (ZERO), which must always be set to 0; three register select bits (REG2, REG1, REG0); three DAC address bits (A2, A1, A0); and 16 data bits (data). The register data is clocked in MSB first on the SDIN pin. Table 17 shows the register format, while Table 18 describes the function of each bit in the register. All registers are read/write registers. Table 17. AD5752R Input Register Format MSB LSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB0 R/W Zero REG2 REG1 REG0 A2 A1 A0 Data Table 18. Input Register Bit Functions Bit Mnemonic Description R/W Indicates a read from or a write to the addressed register. REG2, REG1, REG0 Used in association with the address bits to determine if a write operation is to the DAC register, output range select register, power control register, or control register. REG2 REG1 REG0 Function 0 0 0 DAC register 0 0 1 Output range select register 0 1 0 Power control register 0 1 1 Control register A2, A1, A0 These DAC address bits are used to decode the DAC channels. A2 A1 A0 Channel Address 0 0 0 DAC A 0 1 0 DAC B 1 0 0 Both DACs Data Data bits. Rev. F | Page 26 of 32

Data Sheet AD5722R/AD5732R/AD5752R DAC REGISTER The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel where the data transfer is to take place (see Table 18). The data bits are in positions DB15 to DB0 for the AD5752R (see Table 19), DB15 to DB2 for the AD5732R (see Table 20), and DB15 to DB4 for the AD5722R (see Table 21). Table 19. Programming the AD5752R DAC Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB0 0 0 0 0 0 DAC address 16-bit DAC data Table 20. Programming the AD5732R DAC Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB2 DB1 DB0 0 0 0 0 0 DAC address 14-bit DAC data X X Table 21. Programming the AD5722R DAC Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 DAC address 12-bit DAC data X X X X OUTPUT RANGE SELECT REGISTER The output range select register is addressed by setting the three REG bits to 001. The DAC address bits select the DAC channel, and the range bits (R2, R1, R0) select the required output range (see Table 22 and Table 23). Table 22. Programming the Required Output Range MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB3 DB2 DB1 DB0 0 0 0 0 1 DAC address Don’t care R2 R1 R0 Table 23. Output Range Options R2 R1 R0 Output Range (V) 0 0 0 +5 0 0 1 +10 0 1 0 +10.8 0 1 1 ±5 1 0 0 ±10 1 0 1 ±10.8 Rev. F | Page 27 of 32

AD5722R/AD5732R/AD5752R Data Sheet CONTROL REGISTER The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the control function selected. The control register options are shown in Table 24 and Table 25. Table 24. Programming the Control Register MSB LSB R/W Zero REG2 REG1 REG0 A2 A1 A0 DB15 to DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 0 0 0 NOP, data = don’t care 0 0 0 1 1 0 0 1 Don’t care TSD enable Clamp enable CLR select SDO disable 0 0 0 1 1 1 0 0 Clear, data = don’t care 0 0 0 1 1 1 0 1 Load, data = don’t care Table 25. Explanation of Control Register Options Option Description NOP No operation instruction used in readback operations. Clear Addressing this function sets the DAC registers to the clear code and updates the outputs. Load Addressing this function updates the DAC registers and, consequently, the DAC outputs. SDO Disable Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). CLR Select See Table 26 for a description of the CLR select operation. Clamp Enable Set by the user to enable the current limit clamp. The channel does not power down upon detection of an overcurrent; the current is clamped at 20 mA (default). Cleared by the user to disable the current-limit clamp. The channel powers down upon detection of an overcurrent. TSD Enable Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown feature (default). Table 26. CLR Select Options Output CLR Value CLR Select Setting Unipolar Output Range Bipolar Output Range 0 0 V 0 V 1 Midscale Negative full scale POWER CONTROL REGISTER The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power and thermal status of the AD5722R/AD5732R/AD5752R. The power control register options are shown in Table 27 and Table 28. Table 27. Programming the Power Control Register MSB LSB DB15 to R/W Zero REG2 REG1 REG0 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 0 0 0 X X OCB X OCA 0 TSD PUREF X PUB X PUA Table 28. Power Control Register Functions Option Description PU DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down A mode (default). After setting this bit to power DAC A, a power-up time of 10 µs is required. During this power-up time the DAC register should not be loaded to the DAC output (see the Load DAC (LDAC) section). If the clamp enable bit of the control register is cleared, DAC A powers down automatically on detection of an overcurrent, and PU is cleared to reflect this. A PU DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down B mode (default). After setting this bit to power DAC B, a power-up time of 10 µs is required. During this power-up time the DAC register should not be loaded to the DAC output (see the Load DAC (LDAC) section). If the clamp enable bit of the control register is cleared, DAC B powers down automatically on detection of an overcurrent, and PU is cleared to reflect this. B PU Reference power-up. When set, this bit places the internal reference in normal operating mode. When cleared, this bit places the REF internal reference in power-down mode (default). TSD Thermal shutdown alert. Read-only bit. In the event of an overtemperature situation, both DACs are powered down and this bit is set. OC DAC A overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC A, this bit is set. A OC DAC B overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC B, this bit is set. B Rev. F | Page 28 of 32

Data Sheet AD5722R/AD5732R/AD5752R DESIGN FEATURES Constant Current Clamp (Clamp Enable = 1) ANALOG OUTPUT CONTROL If a short circuit occurs in this configuration, the current is In many industrial process control applications, it is vital that clamped at 20 mA. This event is signaled to the user by the the output voltage be controlled during power-up. When the setting of the appropriate overcurrent (OC ) bit in the power supply voltages change during power-up, the V pins are X OUT control register. Upon removal of the short-circuit fault, the clamped to 0 V via a low impedance path (approximately 4 kΩ). OC bit is cleared. To prevent the output amplifiers from being shorted to 0 V X during this time, Transmission Gate G1 is also opened (see Automatic Channel Power-Down (Clamp Enable = 0) Figure 48). These conditions are maintained until the analog If a short circuit occurs in this configuration, the shorted power supplies have stabilized and a valid word is written to a channel powers down, and its output is clamped to ground via a DAC register. At this time, G2 opens and G1 closes. resistance of approximately 4 kΩ. At this time, the output of the VOLTAGE amplifier is also disconnected from the output pin. The short- MONITOR AND circuit event is signaled to the user via the overcurrent (OCX) CONTROL bits, and the power-up (PU ) bits indicate which channels have X G1 powered down. After the fault is rectified, the channels can be VOUTA powered up again by setting the PU bits. G2 X THERMAL SHUTDOWN 06466-010 The AD5722R/AD5732R/AD5752R incorporate a thermal Figure 48. Analog Output Control Circuitry shutdown feature that automatically shuts down the device if the core temperature exceeds approximately 150°C. The thermal POWER-DOWN MODE shutdown feature is disabled by default and can be enabled via Each DAC channel of the AD5722R/AD5732R/AD5752R can the TSD enable bit of the control register. In the event of a be individually powered down. By default, all channels are in thermal shutdown, the TSD bit of the power control register is set. power-down mode. The power status is controlled by the power INTERNAL REFERENCE control register (see Table 27 and Table 28 for details). When a channel is in power-down mode, its output pin is clamped to The on-chip voltage reference is powered down by default. If an ground through a resistance of approximately 4 kΩ, and the external voltage reference source is to be used, the internal output of the amplifier is disconnected from the output pin. reference must remain powered down at all times. If the internal reference is to be used as the reference source, it must OVERCURRENT PROTECTION be powered up via the PU bit of the power control register. REF Each DAC channel of the AD5722R/AD5732R/AD5752R The internal reference voltage is accessible at the REFIN/REFOUT incorporates individual overcurrent protection. The user has pin for use as a reference source for other devices within the two options for the configuration of the overcurrent protection: system. If the internal reference is to be used external to the constant current clamp or automatic channel power-down. The AD5722R/AD5732R/AD5752R, it must first be buffered. configuration of the overcurrent protection is selected via the clamp enable bit in the control register. Rev. F | Page 29 of 32

AD5722R/AD5732R/AD5752R Data Sheet APPLICATIONS INFORMATION +5 V/±5 V OPERATION VIN + Q2 AVDD C1 R3 When operating from a single +5 V supply or a dual ±5 V supply, an output range of +5 V or ±5 V is not achievable LOAD SWITCH because sufficient headroom for the output amplifier is not SECTION R2 available. In this situation, a reduced reference voltage can be Q1 used. For example, a 2 V reference voltage produces an output DVCC reoanf no2gu.0eg4 oh8f f V+or4 c faVunl ol broe p± ue4rs aeVtd,i oatnno .dp A rtoh sdet au1nc Vde a oorudf t hpveuaaltud rerao nvoogmeltsa igose fm +reo4fr.e0er9 et6hn acVne CSOENCTTRIOONL R1 06466-149 Figure 49. Load Switch Control Circuit and ±4.096 V. Refer to the plots in the Typical Performance Figure 50 shows an example of the analog supplies powering up Characteristics section for performance data at a range of before the digital supply. The circuit delays the AV to power-up voltage reference values. DD after the DV as shown by the AV delayed line. CC DD ALTERNATIVE POWER-UP SEQUENCE SUPPORT There can be cases where it is not possible to use the recommended power-up sequence, and in those instances, it is recommend to use AVDD an external circuit (see Figure 49). The circuit shown in Figure 49 ensures the digital block powers up AVSS prior to the analog block by using a load switch circuit. This circuit t (sec) targets applications that either AV or AV or both supplies power DD SS up before the DV . CC Consider the following design rules when choosing the component DVCC values for the AV delay circuit. DD • R1 ensures that the N-channel MOFSET (Q1) gate to asolsuor cper evvoelntatgs ef ailss zee truor nw honen o Df QV1CC. Hiso iwn eavne ro,p ife nD sVtaCtCe i;s R 1 AVDD (DELAYED) 06466-150 Figure 50. Delayed Power Supplies Sequence Example permanently connected to the source, R1 can be removed to conserve power. LAYOUT GUIDELINES • Select Q1 with a gate to source voltage (V ) threshold that GS In any circuit where accuracy is important, careful considera- is much lower than the minimum operating DV and a CC tion of the power supply and ground return layout helps to ensure drain to source voltage (V ) rating much lower than the DS the rated performance. The printed circuit board on which the maximum operating AV . DD AD5722R/AD5732R/AD5752R are mounted must be designed so • C1, R2, and R3 are the main components that dictate the that the analog and digital sections are separated and confined to delay from the DV enable to AV . Adjust the values CC DD certain areas of the board. If the AD5722R/AD5732R/AD5752R according to desired delay. Choose R2 and R3 values that are in a system where multiple devices require an AGND to DGND ensure P-channel MOSFET (Q2) turn on. connection, the connection must be made at one point only. The star ground point must be established as close as possible to  V  tDELAY(sec)=−C1(R3||R2)×ln1− GS V  the device.   EQ The AD5722R/AD5732R/AD5752R must have ample supply  R  bypassing of a 10 µF capacitor in parallel with a 0.1 µF capacitor Where V = AV  3  EQ DDR +R  on each supply located as close to the package as possible, ideally 3 2 right up against the device. The 10 µF capacitors are the tantalum • Q2 acts as a switch which allows the flow of current from bead type. The 0.1 µF capacitor must have low effective series the input voltage (V ) to the AV pin, thus choosing a IN DD resistance (ESR) and low effective series inductance (ESI), such MOSFET with very low turn on resistance between the as the common ceramic types, which provide a low impedance drain and source terminals (R ) is necessary to minimize DSON path to ground at high frequencies to handle transient currents the losses during operation. Take Other parameters into due to internal logic switching. consideration, such as maximum V rating, maximum DS drain to source current rating, V threshold voltage, and The power supply lines of the AD5722R/AD5732R/AD5752R GS maximum gate to source voltage rating, when choosing Q2. must use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Rev. F | Page 30 of 32

Data Sheet AD5722R/AD5732R/AD5752R Fast switching signals, such as clock signals, must be shielded MICROPROCESSOR INTERFACING with digital ground to avoid radiating noise to other devices of Microprocessor interfacing to the AD5722R/AD5732R/AD5752R the board, and they must never be run near the reference inputs. is via a serial bus that uses standard protocol compatible with A ground line routed between the SDIN and SCLK lines helps microcontrollers and DSP processors. The communications reduce crosstalk between these lines (this is not required on a channel is a 3-wire (minimum) interface consisting of a clock multilayer board that has a separate ground plane, but separating signal, a data signal, and a synchronization signal. Each AD5722R/ the lines does help). It is essential to minimize noise on the AD5732R/AD5752R requires a 24-bit data-word with data valid REFIN line because noise couples through to the DAC output. on the falling edge of SCLK. Avoid crossover of digital and analog signals. Traces on opposite For all interfaces, the DAC output update can be initiated sides of the board must run at right angles to each other. This automatically when all the data is clocked in, or it can be reduces the effects of feedthrough on the board. A microstrip performed under the control of LDAC. The contents of the technique is by far the best method, but it is not always possible registers can be read using the readback function. with a double-sided board. In this technique, the component side AD5722R/AD5732R/AD5752R to Blackfin® DSP Interface of the board is dedicated to a ground plane, and signal traces are placed on the solder side. Figure 52 shows how the AD5722R/AD5732R/AD5752R can be GALVANICALLY ISOLATED INTERFACE interfaced to Analog Devices Blackfin DSP. The Blackfin has an integrated SPI port that can be connected directly to the SPI pins In many process control applications, it is necessary to provide of the AD5722R/AD5732R/AD5752R and the programmable an isolation barrier between the controller and the unit being I/O pins that can be used to set the state of a digital input, such controlled to protect and isolate the controlling circuitry from as the LDAC pin. any hazardous common-mode voltages that may occur. The iCoupler® family of products from Analog Devices, Inc., provides SPISELx SYNC voltage isolation in excess of 2.5 kV. The serial loading structure SCK SCLK of the AD5722R/AD5732R/AD5752R makes them ideal for MOSI SDIN isolated interfaces because the number of interface lines is kept AD5722R/ to a minimum. Figure 51 shows a 4-channel isolated interface to ADSP-BF531 AD5732R/ AD5752R the AD5722R/AD5732R/AD5752R using an ADuM1400. For more information, visit www.analog.com/iCouplers. PF10 LDAC MSICERROIACLO CNLTORCOKL LOEURT VIA ENCOADEDuM140D0E*CODE VOA TO SCLK Figure 52. AD5722R/AD5732R/AD5752R-to-Blackfi06466-012n Interface SERIAL DATA OUT VIB ENCODE DECODE VOB TO SDIN SYNC OUT VIC ENCODE DECODE VOC TO SYNC CONTROL OUT VID ENCODE DECODE VOD TO LDAC *ADDITIONAL PINS OMITTED FOR CLARITY. 06466-011 Figure 51. Isolated Interface Rev. F | Page 31 of 32

Data Sheet AD5722R/AD5732R/AD5752R OUTLINE DIMENSIONS 7.90 5.02 7.80 5.00 7.70 4.95 24 13 4.50 EXPOSED 3.25 4.40 PAD 3.20 4.30 (Pins Up) 3.15 6.40 BSC 1 12 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF 1.05 THE EXPOSED PAD, REFER TO 1.20 MAX 1.00 THE PIN CONFIGURATION AND 8° FUNCTION DESCRIPTIONS 0.80 0° SECTION OF THIS DATA SHEET. 0.15 0.20 0.05 SPLEAATNIENG B0.S6C5 00..3109 0.09 00..7650 0.10 COPLANARITY 0.45 COMPLIANTTO JEDEC STANDARDS MO-153-ADT 061708-A Figure 53. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] (RE-24) Dimensions shown in millimeters ORDERING GUIDE Model1 Resolution Temperature Range INL Package Description Package Option AD5722RBREZ 12 −40°C to +85°C ±1 LSB 24-Lead TSSOP_EP RE-24 AD5722RBREZ-REEL7 12 −40°C to +85°C ±1 LSB 24-Lead TSSOP_EP RE-24 AD5732RBREZ 14 −40°C to +85°C ±4 LSB 24-Lead TSSOP_EP RE-24 AD5732RBREZ-REEL7 14 −40°C to +85°C ±4 LSB 24-Lead TSSOP_EP RE-24 AD5752RBREZ 16 −40°C to +85°C ±16 LSB 24-Lead TSSOP_EP RE-24 AD5752RBREZ-REEL7 16 −40°C to +85°C ±16 LSB 24-Lead TSSOP_EP RE-24 1 Z = RoHS Compliant Part. ©2008–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06466-0-2/17(F) Rev. F | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5752RBREZ-REEL7 AD5722RBREZ-REEL7 AD5752RBREZ AD5722RBREZ AD5732RBREZ-REEL7 AD5732RBREZ