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AD571–SPECIFICATIONS (TA = +25(cid:2)C, V+ = +5 V, V– = –12 V or –15 V, all voltages measured with respect to digital common, unless otherwise noted) AD571J AD571K AD571S Model Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION 10 10 10 Bits RELATIVE ACCURACY, T (cid:3)1 (cid:3)1/2 (cid:3)1 LSB A T to T (cid:3)1 (cid:3)1/2 (cid:3)1 LSB MIN MAX FULL-SCALE CALIBRATION ±2 ±2 ±2 LSB UNIPOLAR OFFSET (cid:3)1 (cid:3)1/2 (cid:3)1 LSB BIPOLAR OFFSET (cid:3)1 (cid:3)1/2 (cid:3)1 LSB DIFFERENTIAL NONLINEAIRTY, T 10 10 10 Bits A T to T 9 10 10 Bits MIN MAX TEMPERATURE RANGE 0 +70 0 +70 –55 +125 °C TEMPERATURE COEFFICIENTS Unipolar Offset (cid:3)2 (cid:3)1 (cid:3)2 LSB Bipolar Offset (cid:3)2 (cid:3)1 (cid:3)2 LSB Full-Scale Calibration2 (cid:3)4 (cid:3)2 (cid:3)8 LSB POWER SUPPLY REJECTION CMOS Positive Supply +13.5 V ≤ V + ≤ +16.5 V – – – (cid:3)1 – – – LSB TTL Positive Supply +4.5 V ≤ V + ≤ +5.5 V (cid:3)2 (cid:3)1 (cid:3)2 LSB Negative Supply –16.0 V ≤ V – ≤ –13.5 V (cid:3)2 (cid:3)1 (cid:3)2 LSB ANALOG INPUT IMPEDANCE 3.0 5.0 7.0 3.0 5.0 7.0 3.0 5.0 7.0 kΩ ANALOG INPUT RANGES Unipolar 0 +10 0 +10 0 +10 V Bipolar –5 +5 –5 +5 –5 +5 V OUTPUT CODING Unipolar Positive True Binary Positive True Binary Positive True Binary Bipolar Positive True Offset Binary Positive True Offset Binary Positive True Offset Binary LOGIC OUTPUT Output Sink Current (V = 0.4 V max, T to T ) 3.2 3.2 3.2 mA OUT MIN MAX Output Source Current1 (V = 2.4 V max, T to T ) 0.5 0.5 0.5 mA OUT MIN MAX Output Leakage (cid:3)40 (cid:3)40 (cid:3)40 μA LOGIC INPUT Input Current (cid:3)100 (cid:3)100 (cid:3)100 μA Logic “1” 2.0 2.0 2.0 V Logic “0” 0.8 0.8 0.8 V CONVERSION TIME, T to T 15 25 40 15 25 40 15 25 40 μs MIN MAX POWER SUPPLY V+ +4.5 +5.0 +7.0 +4.5 +5.0 +16.5 +4.5 +5.0 +7.0 V V– –12.0 –15 –16.5 –12.0 –15 –16.5 –12.0 –15 –16.5 V OPERATING CURRENT V+ 7 15 7 15 7 15 mA V– 9 15 9 15 9 15 mA PACKAGE OPTION2 Ceramic DIP (D-18) AD571JD AD571KD AD571SD NOTES 1The data output lines have active pull-ups to source 0.5 mA. The DATA READY line is open collector with a nominal 6 kΩ internal pull-up resistor. 2For details on grade and package offerings for SD-grade in accordance with MIL-STD-883, refer to Analog Devices’ Military Products databook or current /883B data sheet. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. –2– REV. B

AD571 ABSOLUTE MAXIMUM RATINGS 9 V+ to Digital Common AD571J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +7 V 8 AD571K . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to +16.5 V 7 V– to Digital Common . . . . . . . . . . . . . . . . . . . 0 V to –16.0 V Analog Common to Digital Common . . . . . . . . . . . . . . . ±1 V 6 Analog Input to Analog Common . . . . . . . . . . . . . . . . . ±15 V olts 5 V CDoignittarol lO Iuntppuuttss .( B. .l a.n .k . M. . o. d. e.) . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..00 VV ttoo VV++ V –TH 4 Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .800 mW 3 2 CIRCUIT DESCRIPTION The AD571 is a complete 10-bit A/D converter which requires 1 no external components to provide the complete successive- 5 6 7 8 9 10 11 12 13 14 15 16 approximation analog-to-digital conversion function. A block V+ – Volts diagram of the AD571 is shown on front page of this data sheet. Upon receipt of the CONVERT command, the internal 10-bit Figure 1.Logic Threshold (AD571K Only) current output DAC is sequenced by the I2L successive- approximation register (SAR) from its most-significant bit 12 (MSB) to least-significant bit (LSB) to provide an output cur- I–, CONVERT MODE 11 rent which accurately balances the input signal current through AIN = 0 to +10V the 5 kΩ input resistor. The comparator determines whether the 10 I–, BLANK MODE addition of each successively-weighted bit current causes the A 9 DthAe Csu mcu rirse lnets ss uthme tboit b ies lgerfet aotner, oifr m leosrse t,h tahne tbhiet iisn ptuurtn ceudr roefnf.t ;A iff- NT – m 8 I+, COVNIVNE =R 0TV MODE E 7 ter testing all the bits, the SAR contains a 10-bit binary code R R (w0h.0ic5h% a)c.curately represents the input signal to within ±1/2 LSB PLY CU 56 I+, COVINNV =E +R1T0 MVODE P Upon completion of the sequence, the SAR sends out a DATA U 4 S READY signal (active low), which also brings the three-state 3 I+, BLANK MODE buffers out of their “open” state, making the bit output lines be- 2 come active high or low, depending on the code in the SAR. 1 When the BLANK and CONVERT line is brought high, the 4.55 6 7 8 9 10 11 12 13 14 15 16 output buffers again go “open”, and the SAR is prepared for V+/V– – Volts another conversion cycle. Details of the timing are given in the Control and Timing section. Figure 2.Supply Currents vs. Supply Levels and The temperature compensated buried Zener reference provides Operating Modes the primary voltage reference to the DAC and guarantees excel- lent stability with both time and temperature. The bipolar offset CONNECTING THE AD571 FOR STANDARD OPERATION input controls a switch which allows the positive bipolar offset The AD571 contains all the active components required to per- current (exactly equal to the value of the MSB less 1/2 LSB) form a complete A/D conversion. For most situations, all that is to be injected into the summing (+) node of the comparator to necessary is connection of the power supply (+5 V and –15 V), the offset the DAC output. Thus the nominal 0 V to +10 V unipo- analog input, and the conversion start pulse. However, there are lar input range becomes a –5 V to +5 V range. The 5 kΩ thin- some features and special connections which should be consid- film input resistor is trimmed so that with a full-scale input ered for optimum performance. The functional pinout is shown signal, an input current will be generated which exactly matches in Figure 3. the DAC output with all bits on. (The input resistor is trimmed slightly low to facilitate user trimming, as discussed on the next page.) POWER SUPPLY SELECTION The AD571 is designed for optimum performance using a +5 V and –15 V supply, for which the AD571J and AD571S are specified. AD571K will also operate with up to a +15 V supply, which allows direct interface to CMOS logic. The input logic threshold is a function of V+ as shown in Figure 1. The supply current drawn by the device is a function of both V+ and the operating mode (BLANK or CONVERT). These supply cur- rents variations are shown in Figure 2. The supply currents change only moderately over temperature as shown in Figure 6. REV. B –3–

AD571 1000000000 and 4.99 volts at the input yields the 1111111111). BIT 9 1 18 BIT 10 (LSB) The bipolar offset control input is not directly TTL compatible, BIT 8 2 17 DATAREADY but a TTL interface for logic control can be constructed as BIT 7 3 16 DIGITAL COM shown in Figure 5. BIT 6 4 AD571 15 BIPOLAR OFF BIT 5 5 TOP VIEW 14 ANALOG COM +5V (Not to Scale) BIT 4 6 13 ANALOG IN USE ACTIVE B & C BIT 3 7 12 V– PULL-UP GATE BIT 2 8 11 BLK AND CONV 3x IN4148 AACINOM AD571 DR (MSB) BIT 1 9 10 V+ TTL GATE BIPOLAR OFFSET CONTROL 5V COM Figure 3.AD571 Pin Connections DATA 10 BITS DCOM FULL-SCALE CALIBRATION 30kΩ The 5 kΩ thin-film input resistor is laser trimmed to produce a 15V COM current which matches the full-scale current of the internal –15V DAC—plus about 0.3%—when a full-scale analog input voltage of 9.990 volts (10 volts—1 LSB) is applied at the input. The in- put resistor is trimmed in this way so that if a fine trimming po- Figure 5.Bipolar Offset Controlled by Logic Gate tentiometer is inserted in series with the input signal, the input Gate Output = 1: Unipolar 0 V–10 V Input Range current at the full-scale input voltage can be trimmed down to Gate Output = 0: Bipolar ±5 V Input Range match the DAC full-scale current as precisely as desired. How- ever, for many applications the nominal 9.99 volt full scale can COMMON-MODE RANGE be achieved to sufficient accuracy by simply inserting a 15 Ω re- The AD571 provides separate analog and digital common con- sistor in series with the analog input to Pin 13. Typical full-scale nections. The circuit will operate properly with as much as calibration error will then be about ±2 LSB or ±0.2%. If a more ±200 mV of common-mode range between the two commons. precise calibration is desired, a 50 Ω trimmer should be used in- This permits more flexible control of system common bussing stead. Set the analog input at 9.990 volts, and set the trimmer and digital and analog returns. so that the output code is just at the transition between In normal operation the analog common terminal may generate 1111111110 and 1111111111. Each LSB will then have a weight transient currents of up to 2 mA during a conversion. In addi- of 9.766 mV. If a nominal full scale of 10.24 volts is desired tion, a static current of about 2 mA will flow into analog com- (which makes the LSB have a value of exactly 10.00 mV), a mon in the unipolar mode after a conversion is complete. An 100 Ω resistor in series with a 100 Ω trimmer (or a 200 Ω trim- additional 1 mA will flow in during a blank interval with zero mer with good resolution) should be used. Of course, larger analog input. The analog common current will be modulated by full-scale ranges can be arranged by using a larger input resistor, the variations in input signal. but linearity and full-scale temperature coefficient may be com- The absolute maximum voltage rating between the two com- promised if the external resistor becomes a sizable percentage mons is ±1 volt. We recommend that a parallel pair of back-to- of 5 kΩ. back protection diodes can be connected between the commons if they are not connected locally. BIT 9 1 18 BIT 10 (LSB) BIT 8 2 17 DATA READY C = CONVERT MODE B = BLANK MODE BIT 7 3 16 DIGITAL COM 11 (SHORT TO COM FOR I –15V,C BIT 6 4 AD571 15 BIPOLAR CONTROLUNIPOLAR, OPEN FOR BIPOLAR) 10 I +15V,C BIT 5 5 (NToOt Pto V SIEcaWle) 14 ANALOG COM (DTIOGLITEARLA CTOESM )200mV TO 9 I –15V,B BBBIIITTT 324 678 111321 –B1L5KV AND CROINNV 15(S50EΩΩE FV TIAXEREXAIDATN )BOALRLEOG IN NTS – mA 78 E (MSB) BIT 1 9 10 +5V RR 6 U C 5 LY I +15V,B Figure 4.Standard AD571 Connections UPP 4 I +5V,C S 3 BIPOLAR OPERATION 2 I +5V,B The standard unipolar 0 V to +10 V range is obtained by short- 1.5 1 ing the bipolar offset control pin to digital common. If the pin is –50 –25 0 25 50 70 100 125 TEMPERATURE – °C left open, the bipolar offset current will be switched into the comparator summing node, giving a –5 V to +5 V range with an offset binary output code. (–5.00 volts in will give a 10-bit code Figure 6.AD571 Power Supply Current vs. Temperature of 0000000000; an input of 0.00 volts results in an output code of –4– REV. B

AD571 ZERO OFFSET NOTE: During a conversion transient currents from the analog The apparent zero point of the AD571 can be adjusted by common terminal will disturb the offset voltage. Capacitive de- inserting an offset voltage between the analog common of the coupling should not be used around the offset network. These device and the actual signal return or signal common. Figure 7 transients will settle as appropriate during a conversion. Capaci- illustrates two methods of providing this offset. Figure 7a shows tive decoupling will “pump up” and fail to settle resulting in how the converter zero may be offset by up to ±3 bits to correct conversion errors. Power supply decoupling which returns to the device initial offset and/or input signal offsets. As shown, the analog signal common should go to the signal input side of the circuit gives approximately symmetrical adjustment in unipolar resistive offset network. mode. In bipolar mode R2 should be omitted to obtain a sym- metrical range. OUTPUT CODE 0000000100 AIN INPUT 0000000011 SIGNAL AD571 0000000010 ACOM 0000000001 R1 R2 R3 10Ω 7.5kΩ 4.7kΩ 0000000000 0V10mV 30mV 50mV SIGNAL COMMON INPUT VOLTAGE R4 10kΩ NORMAL CHARACTERISTICS REFERRED TO ANALOG COMMON +15V –15V OUTPUT ZERO OFFSET ADJ ±3 BIT RANGE CODE 0000000100 0000000011 Figure 7a. 0000000010 0000000001 AIN 0000000000 INPUT R1 0V10mV 30mV 50mV SIGNAL 2.7Ω OR AD571 INPUT VOLTAGE 5Ω POT ACOM O2.F7FΩS IENT S CEHRAIERSA WCTITEHR AISNTAICLSO GW ICTOHMMON Figure 8.AD571 Transfer Curve—Unipolar Operation SIGNAL COMMON (Approximate Bit Weights Shown for Illustration, Nominal 1/2 BIT ZERO OFFSET Bit Weights (cid:2) 9.766 mV) BIPOLAR CONNECTION Figure 7b. To obtain the bipolar –5 V to +5 V range with an offset binary Figure 8 shows the nominal transfer curve near zero for an output code the bipolar offset control pin is left open. AD571 in unipolar mode. The code transitions are at the edges A –5.0 volt signal will give a 10-bit code of 0000000000; an in- of the nominal bit weights. In some applications it will be pref- put of 0.00 volts results in an output code of 1000000000; erable to offset the code transitions so that they fall between the +4.99 volts at the input yields 1111111111. The nominal trans- nominal bit weights, as shown in the offset characteristics. This fer curve is shown in Figure 9. offset can easily be accomplished as shown in Figure 7b. At bal- ance (after a conversion) approximately 2 mA flows into the analog common terminal. A 2.7 Ω resistor in series with this OUTPUT terminal will result in approximately the desired 1/2 bit offset of CODE the transfer characteristics. The nominal 2 mA analog common 10000 00010 current is not closely controlled in production. If high accuracy is required, a 5 Ω potentiometer (connected as a rheostat) can 10000 00001 be used as R1. Additional negative offset range may be obtained 10000 00000 by using larger values of R1. Of course, if the zero transition 01111 11111 point is changed, the full-scale transition point will also move. 01111 11110 Thus, if an offset of 1/2 LSB is introduced, full-scale trimming as described on previous page should be done with an analog in- put of 9.985 volts. 0 –30 –20 –10 0 +10 +20 +30 INPUT VOLTAGE – mV Figure 9.AD571 Transfer Curve—Bipolar Operation REV. B –5–

AD571 CONTROL AND TIMING OF THE AD571 BLANK and CONVERT line is driven low and at the end of There are several important timing and control features on the conversion, which is indicated by DATA READY going low, the AD571 which must be understood precisely to allow optimal conversion result will be present at the outputs. When this data interfacing to microprocessor or other types of control systems. has been read from the 10-bit bus, BLANK and CONVERT is All of these features are shown in the timing diagram in Figure restored to the blank mode to clear the data bus for other con- 10. verters. When several AD571s are multiplexed in sequence, a new conversion may be started in one AD571 while data is The normal standby situation is shown at the left end of the drawing. The BLANK and CONVERT (B & C) line is held being read from another. As long as the data is read and the first high, the output lines will be “open”, and the DATA READY AD571 is cleared within 15 μs after the start of conversion of the (DR) line will be high. This mode is the lowest power state of second AD571, no data overlap will occur. the device (typically 150 mW). When the (B & C ) line is brought low, the conversion cycle is initiated; but the DR and data lines do not change state. When the conversion cycle is complete, the DR line goes low, and within 500 ns, the data lines become active with the new data. About 1.5 μs after the B & C line is again brought high, the DR line will go high and the data lines will go open. When the B & C line is again brought low, a new conversion will begin. The minimum pulse width for the B & C line to blank previous Figure 11.Convert Pulse Mode data and start a new conversion is 2 μs. If the B & C line is brought high during a conversion, the conversion will stop, and the DR and data lines will not change. If a 2 μs or longer pulse is applied to the B & C line during a conversion, the converter will clear and start a new conversion cycle. Figure 12.Multiplex Mode SAMPLE-HOLD AMPLIFIER CONNECTION TO THE AD571 Many situations in high-speed acquisition systems or digitizing of rapidly changing signals require a sample-hold amplifier (SHA) in front of the A-D converter. The SHA can acquire and hold a signal faster than the converter can perform a conversion. A SHA can also be used to accurately define the exact point in Figure 10.AD571 Timing and Control Sequences time at which the signal is sampled. For the AD571, a SHA can also serve as a high input impedance buffer. CONTROL MODES WITH BLANK AND CONVERT Figure 13 shows the AD571 connected to the AD582 mono- The timing sequence of the AD571 discussed above allows the lithic SHA for high speed signal acquisition. In this configura- device to be easily operated in a variety of systems with differing tion, the AD582 will acquire a 10 volt signal in less than 10 μs control modes. The two most common control modes, the Con- with a droop rate less than 100 μV/ms. The control signals are vert Pulse Mode and the Multiplex Mode, are illustrated here. arranged so that when the control line goes low, the AD582 is put Convert Pulse Mode–In this mode, data is present at the output into the “hold” mode, and the AD571 will begin its conversion of the converter at all times except when conversion is taking cycle. (The AD582 settles to final value well in advance of the place. Figure 11 illustrates the timing of this mode. The BLANK first comparator decision inside the AD571). The DATA and CONVERT line is normally low and conversions are trig- READY line is fed back to the other side of the differential gered by a positive pulse. A typical application for this timing input control gate so that the AD582 cannot come out of the mode is shown in Figure 14, in which μP bus interfacing is “hold” mode during the conversion cycle. At the end of the con- easily accomplished with three-state buffers. version cycle, the DATA READY line goes low, automatically placing the AD582 back into the sample mode. This feature al- Multiplex Mode—In this mode the outputs are blanked except lows simple control of both the SHA and the A-D converter when the device is selected for conversion and readout; this tim- with a single line. Observe carefully the ground, supply, and by- ing is shown in Figure 12. A typical AD571 multiplexing appli- pass capacitor connections between the two devices. This will cation is shown in Figure 15. minimizes ground noise and interference during the conversion This operating mode allows multiple AD571 devices to drive cycle to give the most accurate measurements. common data lines. All BLANK and CONVERT lines are held high to keep the outputs blanked. A single AD571 is selected, its –6– REV. B

AD571 the new data and the control lines will return to the standby state. The 100 pF capacitor slows down the DR line enough to be used as a latch signal for data outputs. The new data will remain active until a new conversion is commanded. The self- pulsing nature of this circuit guarantees a sufficient convert pulse width. This new data can now be presented to the data bus by en- abling the three-state buffers when desired. A data word (8-bit or 2-bit) is loaded onto the bus when its decoded ad- dress goes low and the RD line goes low. This arrangement presents data to the bus “left-justified,” with the highest bits in the 8-bit word; a “right-justified” data arrangement can be set up by a simple re-wiring. Polling the converter to determine if conversion is complete can be done by addressing the gate which buffers the DR line, as shown. In this configuration, there is no need for additional buffer register storage: the data can be held indefinitely in the AD571, since the B & C line is continu- ally held low. Figure 13. Sample-Hold Interface to the AD571 BUS INTERFACING WITH A PERIPHERAL INTERFACE INTERFACING THE AD571 TO A MICROPROCESSOR CIRCUIT The AD571 can easily be arranged to be driven from standard An improved technique for interfacing to a μP bus involves the microprocessor control lines and to present data to any standard use of special peripheral interfacing circuits (or I/O devices), microprocessor bus (4-, 8-, 12- or 16-bit) with a minimum of such as the MC6821 Peripheral Interface Adapter (PIA). Shown additional control components. The configuration shown in in Figure 15 is a straightforward application of a PIA to multi- Figure 14 is designed to operate with an 8-bit bus and standard plex up to 8 AD571 circuits. The AD571 has 3-state outputs, 8080 control signals. Figure 14. Interfacing AD571 to an 8-Bit Bus Figure 15. Multiplexing 8 AD571s Using Single PIA for (8080 Control Structure) μP Interface. No Other Logic Required (6800 Control Structure) The input control circuitry shown is required to ensure that the hence the data bit outputs can be paralleled, provided that only AD571 receives a sufficiently long B & C input pulse. When the one converter at a time is permitted to be the active state. The converter is ready to start a new conversion, the B & C line is DATA READY output of the AD571 is an open collector with low, and DR is low. To command a conversion, the start ad- resistor pull-up, thus several DR lines can be wire-ored to dress decode line goes low, followed by WR. The B & C line allow indication of the status of the selected device. One of the will now go high, followed about 1.5 μs later by DR. This resets 8-bit ports of the PIA is combined with 2 bits from the other the external flip-flop and brings B & C back to low, which ini- port and programmed as a 10-bit input port. The remaining 6 tiates the conversion cycle. At the end of the conversion cycle, bits of the second port are programmed as outputs and along the DR line goes low, the data outputs will become active with REV. B –7–

AD571 w ith the 2 control bits (which act as outputs), are used to con- zero, blanking the previously active port at the same time. Sub- trol the 8 AD571s. When a control line is in the “1” or high sequently, this second device can be read by the microprocessor, state, the ADC will be automatically blanked. That is, its out- and so-forth. The status lines are wire-ored in 2 groups and p uts will be in the inactive open state. If a single control line is connected to the two remaining control pins. This allows a con- switched low, its ADC will convert and the outputs will auto- version status check to be made after a convert command, if matically go active when the conversion is complete. The result necessary. The ADCs are divided into two groups to minimize c an then be read from the two peripheral ports; when the next the loading effect of the internal pull-up resistors on the DATA conversion is desired, a different control line can be switched to READY buffers. OUTLINE DIMENSIONS 0.005 (0.13) MIN 0.098 (2.49) MAX 18 10 0.310 (7.87) PIN 1 0.220 (5.59) 1 9 0.320 (8.13) 0.290 (7.37) 0.200 (5.08) 0.960 (24.38) MAX 0.060 (1.52) MAX 0.015 (0.38) 0.150 (3.81) 0.200 (5.08) MIN 0.125 (3.18) 0.100 0.070 (1.78) SEATING 0.015 (0.38) 0.023 (0.58) (2.54) 0.030 (0.76) PLANE 0.008 (0.20) BSC 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 16. 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] (D-18) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model Temperature Range Package Description Package Option AD571JD 0°C to +70°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18 AD571SD –55°C to +125°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18 AD571SD/883B –55°C to +125°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18 5962-8680202VA –55°C to +125°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18 REVISION HISTORY 4/12—Rev. A to Rev. B Changes to Temperature Coefficients Full-Scale Calibration Parameter ........................................................................................... 2 Changes to V+ Operating Current Parameter .............................. 2 Updated Outline Dimensions .......................................................... 8 Added Ordering Guide and Revision History Section ................ 8 ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10739-0-4/12(B) –8– REV. B