a 16-Bit Monotonic Voltage Output D/A Converter AD569 FEATURES FUNCTIONAL BLOCK DIAGRAM Guaranteed 16-Bit Monotonicity Monolithic BiMOS II Construction (cid:54)0.01% Typical Nonlinearity 8- and 16-Bit Bus Compatibility 3 (cid:109)s Settling to 16 Bits Low Drift Low Power Low Noise APPLICATIONS Robotics Closed-Loop Positioning High-Resolution ADCs Microprocessor-Based Process Control MIL-STD-883 Compliant Versions Available PRODUCT DESCRIPTION The AD569 is a monolithic 16-bit digital-to-analog converter (DAC) manufactured in Analog Devices’ BiMOS II process. BiMOS II allows the fabrication of low power CMOS logic functions on the same chip as high precision bipolar linear cir- cuitry. The AD569 chip includes two resistor strings, selector switches decoding logic, buffer amplifiers, and double-buffered input latches. PRODUCT HIGHLIGHTS 1. Monotonicity to 16 bits is insured by the AD569’s voltage- The AD569’s voltage-segmented architecture insures 16-bit segmented architecture. monotonicity over time and temperature. Integral nonlinearity is maintained at – 0.01%, while differential nonlinearity is 2. The output range is ratiometric to an external reference or ac – 0.0004%. The on-chip, high-speed buffer amplifiers provide a signal. Gain error and gain drift of the AD569 are negligible. voltage output settling time of 3 m s to within – 0.001% for a 3. The AD569’s versatile data input structure allows loading full-scale step. from 8- and 16-bit buses. The reference input voltage which determines the output range 4. The on-chip output buffer amplifier can supply – 5 V into a can be either unipolar or bipolar. Nominal reference range is 1 kW load, and can drive capacitive loads of up to 1000 pF. – 5 V and separate reference force and sense connections are provided for high accuracy applications. The AD569 can oper- 5. Kelvin connections to the reference inputs preserve the gain ate with an ac reference in multiplying applications. and offset accuracy of the transfer function in the presence of wiring resistances and ground currents. Data may be loaded into the AD569’s input latches from 8- and 16-bit buses. The double-buffered structure simplifies 8-bit bus 6. The AD569 is available in versions compliant with MIL-STD- interfacing and allows multiple DACs to be loaded asynchro- 883. Refer to the Analog Devices Military Products Data- nously and updated simultaneously. Four TTL/LSTTL/5 V book or current AD569/883B data sheet for detailed CMOS-compatible signals control the latches: CS, LBE, HBE, specifications. and LDAC The AD569 is available in five grades: J and K versions are specified from 0(cid:176) C to +70(cid:176) C and are packaged in a 28-pin plas- tic DIP and 28-pin PLCC package; AD and BD versions are specified from –25(cid:176) C to +85(cid:176) C and are packaged in a 28-pin ceramic DIP. The SD version, also in a 28-pin ceramic DIP, is specified from –55(cid:176) C to +125(cid:176) C. REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703

AD569–SPECIFICATIONS (T = +25(cid:56)C, +V = +12 V, –V = –12 V, +V = +5 V, –V = –5 V, unless A S S REF REF otherwise noted.) Model AD569JN/JP/AD AD569KN/KP/BD AD569SD Parameter Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION 16 16 16 Bits LOGIC INPUTS V (Logic “l”) 2.0 5.5 2.0 5.5 2.0 5.5 Volts IH V (Logic “0”) 0 0.8 0 0.8 0 0.8 Volts IL I (V = 5.5 V) 10 10 10 m A IH IH I (V = 0 V) 10 10 10 m A IL IL TRANSFER FUNCTION CHARACTERISTICS Integral Nonlinearity – 0.02 (cid:54)0.04 – 0.01 (cid:54)0.024 (cid:54)0.04 % FSR1 T to T – 0.02 (cid:54)0.04 – 0.020 (cid:54)0.024 (cid:54)0.04 % FSR MIN MAX Differential Nonlinearity – 1/2 (cid:54)1 – 1/4 (cid:54)1/2 (cid:54)1 LSB T to T – 1/2 (cid:54)1 – 1/2 (cid:54)1 (cid:54)1 LSB MIN MAX Unipolar Offset2 (cid:54)500 (cid:54)350 (cid:54)500 m V T to T (cid:54)750 (cid:54)450 (cid:54)750 m V MIN MAX Bipolar Offset2 (cid:54)500 (cid:54)350 (cid:54)500 m V T to T (cid:54)750 (cid:54)450 (cid:54)750 m V MIN MAX Full Scale Error2 (cid:54)350 (cid:54)350 (cid:54)350 m V T to T (cid:54)750 (cid:54)750 (cid:54)750 m V MIN MAX Bipolar Zero2 (cid:54)0.04 (cid:54)0.024 (cid:54)0.04 % FSR T to T (cid:54)0.04 (cid:54)0.024 (cid:54)0.04 % FSR MIN MAX REFERENCE INPUT +V Range3 –5 +5 –5 +5 –5 +5 Volts REF –V Range –5 +5 –5 +5 –5 +5 Volts REF Resistance 15 20 25 15 20 25 15 20 25 kW 4 OUTPUT CHARACTERISTICS Voltage –5 +5 –5 +5 –5 +5 Volts Capacitive Load 1000 1000 1000 pF Resistive Load 1 1 1 kW Short Circuit Current 10 10 10 mA POWER SUPPLIES Voltage +V +10.8 +12 +13.2 +10.8 +12 +13.2 +10.8 +12 +13.2 Volts S –V –10.8 –12 –13.2 –10.8 –12 –13.2 –10.8 –12 –13.2 Volts S Current +I +9 +13 +9 +13 +9 +13 mA S –I –9 –13 –9 –13 –9 –13 mA S Power Supply Sensitivity5 +10.8 V £ +V £ +13.2 V – 0.5 (cid:54)2 – 0.5 (cid:54)2 – 0.5 (cid:54)2 ppm/% S –10.8 V ‡ –V ‡ –13.2 V – 1 (cid:54)3 – 1 (cid:54)3 – 1 (cid:54)3 ppm/% S TEMPERATURE RANGE Specified JN, KN, JP, KP 0 +70 0 +70 (cid:176) C AD, BD –25 +85 –25 +85 (cid:176) C SD –55 +125 (cid:176) C Storage JN, KN, JP, KP –65 +150 –65 +150 (cid:176) C AD, BD, SD –65 +150 –65 +150 –65 +150 (cid:176) C NOTES 1FSR stands for Full-Scale Range, and is 10 V for a –5 V to +5 V span. 2Refer to Definitions section. 3For operation with supplies other than – 12 V, refer to the Power Supply and Reference Voltage Range Section. 4Measured between +V Force and –V Force. REF REF 5Sensitivity of Full-Scale Error due to changes in +V and sensitivity of Offset to changes in –V . S S Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. –2– REV. A

AD569 AC PERFORMANCE CHARACTERISTICS These characteristics are included for Design Guidance Only and are not subject to test. +V = +12 V; –V = –12 V; +V = +5 V; –V = –5 V excepts where stated. S S REF REF Parameter Limit Units Test Conditions/Comments Output Voltage Settling 5 m s max No Load Applied (Time to – 0.001% FS 3 m s typ (DAC output measured from falling edge of LDAC.) For FS Step) 6 m s max V Load = 1 kW , C = 1000 pF. OUT LOAD 4 m s typ (DAC output measured from falling edge of LDAC. ) Digital-to-Analog Glitch 500 nV-sec typ Measured with V = 0 V. DAC registers alternatively loaded REF Impulse with input codes of 8000 and 0FFF (worst-case H H transition). Load = 1 kW . Multiplying Feedthrough –100 dB max +V = 1 V rms 10 kHz sine wave, REF –V = 0 V REF Output Noise Voltage 40 nV/(cid:207)Hz typ Measured between V and –V OUT REF Density (1 kHz-1 MHz) TIMING CHARACTERISTICS (+V = +12 V, –V = –12 V, V = 2.4 V, V = 0.4 V,T to T ) S S IH IL MIN MAX Parameter Limit Units Test Conditions/Comments Case A 150 ns Pulse on HBE, LBE, and LDAC T = 140 ns min, T = 10 ns min HS HH t 120 ns min CS Pulse Width WC t 60 ns min CS Data Setup Time SC t 20 ns min CS Data Hold Time HC Case B None t 70 ns min HBE, LBE Pulse Width WB t 80 ns min HBE, LBE Data Setup Time SB t 20 ns min HBE, LBE Data Hold Time HB t 120 ns min CS Setup Time SCS t 10 ns min CS Hold Time HCS t 120 ns min LDAC Pulse Width WD Case C None Figure 2a. AD569 Timing Diagram – Case B t 120 ns min HBE, LBE Pulse Width WB t 80 ns min HBE, LBE Data Setup Time SB t 20 ns min HBE, LBE Data Hold Time HB t 120 ns min CS Setup Time SCS t 10 ns min CS Hold Time HCS Figure 1. AD569 Timing Diagram – Case A Figure 2b. AD569 Timing Diagram – Case C REV. A –3–

AD569 ABSOLUTE MAXIMUM RATINGS* Power Dissipation (Any Package) . . . . . . . . . . . . . . .1000 mW (T = +25(cid:176) C unless otherwise noted) Operating Temperature Range A +V (Pin 1) to GND (Pin 18) . . . . . . . . . . . . . . +18 V, –0.3 V Commercial Plastic (JN, KN, JP, KP Versions) 0(cid:176) C to +70(cid:176) C S –V (Pin 28) to GND (Pin 18) . . . . . . . . . . . . . . –18 V, +0.3 V Industrial Ceramic (AD, BD Versions) . . . .–25(cid:176) C to +85(cid:176) C S +V (Pin 1) to –V (Pin 28) . . . . . . . . . . . . . . .+26.4 V, –0.3 V Extended Ceramic (SD Versions) . . . . . . .–55(cid:176) C to +125(cid:176) C S S Digital Inputs Storage Temperature . . . . . . . . . . . . . . . . . . .–65(cid:176) C to +150(cid:176) C (Pins 4-14, 19-27) to GND (Pin 18) . . . . . . . . . +V , –0.3 V Lead Temperature Range (Soldering, 10 secs) . . . . . . . +300(cid:176) C S +V Force (Pin 3) to +V Sense (Pin 2) . . . . . . . . – 16.5 V REF REF –V Force (Pin 15) to –V Sense (Pin 16) . . . . . . . – 16.5 V *Stresses above those listed under “Absolute Maximum Ratings” may cause REF REF V Force (Pins 3, 15) to GND (Pin 18) . . . . . . . . . . . . . – V permanent damage to the device. This is a stress rating only and functional REF S V Sense (Pins 2, 16) to GND (Pin 18) . . . . . . . . . . . . . – V operation of the device at these or any other conditions above those indicated in the REF S operational sections of this specification is not implied. Exposure to absolute V (Pin 17) . . . . . . . . . . . . . . . . . . Indefinite Short to GND OUT maximum rating conditions for extended periods may affect device reliability. . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to +V –V S, S ESD SENSITIVITY The AD569 features input protection circuitry consisting of large “distributed” diodes and polysilicon series resistors to dissipate both high-energy discharges (Human Body Model) and fast, low-energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD569 has been classified as a Category A device. WARNING! Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment and discharge without detection. Unused devices must be stored in conductive foam or shunts, and ESD SENSITIVE DEVICE the foam should be discharged to the destination socket before devices are removed. For further information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual. PIN DESIGNATIONS ORDERING GUIDE Integral Nonlinearity Differential Nonlinearity Temperature Package Model1 +25(cid:56)C T –T +25(cid:56)C T –T Range Option2 MIN MAX MIN MAX AD569JN – 0.04% – 0.04% – 1 LSB – 1 LSB 0(cid:176) C to +70(cid:176) C N-28 AD569JP – 0.04% – 0.04% – 1 LSB – 1 LSB 0(cid:176) C to +70(cid:176) C P-28A AD569KN – 0.024% – 0.024% – 1/2 LSB – 1 LSB 0(cid:176) C to +70(cid:176) C N-28 AD569KP – 0.024% – 0.024% – 1/2 LSB – 1 LSB 0(cid:176) C to +70(cid:176) C P-28A AD569AD – 0.04% – 0.04% – 1 LSB – 1 LSB –25(cid:176) C to +85(cid:176) C D-28 AD569BD – 0.024% – 0.024% – 1/2 LSB – 1 LSB –25(cid:176) C to +85(cid:176) C D-28 AD569SD – 0.04% – 0.04% – 1 LSB – 1 LSB –55(cid:176) C to +125(cid:176) C D-28 NOTES 1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current AD569/883B data sheet. 2D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier. –4– REV. A

AD569 FUNCTIONAL DESCRIPTION The AD569 consists of two resistor strings, each of which is di- vided into 256 equal segments (see Figure 3). The 8 MSBs of the digital input word select one of the 256 segments on the first string. The taps at the top and bottom of the selected segment are connected to the inputs of the two buffer amplifiers A1 and A2. These amplifiers exhibit extremely high CMRR and low bias current, and thus accurately preserve the voltages at the top and bottom of the segment. The buffered voltages from the seg- ment endpoints are applied across the second resistor string, where the 8LSBs of the digital input word select one of the 256 taps. Output amplifier A3 buffers this voltage and delivers it to the output. Buffer amplifiers A1 and A2 leap-frog up the first string to pre- serve monotonicity at the segment boundaries. For example, when increasing the digital code from 00FF to 0100 , (the first H H segment boundary), A1 remains connected to the same tap on the first resistor, while A2 jumps over it and is connected to the tap which becomes the top of the next segment. This design guarantees monotonicity even if the amplifiers have offset volt- ages. In fact, amplifier offset only contributes to integral linear- Figure 3. AD569 Block Diagram ity error. CAUTION It is generally considered good engineering practice to avoid negative rail. This condition may result in a large current surge inserting integrated circuits into powered-up sockets. This between the reference force and sense terminals. This current guideline is especially important with the AD569. An empty, surge may permanently damage the AD569. powered-up socket configures external buffer amplifiers in an open-loop mode, forcing their outputs to be at the positive or ANALOG CIRCUIT DETAILS Definitions MONOTONICITY: A DAC is monotonic if the output either LINEARITY ERROR: Analog Devices defines linearity error as increases or remains constant for increasing digital inputs. All the maximum deviation of the actual, adjusted DAC output versions of the AD569 are monotonic over their full operating from the ideal output (a straight line drawn from 0 to FS–1LSB) temperature range. for any bit combination. The AD569’s linearity is primarily lim- DIFFERENTIAL NONLINEARITY: DNL is the measure of ited by resistor uniformity in the first divider (upper byte of the change in the analog output, normalized to full scale, associ- 16-bit input). The plot in Figure 4 shows the AD569’s typical ated: with a 1 LSB change in the digital input code. Monotonic linearity error across the entire output range to be within behavior requires that the differential linearity error be less than – 0.01% of full scale. At 25(cid:176) C the maximum linearity error for 1 LSB over the temperature range of interest. For example, for a the AD569JN, AD and SD grades is specified to be – 0.04%, – 5 V output range, a change of 1 LSB in digital input code and – 0.024% for the KN and BD versions. should result in a 152 m V change in the analog output (1 LSB = 10 V/65,536). If the change is actually 38 m V, however, the dif- ferential linearity error would be –114 m V, or –3/4 LSB. By leap- frogging the buffer amplifier taps on the first divider, a typical AD569 keeps DNL within – 38 m V (– 1/4 LSB) around each of the 256 segment boundaries defined by the upper byte of the in- put word (see Figure 5). Within the second divider, DNL also typically remains less than – 38 m V as shown in Figure 6. Since the second divider is independent of absolute voltage, DNL is the same within the rest of the 256 segments. OFFSET ERROR: The difference between the actual analog output and the ideal output (–V ), with the inputs loaded with REF all zeros is called the offset error. For the AD569, Unipolar Off- set is specified with 0 V applied to –V and Bipolar Offset is REF specified with –5 V applied to –V . Either offset is trimmed by REF adjusting the voltage applied to the –V terminals. REF BIPOLAR ZERO ERROR: The deviation of the analog output from the ideal half-scale output of 0.0000 V when the inputs are Figure 4. Typical Linearity loaded with 8000H is called the Bipolar Zero Error. For the AD569, it is specified with – 5 V applied to the reference terminals. REV. A –5–

AD569 Glitches can be due to either time skews between the input bits or charge injection from the internal switches. Glitch Impulse for the AD569 is mainly due to charge injection, and is mea- sured with the reference connections tied to ground. It is speci- fied as the area of the glitch in nV-secs. TOTAL ERROR: The worst-case Total Error is the sum of the fixed full-scale and offset errors and the linearity error. POWER SUPPLY AND REFERENCE VOLTAGE RANGES The AD569 is specified for operation with – 12 volt power supplies. With – 10% power supply tolerances, the maximum reference voltage range is – 5 volts. Reference voltages up to – 6 volts can be used but linearity will degrade if the supplies approach their lower limits of – 10.8 volts (12 volts - 10%). Figure 5. Typical DNL at Segment Boundary Transitions If – 12 volt power supplies are unavailable in the system, several alternative schemes may be used to obtain the needed supply voltages. For example, in a system with – 15 V supplies, a single Zener diode can be used to reduce one of the supplies to 9 volts with the remaining one left at 15 volts. Figure 7a illustrates this scheme. A 1N753A or equivalent diode is an appropriate choice for the task. Asymmetrical power supplies can be used since the AD569’s output is referenced to –V only and thus floats REF relative to logic ground (GND, Pin 18). Assuming a worst-case – 1.5 volt tolerance on both supplies (10% of 15 volts), the maximum reference voltage ranges would be +6 and –2 volts for +V = +15 V and V = –9 V, and +2 to –8 volts for +V = 9 V S S S and –V = –15 V . S Alternately, two 3 V Zener diodes or voltage regulators can be used to drop each – 15 volt supply to – 12 volts, respectively. In Figure 7b, 1N746A diodes are a good choice for this task. a. Segment 1 A third method may be used if both – 15 volt and – 5 volt sup- plies are available. Figure 7c shows this approach. A combina- tion of +V = +15 V and –V = –5 V can support a reference S S range of 0 to 6 volts, while supplies of +V = +5 V and –V = S S –15 V can support a reference range of 0 to –8 volts. Again, 10% power supply tolerances are assumed. NOTE: Operation with +V = +5 V alters the input latches’ op- S erating conditions causing minimum write pulse widths to ex- tend to 1 m s or more. Control signals CS, HBE, LBE, and LDAC should, therefore, be tied low to render the latches trans- parent. No timing problems exist with operation at +V = 9 V and S –V = –15 V. However, 10% tolerances on these supplies gener- S ate a worst-case condition at –V = –16.5 V and +V = +7.5 V S S (assuming +V is derived from a +15 V supply). Under these S conditions, write pulse widths can stretch to 200 ns with similar b. Segment 256 degradation of data setup and hold times. However, – 0.75 V Figure 6. Typical DNL Within Segments tolerances (– 5%) yield minimal effects on digital timing with write pulse widths remaining below 100 ns. MULTIPLYING FEEDTHROUGH ERROR: This is the error due to capacitive feedthrough from the reference to the output Finally, Figure 7d illustrates the use of the combination of an with the input registers loaded with all zeroes. AD588 and AD569 in a system with – 15 volt supplies. As shown, the AD588 is connected to provide – 5 V to the refer- FULL-SCALE ERROR: The AD569’s voltage dividing archi- ence inputs of the AD569. It is doing double-duty by simulta- tecture gives rise to a fixed full-scale error which is independent neously regulating the supply voltages for the AD569 through of the reference voltage. This error is trimmed by adjusting the the use of the level shifting Zeners and transistors. This scheme voltage applied to the +V terminals. REF utilizes the capability of the outputs of the AD588 to source as DIGITAL-TO-ANALOG GLITCH IMPULSE: The charge in- well as sink current. Two other benefits are realized by using jected into the analog output when a new input is latched into this approach. The first is that the AD569 is no longer directly the DAC register gives rise to the Digital-to-Analog Glitch connected to the system power supplies. Output sensitivity to Impulse. variations in those supplies is, therefore, eliminated. The second –6– REV. A

AD569 benefit is that, should a Zener diode fail (a short circuit would ANALOG CIRCUIT CONNECTIONS be the most likely failure), the supply voltage decreases. This The AD569 is intended for use in applications where high reso- differs from the situation where the diode is used as a series lution and stability are critical. Designed as a multiplying D/A regulator. In that case, a failure would place the unregulated converter, the AD569 may be used with a fixed dc reference or supply voltage on the AD569 terminal. an ac reference. V may be any voltage or combination of REF voltages at +V and –V that remain within the bounds FORCE FORCE set for reference voltages as discussed in the power supply range section. Since the AD569 is a multiplying D/A converter, its output voltage, V , is proportional to the product of the digi- OUT tal input word and the voltage at the reference terminal. The transfer function is V = D·V where D is the fractional bi- OUT REF nary value of the digital word applied to the converter using offset-binary coding. Therefore, the output will range from –V for a digital input code of all zeros (0000 ) to +V for REF H REF an input code of all ones (FFFF ). H For applications where absolute accuracy is not critical, the a. Zener Regulates Negative Supply simple reference connection in Figure 8 can be used. Using only the reference force inputs, this configuration maintains linearity and 16-bit monotonicity, but introduces small, fixed offset and gain errors. These errors are due to the voltage drops across re- sistors R and R shown in Figure 9. With a 10 V reference A B voltage, the gain and offset errors will range from 80 mV to 100 mV. Resistors R and R were included in the first resistor A B string to avoid degraded linearity due to uneven current densi- ties at the string’s endpoints. Similarly, linearity would degrade if the reference voltage were connected across the reference sense terminals. Note that the resistance between the force and sense terminals cannot be measured with an ohmmeter; the lay- out of the thin-film resistor string adds approximately 4 kW of b. Diodes Regulate Both Supplies resistance (R ) at the sense tap. S c. Use of – 15 V and – 5 V Supplies Figure 8. Simple Reference Connection For those applications in which precision references and high accuracy are critical, buffer amplifiers are used at +V and REF –V as shown in Figure 10 to force the voltage across resistors REF R1 to R256. This insures that any errors induced by currents flowing through the resistances of the package pins, bond wires, aluminum interconnections, as well as R and R are mini- A B mized. Suitable amplifiers are the AD517, AD OP07, AD OP27, or the dual amplifier, the AD712. Errors will arise, however, as the buffer amplifiers’ bias currents flow through R (4 kW ). If S d. AD588 Produces References and Supply Voltages the bias currents produce such errors, resistance can be inserted at the noninverting terminal (R ) of the buffer amplifiers to BC Figure 7. Power Supply Options compensate for the errors. REV. A –7–

AD569 Figure 9. MSB Resistor Divider Figure 10. Reference Buffer Amplifier Connections Figures 11, 12, and 13 show reference configurations for various +5 V reference. A dual op amp, the AD712, buffers the refer- output ranges. As shown in Figure 11, the pin-programmable ence input terminals preserving the absolute accuracy of the AD588 can be connected to provides tracking – 5 V outputs AD569. The optional noise-reduction capacitor and gain with 1-3ppm/(cid:176) C temperature stability. Buffer amplifiers are in- adjust trimmer allow further elimination of errors. The low- cluded for direct connection to the AD569. The optional gain cost AD584 offers 2.5 V, 5 V, 7.5 V, and 10 V options and and balance adjust trimmers allow bipolar offset and full-scale can be connected for – 5 V tracking outputs as shown in Figure errors to be nulled. In Figure 12, the low-cost AD586 provides 13. Again, an AD712 is used to buffer the reference input terminals. Figure 11. Ultralow Drift – 5 V Tracking Reference Figure 12. Low-Cost – 5 V Reference –8– REV. A

AD569 Figure 13. Low-Cost – 5 V Tracking Reference MULTIPLYING PERFORMANCE the midpoints of both dividers. Figure 15 illustrates the Figure 14 illustrates the gain and phase characteristics of the AD569’s ability to resolve 16-bits (where 1 LSB is 96 dB below AD569 when operated in the multiplying mode. Full-power full scale) while keeping the noise floor below –130 dB with an bandwidth is shown in Figure 14a and the corresponding phase ac reference of 1 V rms at 200 Hz. shift is shown in Figure 14b. Performance is plotted for both a full-scale input of FFFF and an input of 8080 . An input rep- Multiplying feedthrough is due to capacitive coupling between H H resents worst-case conditions because it places the buffer taps at the reference inputs and the output. As shown in Figure 16, a. Bandwidth a. Time Domain b. Frequency Domain b. Phase Shift Figure 15. Multiplying Mode Performance (Input Code Figure 14. Full Power Multiplying Performance 0001) H REV. A –9–

AD569 under worst-case conditions (hex input code 0000), feedthrough DIGITAL CIRCUIT CONNECTIONS remains below –100 dB at ac reference frequencies up to 10 kHz. The AD569’s truth table appears in Table I. The High Byte En- able (HBE) and Low Byte Enable (LBE) inputs load the upper and lower bytes of the 16-bit input when Chip Select (CS) is valid (low). A similar strobe to Load DAC (LDAC) loads the 16-bit input into the DAC register and completes the DAC up- date. The DAC register can either be loaded with a separate write cycle or synchronously with either of the 8-bit registers in the first rank. A simultaneous update of several AD569s can be achieved by controlling their LDAC inputs with a single control signal. Table I. AD569 Truth Table Figure 16. Multiplying Feedthrough CS HBE LBE LDAC OPERATION BYPASSING AND GROUNDING RULES 1 X X X No Operation It is generally considered good engineering practice to use bypass X 1 1 1 No Operation capacitors on the device supply voltage pins and to insert small 0 0 1 1 Enable 8 MSBs of First Rank valued resistors in the supply lines to provide a measure of decou- 0 1 0 1 Enable 8 LSBs of First Rank pling between various circuits in a system. For the AD569, bypass 0 1 1 0 Enable 16-Bit DAC Register capacitors of at least 4.7 m F and series resistors of 10 W are recom- 0 0 0 0 All Latches Transparent mended. The supply voltage pins should be decoupled to Pin 18. NOISE All four control inputs latches are level-triggered and active low. In high-resolution systems, noise is often the limiting factor. A When the DAC register is loaded directly from a bus, the data at 16-bit DAC with a 10 volt span has an LSB size of 152 m V the digital inputs will be reflected in the output any time CS, (–96 dB). Therefore, the noise floor must remain below this LDAC, LBE and HBE are low. Should this not be the desired level in the frequency ranges of interest. The AD569’s noise case, bring LDAC (or HBE or LBE) high before changing the spectral density is shown in Figures 17 and 18. The lowband data. Alternately, use a second write cycle to transfer the data to noise spectrum in Figure 17 shows the 1/f corner frequency at the DAC register or delay the write strobe pulse until the appro- 1.2 kHz and Figure 18 shows the wideband noise to be below priate data is valid. Be sure to observe the appropriate data 40 nV/(cid:207)Hz. setup and hold times (see Timing Characteristics). Whenever possible, the write strobe signal should be applied to HBE and LBE with the AD569’s decoded address applied to CS. A minimum pulse width of 60 ns at HBE and LBE allows the AD569 to interface to the fastest microprocessors. Actually, data can be latched with narrower pulses, but the data setup and hold times must be lengthened. 16-Bit Microprocessor Interfaces Since 16-bit microprocessors supply the AD569’s complete 16- bit input in one write cycle, the DAC register is often unneces- sary. If so, it should be made transparent by grounding LDAC. The DAC’s decoded address should be applied to CS, with the write strobe applied to HBE and LBE as shown in the 68000 in- terface in Figure 19. Figure 17. Lowband Noise Spectrum Figure 19. AD569/68000 Interface Figure 18. Wideband Noise Spectrum –10– REV. A

AD569 plest method involves applying the two addresses directly to HBE and LBE and strobing the data using CS as shown in Fig- ure 20a. However, the minimum pulse width on CS is 70 ns with a minimum data setup time of 60 ns. If operation with a shorter pulse width is required, the base address should be ap- plied to CS with an address line gated with the strobe signal to supply the HBE and LBE inputs (see Figure 20b). However, since the write pulse sees a propagation delay, the data still must remain valid at least 20 ns after the rising edge of the delayed a. Simple Interface write pulse. OUTPUT SETTLING The AD569’s output buffer amplifier typically settles to within – 0.001% FS of its final value in 3 m s for a 10 V step. Figure 21 shows settling for negative and positive full-scale steps with no load applied. Capable of sourcing or sinking 5 mA, the output buffer can also drive loads of 1 kW and 1000 pF without loss of stability. Typical settling to 0.001% under these worst-case con- ditions is 4 m s, and is guaranteed to be a maximum of 6 m s. The plots of Figure 21 were generated using the settling test proce- dure developed specifically for the AD569. Subranging 16-Bit ADC b. Fast Interface The subranging ADC shown in Figure 22 completes a conver- sion in less than 20 m s, including the sample-hold amplifier’s Figure 20. 8-Bit Microprocessor Interface sample time. The sample-hold amplifier is allocated 5 m s to 8-Bit Microprocessor Interfaces settle to 16 bits. Since 8-bit microprocessors require two write cycles to provide the AD569’s 16-bit input, the DAC register must be utilized. It Before the first flash, the analog input signal is routed through is most often loaded as the second byte enters the first rank of the AD630 at a gain of +1. The lower AD7820 quantizes the latches. This synchronous load method, shown in Figure 20, re- signal to the 8-bit level within 1.4 m s, and the 8-bit result is quires LDAC to be tied to either LBE or HBE, depending upon routed to the AD569 via a digital latch which holds the 8-bit the byte loading sequence. In either case, the propagation delay word for the AD569 and the output logic. through the first rank gives rise to longer timing requirements as The AD569’s reference polarity is reversed so that a full-scale shown in Figure 2. If the DAC register (LDAC) is controlled output is –5 V and zero scale is 0 V, thereby subtracting an 8-bit separately using a third write cycle, the minimum write pulse on approximation from the original sampled signal. The residue LDAC is 70 ns, as shown in Figure 1. from the analog subtraction is then quantized by the second 8- Two basic methods exist for interfacing the AD569 to an 8-bit bit flash conversion to recover the 8 LSBs. Even though only the microprocessor’s address and control buses. In either case, at AD569’s upper 8 MSBs are used, the AD569’s accuracy de- least one address line is needed to differentiate between the up- fines the A/D converter’s overall accuracy. Any errors are di- per and lower bytes of the first rank (HBE and LBE). The sim- rectly reflected in the output. b. Turn-Off Settling a. Turn-On Settling Figure 21. Full-Scale Output Settling REV. A –11–

AD569 Preceding the second flash, the residue signal must be amplified second flash conversion yields a 9-bit word. This provides one by a factor of 256. The OP37 provides a gain of 25.6 and the extra bit of overlap for digital correction of any errors that oc- AD630 provides another gain of 10. In this case, the AD630 curred in the first flash. The correction bit is digitally added to acts as a gain element as well as a channel control switch. The the first flash before the entire 16-bit output is strobed into the output register. 7 8 8/ – 2 1 – a 9 4 9 C Figure 22. 16-Bit Subranging ADC OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Pin Ceramic DIP (D) 28-Pin Plastic DIP (N) A. 28-Pin Plastic Leaded Chip Carrier (P) S. U. N D I E T N RI P –12– REV. A