Quad 16-/14-/12-Bit nanoDAC+ with 2 ppm/°C Reference, I2C Interface Data Sheet AD5696R/AD5695R/AD5694R FEATURES FUNCTIONAL BLOCK DIAGRAM High relative accuracy (INL): ±2 LSB maximum at 16 bits Low drift 2.5 V reference: 2 ppm/°C typical VDD GND VREF Tiny package: 3 mm × 3 mm, 16-lead LFCSP AD5696R/AD5695R/AD5694R 2.5V Total unadjusted error (TUE): ±0.1% of FSR maximum REFERENCE Offset error: ±1.5 mV maximum VLOGIC REINGPISUTTER REGDIASCTER SDTARCIN AG VOUTA Gain error: ±0.1% of FSR maximum SCL BUFFER HUsigehr sderlievcet acabplea gbailiinty o: f2 10 omrA 2, (0G.5A IVN f proinm) supply rails SDA LOGIC REINGPISUTTER REGDIASCTER SDTARCIN BG VOUTB Reset to zero scale or midscale (RSTSEL pin) ACE BUFFER F 1.8 V logic compatibility A1 TER REINGPISUTTER REGDIASCTER SDTARCIN CG VOUTC Low glitch: 0.5 nV-sec IN BUFFER A0 400 kHz I2C-compatible serial interface REINGPISUTTER REGDIASCTER SDTARCIN DG VOUTD Low power: 3.3 mW at 3 V BUFFER 2.7 V to 5.5 V power supply POWER-ON GAIN = POWER- RESET ×1/×2 DOWN −40°C to +105°C temperature range LOGIC APPLICATIONS LDAC RESET RSTSEL GAIN 10486-001 Figure 1. Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5696R/AD5695R/AD5694R family are low power, quad, Table 1. Quad nanoDAC+ Devices 16-/14-/12-bit buffered voltage output DACs. The devices include Interface Reference 16-Bit 14-Bit 12-Bit a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a SPI Internal AD5686R AD5685R AD5684R gain select pin giving a full-scale output of 2.5 V (gain = 1) or External AD5686 AD5684 5 V (gain = 2). All devices operate from a single 2.7 V to 5.5 V I2C Internal AD5696R AD5695R AD5694R supply, are guaranteed monotonic by design, and exhibit less External AD5696 AD5694 than 0.1% FSR gain error and 1.5 mV offset error performance. The devices are available in a 3 mm × 3 mm LFCSP and a TSSOP package. PRODUCT HIGHLIGHTS The AD5696R/AD5695R/AD5694R also incorporate a power- 1. High Relative Accuracy (INL). on reset circuit and a RSTSEL pin that ensures that the DAC AD5696R (16-bit): ±2 LSB maximum. outputs power up to zero scale or midscale and remain there AD5695R (14-bit): ±1 LSB maximum. until a valid write takes place. Each part contains a per-channel AD5694R (12-bit): ±1 LSB maximum. power-down feature that reduces the current consumption of 2. Low Drift 2.5 V On-Chip Reference. the device to 4 µA at 3 V while in power-down mode. 2 ppm/°C typical temperature coefficient. The AD5696R/AD5695R/AD5694R use a versatile 2-wire serial 5 ppm/°C maximum temperature coefficient. interface that operates at clock rates up to 400 kHz, and includes 3. Two Package Options. a V pin intended for 1.8 V/3 V/5 V logic. 3 mm × 3 mm, 16-lead LFCSP. LOGIC 16-lead TSSOP. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5696R/AD5695R/AD5694R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Serial Operation ......................................................................... 21  Applications ....................................................................................... 1  Write Operation.......................................................................... 21  Functional Block Diagram .............................................................. 1  Read Operation........................................................................... 22  General Description ......................................................................... 1  Multiple DAC Readback Sequence .......................................... 22  Product Highlights ........................................................................... 1  Power-Down Operation ............................................................ 23  Revision History ............................................................................... 2  Load DAC (Hardware LDAC Pin) ........................................... 24  Specifications ..................................................................................... 3  LDAC Mask Register ................................................................. 24  AC Characteristics ........................................................................ 5  Hardware Reset (RESET) .......................................................... 25  Timing Characteristics ................................................................ 6  Reset Select Pin (RSTSEL) ........................................................ 25  Absolute Maximum Ratings ............................................................ 7  Internal Reference Setup ........................................................... 25  ESD Caution .................................................................................. 7  Solder Heat Reflow ..................................................................... 25  Pin Configuration and Function Descriptions ............................. 8  Long-Term Temperature Drift ................................................. 25  Typical Performance Characteristics ............................................. 9  Thermal Hysteresis .................................................................... 26  Terminology .................................................................................... 16  Applications Information .............................................................. 27  Theory of Operation ...................................................................... 18  Microprocessor Interfacing ....................................................... 27  Digital-to-Analog Converter .................................................... 18  AD5696R/AD5695R/AD5694R to ADSP-BF531 Interface .... 27  Transfer Function ....................................................................... 18  Layout Guidelines....................................................................... 27  DAC Architecture ....................................................................... 18  Galvanically Isolated Interface ................................................. 27  Serial Interface ............................................................................ 19  Outline Dimensions ....................................................................... 28  Write and Update Commands .................................................. 20  Ordering Guide .......................................................................... 29 REVISION HISTORY 4/2017—Rev. C to Rev. D 5/2014—Rev. B to Rev. C Changes to Features Section............................................................ 1 Deleted Long-Term Stability Drift Parameter, Table 1 ................. 4 Changes to Specifications Section .................................................. 3 Deleted Figure 8; Renumbered Sequentially ................................. 9 Changes to V Parameter, Table 1 ............................................ 4 Changes to Read Operation Section and Figure 51 ................... 22 LOGIC Changes to AC Characteristics Section and Output Noise Deleted Long-Term Temperature Drift Section ......................... 25 Spectral Density Parameter, Table 3 ............................................... 5 Changes to Timing Characteristics Section .................................. 6 6/2013—Rev. A to Rev. B Changes to Table 5 ............................................................................ 7 Changes to Pin GAIN and Pin RSTSEL Descriptions; Table 6 ... 8 Changes to V Pin Description and RESET Pin Description, LOGIC Table 6 ................................................................................................ 8 11/2012—Rev. 0 to Rev. A Changes to Figure 18 to Figure 22 ................................................ 11 Changes to Table 1 ............................................................................. 1 Changes to Figure 23 to Figure 26 and Figure 28 ...................... 12 Changes to Table 4 ............................................................................. 6 Changes to Figure 29, Figure 32, and Figure 34 ......................... 13 Changes to Figure 10......................................................................... 9 Changes to Figure 39 and Figure 40............................................. 14 Changes to Figure 33...................................................................... 13 Changes to Figure 50 ...................................................................... 21 Changes to Serial Interface Section .............................................. 19 Changes to Figure 51 ...................................................................... 22 Changes to Figure 52...................................................................... 22 Changes to Hardware Reset (RESET) Section ............................ 25 Added Long-Term Temperature Drift Section and Figure 55; 4/2012—Revision 0: Initial Version Renumbered Sequentially ................................................................... 25 Changes to Ordering Guide ................................................................ 29 Rev. D | Page 2 of 29

Data Sheet AD5696R/AD5695R/AD5694R SPECIFICATIONS V = 2.7 V to 5.5 V; 1.62 V ≤ V ≤ 5.5 V; all specifications T to T , unless otherwise noted. R = 2 kΩ; C = 200 pF. DD LOGIC MIN MAX L L Table 2. A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE2 AD5696R Resolution 16 16 Bits Relative Accuracy ±2 ±8 ±1 ±2 LSB Gain = 2 ±2 ±8 ±1 ±3 Gain = 1 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design AD5695R Resolution 14 14 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design AD5694R Resolution 12 12 Bits Relative Accuracy ±0.12 ±2 ±0.12 ±1 LSB Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design Zero-Code Error 0.4 4 0.4 1.5 mV All zeros loaded to DAC register Offset Error +0.1 ±4 +0.1 ±1.5 mV Full-Scale Error +0.01 ±0.2 +0.01 ±0.1 % of All ones loaded to DAC register FSR Gain Error ±0.02 ±0.2 ±0.02 ±0.1 % of FSR Total Unadjusted Error ±0.01 ±0.25 ±0.01 ±0.1 % of External reference; gain = 2; TSSOP FSR ±0.25 ±0.2 % of Internal reference; gain = 1; TSSOP FSR Offset Error Drift3 ±1 ±1 μV/°C Gain Temperature ±1 ±1 ppm Of FSR/°C Coefficient3 DC Power Supply Rejection 0.15 0.15 mV/V DAC code = midscale; VDD = 5 V ± 10% Ratio3 DC Crosstalk3 ±2 ±2 μV Due to single channel, full-scale output change ±3 ±3 μV/mA Due to load current change ±2 ±2 μV Due to powering down (per channel) OUTPUT CHARACTERISTICS3 Output Voltage Range 0 VREF 0 VREF V Gain = 1 0 2 × VREF 0 2 × VREF V Gain = 2, see Figure 30 Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 1 kΩ Resistive Load4 1 1 kΩ Load Regulation 80 80 μV/mA 5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT ≤ 30 mA 80 80 μV/mA 3 V ± 10%, DAC code = midscale; −20 mA ≤ IOUT ≤ 20 mA Short-Circuit Current5 40 40 mA Load Impedance at Rails6 25 25 Ω See Figure 30 Power-Up Time 2.5 2.5 μs Coming out of power-down mode; VDD = 5 V Rev. D | Page 3 of 29

AD5696R/AD5695R/AD5694R Data Sheet A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments REFERENCE OUTPUT Output Voltage7 2.4975 2.5025 2.4975 2.5025 V At ambient Reference TC8, 9 5 20 2 5 ppm/°C See the Terminology section Output Impedance3 0.04 0.04 Ω Output Voltage Noise3 12 12 µV p-p 0.1 Hz to 10 Hz Output Voltage Noise 240 240 nV/√Hz At ambient; f = 10 kHz, CL = 10 nF Density3 Load Regulation Sourcing3 20 20 µV/mA At ambient Load Regulation Sinking3 40 40 µV/mA At ambient Output Current Load ±5 ±5 mA VDD ≥ 3 V Capability3 Line Regulation3 100 100 μV/V At ambient Thermal Hysteresis3 125 125 ppm First cycle 25 25 ppm Additional cycles LOGIC INPUTS3 Input Current ±2 ±2 μA Per pin VINL, Input Low Voltage 0.3 × VLOGIC 0.3 × VLOGIC V VINH, Input High Voltage 0.7 × VLOGIC 0.7 × VLOGIC V Pin Capacitance 2 2 pF LOGIC OUTPUTS (SDA)3 Output Low Voltage, VOL 0.4 0.4 V ISINK = 3 mA Floating State Output 4 4 pF Capacitance POWER REQUIREMENTS VLOGIC 1.62 5.5 1.62 5.5 V ILOGIC 3 3 µA VDD 2.7 5.5 2.7 5.5 V Gain = 1 VDD VREF + 1.5 5.5 VREF + 1.5 5.5 V Gain = 2 IDD VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V Normal Mode10 0.59 0.7 0.59 0.7 mA Internal reference off 1.1 1.3 1.1 1.3 mA Internal reference on, at full scale All Power-Down Modes11 1 4 1 4 μA −40°C to +85°C 6 6 μA −40°C to +105°C 1 Temperature range: A and B grade: −40°C to +105°C. 2 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 = VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5696R), 64 to 16,320 (AD5695R), and 12 to 4080 (AD5694R). 3 Guaranteed by design and characterization; not production tested. 4 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to 30 mA up to a junction temperature of 110°C. 5 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded during current limit. Operation above the specified maximum operation junction temperature may impair device reliability. 6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 30). 7 Initial accuracy presolder reflow is ±750 μV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section. 8 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C. 9 Reference temperature coefficient calculated as per the box method. See the Terminology section for further information. 10 Interface inactive. All DACs active. DAC outputs unloaded. 11 All DACs powered down. Rev. D | Page 4 of 29

Data Sheet AD5696R/AD5695R/AD5694R AC CHARACTERISTICS V = 2.7 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; 1.62 V ≤ V ≤ 5.5 V; all specifications T to T , unless otherwise noted.1 DD L L LOGIC MIN MAX Table 3. Parameter2 Min Typ Max Unit Test Conditions/Comments3 Output Voltage Settling Time AD5696R 5 8 µs ¼ to ¾ scale settling to ±2 LSB AD5695R 5 8 µs ¼ to ¾ scale settling to ±2 LSB AD5694R 5 7 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 0.8 V/µs Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry Digital Feedthrough 0.13 nV-sec Digital Crosstalk 0.1 nV-sec Analog Crosstalk 0.2 nV-sec DAC-to-DAC Crosstalk 0.3 nV-sec Total Harmonic Distortion4 −80 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT Output Noise Spectral Density 300 nV/√Hz DAC code = midscale, 10 kHz; gain = 2, internal reference Output Noise 6 µV p-p 0.1 Hz to 10 Hz SNR 90 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT SFDR 83 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT SINAD 80 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical at 25°C. 4 Digitally generated sine wave at 1 kHz. Rev. D | Page 5 of 29

AD5696R/AD5695R/AD5694R Data Sheet TIMING CHARACTERISTICS V = 2.5 V to 5.5 V; 1.62 V ≤ V ≤ 5.5 V; all specifications T to T , unless otherwise noted. 1 DD LOGIC MIN MAX Table 4. Parameter2 Min Max Unit Conditions/Comments t 2.5 μs SCL cycle time 1 t 0.6 μs t , SCL high time 2 HIGH t 1.3 μs t , SCL low time 3 LOW t 0.6 μs t , start/repeated start condition hold time 4 HD,STA t 100 ns t , data setup time 5 SU,DAT t3 0 0.9 μs t , data hold time 6 HD,DAT t 0.6 μs t , setup time for repeated start 7 SU,STA t 0.6 μs t , stop condition setup time 8 SU,STO t 1.3 μs t , bus free time between a stop and a start condition 9 BUF t 0 300 ns t, rise time of SCL and SDA when receiving 10 R t 20 + 0.1C4 300 ns t, fall time of SDA and SCL when transmitting/ receiving 11 B F t 20 ns LDAC pulse width 12 t 400 ns SCL rising edge to LDAC rising edge 13 t 5 0 50 ns Pulse width of suppressed spike SP C4 400 pF Capacitive load for each bus line B 1 See Figure 2. 2 Guaranteed by design and characterization; not production tested. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s falling edge. 4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD. 5 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns. START REPEATED START STOP CONDITION CONDITION CONDITION SDA t 9 t t t 10 11 4 t 3 SCL t4 t2 t1 t t t t 6 5 7 8 t 12 LDAC1 t13 t 12 LDAC2 12NASOYSTNYENCSCHHRROONNOOUUS SL DLDAACC U UPDPDAATET EM MOODDE.E. 10486-002 Figure 2. 2-Wire Serial Interface Timing Diagram Rev. D | Page 6 of 29

Data Sheet AD5696R/AD5695R/AD5694R ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 5. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Operation beyond V to GND −0.3 V to +7 V LOGIC the maximum operating conditions for extended periods may V to GND −0.3 V to V + 0.3 V OUT DD affect product reliability. V to GND −0.3 V to V + 0.3 V REF DD Digital Input Voltage to GND1 −0.3 V to V + 0.3 V LOGIC ESD CAUTION SDA and SCL to GND −0.3 V to +7 V Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 125°C 16-Lead TSSOP, θJA Thermal 112.6°C/W Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP, θ Thermal 70°C/W JA Impedance, 0 Airflow (4-Layer Board) Reflow Soldering Peak 260°C Temperature, Pb Free (J-STD-020) 1 Excluding SDA and SCL. Rev. D | Page 7 of 29

AD5696R/AD5695R/AD5694R Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD5696R/AD5695R/AD5694R L BTUO FER ESTS TESE V V R R 6 5 4 3 1 1 1 1 VOUTA1 12A1 GND2 11SCL VREF 1 16 RSTSEL VOVUTDCD43 190AVL0OGIC VVOOUUTTBA 32 AADD55669965RR// 1154 RAE1SET 5 6 7 8 GND 4 AD5694R 13 SCL D A C N TOP VIEW VTUO DS ADL AIG VOVUTDCD 56 (Not to Scale) 1121 VAL0OGIC TOP VIEW (Not to Scale) VOUTD 7 10 GAIN N1.O TTHEES EXPOSED PAD MUST BE TIED TO GND. 10486-006 SDA 8 9 LDAC 10486-007 Figure 3. 16-Lead LFCSP Pin Configuration Figure 4. 16-Lead TSSOP Pin Configuration Table 6. Pin Function Descriptions Pin No. LFCSP TSSOP Mnemonic Description 1 3 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 2 4 GND Ground Reference Point for All Circuitry on the Part. 3 5 V Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be DD decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 4 6 V C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT 5 7 V D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT 6 8 SDA Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the 24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. 7 9 LDAC LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. This pin can also be tied permanently low. 8 10 GAIN Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to V . If this REF pin is tied to V , all four DACs output a span of 0 V to 2 × V . LOGIC REF 9 11 V Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. LOGIC 10 12 A0 Address Input. Sets the first LSB of the 7-bit slave address. 11 13 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit input register. 12 14 A1 Address Input. Sets the second LSB of the 7-bit slave address. 13 15 RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. If the pin is forced low at power-up, the POR circuit does not initialize correctly until the pin is released. 14 16 RSTSEL Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to V powers up all four DACs to midscale. LOGIC 15 1 V Reference Voltage. The AD5696R/AD5695R/AD5694R have a common reference pin. When using REF the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference output. 16 2 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND. Rev. D | Page 8 of 29

Data Sheet AD5696R/AD5695R/AD5694R TYPICAL PERFORMANCE CHARACTERISTICS 2.5020 1600 DDEEVVIICCEE 12 VDD = 5V TVAD D= =2 55°VC 2.5015 DEVICE 3 1400 DEVICE 4 2.5010 DEVICE 5 1200 V (V)REF 22..55000005 D (nV/ Hz) 1080000 S 2.4995 N 600 2.4990 400 2.4985 200 2.4980–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 10486-212 010 100 FR1EkQUENCY (1M0Hkz) 100k 1M 10486-111 Figure 5. Internal Reference Voltage vs. Temperature (Grade B) Figure 8. Internal Reference Noise Spectral Density vs. Frequency 2.5020 2.5015 DDDEEEVVVIIICCCEEE 123 TVAD D= =2 55°VC T DEVICE 4 2.5010 DEVICE 5 2.5005 V) (REF 2.5000 1 V 2.4995 2.4990 2.4985 VDD = 5V 2.4980–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 10486-109 CH1 2µV M1.0s A CH1 160mV 10486-112 Figure 6. Internal Reference Voltage vs. Temperature (Grade A) Figure 9. Internal Reference Noise, 0.1 Hz to 10 Hz 90 2.5000 VDD = 5V VDD = 5V 80 2.4999 TA = 25°C 70 2.4998 TS 60 NI R OF U 50 (V)REF2.4997 E 40 V2.4996 B M NU 30 2.4995 20 2.4994 10 00 0.5 1.0 TE1M.5PER2A.0TURE2. 5DRIF3T.0 (ppm3./5°C) 4.0 4.5 5.0 10486-250 2.499–30.005 –0.003 –0.00I1LOAD (A0).001 0.003 0.005 10486-113 Figure 7. Reference Output Temperature Drift Histogram Figure 10. Internal Reference Voltage vs. Load Current Rev. D | Page 9 of 29

AD5696R/AD5695R/AD5694R Data Sheet 2.5002 10 TA = 25°C D1 8 2.5000 6 4 2.4998 (V)REF2.4996 D3 L (LSB) 02 V N I –2 2.4994 –4 –6 2.4992 D2 –8 VDD = 5V TA = 25°C INTERNAL REFERENCE = 2.5V 2.4990 –10 2.5 3.0 3.5 V4.D0D (V) 4.5 5.0 5.5 10486-117 0 625 1250 18C75ODE 2500 3125 3750 4096 10486-120 Figure 11. Internal Reference Voltage vs. Supply Voltage Figure 14. AD5694R INL 10 1.0 8 0.8 6 0.6 4 0.4 INL (LSB) –202 DNL (LSB) –00..202 –4 –0.4 –6 –0.6 –8 TVAD D= =2 55°VC –0.8 TVAD D= =2 55°VC –100INTER1N0A0L00 REFE20R0E0N0CE =3 020.C50OV0DE40000 50000 60000 10486-118 –1.00INTER1N0A0L00 REFE20R0E0N0CE =3 020.C50OV0DE40000 50000 60000 10486-121 Figure 12. AD5696R INL Figure 15. AD5696R DNL 10 1.0 8 0.8 6 0.6 4 0.4 INL (LSB) –202 DNL (LSB) –00..202 –4 –0.4 –6 –0.6 –8 TVAD D= =2 55°VC –0.8 VTAD D= =2 55°VC –100INTERN25A0L0 REFE5R0E00NCE =7 25.C050OVDE10000 12500 1500016348 10486-119 –1.00INTERN25A0L0 REFE5R0E00NCE =7 25.C050OVDE10000 12500 1500016383 10486-122 Figure 13. AD5695R INL Figure 16. AD5695R DNL Rev. D | Page 10 of 29

Data Sheet AD5696R/AD5695R/AD5694R 1.0 10 0.8 8 0.6 6 0.4 4 B) 0.2 SB) 2 NL (LS 0 ROR (L 0 DINNLL D –0.2 R –2 E –0.4 –4 –0.6 –6 –0.8 VDD = 5V –8 TA = 25°C TA = 25°C INTERNAL REFERENCE = 2.5V INTERNAL REFERENCE = 2.5V –1.0 –10 0 625 1250 18C75ODE 2500 3125 3750 4096 10486-123 2.7 3.2 S3U.7PPLY VOL4.T2AGE (V)4.7 5.2 10486-126 Figure 17. AD5694R DNL Figure 20. INL Error and DNL Error vs. Supply Voltage 10 0.10 8 0.08 6 0.06 4 0.04 R) LSB) 2 INL of FS 0.02 FULL-SCALE ERROR R ( 0 % 0 ERRO –2 DNL RROR (–0.02 GAIN ERROR –4 E–0.04 –6 –0.06 –8 VDD = 5V –0.08 VDD = 5V INTERNAL REFERENCE = 2.5V INTERNAL REFERENCE = 2.5V –10 –0.10 –40 10 TEMPERATURE6 (0°C) 110 10486-124 –40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 10486-127 Figure 18. INL Error and DNL Error vs. Temperature Figure 21. Gain Error and Full-Scale Error vs. Temperature 10 1.4 VINDTDE =R N5VAL REFERENCE = 2.5V 8 6 1.2 4 1.0 R (LSB) 02 INL OR (mV) 0.8 O DNL R RR –2 ER 0.6 E –4 0.4 ZERO-CODE ERROR –6 0.2 –8 VDD = 5V OFFSET ERROR –100TA =0 2.55°C1.0 1.5 2.0VR2E.F5 (V)3.0 3.5 4.0 4.5 5.0 10486-125 0–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 10486-128 Figure 22. Zero-Code Error and Offset Error vs. Temperature Figure 19. INL Error and DNL Error vs. VREF Rev. D | Page 11 of 29

AD5696R/AD5695R/AD5694R Data Sheet 0.10 0.10 0.08 R) 0.08 S 0.06 of F 0.06 R) 0.04 R (% 0.04 FS 0.02 RO 0.02 of GAIN ERROR ER % 0 D 0 R ( TE RO–0.02 FULL-SCALE ERROR US–0.02 ER–0.04 ADJ–0.04 N U –0.06 AL –0.06 T –0.08 TA = 25°C TO–0.08 TA = 25°C INTERNAL REFERENCE = 2.5V INTERNAL REFERENCE = 2.5V –0.102.7 3.2 S3U.7PPLY VO4L.T2AGE (V)4.7 5.2 10486-129 –0.102.7 3.2 S3U.7PPLY VO4L.T2AGE (V)4.7 5.2 10486-132 Figure 23. Gain Error and Full-Scale Error vs. Supply Figure 26. TUE vs. Supply, Gain = 1 1.5 0 R)–0.01 1.0 S of F–0.02 % 0.5 R (–0.03 V) ZERO-CODE ERROR RO–0.04 m R R ( 0 D E–0.05 O E R T ER OFFSET ERROR US–0.06 –0.5 DJ A–0.07 N U –1.0 AL –0.08 ITNAT =E R25N°ACL REFERENCE = 2.5V TOT–0.09 IVTNADT D=E =R2 5N5°VACL REFERENCE = 2.5V –1.52.7 3.2 S3U.7PPLY VO4L.T2AGE (V)4.7 5.2 10486-130 –0.100 10000 20000 300C0O0DE 40000 50000 6000065535 10486-133 Figure 24. Zero-Code Error and Offset Error vs. Supply Figure 27. TUE vs. Code 0.10 R) 0.09 VINDTDE =R N5VAL REFERENCE = 2.5V 25 TVEADX DT= E =2R 55N°VCAL % of FS 0.08 20 REFERENCE = 2.5V R ( 0.07 O R 0.06 R 15 E S ED 0.05 HIT T US 0.04 10 J D A 0.03 N U AL 0.02 5 T O T 0.01 0–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 10486-131 0 540 560 580IDD (µA)600 620 640 10486-135 Figure 25. TUE vs. Temperature Figure 28. IDD Histogram with External Reference, 5 V Rev. D | Page 12 of 29

Data Sheet AD5696R/AD5695R/AD5694R 30 IVTNADT D=E =R2 5N5°VACL 5 VTAD D= =2 53°VC REFERENCE = 2.5V 4 GAIN = 1 25 EXTERNAL REFERENCE = 2.5V 3 0xFFFF 20 HITS 15 (V)UT 2 00xxC8000000 O V 1 0x4000 10 0x0000 0 5 –1 01000 1020 1040IDD F10U6L0LSCA1L08E0 (µA)1100 1120 1140 10486-136 –2–60 –40 –20 IOUT0 (mA) 20 40 60 10486-139 Figure 29. IDD Histogram with Internal Reference, VREFOUT = 2.5 V, Gain = 2 Figure 32. Source and Sink Capability at 3 V 1.0 1.4 0.8 0.6 1.2 FULL-SCALE 0.4 ∆V (V)OUT –00..202 SINKING 2.7V SINKING 5V URRENT (mA) 001...680 EXTERNAZLE RREOF ECROEDNECE, FULL-SCALE C –0.4 SOURCING 5V 0.4 –0.6 SOURCING 2.7V 0.2 –0.8 –1.00 5 1L0OAD CUR1R5ENT (mA2)0 25 30 10486-200 0–40 10 TEMPERATURE6 (0°C) 110 10486-140 Figure 30. Headroom/Footroom vs. Load Current Figure 33. Supply Current vs. Temperature 7 4.0 VDD = 5V DAC A 6 TA = 25°C 3.5 DAC B GAIN = 2 DAC C INTERNAL 0xFFFF DAC D 5 REFERENCE = 2.5V 3.0 4 0xC000 2.5 (V)OUT 23 0x8000 (V)OUT 2.0 V V 0x4000 1.5 1 0x0000 1.0 0 VDD = 5V –1 0.5 TA = 25°C INTERNAL REFERENCE = 2.5V ¼ TO ¾ SCALE ––20.06 –0.04 –0.0L2OAD CU0RRENT (A0).02 0.04 0.06 10486-138 00 20 40TIME (µs)80 160 320 10486-141 Figure 31. Source and Sink Capability at 5 V Figure 34. Settling Time, 5.25 V Rev. D | Page 13 of 29

AD5696R/AD5695R/AD5694R Data Sheet 0.06 6 0.003 CH A CH B CH B 0.05 CH C 5 CH C CH D CH D VDD 0.002 0.04 4 V) D ( V (V)OUT 00..0023 23 V (V)DD C-COUPLE 0.001 A 0 UT 0.01 1 VO –0.001 0 0 TA = 25°C INTERNAL REFERENCE = 2.5V –0.01–10 –5 0TIME (µs)5 10 15–1 10486-142 –0.0020 5 10TIME (µs)15 20 25 10486-145 Figure 35. Power-On Reset to 0 V Figure 38. Analog Crosstalk, Channel A 3 CH A CH B T CH C GAIN = 2 CH D SYNC 2 V) (OUT GAIN = 1 1 V 1 VTINADT D=E =R2 5N5°VACL REFERENCE = 2.5V TVAD D= =2 55°VC 0–5 0 TIME (µs) 5 10 10486-143 CEHX1 T 2EµRVNAL REFERENCE = 2.5MV1.0s A CH1 802mV 10486-146 Figure 36. Exiting Power-Down to Midscale Figure 39. 0.1 Hz to 10 Hz Output Noise Plot, External Reference 2.5008 T 2.5003 V) (UT 2.4998 O 1 V CHANNEL B 2.4993 TA = 25°C VDD = 5.25V INTERNAL REFERENCE CODE = 7FFF TO 8000 VDD = 5V ENERGY = 0.227206nV-sec TA = 25°C 2.49880 2 4 TIME6 (µs) 8 10 12 10486-144 CIHN1T E 2RµNVAL REFERENCE = 2.5VM1.0s A CH1 802mV 10486-147 Figure 37. Digital-to-Analog Glitch Impulse Figure 40. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference Rev. D | Page 14 of 29

Data Sheet AD5696R/AD5695R/AD5694R 1600 4.0 VDD = 5V FULL-SCALE 0nF VDD = 5V 1400 TINAT =E R25N°ACL REFERENCE = 2.5V MZEIDRSOC-SACLAELE 3.9 010.0.12nn2FnFF TINAT =E R25N°ACL REFERENCE = 2.5V 3.8 4.7nF 1200 3.7 NSD (nV/ Hz) 1068000000 V (V)OUT 333...456 3.3 400 3.2 200 3.1 010 100 FR1kEQUENCY 1(H0kz) 100k 1M 10486-148 3.10.590 1.595 1.600 1.605TIM1.E6 1(m0s)1.615 1.620 1.625 1.630 10486-150 Figure 41. Noise Spectral Density Figure 43. Settling Time vs. Capacitive Load 20 0 VDD = 5V 0 TA = 25°C INTERNAL REFERENCE = 2.5V –10 –20 –40 B) –20 D (dBV) ––8600 WIDTH (d –30 H D T –100 N A B –40 –120 –140 –50 –160 TVAD D= =2 55°VC EXTERNAL REFERENCE = 2.5V, ±0.1V p-p –1800 2000 4000 6000 F8R00E0QU10E0N0C0Y1 2(H00z0)14000160001800020000 10486-149 –6010k 100kFREQUENCY (Hz)1M 10M 10486-151 Figure 42. Total Harmonic Distortion at 1 kHz Figure 44. Multiplying Bandwidth, External Reference = 2.5 V, ±0.1 V p-p, 10 kHz to 10 MHz Rev. D | Page 15 of 29

AD5696R/AD5695R/AD5694R Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Output Voltage Settling Time For the DAC, relative accuracy or integral nonlinearity is a This is the amount of time it takes for the output of a DAC to measurement of the maximum deviation, in LSBs, from a settle to a specified level for a ¼ to ¾ full-scale input change. straight line passing through the endpoints of the DAC transfer Digital-to-Analog Glitch Impulse function. A typical INL vs. code plot is shown in Figure 12. Digital-to-analog glitch impulse is the impulse injected into the Differential Nonlinearity (DNL) analog output when the input code in the DAC register changes Differential nonlinearity is the difference between the measured state. It is normally specified as the area of the glitch in nV-sec, change and the ideal 1 LSB change between any two adjacent and is measured when the digital input code is changed by codes. A specified differential nonlinearity of ±1 LSB maximum 1 LSB at the major carry transition (0x7FFF to 0x8000) (see ensures monotonicity. This DAC is guaranteed monotonic by Figure 37). design. A typical DNL vs. code plot can be seen in Figure 15. Digital Feedthrough Zero-Code Error Digital feedthrough is a measure of the impulse injected into the Zero-code error is a measurement of the output error when analog output of the DAC from the digital inputs of the DAC, zero code (0x0000) is loaded to the DAC register. Ideally, the but is measured when the DAC output is not updated. It is output should be 0 V. The zero-code error is always positive in specified in nV-sec, and measured with a full-scale code change the AD5696R because the output of the DAC cannot go below on the data bus, that is, from all 0s to all 1s and vice versa. 0 V due to a combination of the offset errors in the DAC and Reference Feedthrough the output amplifier. Zero-code error is expressed in mV. A plot Reference feedthrough is the ratio of the amplitude of the signal of zero-code error vs. temperature can be seen in Figure 22. at the DAC output to the reference input when the DAC output Full-Scale Error is not being updated. It is expressed in dB. Full-scale error is a measurement of the output error when full- Noise Spectral Density scale code (0xFFFF) is loaded to the DAC register. Ideally, the This is a measurement of the internally generated random output should be V − 1 LSB. Full-scale error is expressed in DD noise. Random noise is characterized as a spectral density percent of full-scale range (% of FSR). A plot of full-scale error (nV/√Hz). It is measured by loading the DAC to midscale and vs. temperature can be seen in Figure 21. measuring noise at the output. It is measured in nV/√Hz. A plot Gain Error of noise spectral density is shown in Figure 41. This is a measure of the span error of the DAC. It is the deviation DC Crosstalk in slope of the DAC transfer characteristic from the ideal DC crosstalk is the dc change in the output level of one DAC in expressed as % of FSR. response to a change in the output of another DAC. It is Offset Error Drift measured with a full-scale output change on one DAC (or soft This is a measurement of the change in offset error with a power-down and power-up) while monitoring another DAC kept change in temperature. It is expressed in µV/°C. at midscale. It is expressed in μV. Gain Temperature Coefficient DC crosstalk due to load current change is a measure of the This is a measurement of the change in gain error with changes impact that a change in load current on one DAC has to in temperature. It is expressed in ppm of FSR/°C. another DAC kept at midscale. It is expressed in μV/mA. Offset Error Digital Crosstalk Offset error is a measure of the difference between V (actual) This is the glitch impulse transferred to the output of one DAC OUT and V (ideal) expressed in mV in the linear region of the at midscale in response to a full-scale code change (all 0s to all OUT transfer function. Offset error is measured on the AD5696R 1s and vice versa) in the input register of another DAC. It is with Code 512 loaded in the DAC register. It can be negative measured in standalone mode and is expressed in nV-sec. or positive. DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V to OUT a change in V for full-scale output of the DAC. It is measured DD in mV/V. V is held at 2 V, and V is varied by ±10%. REF DD Rev. D | Page 16 of 29

Data Sheet AD5696R/AD5695R/AD5694R Analog Crosstalk Total Harmonic Distortion (THD) This is the glitch impulse transferred to the output of one DAC This is the difference between an ideal sine wave and its due to a change in the output of another DAC. It is measured by attenuated version using the DAC. The sine wave is used as the loading one of the input registers with a full-scale code change reference for the DAC, and the THD is a measurement of the (all 0s to all 1s and vice versa). Then execute a software LDAC harmonics present on the DAC output. It is measured in dB. and monitor the output of the DAC whose digital code was not Voltage Reference TC changed. The area of the glitch is expressed in nV-sec. Voltage reference TC is a measure of the change in the reference DAC-to-DAC Crosstalk output voltage with a change in temperature. The reference TC This is the glitch impulse transferred to the output of one DAC is calculated using the box method, which defines the TC as the due to a digital code change and subsequent analog output maximum change in the reference output over a given tempera- change of another DAC. It is measured by loading the attack ture range expressed in ppm/°C as follows; channel with a full-scale code change (all 0s to all 1s and vice  V −V  versa), using the write to and update commands while monitor- TC= REFmax REFmin ×106 ing the output of the victim channel that is at midscale. The VREFnom×TempRange energy of the glitch is expressed in nV-sec. where: Multiplying Bandwidth V is the maximum reference output measured over the REFmax The amplifiers within the DAC have a finite bandwidth. The total temperature range. multiplying bandwidth is a measure of this. A sine wave on the V is the minimum reference output measured over the total REFmin reference (with full-scale code loaded to the DAC) appears on temperature range. the output. The multiplying bandwidth is the frequency at V is the nominal reference output voltage, 2.5 V. REFnom which the output amplitude falls to 3 dB below the input. TempRange is the specified temperature range of −40°C to +105°C. Rev. D | Page 17 of 29

AD5696R/AD5695R/AD5694R Data Sheet THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER The resistor string structure is shown in Figure 46. It is a string of resistors, each of Value R. The code loaded to the DAC register The AD5696R/AD5695R/AD5694R are quad 16-/14-/12-bit, determines the node on the string where the voltage is to be serial input, voltage output DACs with an internal reference. tapped off and fed into the output amplifier. The voltage is The parts operate from supply voltages of 2.7 V to 5.5 V. Data is tapped off by closing one of the switches connecting the written to the AD5696R/AD5695R/AD5694R in a 24-bit word string to the amplifier. Because it is a string of resistors, it is format via a 2-wire serial interface. The AD5696R/AD5695R/ guaranteed monotonic. AD5694R incorporate a power-on reset circuit to ensure that the DAC output powers up to a known output state. The devices also VREF have a software power-down mode that reduces the typical R current consumption to typically 4 µA. TRANSFER FUNCTION R The internal reference is on by default. To use an external reference, only a nonreference option is available. Because the R TO OUTPUT AMPLIFIER input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by  D  VOUT =VREF×Gain2N R where: D is the decimal equivalent of the binary code that is loaded to the DAC register as follows: R 00 ttoo 41,60,9358 3f ofor rt hthe e1 214-b-biti td deveivciec.e . 10486-053 Figure 46. Resistor String Structure 0 to 65,535 for the 16-bit device. N is the DAC resolution. Internal Reference Gain is the gain of the output amplifier and is set to 1 by default. The AD5696R/AD5695R/AD5694R on-chip reference is on at This can be set to ×1 or ×2 using the gain select pin. When this power-up but can be disabled via a write to a control register. pin is tied to GND, all four DAC outputs have a span from 0 V See the Internal Reference Setup section for details. to V . If this pin is tied to V , all four DACs output a span of REF DD The AD5696R/AD5695R/AD5694R have a 2.5 V, 2 ppm/°C 0 V to 2 × V . REF reference, giving a full-scale output of 2.5 V or 5 V depending DAC ARCHITECTURE on the state of the GAIN pin. The internal reference associated The DAC architecture consists of a string DAC followed by an with the device is available at the VREF pin. This buffered output amplifier. Figure 45 shows a block diagram of the DAC reference is capable of driving external loads of up to 10 mA. architecture. Output Amplifiers VREF The output buffer amplifier can generate rail-to-rail voltages on 2.5V its output, which gives an output range of 0 V to V . The actual REF DD range depends on the value of V , the GAIN pin, offset error, REF REF (+) and gain error. The GAIN pin selects the gain of the output. REINGPISUTTER REGDIASCTER RSETSRISINTOGR VOUTX REF (–) • If this pin is tied to GND, all four outputs have a gain of 1 GND (GAING =A I1N OR 2) 10486-052 • Iafn tdh itsh pe ionu itsp tuiet dra tnog Ve LiOs G0IC V, a tlol f VouRErF o. utputs have a gain of 2 Figure 45. Single DAC Channel Architecture Block Diagram and the output range is 0 V to 2 × V . REF These amplifiers are capable of driving a load of 1 kΩ in parallel with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale settling time of 5 µs. Rev. D | Page 18 of 29

Data Sheet AD5696R/AD5695R/AD5694R SERIAL INTERFACE Table 7. Command Definitions Command The AD5696R/AD5695R/AD5694R have 2-wire I2C-compati- C3 C2 C1 C0 Description ble serial interfaces (refer to I2C-Bus Specification, Version 2.1, 0 0 0 0 No operation January 2000, available from Philips Semiconductor). See Figure 2 0 0 0 1 Write to Input Register n (dependent on LDAC) for a timing diagram of a typical write sequence. The AD5696R/ 0 0 1 0 Update DAC Register n with contents of Input AD5695R/AD5694R can be connected to an I2C bus as a slave Register n device, under the control of a master device. The AD5696R/ 0 0 1 1 Write to and update DAC Channel n AD5695R/AD5694R support standard (100 kHz) and fast 0 1 0 0 Power down/power up DAC (400 kHz) data transfer modes. Support is not provided for 10- 0 1 0 1 Hardware LDAC mask register bit addressing and general call addressing. Power should not be 0 1 1 0 Software reset (power-on reset) removed while the device is connected to an active I2C bus. 0 1 1 1 Internal reference setup register 1 0 0 0 Reserved Input Shift Register … … … … Reserved The input shift register of the AD5696R/AD5695R/AD5694R is 1 1 1 1 Reserved 24 bits wide. Data is loaded into the device as a 24-bit word Table 8. Address Commands under the control of a serial clock input, SCL. The first eight Address (n) MSBs make up the command byte. The first four bits are the DAC D DAC C DAC B DAC A Selected DAC Channel1 command bits (C3, C2, C1, C0) that control the mode of 0 0 0 1 DAC A operation of the device (see Table 7). The last 4 bits of first byte 0 0 1 0 DAC B are the address bits (DAC A, DAC B, DAC C, DAC D) (see 0 1 0 0 DAC C Table 8). 1 0 0 0 DAC D The data-word comprises 16-bit, 14-bit, or 12-bit input code, 0 0 1 1 DAC A and DAC B1 followed by four, two, or zero don’t care bits for the AD5696R, 1 1 1 1 All DACs AD5695R, and AD5694R, respectively (see Figure 47, Figure 48, and Figure 49). These data bits are transferred to the input 1 Any combination of DAC channels can be selected using the address bits. register on the 24 falling edges of SCL. Commands can be executed on individual DAC channels, combined DAC channels, or on all DACs, depending on the address bits selected. DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C3 C2 C1 C0 DAC DDAC CDAC BDAC A D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X COMMAND DAC ADDRESS DAC DATA DAC DATA COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE 10486-300 Figure 47. AD5696R Input Shift Register Content DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C3 C2 C1 C0 DAC DDAC CDAC BDAC A D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X COMMAND DAC ADDRESS DAC DATA DAC DATA COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE 10486-301 Figure 48. AD5695R Input Shift Register Content Rev. D | Page 19 of 29

AD5696R/AD5695R/AD5694R Data Sheet DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C3 C2 C1 C0 DAC DDAC CDAC BDAC A D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 COMMAND DAC ADDRESS DAC DATA DAC DATA COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE 10486-302 Figure 49. AD5694R Input Shift Register Content WRITE AND UPDATE COMMANDS Update DAC Register n with Contents of Input Register n Write to Input Register n (Dependent on LDAC) Command 0010 loads the DAC registers/outputs with the contents of the input registers selected and updates the DAC Command 0001 allows the user to write to each DAC’s outputs directly. dedicated input register individually. When LDAC is low, the input register is transparent (if not controlled by the LDAC Write to and Update DAC Channel n (Independent of LDAC) mask register). Command 0011 allows the user to write to the DAC registers and update the DAC outputs directly. Rev. D | Page 20 of 29

Data Sheet AD5696R/AD5695R/AD5694R SERIAL OPERATION 2. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge The AD5696R/AD5695R/AD5694R each have a 7-bit slave bit). The transitions on the SDA line must occur during address. The five MSBs are 00011 and the two LSBs (A1, A0) the low period of SCL and remain stable during the high are set by the state of the A0 and A1 address pins. The ability period of SCL. to make hardwired changes to A0 and A1 allows the user to 3. When all data bits have been read or written, a stop incorporate up to four of these devices on one bus, as outlined condition is established. In write mode, the master pulls in Table 9. the SDA line high during the 10th clock pulse to establish Table 9. Device Address Selection a stop condition. In read mode, the master issues a no A0 Pin Connection A1 Pin Connection A0 A1 acknowledge for the 9th clock pulse (that is, the SDA line GND GND 0 0 remains high). The master then brings the SDA line low V GND 1 0 before the 10th clock pulse, and then high during the 10th LOGIC GND V 0 1 clock pulse to establish a stop condition. LOGIC VLOGIC VLOGIC 1 1 WRITE OPERATION The 2-wire serial bus protocol operates as follows: When writing to the AD5696R/AD5695R/AD5694R, the user 1. The master initiates data transfer by establishing a start must begin with a start command followed by an address byte condition when a high-to-low transition on the SDA line (R/W = 0), after which the DAC acknowledges that it is occurs while SCL is high. The following byte is the address prepared to receive data by pulling SDA low. The AD5696R/ byte, which consists of the 7-bit slave address. The slave AD5695R/AD5694R require two bytes of data for the DAC address corresponding to the transmitted address responds and a command byte that controls various DAC functions. by pulling SDA low during the 9th clock pulse (this is Three bytes of data must, therefore, be written to the DAC with termed the acknowledge bit). At this stage, all other devices the command byte followed by the most significant data byte on the bus remain idle while the selected device waits for and the least significant data byte, as shown in Figure 50. All data to be written to, or read from, its shift register. these data bytes are acknowledged by the AD5696R/AD5695R/ AD5694R. A stop condition follows. 1 9 1 9 SCL SDA 0 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 START BY ACK. BY ACK. BY MASTER AD5696R/AD5695R/AD5694R AD5696R/AD5695R/AD5694R FRAME 1 FRAME 2 SLAVE ADDRESS COMMAND BYTE 1 9 1 9 SCL (CONTINUED) SDA DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (CONTINUED) ACK. BY ACK. BY MOSDTFA RSTIAAGM BNEYIF T3ICEANT AD5696R/AD5695R/AD5694R LEASDTFA RTSAAIGM BNEYI FT4IECANT AD5696R/AD5695R/ASDMT5AO6S9PT4 ERBRY 10486-303 Figure 50. I2C Write Operation Rev. D | Page 21 of 29

AD5696R/AD5695R/AD5694R Data Sheet READ OPERATION MULTIPLE DAC READBACK SEQUENCE When reading data back from the AD5696R DACs, the user The user begins with an address byte (R/W = 0), after which the begins with an address byte (R/W = 0), after which the DAC DAC acknowledges that it is prepared to receive data by pulling SDA low. This address byte must be followed by the control acknowledges that it is prepared to receive data by pulling SDA byte, which is also acknowledged by the DAC. The user low. This address byte must be followed by the NOP command configures which channel to start the readback using the operation that sets the internal pointer to the DAC address to control byte. Following this, there is a repeated start condition read from, which is also acknowledged by the DAC. Following this, there is a repeated start condition by the master and the by the master and the address is resent with R/W = 1. This is address is resent with R/W = 1. This is acknowledged by the acknowledged by the DAC, indicating that it is prepared to transmit data. The first two bytes of data are then read from the DAC, indicating that it is prepared to transmit data. Two bytes DAC Input Register n selected using the control byte, most of data are then read from the DAC, as shown in Figure 51. A NACK condition from the master, followed by a STOP significant byte first as shown in Figure 51. The next two bytes condition, completes the read sequence. Default readback read back are the contents of DAC Input Register n + 1, the next is Channel A if more than one DAC is selected. bytes read back are the contents of DAC Input Register n + 2. Data continues to be read from the DAC input registers in this auto-incremental fashion, until a NACK followed by a stop condition follows. If the contents of DAC Input Register D are read out, the next two bytes of data that are read are from the contents of DAC Input Register A. 1 9 1 9 SCL SDA 0 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 START BY ACK. BY ACK. BY MASTER AD5696R/AD5695R/AD5694R AD5696R/AD5695R/AD5694R FRAME 1 FRAME 2 SLAVE ADDRESS COMMAND BYTE 1 9 1 9 SCL SDA 0 0 0 1 1 A1 A0 R/W DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 REPEATED START BY ACK. BY MASTER AD5696R/AD5695R/AD5694R FRAME 3 SLAVE ADDRESS 1 9 SCL (CONTINUED) SDA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (CONTINUED) STOP BY SIGNSIFLICAAVFERN ATA MDDEAD TR5AE SBSYTE n MASTER 10486-304 Figure 51. I2C Read Operation Rev. D | Page 22 of 29

Data Sheet AD5696R/AD5695R/AD5694R POWER-DOWN OPERATION output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the The AD5696R/AD5695R/AD5694R contain three separate advantage that the output impedance of the part is known while power-down modes. Command 0100 is designated for the power- the part is in power-down mode. There are three different down function (see Table 7). These power-down modes are power-down options. The output is connected internally to software-programmable by setting eight bits, Bit DB7 to Bit DB0, GND through either a 1 kΩ or a 100 kΩ resistor, or it is left in the shift register. There are two bits associated with each DAC open-circuited (three-state). The output stage is illustrated in channel. Table 10 shows how the state of the two bits corresponds Figure 52. to the mode of operation of the device. Table 10. Modes of Operation Operating Mode PDx1 PDx0 DAC AMPLIFIER VOUTX Normal Operation 0 0 Power-Down Modes 1 kΩ to GND 0 1 POWER-DOWN CIRCUITRY RESISTOR 1Th00re keΩ-S ttoat Ge N D 11 01 NETWORK 10486-058 Any or all DACs (DAC A to DAC D) can be powered down Figure 52. Output Stage During Power-Down to the selected mode by setting the corresponding bits. See The bias generator, output amplifier, resistor string, and other Table 11 for the contents of the input shift register during associated linear circuitry are shut down when the power-down the power-down/power-up operation. mode is activated. However, the contents of the DAC register When both Bit PDx1 and Bit PDx0 (where x is the channel are unaffected when in power-down. The DAC register can be selected) in the input shift register are set to 0, the parts work updated while the device is in power-down mode. The time normally with its normal power consumption of 4 mA at 5 V. required to exit power-down is typically 4.5 µs for VDD = 5 V. However, for the three power-down modes, the supply current To reduce the current consumption further, the on-chip reference falls to 4 μA at 5 V. Not only does the supply current fall, but the can be powered off. See the Internal Reference Setup section. Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation1 DB15 to DB0 DB23 DB22 DB21 DB20 DB19 to DB16 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 (LSB) 0 1 0 0 X X PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0 Command bits (C3 to C0) Address bits Power-Down Power-Down Power-Down Power-Down Don’t care Select DAC D Select DAC C Select DAC B Select DAC A 1 X = don’t care. Rev. D | Page 23 of 29

AD5696R/AD5695R/AD5694R Data Sheet LOAD DAC (HARDWARE LDAC PIN) LDAC MASK REGISTER The AD5696R/AD5695R/AD5694R DACs have double Command 0101 is reserved for this software LDAC function. buffered interfaces consisting of two banks of registers: Address bits are ignored. Writing to the DAC, using Command input registers and DAC registers. The user can write to 0101, loads the 4-bit LDAC register (DB3 to DB0). The default any combination of the input registers. Updates to the DAC for each channel is 0; that is, the LDAC pin works normally. register are controlled by the LDAC pin. Setting the bits to 1 forces this DAC channel to ignore transitions OUTPUT on the LDAC pin, regardless of the state of the hardware LDAC AMPLIFIER pin. This flexibility is useful in applications where the user REFIN 12-/1D4-A/1C6-BIT VOUT wishes to select which channels respond to the LDAC pin. Table 12. LDAC Overwrite Definition DAC LDAC REGISTER Load LDAC Register LDAC Bits INPUT (DB3 to DB0) LDAC Pin LDAC Operation REGISTER 0 1 or 0 Determined by the LDAC pin. 1 X1 DAC channels update and SSDCOL INRPEUGTIS STHEIRFT 10486-059 ochveanrrnideels t sheee L LDDAACC p aisn 1. D. AC Figure 53. Simplified Diagram of Input Loading Circuitry for a Single DAC 1 X = don’t care. Instantaneous DAC Updating (LDAC Held Low) The LDAC register gives the user extra flexibility and control LDAC is held low while data is clocked into the input register over the hardware LDAC pin (see Table 12). Setting the LDAC using Command 0001. Both the addressed input register and bits (DB0 to DB3) to 0 for a DAC channel means that this the DAC register are updated on the 24th clock and the output channel’s update is controlled by the hardware LDAC pin. begins to change (see Table 13). Deferred DAC Updating (LDAC is Pulsed Low) LDAC is held high while data is clocked into the input register using Command 0001. All DAC outputs are asynchronously updated by taking LDAC low after the 24th clock. The update now occurs on the falling edge of LDAC. Table 13. Write Commands and LDAC Pin Truth Table1 Hardware LDAC Input Register Commands Description Pin State Contents DAC Register Contents 0001 Write to Input Register n (dependent on LDAC) VLOGIC Data update No change (no update) GND2 Data update Data update 0010 Update DAC Register n with contents of Input V No change Updated with input register LOGIC Register n contents GND No change Updated with input register contents 0011 Write to and update DAC Channel n V Data update Data update LOGIC GND Data update Data update 1 A high to low hardware LDAC pin transition always updates the contents of the contents of the DAC register with the contents of the input register on channels that are not masked (blocked) by the LDAC mask register. 2 When LDAC is permanently tied low, the LDAC mask bits are ignored. Rev. D | Page 24 of 29

Data Sheet AD5696R/AD5695R/AD5694R HARDWARE RESET (RESET) SOLDER HEAT REFLOW RESET is an active low reset that allows the outputs to be As with all IC reference voltage circuits, the reference value cleared to either zero scale or midscale. The clear code value is experiences a shift induced by the soldering process. Analog user selectable via the RESET select pin. It is necessary to keep Devices, Inc., performs a reliability test called precondition to RESET low for a minimum amount of time to complete the mimic the effect of soldering a device to a board. The output operation (see Figure 2). When the RESET signal is returned voltage specification quoted previously includes the effect of this reliability test. high, the output remains at the cleared value until a new value is programmed. The outputs cannot be updated with a new value Figure 54 shows the effect of solder heat reflow (SHR) as while the RESET pin is low. There is also a software executable measured through the reliability test (precondition). reset function that resets the DAC to the power-on reset code. Command 0110 is designated for this software reset function 60 POSTSOLDER HEAT REFLOW (see Table 7). Any events on LDAC during a power-on reset are PRESOLDER ignored. If the RESET pin is pulled low at power-up, the device 50 HEAT REFLOW does not initialize correctly until the pin is released. 40 RESET SELECT PIN (RSTSEL) S T HI 30 The AD5696R/AD5695R/AD5694R contain a power-on reset circuit that controls the output voltage during power-up. By 20 connecting the RSTSEL pin low, the output powers up to zero scale. Note that this is outside the linear region of the DAC; by 10 connecting the RSTSEL pin high, V powers up to midscale. OUT The output remains powered up at this level until a valid write 0 sequence is made to the DAC. 2.498 2.499 V2R.E5F0 0(V) 2.501 2.502 10486-060 INTERNAL REFERENCE SETUP Figure 54. SHR Reference Voltage Shift LONG-TERM TEMPERATURE DRIFT The on-chip reference is on at power-up by default. To reduce the supply current, this reference can be turned off by setting Figure 55 shows the change in the V (ppm) value after 1000 REF software programmable bit, DB0, in the control register. hours at 25°C ambient temperature. Table 14 shows how the state of the bit corresponds to the 140 mode of operation. Command 0111 is reserved for setting up the internal reference (see Figure 6). Table 14 shows how the M)120 P state of the bits in the input shift register corresponds to the P T (100 mode of operation of the device during internal reference setup. FI R D 80 E Table 14. Reference Setup Register NC E 60 Internal Reference ER F Setup Register (DB0) Action RE 40 0 Reference on (default) AL 1 Reference off ERN 20 T N I 0 –20 0 100 200 300ELA4P0S0ED5 T0I0ME 6(H0o0urs7)00 800 900 1000 10486-055 Figure 55. Reference Drift Through to 1000 Hours Rev. D | Page 25 of 29

AD5696R/AD5695R/AD5694R Data Sheet THERMAL HYSTERESIS 9 FIRST TEMPERATURE SWEEP Thermal hysteresis is the voltage difference induced on the 8 SUBSEQUENT TEMPERATURE SWEEPS reference voltage by sweeping the temperature from ambient 7 to cold, to hot and then back to ambient. 6 Thermal hysteresis data is shown in Figure 56. It is measured by 5 S sweeping temperature from ambient to −40°C, then to +105°C, T HI 4 and returning to ambient. The V delta is then measured REF between the two ambient measurements and shown in blue 3 in Figure 56. The same temperature sweep and measurements 2 were immediately repeated and the results are shown in red in 1 Figure 56. –0200 –150 D–IS10T0ORTION (–p5p0m) 0 50 10486-062 Figure 56. Thermal Hysteresis Table 15. 24-Bit Input Shift Register Contents for Internal Reference Setup Command1 DB23 (MSB) DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0 (LSB) 0 1 1 1 X X X X X 1/0 Command bits (C3 to C0) Address bits (A2 to A0) Don’t care Reference setup register 1 X = don’t care. Rev. D | Page 26 of 29

Data Sheet AD5696R/AD5695R/AD5694R APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING special considerations to design the motherboard and to mount the package. For enhanced thermal, electrical, and board level Microprocessor interfacing to the AD5696R/AD5695R/ performance, solder the exposed paddle on the bottom of the AD5694R is via a serial bus that uses a standard protocol that package to the corresponding thermal land paddle on the PCB. is compatible with DSP processors and microcontrollers. The Design thermal vias into the PCB land paddle area to further communications channel requires a 2-wire interface consisting of improve heat dissipation. a clock signal and a data signal. The GND plane on the device can be increased (as shown in AD5696R/AD5695R/AD5694R TO ADSP-BF531 Figure 58) to provide a natural heat sinking effect. INTERFACE AD5696R/ The I2C interface of the AD5696R/AD5695R/AD5694R is AD5695R/ designed to be easily connected to industry-standard DSPs and AD5694R microcontrollers. Figure 57 shows the AD5696R/AD5695R/ AD5694R connected to the Analog Devices Blackfin® DSP. The Blackfin has an integrated I2C port that can be connected directly to the I2C pins of the AD5696R/AD5695R/AD5694R. GND PLANE AD5696R/ AD5695R/ ADSP-BF531 AD5694R BOARD 10486-166 Figure 58. Paddle Connection to Board GPIO1 SCL GPIO2 SDA GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to PPFF98 LRDEASCET 10486-164 pthreo vuindiet abne iinsgo lcaotinotnro blalerdri teor bperotwteecetn a nthde i csoolnattreo tlhleer caonndt r olling Figure 57. ADSP-BF531 Interface circuitry from any hazardous common-mode voltages that LAYOUT GUIDELINES may occur. iCoupler® products from Analog Devices provide In any circuit where accuracy is important, careful consider- voltage isolation in excess of 2.5 kV. The serial loading struc- ation of the power supply and ground return layout helps ture of the AD5696R/AD5695R/AD5694R makes the part ideal to ensure the rated performance. The PCB on which the for isolated interfaces because the number of interface lines is AD5696R/AD5695R/AD5694R are mounted should be kept to a minimum. Figure 59 shows a 4-channel isolated designed so that the AD5696R/AD5695R/AD5694R lie interface to the AD5696R/AD5695R/AD5694R using an on the analog plane. ADuM1400. For further information, visit http://www.analog.com/icouplers. The AD5696R/AD5695R/AD5694R should have ample supply bypassing of 10 μF in parallel with 0.1 μF on each supply, located as CONTROLLER ADuM14001 close to the package as possible, ideally right up against the SERIAL VIA VOA TO device. The 10 μF capacitors are the tantalum bead type. The CLOCK IN ENCODE DECODE SCL 0.1 μF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI) such as the DATSAE ROIAULT VIB ENCODE DECODE VOB TSODA common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to VIC VOC TO RESET OUT ENCODE DECODE internal logic switching. RESET Ionft seyns tuesmefsu wl thoe prer otvhiedree saorme me haneayt d seinvikciensg o cna poanbei lbitoya trod ,a iltl oisw LOAD DOAUCT VID ENCODE DECODE VOD TLODAC tThhee p AoDwe5r6 9to6 Rd/isAsiDp5at6e9 e5aRs/iAly.D 5694R LFCSP models have an 1ADDITIONAL PINS OMITTED FOR CLARITY. 10486-167 exposed paddle beneath the device. Connect this paddle to the Figure 59. Isolated Interface GND supply for the part. For optimum performance, use Rev. D | Page 27 of 29

AD5696R/AD5695R/AD5694R Data Sheet OUTLINE DIMENSIONS 3.10 0.30 3.00 SQ 0.23 PIN 1 2.90 0.18 INDICATOR PIN 1 0.50 13 16 INDICATOR BSC 12 1 EXPOSED 1.75 PAD 1.60 SQ 1.45 9 4 0.50 8 5 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 0.80 FOR PROPER CONNECTION OF 0.75 THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANTTOJEDEC STANDARDS MO-220-WEED-6. 08-16-2010-E Figure 60. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 0.65 0.19 SEATING 0° 0.45 BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 61. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. D | Page 28 of 29

Data Sheet AD5696R/AD5695R/AD5694R ORDERING GUIDE Reference Temperature Tempco Package Package Model1 Resolution Range Accuracy (ppm/°C) Description Option Branding AD5696RACPZ-RL7 16 Bits −40°C to +105°C ±8 LSB INL ±5 (typ) 16-Lead LFCSP_WQ CP-16-22 DJA AD5696RBCPZ-RL7 16 Bits −40°C to +105°C ±2 LSB INL ±5 (max) 16-Lead LFCSP_WQ CP-16-22 DJD AD5696RARUZ 16 Bits −40°C to +105°C ±8 LSB INL ±5 (typ) 16-Lead TSSOP RU-16 AD5696RARUZ-RL7 16 Bits −40°C to +105°C ±8 LSB INL ±5 (typ) 16-Lead TSSOP RU-16 AD5696RBRUZ 16 Bits −40°C to +105°C ±2 LSB INL ±5 (max) 16-Lead TSSOP RU-16 AD5696RBRUZ-RL7 16 Bits −40°C to +105°C ±2 LSB INL ±5 (max) 16-Lead TSSOP RU-16 AD5695RBCPZ-RL7 14 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead LFCSP_WQ CP-16-22 DJR AD5695RARUZ 14 Bits −40°C to +105°C ±4 LSB INL ±5 (typ) 16-Lead TSSOP RU-16 AD5695RARUZ-RL7 14 Bits −40°C to +105°C ±4 LSB INL ±5 (typ) 16-Lead TSSOP RU-16 AD5695RBRUZ 14 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead TSSOP RU-16 AD5695RBRUZ-RL7 14 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead TSSOP RU-16 AD5694RBCPZ-RL7 12 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead LFCSP_WQ CP-16-22 DJL AD5694RARUZ 12 Bits −40°C to +105°C ±2 LSB INL ±5 (typ) 16-Lead TSSOP RU-16 AD5694RARUZ-RL7 12 Bits −40°C to +105°C ±2 LSB INL ±5 (typ) 16-Lead TSSOP RU-16 AD5694RBRUZ 12 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead TSSOP RU-16 AD5694RBRUZ-RL7 12 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead TSSOP RU-16 EVAL-AD5696RSDZ AD5696R TSSOP Evaluation Board 1 Z = RoHS Compliant Part. ©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10486-0-4/17(D) Rev. D | Page 29 of 29

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5696RSDZ AD5694RARUZ-RL7 AD5696RBRUZ-RL7 AD5694RBRUZ-RL7 AD5695RBRUZ AD5695RARUZ AD5695RBRUZ-RL7 AD5695RBCPZ-RL7 AD5694RARUZ AD5694RBRUZ AD5696RBRUZ AD5694RBCPZ-RL7 AD5696RARUZ-RL7 AD5695RARUZ-RL7 AD5696RBCPZ-RL7 AD5696RACPZ-RL7 AD5696RARUZ