Dual, 16-/12-Bit nanoDAC+ with 2 ppm/°C Reference, SPI Interface Data Sheet AD5689R/AD5687R FEATURES FUNCTIONAL BLOCK DIAGRAM High relative accuracy (INL): ±2 LSB maximum at 16 bits VDD GND VREF Low drift 2.5 V reference: 2 ppm/°C typical AD5689R/AD5687R VLOGIC 2.5V Tiny package: 3 mm × 3 mm, 16-lead LFCSP REFERENCE TUE: ±0.1% of FSR maximum SCLK C Offset error: ±1.5 mV maximum SYNC LOGI REIGNPISUTTER REGDIASCTER SDTARCIN AG VOUTA Gain error: ±0.1% of FSR maximum CE BUFFER A HUsigehr- dserliveect caabplea bgialiitny o: 2f 01 morA 2, 0(G.5A VIN f rpoimn) supply rails SDIN INTERF REIGNPISUTTER REGDIASCTER SDTARCIN BG BUFFER VOUTB Reset to zero scale or midscale (RSTSEL pin) SDO 1.8 V logic compatibility 50 MHz SPI with readback or daisy chain PORWEESRE-TON G×A1I/N×2 = PDOOWWENR- LOGIC LLooww pgolitwcehr: :0 3.5.3 n mVW-se act 3 V LDAC RESET RSTSEL GAIN 11256-001 Figure 1. 2.7 V to 5.5 V power supply −40°C to +105°C temperature range APPLICATIONS Optical transceivers Base station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5689R/AD5687R members of the nanoDAC+™ Table 1. Dual nanoDAC+ Devices family are low power, dual, 16-/12-bit buffered voltage output Interface Reference 16-Bit 12-Bit digital-to-analog converters (DACs). The devices include SPI Internal AD5689R AD5687R a 2.5 V, 2 ppm/°C internal reference (enabled by default) External AD5689 AD5687 and a gain select pin giving a full-scale output of 2.5 V I2C Internal AD5697R (gain = 1) or 5 V (gain = 2). The devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and PRODUCT HIGHLIGHTS 1.5 mV offset error performance. Both devices are available in a 3 mm × 3 mm LFCSP and a TSSOP package. 1. High Relative Accuracy (INL). AD5689R (16-bit): ±2 LSB maximum The AD5689R/AD5687R also incorporate a power-on reset AD5687R (12-bit): ±1 LSB maximum circuit and a RSTSEL pin that ensure that the DAC outputs 2. Low Drift 2.5 V On-Chip Reference. power up to zero scale or midscale and remain there until 2 ppm/°C typical temperature coefficient a valid write takes place. Each part contains a per channel 5 ppm/°C maximum temperature coefficient power-down feature that reduces the current consumption 3. Two Package Options. of the device to 4 μA at 3 V while in power-down mode. 3 mm × 3 mm, 16-lead LFCSP The AD5689R/AD5687R use a versatile serial peripheral 16-lead TSSOP interface (SPI) that operates at clock rates up to 50 MHz. and both devices contain a V pin that is intended for LOGIC 1.8 V/3 V/5 V logic. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5689R/AD5687R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Write and Update Commands .................................................. 21  Applications ....................................................................................... 1  Daisy-Chain Operation ............................................................. 21  Functional Block Diagram .............................................................. 1  Readback Operation .................................................................. 22  General Description ......................................................................... 1  Power-Down Operation ............................................................ 22  Product Highlights ........................................................................... 1  Load DAC (Hardware LDAC Pin) ........................................... 23  Revision History ............................................................................... 2  LDAC Mask Register ................................................................. 23  Specifications ..................................................................................... 3  Hardware Reset (RESET) .......................................................... 24  AC Characteristics ........................................................................ 5  Reset Select Pin (RSTSEL) ........................................................ 24  Timing Characteristics ................................................................ 6  Internal Reference Setup ........................................................... 24  Daisy-Chain and Readback Timing Characteristics ............... 7  Solder Heat Reflow ..................................................................... 24  Absolute Maximum Ratings ............................................................ 9  Long-Term Temperature Drift ................................................. 24  ESD Caution .................................................................................. 9  Thermal Hysteresis .................................................................... 25  Pin Configurations and Function Descriptions ......................... 10  Applications Information .............................................................. 26  Typical Performance Characteristics ........................................... 11  Microprocessor Interfacing ....................................................... 26  Terminology .................................................................................... 17  AD5689R/AD5687R to ADSP-BF531 Interface ...................... 26  Theory of Operation ...................................................................... 19  AD5689R/AD5687R to SPORT Interface ................................ 26  Digital-to-Analog Converters ................................................... 19  Layout Guidelines....................................................................... 26  Transfer Function ....................................................................... 19  Galvanically Isolated Interface ................................................. 26  DAC Architecture ....................................................................... 19  Outline Dimensions ....................................................................... 27  Serial Interface ............................................................................ 20  Ordering Guide .......................................................................... 28  Standalone Operation ................................................................ 21  REVISION HISTORY 3/2017—Rev. A to Rev. B Changes to Figure 26, Figure 27, Figure 29, and Figure 30....... 14 Changes to Features and Table 1 .................................................... 1 Changes to Figure 33, Figure 36, and Figure 37 ......................... 15 Changed 1.8 V ≤ V ≤ 5.5 V to 1.62 V ≤ V ≤ 5.5 V ......... 3 Change to Table 9 ........................................................................... 20 LOGIC LOGIC Change to V Parameter, Table 2 .............................................. 4 Change to Readback Operation Section ..................................... 22 LOGIC Changed 1.8 V ≤ V ≤ 5.5 V to 1.8 V – 10% ≤ V ≤ 5 V + Change to Table 14 ......................................................................... 23 LOGIC LOGIC 10% ..................................................................................................... 5 Changes to Hardware Reset Section and Reset Select Pin Changed 1.8 V ≤ V ≤ 5.5 V to 1.62 V ≤ V ≤ 5.5 V ......... 6 (RSTSEL) Section ........................................................................... 24 LOGIC LOGIC Changes to Table 4 and Figure 2 ..................................................... 6 Added Long-Term Temperature Drift Section and Figure 49; Changed 1.8 V ≤ V ≤ 5.5 V to 1.62 V ≤ V ≤ 5.5 V ......... 7 Renumbered Sequentially ............................................................. 24 LOGIC LOGIC Changes to Table 5 and Figure 4 ..................................................... 7 Changes to Figure 5 .......................................................................... 8 5/2014—Rev. 0 to Rev. A Changes to Table 6 ............................................................................ 9 Deleted Long-Term Stability/Drift Parameter, Table 1 ................ 4 Changes to Table 7 .......................................................................... 10 Deleted Figure 11; Renumbered Sequentially ............................ 11 Changes to Figure 12 ...................................................................... 11 Deleted Long-Term Temperature Drift Section ......................... 24 Changes to Figure 19 ...................................................................... 12 Changes to Figure 20 to Figure 23 and Figure 25 ....................... 13 2/2013—Revision 0: Initial Version Rev. B | Page 2 of 28

Data Sheet AD5689R/AD5687R SPECIFICATIONS V = 2.7 V to 5.5 V; 1.62 V≤ V ≤ 5.5 V; all specifications T to T , unless otherwise noted. R = 2 kΩ; C = 200 pF. DD LOGIC MIN MAX L L Table 2. A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE2 AD5689R Resolution 16 16 Bits Relative Accuracy ±2 ±8 ±1 ±2 LSB Gain = 2 ±2 ±8 ±1 ±3 Gain = 1 Differential ±1 ±1 LSB Guaranteed monotonic by design Nonlinearity AD5687R Resolution 12 12 Bits Relative Accuracy ±0.12 ±2 ±0.12 ±1 LSB Differential ±1 ±1 LSB Guaranteed monotonic by design Nonlinearity Zero-Code Error 0.4 4 0.4 1.5 mV All 0s loaded to DAC register Offset Error +0.1 ±4 +0.1 ±1.5 mV Full-Scale Error +0.01 ±0.2 +0.01 ±0.1 % of FSR All 1s loaded to DAC register Gain Error ±0.02 ±0.2 ±0.02 ±0.1 % of FSR Total Unadjusted Error ±0.01 ±0.25 ±0.01 ±0.1 % of FSR External reference; gain = 2; TSSOP ±0.25 ±0.2 % of FSR Internal reference; gain = 1; TSSOP Offset Error Drift3 ±1 ±1 μV/°C Gain Temperature ±1 ±1 ppm Of FSR/°C Coefficient3 DC Power Supply 0.15 0.15 mV/V DAC code = midscale; Rejection Ratio3 V = 5 V ± 10% DD DC Crosstalk3 ±2 ±2 μV Due to single channel, full-scale output change ±3 ±3 μV/mA Due to load current change ±2 ±2 μV Due to powering down (per channel) OUTPUT CHARACTERISTICS3 Output Voltage Range 0 V 0 V V Gain = 1 REF REF 0 2 × V 0 2 × V V Gain = 2, see Figure 31 REF REF Capacitive Load Stability 2 2 nF R = ∞ L 10 10 nF R = 1 kΩ L Resistive Load4 1 1 kΩ Load Regulation 80 80 μV/mA 5 V ± 10%, DAC code = midscale; −30 mA ≤ I ≤ 30 mA OUT 80 80 μV/mA 3 V ± 10%, DAC code = midscale; −20 mA ≤ I ≤ 20 mA OUT Short-Circuit Current5 40 40 mA Load Impedance at Rails6 25 25 Ω See Figure 31 Power-Up Time 2.5 2.5 μs Coming out of power-down mode; V = 5 V DD Rev. B | Page 3 of 28

AD5689R/AD5687R Data Sheet A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments REFERENCE OUTPUT Output Voltage7 2.4975 2.5025 2.4975 2.5025 V At ambient Reference Temperature 5 20 2 5 ppm/°C See the Long-Term Temperature Coefficient8, 9 Driftsection Output Impedance3 0.04 0.04 Ω Output Voltage Noise3 12 12 μV p-p 0.1 Hz to 10 Hz Output Voltage Noise 240 240 nV/√Hz At ambient; f = 10 kHz, Density3 CL = 10 nF Load Regulation Sourcing3 20 20 µV/mA At ambient Load Regulation Sinking3 40 40 µV/mA At ambient Output Current Load ±5 ±5 mA VDD ≥ 3 V Capability3 Line Regulation3 100 100 μV/V At ambient Thermal Hysteresis3 125 125 ppm First cycle 25 25 ppm Additional cycles LOGIC INPUTS3 Input Current ±2 ±2 μA Per pin Input Low Voltage (V ) 0.3 × V 0.3 × V V INL LOGIC LOGIC Input High Voltage (V ) 0.7 × V 0.7 × V V INH LOGIC LOGIC Pin Capacitance 2 2 pF LOGIC OUTPUTS (SDO)3 Output Low Voltage (VOL) 0.4 0.4 V ISINK = 200 μA Output High Voltage (VOH) VLOGIC − 0.4 VLOGIC − 0.4 V ISOURCE = 200 μA Floating State Output 4 4 pF Capacitance POWER REQUIREMENTS V 1.62 5.5 1.62 5.5 V LOGIC ILOGIC 3 3 µA V 2.7 5.5 2.7 5.5 V Gain = 1 DD V V + 1.5 5.5 V + 1.5 5.5 V Gain = 2 DD REF REF I V = V , V = GND, DD IH DD IL V = 2.7 V to 5.5 V DD Normal Mode10 0.59 0.7 0.59 0.7 mA Internal reference off 1.1 1.3 1.1 1.3 mA Internal reference on, at full scale All Power-Down 1 4 1 4 μA −40°C to +85°C Modes11 6 6 μA −40°C to +105°C 1 Temperature range for A and B grades: −40°C to +105°C. 2 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV; it exists only when VREF = VDD with gain = 1 or when VREF/2 = VDD with gain = 2. Linearity is calculated using a reduced code range of 256 to 65,280 (AD5689R) and 12 to 4080 (AD5687R). 3 Guaranteed by design and characterization; not production tested. 4 Channel A can have an output current of up to 30 mA. Similarly, Channel B can have an output current of up to 30 mA, up to a junction temperature of 110°C. 5 VDD = 5 V. The devices include current limiting that is intended to protect them during temporary overload conditions. Junction temperature may be exceeded during current limit, but operation above the specified maximum operation junction temperature can impair device reliability. 6 When drawing a load current at either rail, the output voltage headroom, with respect to that rail, is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 31). 7 Initial accuracy presolder reflow is ±750 μV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section. 8 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C. 9 Reference temperature coefficient is calculated as per the box method. See the Terminology section for more information. 10 Interface inactive. Both DACs active. DAC outputs unloaded. 11 Both DACs powered down. Rev. B | Page 4 of 28

Data Sheet AD5689R/AD5687R AC CHARACTERISTICS V = 2.7 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; 1.8 V – 10% ≤ V ≤ 5 V + 10%; all specifications T to T , unless DD L L LOGIC MIN MAX otherwise noted. Guaranteed by design and characterization; not production tested. Table 3. Parameter1 Min Typ Max Unit Test Conditions/Comments2 Output Voltage Settling Time AD5689R 5 8 μs ¼ to ¾ scale settling to ±2 LSB AD5687R 5 7 μs ¼ to ¾ scale settling to ±2 LSB Slew Rate 0.8 V/μs Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry Digital Feedthrough 0.13 nV-sec Digital Crosstalk 0.1 nV-sec Analog Crosstalk 0.2 nV-sec DAC-to-DAC Crosstalk 0.3 nV-sec Total Harmonic Distortion (THD)3 −80 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT Output Noise Spectral Density (NSD) 300 nV/√Hz DAC code = midscale, 10 kHz; gain = 2 Output Noise 6 μV p-p 0.1 Hz to 10 Hz Signal-to-Noise Ratio (SNR) 90 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT Spurious Free Dynamic Range (SFDR) 83 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT Signal-to-Noise-and-Distortion Ratio (SINAD) 80 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT 1 See the Terminology section. 2 Temperature range is −40°C to +105°C, typical at 25°C. 3 Digitally generated sine wave at 1 kHz. Rev. B | Page 5 of 28

AD5689R/AD5687R Data Sheet TIMING CHARACTERISTICS All input signals are specified with t = t = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2. See Figure 2. R F DD IL IH V = 2.7 V to 5.5 V, 1.62 V ≤ V ≤ 5.5 V; V = 2.5 V. All specifications T to T , unless otherwise noted. DD LOGIC REF MIN MAX Table 4. 1.62 V ≤ V < 2.7 V 2.7 V ≤ V ≤ 5.5 V LOGIC LOGIC Parameter1 Symbol Min Max Min Max Unit SCLK Cycle Time t 20 20 ns 1 SCLK High Time t 10 10 ns 2 SCLK Low Time t 10 10 ns 3 SYNCE to SCLK Falling Edge Setup Time t4 15 10 ns Data Setup Time t 5 5 ns 5 Data Hold Time t 5 5 ns 6 SCLK Falling Edge to SYNCE Rising Edge t7 10 10 ns Minimum SYNCE High Time t8 20 20 ns SYNCE Rising Edge to SYNCE Rising Edge (DAC Register Updates) t9 870 830 ns SYNCE Falling Edge to SCLK Fall Ignore t10 16 10 ns LDACE Pulse Width Low t11 15 15 ns SYNCE Rising Edge to LDACE Rising Edge t12 20 20 ns SYNCE Rising Edge to LDACE Falling Edge t13 30 30 ns LDACE Falling Edge to SYNCE Rising Edge t14 840 800 ns Minimum Pulse Width Low t 30 30 ns 15 Pulse Activation Time t 30 30 ns 16 Power-Up Time2 4.5 4.5 μs 1Guaranteed by design and characterization; not production tested. 2 Time to exit power-down to normal mode of AD5689R/AD5687R operation, SYNCE rising edge to 90% of DAC midscale value, with output unloaded. t10 t1 SCLK t8 t3 t2 t7 t14 t 4 SYNC t 9 t 6 t 5 SDIN DB23 DB0 t13 t11 1 t 12 2 t 15 VOUT t16 21 11256-002 Figure 2. Serial Write Operation Rev. B | Page 6 of 28

Data Sheet AD5689R/AD5687R DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS All input signals are specified with t = t = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2. See Figure 4 R F DD IL IH and Figure 5. V = 2.7 V to 5.5 V, 1.62 V ≤ V ≤ 5.5 V; V = 2.5 V. All specifications T to T , unless otherwise noted. V = 2.7 DD LOGIC REF MIN MAX DD V to 5.5 V. Table 5. 1.62 V ≤ V < 2.7 V 2.7 V ≤ V ≤ 5.5 V LOGIC LOGIC Parameter1 Symbol Min Max Min Max Unit SCLK Cycle Time t 66 40 ns 1 SCLK High Time t 33 20 ns 2 SCLK Low Time t 33 20 ns 3 SYNCE to SCLK Falling Edge t4 33 20 ns Data Setup Time t 5 5 ns 5 Data Hold Time t 5 5 ns 6 SCLK Falling Edge to SYNCE Rising Edge t7 15 10 ns Minimum SYNCE High Time t8 60 30 ns SDO Data Valid from SCLK Rising Edge t 45 30 ns 9 SYNCE Rising Edge to SCLK Rising Edge t10 15 10 ns SYNCE Rising Edge to SDO Disable t11 60 60 ns 1 Guaranteed by design and characterization; not production tested. Circuit and Timing Diagrams 200µA IOL TO OUTPPUINT VOH (MIN) CL 20pF 200µA IOH 11256-004 Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications t 1 24 48 t8 t2 t7 t t3 t10 4 t 6 t 5 DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N INPUT WORD FOR DAC N + 1 t 9 UNDEFINED INPUT WORD FOR DAC N 11256-004 Figure 4. Daisy-Chain Timing Diagram Rev. B | Page 7 of 28

AD5689R/AD5687R Data Sheet t 1 SCLK 1 24 1 24 t t t4 3 t2 t7 t8 t10 8 SYNC t 6 t 5 SDIN DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ t t 9 11 SDO DB23 DB0 HI-Z SELECCTLEOD CRKEEGDIS OTUETR DATA 11256-005 Figure 5. Readback Timing Diagram Rev. B | Page 8 of 28

Data Sheet AD5689R/AD5687R ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 6. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Operation beyond V to GND −0.3 V to +7 V LOGIC the maximum operating conditions for extended periods may V to GND −0.3 V to V + 0.3 V OUT DD affect product reliability. V to GND −0.3 V to V + 0.3 V REF DD Digital Input Voltage to GND −0.3 V to V + 0.3 V LOGIC Operating Temperature Range −40°C to +105°C ESD CAUTION Storage Temperature Range −65°C to +150°C Junction Temperature 125°C 16-Lead TSSOP, θ Thermal Impedance, 112.6°C/W JA 0 Airflow (4-Layer Board) 16-Lead LFCSP, θ Thermal Impedance, 70°C/W JA 0 Airflow (4-Layer Board) Reflow Soldering Peak Temperature, 260°C Pb Free (J-STD-020) Rev. B | Page 9 of 28

AD5689R/AD5687R Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS L E T CN VFER STSR ESER 6 5 4 3 1 1 1 1 VOUTA1 12SDIN GND2 AD5689R/ 11SYNC VREF 1 16 RSTSEL VDD3 AD5687R 10SCLK NC 2 15 RESET NC4 9 VLOGIC VOUTA 3 AD5689R/ 14 SDIN AD5687R GND 4 13 SYNC 5 6 7 8 TOP VIEW B O C N VDD 5 (Not to Scale) 12 SCLK VTUO DS ADL IAG NC 6 11 VLOGIC TOP VIEW VOUTB 7 10 GAIN (Not to Scale) SDO 8 9 LDAC NOTES 12 .. TNTHHCEI S= E NPXIONP O.CSOENDN EPCATD. MDOUS NTO BTE C TOIENDN ETCOT G TNOD. 11256-007 N1 . O NTTOCE S=T HNIOS PCIONN.NECT. DO NOT CONNECT 11256-008 Figure 6. 16-Lead LFCSP Pin Configuration Figure 7. 16-Lead TSSOP Pin Configuration Table 7. Pin Function Descriptions Pin No. LFCSP TSSOP Mnemonic Description 1 3 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 2 4 GND Ground Reference Point for All Circuitry on the AD5689R/AD5687R. 3 5 V Power Supply Input. The AD5689R/AD5687R can be operated from 2.7 V to 5.5 V. Decouple the supply DD with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 4 6 NC No Connect. Do not connect to this pin. 5 7 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 6 8 SDO Serial Data Output. SDO can be used to daisy-chain a number of AD5689R/AD5687R devices together, or it can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. 7 9 LDAC LDAC can be operated in two modes: asynchronous and synchronous. Pulsing this pin low allows either or both DAC registers to be updated if the input registers have new data; both DAC outputs can be updated simultaneously. This pin can also be tied permanently low. 8 10 GAIN Gain Select. When this pin is tied to GND, both DACs output a span from 0 V to V . If this pin is tied to REF V , both DACs output a span of 0 V to 2 × V . LOGIC REF 9 11 V Digital Power Supply. The voltage on this pin ranges from 1.62 V to 5.5 V. LOGIC 10 12 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. 11 13 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 24 clocks. 12 14 SDIN Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 13 15 RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. If this pin is forced low at power-up, the power-on reset (POR) circuit does not initialize the device correctly until this pin is released. 14 16 RSTSEL Power-On Reset Select.Tying this pin to GND powers up bothDACs to zero scale. Tying this pin to V powers up both DACs to midscale. LOGIC 15 1 V Reference Voltage. The AD5689R/AD5687R have a common reference pin. When using the internal REF reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference output. 16 2 NC No Connect. Do not connect to this pin. 17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND. Rev. B | Page 10 of 28

Data Sheet AD5689R/AD5687R TYPICAL PERFORMANCE CHARACTERISTICS 2.5020 1600 DDEEVVIICCEE 12 VDD = 5V VTAD D= =2 55°VC 2.5015 DEVICE 3 1400 DEVICE 4 2.5010 DEVICE 5 1200 V (V)REF 22..55000005 D (nV/ Hz) 1080000 S 2.4995 N 600 2.4990 400 2.4985 200 2.4980–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 11256-009 010 100 FR1kEQUENCY 1(H0kz) 100k 1M 11256-013 Figure 8. Internal Reference Voltage vs. Temperature (Grade B) Figure 11. Internal Reference Noise Spectral Density vs. Frequency 2.5020 2.5015 DDDEEEVVVIIICCCEEE 123 TVAD D= =2 55°VC T DEVICE 4 2.5010 DEVICE 5 2.5005 V) (EF 2.5000 1 R V 2.4995 2.4990 2.4985 VDD = 5V 2.4980–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 11256-010 CCHH11 22µµVV M1.0s A CH1 160mV 11256-112 Figure 9. Internal Reference Voltage vs. Temperature (Grade A) Figure 12. Internal Reference Noise, 0.1 Hz to 10 Hz 90 2.5000 VDD = 5V VDD = 5V 80 TA = 25°C 2.4999 70 2.4998 TS 60 NI BER OF U 4500 V (V)REF22..44999976 M NU 30 2.4995 20 2.4994 10 0 2.4993 0 0.5 1.0 TE1M.5PER2A.0TURE2. 5DRIF3T.0 (ppm3./5°C) 4.0 4.5 5.0 11256-011 –0.005 –0.003 –0.00I1LOAD (A0).001 0.003 0.005 11256-015 Figure 10. Reference Output Temperature Drift Histogram Figure 13. Internal Reference Voltage vs. Load Current Rev. B | Page 11 of 28

AD5689R/AD5687R Data Sheet 10 10 8 8 6 6 4 4 B) 2 B) 2 S S INL (L –20 INL (L –20 –4 –4 –6 –6 –8 TVAD D= =2 55°VC –8 VTAD D= =2 55°VC –100REFER1E00N0C0E = 22.050V00 300C0O0DE40000 50000 60000 11256-017 –100INTERN6A2L5 REFE1R2E5N0CE =1 28.C755OVDE 2500 3125 3750 4096 11256-018 Figure 14. AD5689R Integral Nonlinearity (INL) vs. Code Figure 17. AD5687R INL vs. Code 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 B) 0.2 B) 0.2 DNL (LS –0.20 DNL (LS –0.20 –0.4 –0.4 –0.6 –0.6 ––10..080TVRADE DF= E =2R 155E0°VC0N0C0E = 22.050V00 300C0O0DE40000 50000 60000 11256-019 ––10..080IVTNADT D=E =R2 5N56°VAC2L5 REFE1R2E50NCE =1 28.C755OVDE 2500 3125 3750 4096 11256-020 Figure 15. AD5689R Differential Nonlinearity (DNL) vs. Code Figure 18. AD5687R DNL vs. Code 2.5002 10 TA = 25°C D1 8 2.5000 6 4 2.4998 D3 B) 2 (V)REF2.4996 OR (LS 0 DINNLL V R R –2 E 2.4994 –4 2.4992 –6 D2 –8 VDD = 5V INTERNAL REFERENCE = 2.5V 2.4990 –10 2.5 3.0 3.5 V4.D0D (V) 4.5 5.0 5.5 11256-016 –40 10 TEMPERATURE6 (0°C) 110 11256-124 Figure 16. Internal Reference Voltage vs. Supply Voltage Figure 19. INL Error and DNL Error vs. Temperature Rev. B | Page 12 of 28

Data Sheet AD5689R/AD5687R 10 1.4 VINDTDE =R N5VAL REFERENCE = 2.5V 8 6 1.2 4 1.0 R (LSB) 02 INL OR (mV) 0.8 O DNL R RR –2 ER 0.6 E –4 0.4 ZERO-CODE ERROR –6 VDD = 5V TA = 25°C 0.2 –8 OFFSET ERROR –100 0.5 1.0 1.5 2.0VRE2.F5 (V)3.0 3.5 4.0 4.5 5.0 11256-125 0–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 11256-128 Figure 20. INL Error and DNL Error vs. VREF Figure 23. Zero-Code Error and Offset Error vs. Temperature 10 0.10 8 0.08 6 0.06 4 0.04 R) B) 2 FS 0.02 R (LS 0 INL % of 0 GAIN ERROR ERRO –2 DNL RROR (–0.02 FULL-SCALE ERROR –4 E–0.04 –6 –0.06 –8 TA = 25°C –0.08 VTAD D= =2 55°VC INTERNAL REFERENCE = 2.5V INTERNAL REFERENCE = 2.5V –102.7 3.2 S3U.7PPLY VOL4.T2AGE (V)4.7 5.2 11256-126 –0.102.7 3.2 S3U.7PPLY VO4L.T2AGE (V)4.7 5.2 11256-026 Figure 21. INL Error and DNL Error vs. Supply Voltage Figure 24. Gain Error and Full-Scale Error vs. Supply 0.10 0.10 0.08 0.08 0.06 0.06 0.04 0.04 R) R) % of FS 0.002 FULL-SCALE ERROR % of FS 0.002 GAIN ERROR R ( GAIN ERROR R ( RO–0.02 RO–0.02 FULL-SCALE ERROR R R E–0.04 E–0.04 –0.06 –0.06 –0.08 VDD = 5V –0.08 TA = 25°C INTERNAL REFERENCE = 2.5V INTERNAL REFERENCE = 2.5V –0.10–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 11256-127 –0.102.7 3.2 S3U.7PPLY VO4L.T2AGE (V)4.7 5.2 11256-129 Figure 22. Gain Error and Full-Scale Error vs. Temperature Figure 25. Zero-Code Error and Offset Error vs. Supply Voltage Rev. B | Page 13 of 28

AD5689R/AD5687R Data Sheet R) 00..1009 VINDTDE =R N5VAL REFERENCE = 2.5V 25 VTEADX DT= E =2R 55N°VCAL S REFERENCE = 2.5V of F 0.08 20 % R ( 0.07 O R 0.06 R 15 ED E 0.05 HITS T US 0.04 10 J D A 0.03 N U AL 0.02 5 T O T 0.01 0 0–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 11256-131 540 560 580IDD (µA)600 620 640 11256-135 Figure 26. Total Unadjusted Error (TUE) vs. Temperature Figure 29. IDD Histogram with External Reference, VDD = 5 V R) 00..1008 30 VTINADT D=E =R2 5N5°VACL S REFERENCE = 2.5V of F 0.06 25 % OR ( 0.04 20 R 0.02 R ED E 0 HITS 15 T US–0.02 J D 10 A–0.04 N U AL –0.06 5 T TO–0.08 ITNAT =E R25N°ACL REFERENCE = 2.5V 0 –0.102.7 3.2 S3U.7PPLY VO4L.T2AGE (V)4.7 5.2 11256-132 1000 1020 1040 106ID0D (µA10)80 1100 1120 1140 11256-136 Figure 27. TUE vs. Supply, Gain = 1 Figure 30. IDD Histogram with Internal Reference, VREF = 2.5 V, Gain = 2 0 1.0 R)–0.01 0.8 S of F–0.02 0.6 (% –0.03 0.4 R SINKING 2.7V O RR–0.04 V) 0.2 SINKING 5V EDE–0.05 (OUT 0 T V US–0.06 ∆ –0.2 J D A–0.07 –0.4 SOURCING 5V N U AL–0.08 –0.6 TOT–0.09 TVADD==255°VC –0.8 SOURCING 2.7V INTERNALREFERENCE=2.5V –0.10 –1.0 0 10000 20000 300C0O0DE 40000 50000 6000065535 11256-030 0 5 1L0OAD CUR1R5ENT (mA2)0 25 30 11256-033 Figure 28. TUE vs. Code Figure 31. Headroom/Footroom vs. Load Current Rev. B | Page 14 of 28

Data Sheet AD5689R/AD5687R 7 2.5008 VDD = 5V 6 TA = 25°C GAIN = 2 REFERENCE = 2.5V FULL SCALE 5 2.5003 4 THREE-QUARTER SCALE (V)UT 3 MIDSCALE (V)UT 2.4998 O 2 O V V ONE-QUARTER SCALE 1 0 ZERO SCALE 2.4993 CTAH A= N2N5°ECL B VDD = 5.25V INTERNAL REFERENCE –1 POSITIVE MAJOR CODE TRANSITION ENERGY = 0.227206nV-sec –2 2.4988 –0.06 –0.04 –0.0L2OAD CU0RRENT (A0).02 0.04 0.06 11256-034 0 2 4 TIME6 (µs) 8 10 12 11256-037 Figure 32. Source and Sink Capability at 5 V, Gain = 2 Figure 35. Digital-to-Analog Glitch Impulse 5 VTAD D= =2 53°VC T 4 GAIN = 1 EXTERNAL REFERENCE = 2.5V 3 0xFFFF V) 2 0xC000 (OUT 0x8000 1 V 1 0x4000 0x0000 0 –1 VDD = 5V TA = 25°C –2–60 –40 –20 IOUT0 (mA) 20 40 60 11256-139 CEHX1 T2EµRVNAL REFERENCE = 2.5MV1.0s A CH1 802mV 11256-146 Figure 33. Source and Sink Capability at 3 V, Gain = 1 Figure 36. 0.1 Hz to 10 Hz Output Noise Plot, External Reference 1.4 T mA) 1.2 FULL SCALE ( T EN 1.0 ZEROCODE R R U C 0.8 Y PL EXTERNALREFERENCE, FULL SCALE 1 P 0.6 U S 0.4 0.2 VDD = 5V TA = 25°C 0 INTERNAL REFERENCE = 2.5V –40 10 TEMPERATURE6(0°C) 110 11256-036 CH1 2µV M1.0s A CH1 802mV 11256-147 Figure 34. Supply Current vs. Temperature Figure 37. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference Rev. B | Page 15 of 28

AD5689R/AD5687R Data Sheet 1600 0 VDD=5V FULL SCALE TA=25°C MIDSCALE 1400 INTERNALREFERENCE=2.5V ZERO SCALE –10 1200 Hz) 1000 H (dB) –20 (nV/ 800 WIDT –30 D D S N N 600 A B –40 400 –50 200 VDD = 5V TA = 25°C REFERENCE = 2.5V, ±0.1V p-p 010 100 FR1kEQUENCY1(H0kz) 100k 1M 11256-040 –6010k 100kFREQUENCY (Hz)1M 10M 11256-042 Figure 38. Noise Spectral Density (NSD) Figure 40. Multiplying Bandwidth, External Reference = 2.5 V, ±0.1 V p-p, 10 kHz to 10 MHz 20 VDD = 5V 0 TA = 25°C REFERENCE = 2.5V –20 –40 V) –60 B D (d –80 H T –100 –120 –140 –160 –180 0 2000 4000 6000 F8R00E0QU10E0N0C0Y1 2(H00z0)14000160001800020000 11256-041 Figure 39. Total Harmonic Distortion at 1 kHz Rev. B | Page 16 of 28

Data Sheet AD5689R/AD5687R TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Output Voltage Settling Time For the DAC, relative accuracy or integral nonlinearity is a Output voltage settling time is the amount of time it takes for measurement of the maximum deviation, in LSBs, from a straight the output of a DAC to settle to a specified level for a ¼ to ¾ line passing through the endpoints of the DAC transfer function. full-scale input change and is measured from the rising edge Typical INL vs. code plots are shown in Figure 14 and Figure 17. of SYNC. Differential Nonlinearity (DNL) Digital-to-Analog Glitch Impulse Differential nonlinearity is the difference between the measured Digital-to-analog glitch impulse is the impulse injected into the change and the ideal 1 LSB change between any two adjacent analog output when the input code in the DAC register changes codes. A specified differential nonlinearity of ±1 LSB maximum state. It is normally specified as the area of the glitch in nV-sec, ensures monotonicity. This DAC is guaranteed monotonic by and is measured when the digital input code is changed by 1 LSB design. Typical DNL vs. code plots are shown in Figure 15 and at the major carry transition (0x7FFF to 0x8000) (see Figure 35). Figure 18. Digital Feedthrough Zero-Code Error Digital feedthrough is a measure of the impulse injected into the Zero-code error is a measurement of the output error when analog output of the DAC from the digital inputs of the DAC, zero code (0x0000) is loaded to the DAC register. Ideally, the but it is measured when the DAC output is not updated. It is output should be 0 V. The zero-code error is always positive in specified in nV-sec and measured with a full-scale code change the device because the output of the DAC cannot go below 0 V on the data bus, that is, from all 0s to all 1s and vice versa. due to a combination of the offset errors in the DAC and the Reference Feedthrough output amplifier. Zero-code error is expressed in mV. A plot of Reference feedthrough is the ratio of the amplitude of the signal zero-code error vs. temperature is shown in Figure 23. at the DAC output to the reference input when the DAC output Full-Scale Error is not being updated. It is expressed in dB. Full-scale error is a measurement of the output error when full- Noise Spectral Density (NSD) scale code (0xFFFF) is loaded to the DAC register. Ideally, the NSD is a measurement of the internally generated random noise. output should be V − 1 LSB. Full-scale error is expressed in DD Random noise is characterized as a spectral density (nV/√Hz). percent of full-scale range (% of FSR). A plot of full-scale error It is measured, in nV/√Hz, by loading the DAC to midscale and vs. temperature is shown in Figure 22. measuring noise at the output. A noise spectral density plot is Gain Error shown in Figure 38. Gain error is a measure of the span error of the DAC. It is the DC Crosstalk deviation in slope of the DAC transfer characteristic from the DC crosstalk is the dc change in the output level of one DAC in ideal and is expressed as % of FSR. response to a change in the output of another DAC. It is Offset Error Drift measured with a full-scale output change on one DAC (or soft Offset error drift is a measurement of the change in offset error power-down and power-up) while monitoring another DAC kept with a change in temperature. It is expressed in μV/°C. at midscale. It is expressed in μV. Gain Temperature Coefficient DC crosstalk due to load current change is a measure of the Gain temperature coefficient is a measurement of the change in impact that a change in load current on one DAC has to gain error with changes in temperature. It is expressed in ppm another DAC kept at midscale. It is expressed in μV/mA. of FSR/°C. Digital Crosstalk Offset Error Digital crosstalk is the glitch impulse transferred to the output Offset error is a measure of the difference between VOUT (actual) of one DAC at midscale in response to a full-scale code change and VOUT (ideal) expressed in mV in the linear region of the (all 0s to all 1s and vice versa) in the input register of another DAC. transfer function. Offset error is measured on the device with It is measured in standalone mode and expressed in nV-sec. Code 512 loaded in the DAC register. It can be negative or Analog Crosstalk positive. Analog crosstalk is the glitch impulse transferred to the output DC Power Supply Rejection Ratio (PSRR) of one DAC due to a change in the output of another DAC. It is PSRR indicates how the output of the DAC is affected by changes measured by loading one of the input registers with a full-scale in the supply voltage. It is the ratio of the change in VOUT to a code change (all 0s to all 1s and vice versa). Then execute a change in VDD for full-scale output of the DAC. It is measured software LDAC and monitor the output of the DAC whose in mV/V. VREF is held at 2 V, and VDD is varied by ±10%. digital code was not changed. The area of the glitch is expressed in nV-sec. Rev. B | Page 17 of 28

AD5689R/AD5687R Data Sheet DAC-to-DAC Crosstalk reference for the DAC, and the THD is a measurement of the DAC-to-DAC crosstalk is the glitch impulse transferred to the harmonics present on the DAC output. It is measured in dB. output of one DAC due to a digital code change and subsequent Voltage Reference Temperature Coefficient analog output change of another DAC. It is measured by loading Voltage reference TC is a measure of the change in the reference the attack channel with a full-scale code change (all 0s to all 1s output voltage with a change in temperature. The reference TC and vice versa), using the write to and update commands while is calculated using the box method, which defines the TC as the monitoring the output of the victim channel that is at midscale. maximum change in the reference output over a given tempera- The energy of the glitch is expressed in nV-sec. ture range expressed in ppm/°C, as follows; Multiplying Bandwidth  V V  The amplifiers within the DAC have a finite bandwidth. The TC REFmax REFmin 106 multiplying bandwidth is a measure of this. A sine wave on the VREFnomTempRange reference (with full-scale code loaded to the DAC) appears on where: the output. The multiplying bandwidth is the frequency at V is the maximum reference output measured over the which the output amplitude falls to 3 dB below the input. REFmax total temperature range. Total Harmonic Distortion (THD) V is the minimum reference output measured over the total REFmin THD is the difference between an ideal sine wave and its temperature range. attenuated version using the DAC. The sine wave is used as the V is the nominal reference output voltage, 2.5 V. REFnom TempRange is the specified temperature range of −40°C to +105°C. Rev. B | Page 18 of 28

Data Sheet AD5689R/AD5687R THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTERS The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of The AD5689R/AD5687R are dual 16-/12-bit, serial input, resistors, it is guaranteed monotonic. voltage output DACs with an internal reference. The parts operate from supply voltages of 2.7 V to 5.5 V. Data is written VREF to the AD5689R/AD5687R in a 24-bit word format via R a 3-wire serial interface. The devices incorporate a power-on reset circuit to ensure that the DAC output powers up to a known output state. The AD5689R/AD5687R also have R a software power-down mode that reduces the typical current consumption to 4 μA. R TO OUTPUT AMPLIFIER TRANSFER FUNCTION The internal reference is on by default. To use an external reference, only a nonreference option is available. Because the input coding to the DAC is straight binary, the ideal R output voltage when using an external reference is given by  D V V Gain R where:O UT REF 2N 11256-044 Figure 42. Resistor String Structure Gain is the output amplifier gain and is set to 1 by default. Internal Reference It can be set to ×1 or ×2 using the gain select pin. When the GAIN pin is tied to GND, both DACs output a span from The AD5689R/AD5687R on-chip reference is on at power-up 0 V to V . If the GAIN pin is tied to V , both DACs but can be disabled via a write to a control register. See the REF LOGIC output a span of 0 V to 2 × V . Internal Reference Setup section for details. REF D is the decimal equivalent of the binary code that is The AD5689R/AD5687R have a 2.5 V, 2 ppm/°C reference, loaded to the DAC register as follows: 0 to 4,095 for the giving a full-scale output of 2.5 V or 5 V, depending on the state 12-bit device and 0 to 65,535 for the 16-bit device. of the GAIN pin. The internal reference associated with the N is the DAC resolution. device is available at the V pin. This buffered reference is REF DAC ARCHITECTURE capable of driving external loads of up to 10 mA. The DAC architecture consists of a string DAC followed by Output Amplifiers an output amplifier. Figure 41 shows a block diagram of the The output buffer amplifier can generate rail-to-rail voltages on DAC architecture. its output, which gives an output range of 0 V to V . The actual DD VREF range depends on the value of VREF, the GAIN pin, the offset 2.5V error, and the gain error. The GAIN pin selects the gain of the REF output, as follows: REF (+) REINGPISUTTER REGDIASCTER RSETSRISINTOGR VOUTX  Iaf gtahien G oAf 1IN, a npdin t hise t ioeudt ptou tG rNanDg,e b ios t0h V D tAoC V out.p uts have REF (–) REF GND (GAING =A I1N OR 2) 11256-043  aIf gtahien G oAf 2IN, a npdin t hise t ioeudt ptou tV rLaOnGgICe, ibso 0t hV D toA C2 ×o uVtpREuFt. s have Figure 41. Single DAC Channel Architecture Block Diagram These amplifiers are capable of driving a load of 1 kΩ in parallel The resistor string structure is shown in Figure 42. It is a with 2 nF to GND. The slew rate is 0.8 V/μs with a ¼ to ¾ scale string of resistors, each of Value R. The code loaded to the settling time of 5 μs. DAC register determines the node on the string where the voltage is to be tapped off and fed into the output amplifier. Rev. B | Page 19 of 28

AD5689R/AD5687R Data Sheet SERIAL INTERFACE The data-word comprises 16-bit or 12-bit input code, followed by zero don’t care bits (for the AD5689R) or four don’t care bits The AD5689R/AD5687R have a 3-wire serial interface (for the AD5687R), as shown in Figure 43 and Figure 44, respec- (SYNC, SCLK, and SDIN) that is compatible with SPI, QSPI™, tively). These data bits are transferred to the input shift register and MICROWIRE® interface standards as well as most DSPs. on the 24 falling edges of SCLK and updated on the rising edge See Figure 2 for a timing diagram of a typical write sequence. of SYNC. The AD5689R/AD5687R contain an SDO pin that allows the user to daisy-chain multiple devices together (see the Commands can be executed on individual DAC channels or on Daisy-Chain Operation section) or read back data. both DAC channels, depending on the address bits selected. Input Shift Register Table 8. Address Commands The input shift register of the AD5689R/AD5687R is 24 bits Address (n) wide, and data is loaded MSB first (DB23). The first four bits DAC B 0 0 DAC A Selected DAC Channel are the command bits, C3 to C0 (see Table 9), followed by 0 0 0 1 DAC A the 4-bit DAC address bits, composed of DAC B, DAC A, 1 0 0 0 DAC B and two don’t care bits that must be set to 0 (see Table 8). 1 0 0 1 DAC A and DAC B Finally, the data-word completes the input shift register. Table 9. Command Definitions Command C3 C2 C1 C0 Description 0 0 0 0 No operation 0 0 0 1 Write to Input Register n (dependent on LDAC) 0 0 1 0 Update DAC Register n with contents of Input Register n 0 0 1 1 Write to and update DAC Channel n 0 1 0 0 Power down/power up DAC 0 1 0 1 Hardware LDAC mask register 0 1 1 0 Software reset (power-on reset) 0 1 1 1 Internal reference setup register 1 0 0 0 Set up DCEN register (daisy-chain enable) 1 0 0 1 Set up readback register (readback enable) 1 0 1 0 Reserved … … … … Reserved 1 1 1 1 No operation in daisy-chain mode DB23 (MSB) DB0 (LSB) DAC DAC C3 C2 C1 C0 B 0 0 A D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS COMMAND BITS ADDRESS BITS 11256-045 Figure 43. AD5689R Input Shift Register Content DB23 (MSB) DB0 (LSB) DAC DAC C3 C2 C1 C0 B 0 0 A D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DATA BITS COMMAND BITS ADDRESS BITS 11256-046 Figure 44. AD5687R Input Shift Register Content Rev. B | Page 20 of 28

Data Sheet AD5689R/AD5687R STANDALONE OPERATION AD5689R/ 68HC11* AD5687R The write sequence begins by bringing the SYNC line low. Data from the SDIN line is clocked into the 24-bit input shift register MOSI SDIN on the falling edge of SCLK. After the last of 24 data bits is clocked SCK SCLK in, SYNC is brought high. The programmed function is then PC7 SYNC executed; that is, an LDAC-dependent change in DAC register PC6 LDAC MISO SDO contents and/or a change in the mode of operation occurs. If SYNC is taken high at a clock before the 24th clock, it is considered a valid frame and invalid data may be loaded to the DAC. SYNC SDIN AD5689R/ must be brought high for a minimum of 20 ns (single channel, AD5687R see t in Figure 2) before the next write sequence so that a 8 SCLK falling edge of SYNC can initiate the next write sequence. Idle SYNC SYNC at the rails between write sequences for an even lower LDAC power operation of the part. The SYNC line is kept low for 24 SDO falling edges of SCLK, and the DAC is updated on the rising edge of SYNC. When the data has been transferred into the input register of SDIN AD5689R/ the addressed DAC, both DAC registers and outputs can be AD5687R updated by taking LDAC low while the SYNC line is high. SCLK WRITE AND UPDATE COMMANDS SYNC Write to Input Register n (Dependent on LDAC) LDAC SDO Command 0001 allows the user to write to the dedicated input rreeggiisstteerr iosf teraacnhs pDaAreCn ti n(idf invoidt ucaolnlyt.r Wollheden b Ly DthAeC L DisA loCw m, thasek i nput *ADDITIONAL PINS OMITTED FOR CLARITY. 11256-047 register). Figure 45. Daisy-Chaining Multiple AD5689R/AD5687R Devices Update DAC Register n with Contents of Input Register n The SCLK pin is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the Command 0010 loads the DAC registers/outputs with the data ripples out of the input shift register and appears on the contents of the input registers selected and updates the DAC SDO line. This data is clocked out on the rising edge of SCLK outputs directly. and is valid on the falling edge. By connecting this line to the Write to and Update DAC Channel n (Independent of LDAC) SDIN input on the next DAC in the chain, a daisy-chain interface Command 0011 allows the user to write to the DAC registers is constructed. Each DAC in the system requires 24 clock pulses. and update the DAC outputs directly. Therefore, the total number of clock cycles must equal 24 × N, DAISY-CHAIN OPERATION where N is the total number of devices that are updated. If SYNC is taken high at a clock that is not a multiple of 24, it is considered For systems that contain several DACs, the SDO pin can be a valid frame, and invalid data may be loaded to the DAC. When used to daisy-chain several devices together. SDO is enabled the serial transfer to all devices is complete, SYNC is taken high. through a software executable daisy-chain enable (DCEN) This latches the input data in each device in the daisy chain and command. Command 1000 is reserved for this DCEN function prevents any further data from being clocked into the input shift (see Table 9). Daisy-chain mode is enabled by setting Bit DB0 in register. The serial clock can be continuous or a gated clock. A the DCEN register. The default setting is standalone mode, continuous SCLK source can be used only if SYNC can be held where DB0 (LSB) = 0. Table 10 shows how the state of the bit low for the correct number of clock cycles. In gated clock mode, corresponds to the mode of operation of the device. a burst clock containing the exact number of clock cycles must Table 10. Daisy-Chain Enable (DCEN) Register be used, and SYNC must be taken high after the final clock to latch DB0 (LSB) Description the data. 0 Standalone mode (default) 1 DCEN mode Rev. B | Page 21 of 28

AD5689R/AD5687R Data Sheet READBACK OPERATION Table 11. Modes of Operation Readback mode is invoked through a software executable read- Operating Mode PDx1 PDx0 back command. If the SDO output is disabled via the daisy-chain Normal Operation Mode 0 0 mode disable bit in the control register, it is automatically enabled Power-Down Modes for the duration of the read operation, after which it is disabled 1 kΩ to GND 0 1 again. Command 1001 is reserved for the readback function in 100 kΩ to GND 1 0 when DCEN is enable. This command, in association with Three-State 1 1 selecting one of the address bits, DAC B or DAC A, selects the When both Bit PDx1 and Bit PDx0 (where x is the channel that is register to be read. Note that only one DAC register can be selected) in the input shift register are set to 0, the parts work selected during readback. The remaining three address bits normally, with a normal power consumption of 4 mA at 5 V. (which include the two don’t care bits) must be set to Logic 0. The However, for the three power-down modes of the AD5689R/ remaining data bits in the write sequence are ignored. If more AD5687R, the supply current falls to 4 μA at 5 V. Not only does than one address bit is selected or no address bit is selected, DAC the supply current fall, but the output stage is also internally Channel A is read back by default. During the next SPI write, the switched from the output of the amplifier to a resistor network data that appears on the SDO output contains the data from the of known values. This switchover has the advantage that the output previously addressed register. impedance of the part is known while the part is in power-down For example, to read back the DAC register for Channel A, mode. The three power-down options are as follows: implement the following sequence:  The output is connected internally to GND through a 1 kΩ 1. Write 0x900000 to the AD5689R/AD5687R input register. resistor. This setting configures the part for read mode with the  The output is connected internally to GND through a 100 kΩ Channel A DAC register selected. Note that all data bits, resistor. DB15 to DB0, are don’t care bits.  The output is left open-circuited (three-state). 2. Follow this write operation with a second write, a nop operation, 0x000000 (0xF00000 in daisy-chain mode). The output stage is illustrated in Figure 46. During this write, the data from the register is clocked out on the SDO line. DB23 to DB20 contain undefined data, and the last 16 bits contain the DB19 to DB4 DAC register DAC AMPLIFIER VOUTX contents. POWER-DOWN OPERATION POWER-DOWN The AD5689R/AD5687R contain three separate power-down CIRCUITRY NREETSWISOTORRK mTaobdlee s9. )C. oTmhemsea npdo w01e0r-0d coownntr omlso tdhees p aorwe esro-fdtowwanre f-upnrcotgioranm (smeea ble 11256-048 Figure 46. Output Stage During Power-Down by setting eight bits, Bit DB7 to Bit DB0, in the input shift register. The bias generator, output amplifier, resistor string, and other There are two bits associated with each DAC channel. Table 11 associated linear circuitry are shut down when the power-down explains how the state of the two bits corresponds to the mode of mode is activated. However, the contents of the DAC register operation of the device. are unaffected when in power-down, and the DAC register can Either or both DACs (DAC B, DAC A) can be powered down to be updated while the device is in power-down mode. The time the selected mode by setting the corresponding bits. See Table 12 that is required to exit power-down is typically 4.5 μs for V = 5 V. DD for the contents of the input shift register during the power-down/ To further reduce the current consumption, the on-chip reference power-up operation. can be powered off (see the Internal Reference Setup section). Table 12. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation1 DB23 DB0 (MSB) DB22 DB21 DB20 DB19 to DB16 DB15 to DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 (LSB) 0 1 0 0 X X PDB1 PDB0 1 1 1 1 PDA1 PDA0 Command bits (C3 to C0) Address bits; don’t care Power-down, Set to 1 Set to 1 Power-down, select DAC B select DAC A 1 X = don’t care. Rev. B | Page 22 of 28

Data Sheet AD5689R/AD5687R LOAD DAC (HARDWARE LDAC PIN) updated by taking LDAC low after SYNC is taken high. The update then occurs on the falling edge of LDAC. The AD5689R/AD5687R DACs have double buffered interfaces consisting of two banks of registers: input registers and DAC LDAC MASK REGISTER registers. The user can write to any combination of the input Command 0101 is reserved for a software LDAC mask function, registers. Updates to the DAC register are controlled by the which allows the address bits to be ignored. A write to the DAC, LDAC pin. using Command 0101, loads the 4-bit LDAC mask register (DB3 OUTPUT to DB0). The default setting for each channel is 0; that is, the AMPLIFIER LDAC pin works normally. Setting the selected bit to 1 forces the VREF 16-/1D2-ABCIT VOUTX DAC channel to ignore transitions on the LDAC pin, regardless of the state of the hardware LDAC pin. This flexibility is useful in applications where the user wishes to select which channels DAC LDAC REGISTER respond to the LDAC pin. The LDAC mask register gives the user extra flexibility and control over the hardware LDAC pin (see Table 13). Setting an LDAC INPUT REGISTER bit (DB3, DB0) to 0 for a DAC channel means that the update of this channel is controlled by the hardware LDAC pin. SCLK Table 13. LDAC Overwrite Definition INTERFACE SSYDNICN LOGIC SDO 11256-049 LDLAoCa dB iLtDs AC Register Figure 47. Simplified Diagram of Input Loading Circuitry for a Single DAC (DB3, DB0) LDAC Pin LDAC Operation Instantaneous DAC Updating (LDAC Held Low) 0 1 or 0 Determined by the LDAC pin. LDAC is held low while data is clocked into the input register 1 X1 DAC channels update and override the LDAC pin. DAC channels see the using Command 0001. Both the addressed input register and LDAC pin as set to 1. the DAC register are updated on the rising edge of SYNC, and then the output begins to change (see Table 14 and Table 15). 1 X = don’t care. Deferred DAC Updating (LDAC Pulsed Low) LDAC is held high while data is clocked into the input register using Command 0001. Both DAC outputs are asynchronously Table 14. 24-Bit Input Shift Register Contents for LDAC Operation1 DB23 DB0 (MSB) DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB4 DB3 DB2 DB1 (LSB) 0 1 0 1 X X X X X DAC B 0 0 DAC A Command bits (C3 to C0) Address bits, don’t care Don’t care Setting the LDAC bit to 1 overrides the LDAC pin 1 X = don’t care. Table 15. Write Commands and LDAC Pin Truth Table1 Hardware LDAC Command Description Pin State Input Register Contents DAC Register Contents 0001 Write to Input Register n V Data update No change (no update) LOGIC (dependent on LDAC) GND2 Data update Data update 0010 Update DAC Register n with V No change Updated with input register contents LOGIC contents of Input Register n GND No change Updated with input register contents 0011 Write to and update DAC Channel n V Data update Data update LOGIC GND Data update Data update 1 A high-to-low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked (blocked) by the LDAC mask register. 2 When the LDAC pin is permanently tied low, the LDAC mask bits are ignored. Rev. B | Page 23 of 28

AD5689R/AD5687R Data Sheet HARDWARE RESET (RESET) SOLDER HEAT REFLOW RESET is an active low reset that allows the outputs to be cleared As with all IC reference voltage circuits, the reference value to either zero scale or midscale. The clear code value is user experiences a shift induced by the soldering process. Analog selectable via the power-on reset select pin (RSTSEL). RESET Devices, Inc., performs a reliability test, called precondition, that mimics the effect of soldering a device to a board. The must be kept low for a minimum amount of time to complete output voltage specification that is listed in Table 2 includes the the operation (see Figure 2). When the RESET signal is returned effect of this reliability test. high, the output remains at the cleared value until a new value is programmed. The outputs cannot be updated with a new value Figure 48 shows the effect of solder heat reflow (SHR) as while the RESET pin is low. There is also a software executable measured through the reliability test (precondition). reset function that resets the DAC to the power-on reset code. POSTSOLDER Command 0110 is designated for this software reset function 60 HEATREFLOW PRESOLDER (see Table 9). Any events on LDAC during a power-on reset are HEATREFLOW 50 ignored. If the RESET pin is pulled low at power-up, the device does not initialize correctly until the pin is released. 40 RESET SELECT PIN (RSTSEL) S T HI 30 The AD5689R/AD5687R contain a power-on reset circuit that controls the output voltage during power-up. When the RSTSEL 20 pin is connected low (to GND), the output powers up to zero scale. Note that this is outside the linear region of the DAC. 10 When the RSTSEL pin is connected high (to V ), V X LOGIC OUT 0 powers up to midscale. The output remains powered up at this level until a valid write sequence is sent to the DAC. 2.498 2.499 V2R.E5F00(V) 2.501 2.502 11256-050 To ensure that the RSTSEL pin functions correctly, a power Figure 48. SHR Reference Voltage Shift sequence must be followed. Power up VLOGIC first, before VDD; LONG-TERM TEMPERATURE DRIFT otherwise, V remains at zero scale. OUT Figure 49 shows the change in the V (ppm) value after REF INTERNAL REFERENCE SETUP 1000 hours at 25°C ambient temperature. 140 Command 0111 is reserved for setting up the internal reference (see Table 9). By default, the on-chip reference is on at power-up. 120 To reduce the supply current, this reference can be turned off by setting the software-programmable bit, DB0, as shown in Table 17. 100 Table 16 shows how the state of the bit corresponds to the mode 80 of operation. 60 Table 16. Reference Setup Register Internal Reference 40 Setup Register (DB0) Action 0 Reference on (default) 20 1 Reference off 0 –20 0 100 200 300 400 500 600 700 800 900 1000 11256-155 Figure 49. Reference Drift Through to 1000 Hours Table 17. 24-Bit Input Shift Register Contents for Internal Reference Setup Command1 DB23 (MSB) DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0 (LSB) 0 1 1 1 X X X X X 1 or 0 Command bits (C3 to C0) Address bits (A3 to A0) Don’t care Reference setup register 1 X = don’t care. Rev. B | Page 24 of 28

Data Sheet AD5689R/AD5687R 9 THERMAL HYSTERESIS FIRST TEMPERATURESWEEP 8 SUBSEQUENT TEMPERATURESWEEPS Thermal hysteresis is the voltage difference induced on the refer- ence voltage by sweeping the temperature from ambient to cold, 7 to hot, and then back to ambient. 6 Thermal hysteresis data is shown in Figure 50. It is measured 5 S by sweeping the temperature from ambient to −40°C, next to HIT 4 +105°C, and then returning to ambient. The VREF delta is then measured between the two ambient measurements and shown 3 in blue in Figure 50. The same temperature sweep and measure- 2 ments are immediately repeated and the results are shown in 1 red in Figure 50. 0 –200 –150 D–IS10T0ORTION(–p5p0m) 0 50 11256-052 Figure 50. Thermal Hysteresis Rev. B | Page 25 of 28

AD5689R/AD5687R Data Sheet APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Microprocessor interfacing to the AD5689R/AD5687R is achieved via a serial bus using a standard protocol that is compatible with In systems where there are many devices on one board, it is DSP processors and microcontrollers. The communications often useful to provide some heat sinking capability to allow channel requires a 3-wire or 4-wire interface consisting of a the power to dissipate easily. clock signal, a data signal, and a synchronization signal. Each Each AD5689R or AD5687R has an exposed paddle beneath the device requires a 24-bit data-word with data valid on the rising device. Connect this paddle to the GND supply for the part. For edge of SYNC. optimum performance, use special considerations to design the AD5689R/AD5687R TO ADSP-BF531 INTERFACE motherboard and to mount the package. For enhanced thermal, electrical, and board level performance, solder the exposed paddle The SPI interface of the AD5689R/AD5687R is designed to be on the bottom of the package to the corresponding thermal land easily connected to industry-standard DSPs and microcontrollers. paddle on the PCB. Design thermal vias into the PCB land paddle Figure 51 shows the AD5689R/AD5687R connected to an Analog area to further improve heat dissipation. Devices Blackfin® DSP. The Blackfin has an integrated SPI port that connects directly to the SPI pins of the AD5689R/AD5687R. The GND plane on the device can be increased (as shown in Figure 53) to provide a natural heat sinking effect. AD5689R/ AD5687R AD5689R/ AD5687R ADSP-BF531 SPISELx SYNC SCK SCLK MOSI SDIN GND PPFF98 LRDEASCET 11256-053 PLANE Figure 51. ADSP-BF531 Interface to the AD5689R/AD5687R AD5689R/AD5687R TO SPORT INTERFACE BOARD 11256-055 Figure 53. Paddle Connection to Board The Analog Devices ADSP-BF527 has one SPORT serial port. Figure 52 shows how one SPORT interface can be used to GALVANICALLY ISOLATED INTERFACE control the AD5689R/AD5687R. In many process control applications, it is necessary to provide AD5689R/ an isolation barrier between the controller and the unit being AD5687R controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. The ADSP-BF527 iCoupler® products from Analog Devices provide voltage isolation SPORT_TFS SYNC in excess of 2.5 kV. The serial loading structure of the AD5689R/ SPORT_TSCK SCLK AD5687R makes these parts ideal for isolated interfaces because SPORT_DTO SDIN the number of interface lines is kept to a minimum. Figure 54 GGPPIIOO01 LRDEASCET 11256-054 suhsoinwgs aan 4 A-cDhaunMn1e4l 0is0o.l Fatoerd a idndteitrifoancea lt ion tfhoerm AaDti5o6n8, 9vRis/iAt D5687R Figure 52. SPORT Interface to the AD5689R/AD5687R www.analog.com/icouplers. LAYOUT GUIDELINES CONTROLLER ADuM14001 In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the CLSOECRKIA INL VIA ENCODE DECODE VOA TSOCLK rated performance. Design the PCB on which the AD5689R/ AD5687R are mounted so that the AD5689R/AD5687R lie on DATSAE ROIAULT VIB ENCODE DECODE VOB TSODIN the analog plane. Provide the AD5689R/AD5687R with ample supply bypassing SYNC OUT VIC ENCODE DECODE VOC TO of 10 μF in parallel with 0.1 μF on each supply, located as close SYNC tToh teh 1e0 p μaFck caagpea caist opro isss oibf lteh,e i dtaenatlalylu rmig bhet audp t aygpaei. nUsste t ha e0 .d1e μvFic cea. pa- LOAD DOAUCT VID ENCODE DECODE VOD TLODAC citor with low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, 1ADDITIONAL PINS OMITTED FOR CLARITY. 11256-056 Figure 54. Isolated Interface Rev. B | Page 26 of 28

Data Sheet AD5689R/AD5687R OUTLINE DIMENSIONS 3.10 0.30 3.00 SQ 0.23 PIN 1 2.90 0.18 INDICATOR PIN 1 0.50 13 16 INDICATOR BSC 12 1 EXPOSED 1.75 PAD 1.60 SQ 1.45 9 4 0.50 8 5 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 0.80 FOR PROPER CONNECTION OF 0.75 THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANTTOJEDEC STANDARDS MO-220-WEED-6. 08-16-2010-E Figure 55. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 0.65 0.19 SEATING 0° 0.45 BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 56. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. B | Page 27 of 28

AD5689R/AD5687R Data Sheet ORDERING GUIDE Reference Temperature Tempco Package Package Model1 Resolution Range Accuracy (ppm/°C) Description Option Branding AD5689RACPZ-RL7 16 Bits −40°C to +105°C ±8 LSB INL ±5 (typ) 16-Lead LFCSP_WQ CP-16-22 DLU AD5689RBCPZ-RL7 16 Bits −40°C to +105°C ±2 LSB INL ±5 (max) 16-Lead LFCSP_WQ CP-16-22 DL2 AD5689RARUZ 16 Bits −40°C to +105°C ±8 LSB INL ±5 (typ) 16-Lead TSSOP RU-16 AD5689RARUZ-RL7 16 Bits −40°C to +105°C ±8 LSB INL ±5 (typ) 16-Lead TSSOP RU-16 AD5689RBRUZ 16 Bits −40°C to +105°C ±2 LSB INL ±5 (max) 16-Lead TSSOP RU-16 AD5689RBRUZ-RL7 16 Bits −40°C to +105°C ±2 LSB INL ±5 (max) 16-Lead TSSOP RU-16 AD5687RBCPZ-RL7 12 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead LFCSP_WQ CP-16-22 DL1 AD5687RBRUZ 12 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead TSSOP RU-16 AD5687RBRUZ-RL7 12 Bits −40°C to +105°C ±1 LSB INL ±5 (max) 16-Lead TSSOP RU-16 EVAL-AD5687RSDZ Evaluation Board EVAL-AD5689RSDZ Evaluation Board 1 Z = RoHS Compliant Part. ©2013–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11256-0-3/17(B) Rev. B | Page 28 of 28