Quad, 16-/12-Bit nanoDAC+ with SPI Interface Data Sheet AD5686/AD5684 FEATURES FUNCTIONAL BLOCK DIAGRAM High relative accuracy (INL): ±2 LSB maximum @ 16 bits VDD GND VREF Tiny package: 3 mm × 3 mm, 16-lead LFCSP AD5686/AD5684 Total unadjusted error (TUE): ±0.1% of FSR maximum VLOGIC Offset error: ±1.5 mV maximum REINGPISUTTER REGDIASCTER SDTARCIN AG VOUTA Gain error: ±0.1% of FSR maximum SCLK BUFFER C High drive capability: 20 mA, 0.5 V from supply rails SYNC LOGI REINGPISUTTER REGDIASCTER SDTARCIN BG VOUTB User selectable gain of 1 or 2 (GAIN pin) CE BUFFER A R1.e8s Vet l toog zice croo mscpaaleti obril mityid scale (RSTSEL pin) SDIN INTERF REINGPISUTTER REGDIASCTER SDTARCIN CG BUFFER VOUTC 50 MHz SPI with readback or daisy chain SDO Low glitch: 0.5 nV-sec REINGPISUTTER REGDIASCTER SDTARCIN DG VOUTD BUFFER Low power: 1.8 mW at 3 V POWER-ON GAIN POWER- RESET ×1/×2 DOWN 2−.470 V°C t oto 5 +.51 V0 5p°oCw teemr spueprpaltyu re range LDAC RESET RSTSEL GAIN LOGIC 10797-001 APPLICATIONS Figure 1. Digital gain and offset adjustment Programmable attenuators Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5686/AD5684, members of the nanoDAC+™ family, are Table 1. Quad nanoDAC+ Devices low power, quad, 16-/12-bit buffered voltage output DACs. Interface Reference 16-Bit 14-Bit 12-Bit The devices include a gain select pin giving a full-scale output SPI Internal AD5686R AD5685R AD5684R of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from SPI External AD5686 AD5684 a single 2.7 V to 5.5 V supply, are guaranteed monotonic by I2C Internal AD5696R AD5695R AD5694R design, and exhibit less than 0.1% FSR gain error and 1.5 mV I2C External AD5696 AD5694 offset error performance. The devices are available in a 3 mm × 3 mm LFCSP and a TSSOP package. PRODUCT HIGHLIGHTS The AD5686/AD5684 also incorporate a power-on reset circuit 1. High Relative Accuracy (INL). and a RSTSEL pin that ensures that the DAC outputs power up AD5686 (16-bit): ±2 LSB maximum to zero scale or midscale and remain at that level until a valid AD5684 (12-bit): ±1 LSB maximum write takes place. Each part contains a per-channel power-down 2. Excellent DC Performance. feature that reduces the current consumption of the device to Total unadjusted error: ±0.1% of FSR maximum 4 µA at 3 V while in power-down mode. Offset error: ±1.5 mV maximum The AD5686/AD5684 employ a versatile SPI interface that Gain error: ±0.1% of FSR maximum operates at clock rates up to 50 MHz, and all devices contain 3. Two Package Options. a VLOGIC pin intended for 1.8 V/3 V/5 V logic. 3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOP Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5686/AD5684 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 19 Applications ....................................................................................... 1 Standalone Operation ................................................................ 20 Functional Block Diagram .............................................................. 1 Write and Update Commands .................................................. 20 General Description ......................................................................... 1 Daisy-Chain Operation ............................................................. 20 Product Highlights ........................................................................... 1 Readback Operation .................................................................. 21 Revision History ............................................................................... 2 Power-Down Operation ............................................................ 21 Specifications ..................................................................................... 3 Load DAC (Hardware LDAC Pin) ........................................... 22 AC Characteristics ........................................................................ 5 LDAC Mask Register ................................................................. 22 Timing Characteristics ................................................................ 6 Hardware Reset (RESET) .......................................................... 23 Daisy-Chain and Readback Timing Characteristics................ 7 Reset Select Pin (RSTSEL) ........................................................ 23 Absolute Maximum Ratings ............................................................ 9 Applications Information .............................................................. 24 ESD Caution .................................................................................. 9 Microprocessor Interfacing ....................................................... 24 Pin Configurations and Function Descriptions ......................... 10 AD5686/AD5684 to ADSP-BF531 Interface .......................... 24 Typical Performance Characteristics ........................................... 11 AD5686/AD5684 to SPORT Interface .................................... 24 Terminology .................................................................................... 16 Layout Guidelines....................................................................... 24 Theory of Operation ...................................................................... 18 Galvanically Isolated Interface ................................................. 25 Digital-to-Analog Converter .................................................... 18 Outline Dimensions ....................................................................... 26 Transfer Function ....................................................................... 18 Ordering Guide .......................................................................... 27 DAC Architecture ....................................................................... 18 REVISION HISTORY 6/2017—Rev. B to Rev. C 3/2015—Rev. A to Rev. B Changes to Features Section 1 ........................................................ 1 Changes to Table 4 and Figure 2 ...................................................... 6 Changes to Table 2 ............................................................................ 3 Inserted Note 2 to Ordering Guide .............................................. 27 Changes to Table 3 ............................................................................ 5 Changes to Table 4 ............................................................................ 6 6/2013—Rev. 0 to Rev. A Changes to Table 5 and Figure 4 ..................................................... 7 Changes to Pin GAIN and Pin RSTSEL Descriptions; Table 7 .. 10 Changes to Figure 5 .......................................................................... 8 Changes to Table 6 ............................................................................ 9 7/2012—Revision 0: Initial Version Change to V Pin Description and RESET Pin Description, LOGIC Table 7 ................................................................................................ 9 Changes to Figure 12 and Figure 13 ............................................. 11 Changes to Figure 14 to Figure 19 ................................................ 12 Changes to Figure 20, Figure 22, and Figure 25 ......................... 13 Changes to Figure 32 ...................................................................... 15 Changes to Table 8 .......................................................................... 19 Changes to Readback Operation Section .................................... 21 Changes to Hardware Reset (RESET) Section ............................ 23 Changes to Ordering Guide .......................................................... 27 Rev. C | Page 2 of 27

Data Sheet AD5686/AD5684 SPECIFICATIONS V = 2.7 V to 5.5 V; V = 2.5 V; 1.62 V ≤ V ≤ 5.5 V; all specifications T to T , unless otherwise noted. R = 2 kΩ; C = 200 pF. DD REF LOGIC MIN MAX L L Table 2. A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE2 AD5686 Resolution 16 16 Bits Relative Accuracy ±2 ±8 ±1 ±2 LSB Gain = 2 ±2 ±8 ±1 ±3 LSB Gain = 1 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design AD5684 Resolution 12 12 Bits Relative Accuracy ±0.12 ±2 ±0.12 ±1 LSB Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design Zero-Code Error 0.4 4 0.4 1.5 mV All 0s loaded to DAC register Offset Error +0.1 ±4 +0.1 ±1.5 mV Full-Scale Error +0.01 ±0.2 +0.01 ±0.1 % of All 1s loaded to DAC register FSR Gain Error ±0.02 ±0.2 ±0.02 ±0.1 % of FSR Total Unadjusted Error ±0.01 ±0.25 ±0.01 ±0.1 % of Gain = 2 FSR ±0.25 ±0.2 % of Gain = 1 FSR Offset Error Drift3 ±1 ±1 µV/°C Gain Temperature ±1 ±1 ppm Of FSR/°C Coefficient3 DC Power Supply Rejection 0.15 0.15 mV/V DAC code = midscale; VDD = 5 V ± 10% Ratio3 DC Crosstalk3 ±2 ±2 µV Due to single channel, full-scale output change ±3 ±3 µV/mA Due to load current change ±2 ±2 µV Due to powering down (per channel) OUTPUT CHARACTERISTICS3 Output Voltage Range 0 VREF 0 VREF V Gain = 1 0 2 × VREF 0 2 × VREF V Gain = 2, see Figure 23 Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 1 kΩ Resistive Load4 1 1 kΩ Load Regulation 80 80 µV/mA 5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT ≤ +30 mA 80 80 µV/mA 3 V ± 10%, DAC code = midscale; −20 mA ≤ IOUT ≤ +20 mA Short-Circuit Current5 40 40 mA Load Impedance at Rails6 25 25 Ω See Figure 23 Power-Up Time 2.5 2.5 µs Coming out of power-down mode; VDD = 5 V REFERENCE INPUT Reference Current 90 90 µA VREF = VDD = VLOGIC = 5.5 V, gain = 1 180 180 µA VREF = VDD = VLOGIC = 5.5 V, gain = 2 Reference Input Range 1 VDD 1 VDD V Gain = 1 1 VDD/2 1 VDD/2 V Gain = 2 Reference Input Impedance 16 16 kΩ Gain = 2 32 32 kΩ Gain = 1 Rev. C | Page 3 of 27

AD5686/AD5684 Data Sheet A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS3 Input Current ±2 ±2 µA Per pin Input Low Voltage (VINL) 0.3 × VLOGIC 0.3 × VLOGIC V Input High Voltage (VINH) 0.7 × VLOGIC 0.7 × VLOGIC V Pin Capacitance 2 2 pF LOGIC OUTPUTS (SDO)3 Output Low Voltage, VOL 0.4 0.4 V ISINK = 200 μA Output High Voltage, VOH VLOGIC − 0.4 VLOGIC − 0.4 V ISOURCE = 200 μA Floating State Output 4 4 pF Capacitance POWER REQUIREMENTS VLOGIC 1.62 5.5 1.62 5.5 V ILOGIC 3 3 µA VDD 2.7 5.5 2.7 5.5 V Gain = 1 VREF + 1.5 5.5 VREF + 1.5 5.5 V Gain = 2 IDD VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V Normal Mode7 0.59 0.7 0.59 0.7 mA All Power-Down Modes8 1 4 1 4 µA −40°C to +85°C 6 6 µA −40°C to +105°C 1 Temperature range, A and B grade: −40°C to +105°C. 2 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 = VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5686) or 12 to 4080 (AD5684). 3 Guaranteed by design and characterization; not production tested. 4 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to 30 mA up to a junction temperature of 110°C. 5 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded during current limit. Operation above the specified maximum operation junction temperature may impair device reliability. 6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 23). 7 Interface inactive. All DACs active. DAC outputs unloaded. 8 All DACs powered down. Rev. C | Page 4 of 27

Data Sheet AD5686/AD5684 AC CHARACTERISTICS V = 2.7 V to 5.5 V; V = 2.5 V; 1.62 V ≤ V ≤ 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; all specifications T to T , unless DD REF LOGIC L L MIN MAX otherwise noted.1 Table 3. Parameter2 Min Typ Max Unit Test Conditions/Comments3 Output Voltage Settling Time AD5686 5 8 µs ¼ to ¾ scale settling to ±2 LSB AD5684 5 7 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 0.8 V/µs Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry Digital Feedthrough 0.13 nV-sec Multiplying Bandwidth 500 kHz Digital Crosstalk 0.1 nV-sec Analog Crosstalk 0.2 nV-sec DAC-to-DAC Crosstalk 0.3 nV-sec Total Harmonic Distortion4 −80 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT Output Noise Spectral Density 100 nV/√Hz DAC code = midscale, 10 kHz; gain = 2, internal reference enabled Output Noise 6 µV p-p 0.1 Hz to 10 Hz SNR 90 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT SFDR 83 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT SINAD 80 dB At ambient, BW = 20 kHz, V = 5 V, f = 1 kHz DD OUT 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical @ 25°C. 4 Digitally generated sine wave @ 1 kHz. Rev. C | Page 5 of 27

AD5686/AD5684 Data Sheet TIMING CHARACTERISTICS All input signals are specified with t = t = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2. See Figure 2. R F DD IL IH V = 2.7 V to 5.5 V, 1.62 V ≤ V ≤ 5.5 V; V = 2.5 V. All specifications T to T , unless otherwise noted. DD LOGIC REF MIN MAX Table 4. 1.62 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V Parameter1 Symbol Min Max Min Max Unit SCLK Cycle Time t 20 20 ns 1 SCLK High Time t 10 10 ns 2 SCLK Low Time t 10 10 ns 3 SYNC to SCLK Falling Edge Setup Time t4 15 10 ns Data Setup Time t 5 5 ns 5 Data Hold Time t 5 5 ns 6 SCLK Falling Edge to SYNC Rising Edge t7 10 10 ns Minimum SYNC High Time t8 20 20 ns SYNC Rising Edge to SYNC Rising Edge (DAC Register Update/s) t9 870 830 ns SYNC Falling Edge to SCLK Fall Ignore t10 16 10 ns LDAC Pulse Width Low t11 15 15 ns SYNC Rising Edge to LDAC Rising Edge t12 20 20 ns SYNC Rising Edge to LDAC Falling Edge t13 30 30 ns LDAC Falling Edge to SYNC Rising Edge t14 840 800 ns Minimum Pulse Width Low t 30 30 ns 15 Pulse Activation Time t 30 30 ns 16 Power-Up Time2 4.5 4.5 µs 1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested. 2 Time to exit power-down to normal mode of AD5686/AD5684 operation, SYNC rising edge to 90% of DAC midscale value, with output unloaded. t10 t1 SCLK t8 t3 t2 t7 t14 t4 SYNC t9 t6 t5 SDIN DB23 DB0 t13 t11 LDAC1 t12 LDAC2 RESET t15 VOUT t16 12ASYSNYCNHCHRROONNOOUUS SL DLDAACC U UPDPDAATET EM MOODDE.E. 10797-002 Figure 2. Serial Write Operation Rev. C | Page 6 of 27

Data Sheet AD5686/AD5684 DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS All input signals are specified with t = t = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2. See Figure 4 R F DD IL IH and Figure 5. V = 2.7 V to 5.5 V, 1.62 V ≤ V ≤ 5.5 V; V = 2.5 V. All specifications T to T , unless otherwise noted. DD LOGIC REF MIN MAX Table 5. 1.62 V ≤ V < 2.7 V 2.7 V ≤ V ≤ 5.5 V LOGIC LOGIC Parameter1 Symbol Min Max Min Max Unit SCLK Cycle Time t 66 40 ns 1 SCLK High Time t 33 20 ns 2 SCLK Low Time t 33 20 ns 3 SYNC to SCLK Falling Edge t4 33 20 ns Data Setup Time t 5 5 ns 5 Data Hold Time t 5 5 ns 6 SCLK Falling Edge to SYNC Rising Edge t7 15 10 ns Minimum SYNC High Time t8 60 30 ns SDO Data Valid from SCLK Rising Edge t 45 30 ns 9 SYNC Rising Edge to SCLK Falling Edge t10 15 10 ns SYNC Rising Edge to SDO Disable t11 60 60 ns 1 Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested. Circuit and Timing Diagrams 200µA IOL TO OUTPPUINT VOH (MIN) CL 20pF 200µA IOH 10797-003 Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications t1 SCLK 24 48 t8 t2 t7 t4 t3 t10 SYNC t6 t5 SDIN DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N INPUT WORD FOR DAC N + 1 t9 SDO DB23 DB0 UNDEFINED INPUT WORD FOR DAC N 10797-004 Figure 4. Daisy-Chain Timing Diagram Rev. C | Page 7 of 27

AD5686/AD5684 Data Sheet t1 SCLK 1 24 1 24 t8 t4 t3 t2 t7 t8 t10 SYNC t6 t5 SDIN DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ t9 t11 SDO DB23 DB0 HI-Z SELECCTLEOD CRKEEGDIS OTUETR DATA 10797-005 Figure 5. Readback Timing Diagram Rev. C | Page 8 of 27

Data Sheet AD5686/AD5684 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 6. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Operation beyond V to GND −0.3 V to +7 V LOGIC the maximum operating conditions for extended periods may V to GND −0.3 V to V + 0.3 V OUT DD affect product reliability. V to GND −0.3 V to V + 0.3 V REF DD Digital Input Voltage to GND −0.3 V to V + 0.3 V LOGIC ESD CAUTION Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 125°C 16-Lead TSSOP, θ Thermal 112.6°C/W JA Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP, θJA Thermal 70°C/W Impedance, 0 Airflow (4-Layer Board) Reflow Soldering Peak 260°C Temperature, Pb Free (J-STD-020) Rev. C | Page 9 of 27

AD5686/AD5684 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD5686/AD5684 L BTUO FER ESTS TESE V V R R 6 5 4 3 1 1 1 1 VOUTA1 12SDIN GND2 11SYNC VREF 1 16 RSTSEL VDD3 10SCLK VOUTB 2 15 RESET VOUTC4 9 VLOGIC AD5686/ VOUTA 3 AD5684 14 SDIN 5 6 7 8 GND 4 13 SYNC DVTUO ODS CADL NAIG VOVUTDCD 56 (NToOt Pto V SIEcaWle) 1121 VSCLOLGKIC TOP VIEW N1.O TTHEES EXPOSED( NPoAtD t oM SUcSaTle B)E TIED TO GND. 10797-006 VOSUDTOD 87 190 GLDAAINC 10797-007 Figure 6. 16-Lead LFCSP Pin Configuration Figure 7. 16-Lead TSSOP Pin Configuration Table 7. Pin Function Descriptions Pin No. LFCSP TSSOP Mnemonic Description 1 3 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 2 4 GND Ground Reference Point for All Circuitry on the Part. 3 5 V Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be DD decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 4 6 V C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT 5 7 V D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT 6 8 SDO Serial Data Output. Can be used to daisy-chain a number of AD5686/AD5684 devices together or can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. 7 9 LDAC LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to be simultaneously updated. This pin can also be tied permanently low. 8 10 GAIN Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to V . When REF this pin is tied to V , all four DAC outputs have a span from 0 V to 2 × V . LOGIC REF 9 11 V Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. LOGIC 10 12 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. 11 13 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 24 clocks. 12 14 SDIN Serial Data Input. These devices have a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 13 15 RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. If the pin is forced low at power-up, the POR circuit does not initialize correctly until the pin is released. 14 16 RSTSEL Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to V powers up all four DACs to midscale. LOGIC 15 1 V Reference Input Voltage. REF 16 2 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND. Rev. C | Page 10 of 27

Data Sheet AD5686/AD5684 TYPICAL PERFORMANCE CHARACTERISTICS 10 1.0 8 0.8 6 0.6 4 0.4 INL (LSB) –202 DNL (LSB)–00..220 –4 –0.4 –6 –0.6 –8 TVAD D= =2 55°VC –0.8 VTAD D= =2 55°VC –100REFER1E00N0C0E = 22.050V00 300C0O0DE40000 50000 60000 10797-118 –1.00REFERE62N5CE = 21.52V50 18C75ODE 2500 3125 3750 4096 10797-123 Figure 8. AD5686 INL Figure 11. AD5684 DNL 10 10 8 8 6 6 4 4 B) 2 LSB) 2 INL INL (LS –20 ERROR ( –20 DNL –4 –4 –6 –6 –8 VDD = 5V –8 VDD = 5V TA = 25°C REFERENCE = 2.5V –100REFERE62N5CE = 21.52V50 18C75ODE 2500 3125 3750 4096 10797-120 –10–40 10 TEMPERATURE6 (0°C) 110 10797-124 Figure 9. AD5684 INL Figure 12. INL Error and DNL Error vs. Temperature 1.0 10 0.8 8 6 0.6 4 0.4 B) 0.2 LSB) 2 INL DNL (LS–0.20 ERROR ( –20 DNL –4 –0.4 –6 VDD = 5V –0.6 TA = 25°C –0.8 VDD = 5V –8 TA = 25°C REFERENCE = 2.5V –10 –1.00 10000 20000 300C0O0DE40000 50000 60000 10797-121 0 0.5 1.0 1.5 2.0VR2E.F5 (V)3.0 3.5 4.0 4.5 5.0 10797-125 Figure 10. AD5686 DNL Figure 13. INL Error and DNL Error vs. VREF Rev. C | Page 11 of 27

AD5686/AD5684 Data Sheet 10 0.10 8 0.08 6 0.06 4 0.04 R) B) 2 FS 0.02 R (LS 0 INL % of 0 GAIN ERROR RRO –2 DNL OR (–0.02 FULL-SCALE ERROR E R R –4 E–0.04 –6 –0.06 –8 TA = 25°C –0.08 TA = 25°C REFERENCE = 2.5V REFERENCE = 2.5V –102.7 3.2 S3U.7PPLY VOL4.T2AGE (V)4.7 5.2 10797-126 –0.102.7 3.2 S3U.7PPLY VO4L.T2AGE (V)4.7 5.2 10797-129 Figure 14. INL Error and DNL Error vs. Supply Voltage Figure 17. Gain Error and Full-Scale Error vs. Supply Voltage 0.10 1.5 0.08 1.0 0.06 0.04 R) 0.5 of FS 0.02 FULL-SCALE ERROR mV) ZERO-CODE ERROR % 0 R ( 0 RROR (–0.02 GAIN ERROR ERRO OFFSET ERROR E–0.04 –0.5 –0.06 –1.0 –0.08 VDD = 5V TA = 25°C REFERENCE = 2.5V REFERENCE = 2.5V –0.10–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 10797-127 –1.52.7 3.2 S3U.7PPLY VO4L.T2AGE (V)4.7 5.2 10797-130 Figure 15. Gain Error and Full-Scale Error vs. Temperature Figure 18. Zero-Code Error and Offset Error vs. Supply Voltage 0.10 1.4 RVDEDF E=R 5EVNCE = 2.5V R) 0.09 RVDEDF E=R 5EVNCE = 2.5V S 1.2 of F 0.08 % 1.0 R ( 0.07 V) RO 0.06 m R R ( 0.8 D E 0.05 O E R T ER 0.6 US 0.04 J D A 0.03 0.4 ZERO-CODE ERROR N U AL 0.02 0.2 OT OFFSET ERROR T 0.01 0–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 10797-128 0–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 10797-131 Figure 16. Zero-Code Error and Offset Error vs. Temperature Figure 19. TUE vs. Temperature Rev. C | Page 12 of 27

Data Sheet AD5686/AD5684 0.10 1.0 R) 0.08 0.8 S of F 0.06 0.6 R (% 0.04 0.4 SINKING 2.7V RRO 0.02 V) 0.2 SINKING 5V D E 0 (UT 0 E O T V US–0.02 ∆ –0.2 J AD–0.04 –0.4 SOURCING 5V N U AL –0.06 –0.6 TOT–0.08 TVAD D= =2 55°VC –0.8 SOURCING 2.7V INTERNAL REFERENCE = 2.5V –0.102.7 3.2 S3U.7PPLY VO4L.T2AGE (V)4.7 5.2 10797-132 –1.00 5 1L0OAD CUR1R5ENT (mA2)0 25 30 10797-200 Figure 20. TUE vs. Supply Voltage, Gain = 1 Figure 23. Headroom/Footroom vs. Load Current 0 7 VDD = 5V R)–0.01 6 TGAA =IN 2 =5 °2C S of F–0.02 5 REFERENCE = 2.5V 0xFFFF % R (–0.03 4 0xC000 O R–0.04 USTED ER––00..0056 V (V)OUT 23 00xx48000000 J D 1 A–0.07 N U 0x0000 AL –0.08 0 TOT–0.09 TVAD D= =2 55°VC –1 REFERENCE = 2.5V –0.100 10000 20000 300C0O0DE 40000 50000 6000065535 10797-133 ––20.06 –0.04 –0.0L2OAD CU0RRENT (A0).02 0.04 0.06 10797-138 Figure 21. TUE vs. Code Figure 24. Source and Sink Capability at 5 V 5 25 VTAD D= =2 55°VC TVAD D= =2 53°VC EXTERNAL 4 GAIN = 1 REFERENCE = 2.5V EXTERNAL 20 REFERENCE = 2.5V 0xFFFF 3 0xC000 HITS 15 V (V)OUT 12 00xx48000000 10 0x0000 0 5 –1 0 –2 540 560 580IDD (µA)600 620 640 10797-135 –0.06 –0.04 –0.0L2OAD CU0RRENT (A0).02 0.04 0.06 10797-139 Figure 22. IDD Histogram Figure 25. Source and Sink Capability at 3 V Rev. C | Page 13 of 27

AD5686/AD5684 Data Sheet 3 CH A 1.4 CH B CH C GAIN = 2 CH D 1.2 SYNC 2 1.0 A) ENT (m 0.8 (V)OUT GAIN = 1 R FULL-SCALE V UR 0.6 C 1 0.4 0.2 VDD = 5V TA = 25°C REFERENCE = 2.5V 0–40 10 TEMPERATURE6 (0°C) 110 10797-140 0–5 0 TIME (µs) 5 10 10797-143 Figure 26. Supply Current vs. Temperature Figure 29. Exiting Power-Down to Midscale 4.0 2.5008 DAC A DAC B 3.5 DAC C DAC D 3.0 2.5003 2.5 V) V) (UT 2.0 (UT 2.4998 O O V V 1.5 CHANNEL B 1.0 2.4993 TA = 25°C VDD = 5V VDD = 5.25V 0.5 TA = 25°C REFERENCE = 2.5V REFERENCE = 2.5V CODE = 7FFF TO 8000 ¼ TO ¾ SCALE ENERGY = 0.227206nV-sec 010 20 40TIME (µs)80 160 320 10797-141 2.49880 2 4 TIME6 (µs) 8 10 12 10797-144 Figure 27. Settling Time, 5 V Figure 30. Digital-to-Analog Glitch Impulse 0.06 6 0.003 CH A CH B CH B CH C 0.05 CCHH DC 5 0.002 CH D VDD 0.04 4 V) D ( V (V)OUT 00..0023 23 V (V)DD AC-COUPLE 0.0010 UT O 0.01 1 V –0.001 0 0 TA = 25°C REFERENCE = 2.5V –0.01–10 –5 0 TIME (µs)5 10 15–1 10797-142 –0.0020 5 10TIME (µs)15 20 25 10797-145 Figure 28. Power-On Reset to 0 V Figure 31. Analog Crosstalk, Channel A Rev. C | Page 14 of 27

Data Sheet AD5686/AD5684 4.0 0nF VDD = 5V T 3.9 01.01nnFF TRAE F=E 2R5E°CNCE = 2.5V 0.22nF 3.8 4.7nF 3.7 3.6 V) (UT 3.5 1 O V 3.4 3.3 3.2 VDD = 5V 3.1 TA = 25°C CEHX1 T 1E0RµNVAL REFERENCE = 2.5MV1.0s A CH1 802mV 10797-146 3.10.590 1.595 1.600 1.605TIM1.E6 1(m0s)1.615 1.620 1.625 1.630 10797-150 Figure 32. 0.1 Hz to 10 Hz Output Noise Plot Figure 34. Settling Time vs. Capacitive Load 20 0 VDD = 5V 0 TA = 25°C REFERENCE = 2.5V –10 –20 –40 B) –20 V) –60 H (d B T D (d –80 WID –30 H D T –100 N A B –40 –120 –140 –50 VDD = 5V –160 TA = 25°C REFERENCE = 2.5V, ±0.1V p-p –1800 2000 4000 6000 F8R00E0QU10E0N0C0Y1 2(H00z0)14000160001800020000 10797-149 –6010k 100kFREQUENCY (Hz)1M 10M 10797-151 Figure 33. Total Harmonic Distortion @ 1 kHz Figure 35. Multiplying Bandwidth, Reference = 2.5 V, ±0.1 V p-p, 10 kHz to 10 MHz Rev. C | Page 15 of 27

AD5686/AD5684 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Output Voltage Settling Time For the DAC, relative accuracy or integral nonlinearity is a The output voltage setting time is the amount of time it takes measurement of the maximum deviation, in LSBs, from a for the output of a DAC to settle to a specified level for a ¼ to ¾ straight line passing through the endpoints of the DAC transfer full-scale input change and is measured from the rising edge function. A typical INL vs. code plot is shown in Figure 8. of SYNC. Differential Nonlinearity (DNL) Digital-to-Analog Glitch Impulse Differential nonlinearity is the difference between the measured Digital-to-analog glitch impulse is the impulse injected into the change and the ideal 1 LSB change between any two adjacent analog output when the input code in the DAC register changes codes. A specified differential nonlinearity of ±1 LSB maximum state. It is normally specified as the area of the glitch in nV-sec, ensures monotonicity. These DACs are guaranteed monotonic and is measured when the digital input code is changed by by design. A typical DNL vs. code plot can be seen in Figure 10. 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Zero-Code Error Figure 30). Zero-code error is a measurement of the output error when Digital Feedthrough zero code (0x0000) is loaded to the DAC register. Ideally, the Digital feedthrough is a measure of the impulse injected into the output should be 0 V. The zero-code error is always positive in analog output of the DAC from the digital inputs of the DAC, the AD5686/AD5684 because the output of the DAC cannot go but is measured when the DAC output is not updated. It is below 0 V due to a combination of the offset errors in the DAC specified in nV-sec and measured with a full-scale code change and the output amplifier. Zero-code error is expressed in mV. A on the data bus, that is, from all 0s to all 1s and vice versa. plot of zero-code error vs. temperature can be seen in Figure 16. Noise Spectral Density Full-Scale Error Noise spectral density is a measurement of the internally Full-scale error is a measurement of the output error when full- generated random noise. Random noise is characterized as a scale code (0xFFFF) is loaded to the DAC register. Ideally, the spectral density (nV/√Hz). It is measured by loading the DAC output should be VDD − 1 LSB. Full-scale error is expressed in to midscale and measuring noise at the output. It is measured in percent of full-scale range (% of FSR). A plot of full-scale error nV/√Hz. vs. temperature can be seen in Figure 15. DC Crosstalk Gain Error DC crosstalk is the dc change in the output level of one DAC Gain error is a measurement of the span error of the DAC. It is in response to a change in the output of another DAC. It is the deviation in slope of the DAC transfer characteristic from measured with a full-scale output change on one DAC (or soft the ideal expressed as % of FSR. power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in μV. Offset Error Drift Offset error drift is a measurement of the change in offset error DC crosstalk due to load current change is a measurement of with a change in temperature. It is expressed in µV/°C. the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in μV/mA. Gain Temperature Coefficient Gain temperature coefficient is a measurement of the change in Digital Crosstalk gain error with changes in temperature. It is expressed in ppm Digital crosstalk is the glitch impulse transferred to the output of FSR/°C. of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another Offset Error DAC. It is measured in standalone mode and is expressed in Offset error is a measurement of the difference between V OUT nV-sec. (actual) and V (ideal) expressed in mV in the linear region of OUT the transfer function. It can be negative or positive. DC Power Supply Rejection Ratio (PSRR) DC PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V to a change in V for full-scale output of the DAC. It is OUT DD measured in mV/V. V is held at 2.5 V, and V is varied by REF DD ±10%. Rev. C | Page 16 of 27

Data Sheet AD5686/AD5684 Analog Crosstalk Multiplying Bandwidth Analog crosstalk is the glitch impulse transferred to the output The amplifiers within the DAC have a finite bandwidth. The of one DAC due to a change in the output of another DAC. It is multiplying bandwidth is a measure of this. A sine wave on the measured by loading one of the input registers with a full-scale reference (with full-scale code loaded to the DAC) appears on code change (all 0s to all 1s and vice versa). Then execute a the output. software LDAC and monitor the output of the DAC whose Total Harmonic Distortion (THD) digital code was not changed. The area of the glitch is expressed THD is the difference between an ideal sine wave and its in nV-sec. attenuated version using the DAC. The sine wave is used as the DAC-to-DAC Crosstalk reference for the DAC, and the THD is a measurement of the DAC-to-DAC crosstalk is the glitch impulse transferred to harmonics present on the DAC output. It is measured in dB. the output of one DAC in response to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa) using the write to and update commands while monitoring the output of another channel that is at midscale. The energy of the glitch is expressed in nV-sec. Rev. C | Page 17 of 27

AD5686/AD5684 Data Sheet THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER The resistor string structure is shown in Figure 37. It is a string of resistors, each of Value R. The code loaded to the DAC register The AD5686/AD5684 are quad, 16-/12-bit, serial input, voltage determines the node on the string where the voltage is to be output DACs. The parts operate from supply voltages of 2.7 V to tapped off and fed into the output amplifier. The voltage is 5.5 V. Data is written to the AD5686/AD5684 in a 24-bit word tapped off by closing one of the switches connecting the format via a 3-wire serial interface. The AD5686/AD5684 string to the amplifier. Because the DAC is a string of resistors, incorporate a power-on reset circuit to ensure that the DAC it is guaranteed monotonic. output powers up to a known output state. The devices also have a software power-down mode that reduces the typical VREF current consumption to typically 4 µA. R TRANSFER FUNCTION Because the input coding to the DAC is straight binary, the ideal R output voltage when using an external reference is given by V =V ×Gain D  R TAOM POLUIFTIPEURT OUT REF 2N where: D is the decimal equivalent of the binary code that is loaded to the DAC register as follows: R 0 to 4095 for the 12-bit device. 0 to 65,535 for the 16-bit device. N is the DAC resolution. R VGRaEiFn i sis t hthee v gaaluine ooff tthhee oeuxtteprunta alm repfleirfeienrc aen. d is set to 1 by default. 10797-053 Figure 37. Resistor String Structure The gain can be set to ×1 or ×2 using the gain select pin. When this pin is tied to GND, all four DAC outputs have a span of 0 V Output Amplifiers to VREF. When this pin is tied to VDD, all four DAC outputs have The output buffer amplifier can generate rail-to-rail voltages on a span of 0 V to 2 × VREF. its output, which gives an output range of 0 V to VDD. The actual DAC ARCHITECTURE range depends on the value of VREF, the GAIN pin, offset error, and gain error. The GAIN pin selects the gain of the output. The DAC architecture consists of a string DAC followed by an output amplifier. Figure 36 shows a block diagram of the DAC • If this pin is tied to GND, all four outputs have a gain of 1, architecture. and the output range is 0 V to VREF. VREF • If this pin is tied to VDD, all four outputs have a gain of 2, and the output range is 0 V to 2 × V . REF These amplifiers are capable of driving a load of 1 kΩ in parallel REF (+) REINGPISUTTER REGDIASCTER RSETSRISINTOGR VOUTX wseittthli n2g n tFim toe GofN 5D µ. sT. he slew rate is 0.8 V/µs with a ¼ to ¾ scale REF (–) GND (GAING =A I1N OR 2) 10797-052 Figure 36. Single DAC Channel Architecture Block Diagram Rev. C | Page 18 of 27

Data Sheet AD5686/AD5684 SERIAL INTERFACE Table 8. Command Bit Definitions Command Bits The AD5686/AD5684 have a 3-wire serial interface (SYNC, C3 C2 C1 C0 Description SCLK, and SDIN) that is compatible with SPI, QSPI™, and 0 0 0 0 No operation MICROWIRE® interface standards as well as most DSPs. See 0 0 0 1 Write to Input Register n (dependent on LDAC) Figure 2 for a timing diagram of a typical write sequence. The 0 0 1 0 Update DAC Register n with contents of Input AD5686/AD5684 contain an SDO pin to allow the user to daisy- Register n chain multiple devices together (see the Daisy-Chain Operation 0 0 1 1 Write to and update DAC Channel n section) or for readback. 0 1 0 0 Power down/power up DAC 0 1 0 1 Hardware LDAC mask register Input Shift Register 0 1 1 0 Software reset (power-on reset) The input shift register of the AD5686/AD5684 is 24 bits wide. 0 1 1 1 Reserved Data is loaded MSB first (DB23). The first four bits are the 1 0 0 0 Set up DCEN register (daisy-chain enable) command bits, C3 to C0 (see Table 8), followed by the 4-bit 1 0 0 1 Set up readback register (readback enable) DAC address bits, DAC A, DAC B, DAC C, andDAC D (see 1 0 1 0 Reserved Table 9), and finally the bit data-word. … … … … Reserved 1 1 1 1 No operation, daisy-chain mode For the AD5686, the data-word comprises 16-bit input code(see Figure 38). For the AD5684, the data-word comprises 12-bit input Table 9. Address Bits and Selected DACs code, followed by zero or four don’t care bits (see Figure 39). Address Bits These data bits are transferred to the input register on the 24 DAC D DAC C DAC B DAC A Selected DAC Channel1 falling edges of SCLK and are updated on the rising edge 0 0 0 1 DAC A of SYNC. 0 0 1 0 DAC B 0 1 0 0 DAC C Commands can be executed on individual DAC channels, 1 0 0 0 DAC D combined DAC channels, or on all DACs, depending on the 0 0 1 1 DAC A and DAC B address bits selected (see Table 9). 1 1 1 1 All DACs 1 Any combination of DAC channels can be selected using the address bits. DB23 (MSB) DB0 (LSB) DAC DAC DAC DAC C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D C B A DATA BITS COMMAND BITS ADDRESS BITS 10797-054 Figure 38. AD5686 Input Shift Register Contents DB23 (MSB) DB0 (LSB) DAC DAC DAC DAC C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X D C B A DATA BITS COMMAND BITS ADDRESS BITS 10797-056 Figure 39. AD5684 Input Shift Register Contents Rev. C | Page 19 of 27

AD5686/AD5684 Data Sheet STANDALONE OPERATION AD5686/ The write sequence begins by bringing the SYNC line low. Data 68HC11* AD5684 from the SDIN line is clocked into the 24-bit input shift register MOSI SDIN on the falling edge of SCLK. After the last of 24 data bits is SCK SCLK clocked in, SYNC should be brought high. The programmed PC7 SYNC function is then executed, that is, an LDAC-dependent change PC6 LDAC in DAC register contents and/or a change in the mode of MISO SDO operation. If SYNC is taken high at a clock before the 24th clock, it is considered a valid frame and invalid data may be SDIN loaded to the DAC. SYNC must be brought high for a minimum AD5686/ of 20 ns (single channel, see t in Figure 2) before the next write AD5684 8 sequence so that a falling edge of SYNC can initiate the next SCLK write sequence. SYNC should be idle at rails between write SYNC sequences for even lower power operation of the part. LDAC The SYNC line is kept low for 24 falling edges of SCLK, and the SDO DAC is updated on the rising edge of SYNC. After data is transferred into the input register of the addressed SDIN DAC, all DAC registers and outputs can be updated by AD5686/ taking LDAC low while the SYNC line is high. AD5684 SCLK WRITE AND UPDATE COMMANDS SYNC Write to Input Register n (Dependent on LDAC) LDAC Command 0001 allows the user to write to each DAC’s SDO dedicated input register individually. When LDAC is low, tLhDeA inCp muta rsekg irsetgeirs ties rt)r.a nsparent (if not controlled by the *ADDITIONAL PINS OMITTED FOR CLARITY. 10797-057 Figure 40. Daisy-Chaining the AD5686/AD5684 Update DAC Register n with Contents of Input Register n The SCLK pin is continuously applied to the input shift register Command 0010 loads the DAC registers/outputs with the when SYNC is low. If more than 24 clock pulses are applied, the contents of the selected input registers and updates the DAC data ripples out of the input shift register and appears on the outputs directly. SDO line. This data is clocked out on the rising edge of SCLK Write to and Update DAC Channel n (Independent and is valid on the falling edge. By connecting the SDO line to of LDAC) the SDIN input on the next DAC in the chain, a daisy-chain Command 0011 allows the user to write to the DAC registers interface is constructed. Each DAC in the system requires 24 and update the DAC outputs directly. clock pulses. Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of devices that are DAISY-CHAIN OPERATION updated. If SYNC is taken high at a clock that is not a multiple For systems that contain several DACs, the SDO pin can be of 24, it is considered a valid frame and invalid data may be used to daisy-chain several devices together. This function loaded to the DAC. When the serial transfer to all devices is is enabled through a software executable daisy-chain enable complete, SYNC is taken high. This latches the input data in (DCEN) command. Command 1000 is reserved for this DCEN each device in the daisy chain and prevents any further data function (see Table 8). The daisy-chain mode is enabled by from being clocked into the input shift register. The serial clock setting Bit DB0 in the DCEN register. The default setting is can be continuous or a gated clock. A continuous SCLK source standalone mode, where DB0 = 0. Table 10 shows how the state can be used only if SYNC can be held low for the correct of the bit corresponds to the mode of operation of the device. number of clock cycles. In gated clock mode, a burst clock Table 10. Daisy-Chain Enable (DCEN) Register containing the exact number of clock cycles must be used, DB0 Description and SYNC must be taken high after the final clock to latch the data. 0 Standalone mode (default) 1 DCEN mode Rev. C | Page 20 of 27

Data Sheet AD5686/AD5684 READBACK OPERATION Table 11. Modes of Operation Operating Mode PDx1 PDx0 Readback mode is invoked through a software executable Normal Operation 0 0 readback command. If the SDO output is disabled via the daisy- Power-Down Modes chain mode disable bit in the control register, it is automatically 1 kΩ to GND 0 1 enabled for the duration of the read operation, after which it is 100 kΩ to GND 1 0 disabled again. Command 1001 is reserved for the readback Three-State 1 1 function. This command, in association with selecting one of the address bits, DAC A to DAC D, selects the register to Any or all DACs (DAC A to DAC D) can be powered down read. Note that only one DAC register can be selected during to the selected mode by setting the corresponding bits. See readback. The remaining three address bits must be set to Table 12 for the contents of the input shift register during the Logic 0. The remaining data bits in the write sequence are power-down/power-up operation. don’t care bits. If more than one or no bits are selected, DAC When both Bit PDx1 and Bit PDx0 (where x is the channel Channel A is read back by default. During the next SPI write, selected) in the input shift register are set to 0, the parts work the data appearing on the SDO output contains the data from normally with their normal power consumption of 0.59 mA at the previously addressed register. 5 V. However, for the three power-down modes, the supply For example, to read back the DAC register for Channel A, the current falls to 4 μA at 5 V. Not only does the supply current following sequence should be implemented: fall, but the output stage is also internally switched from the 1. Write 0x900000 to the AD5686/AD5684 input register. output of the amplifier to a resistor network of known values. This configures the part for read mode with the DAC This has the advantage that the output impedance of the part is register of Channel A selected. Note that all data bits, known while the part is in power-down mode. There are three DB15 to DB0, are don’t care bits. different power-down options (see Table 11). The output is 2. Follow this with a second write, a NOP condition, connected internally to GND through either a 1 kΩ or a 100 kΩ 0x000000 (0xF00000 in daisy-chain mode). During this resistor, or it is left open-circuited (three-state). The output stage write, the data from the register is clocked out on the SDO is illustrated in Figure 41. line. DB23 to DB20 contain undefined data, and the last 16 bits contain the DB19 to DB4 DAC register contents. POWER-DOWN OPERATION DAC AMPLIFIER VOUTX The AD5686/AD5684 provide three separate power-down modes (see Table 11). Command 0100 is designated for the power- POWER-DOWN down function (see Table 8). These power-down modes are CIRCUITRY RESISTOR isno ftthwea irnep purto sghriafmt rmegaisbtleer .b Tyw soet btiintsg a erieg ahsts boictisa,t Bedit wDiBth7 e taoc hB iDt DACB0 , NETWORK 10797-058 Figure 41. Output Stage During Power-Down channel. Table 11 shows how the state of the two bits corresponds to the mode of operation of the device. The bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the DAC registers are unaffected when in power-down. The DAC registers can be updated while the device is in power-down mode. The time required to exit power-down is typically 4.5 µs for V = 5 V. DD Table 12. 24-Bit Input Shift Register Contents for Power-Down/Power-Up Operation1 DB15 to DB0 DB23 DB22 DB21 DB20 DB19 to DB16 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 (LSB) 0 1 0 0 X X PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0 Command bits (C3 to C0) Address bits Power-Down Power-Down Power-Down Power-Down (don’t care) Select DAC D Select DAC C Select DAC B Select DAC A 1 X = don’t care. Rev. C | Page 21 of 27

AD5686/AD5684 Data Sheet LOAD DAC (HARDWARE LDAC PIN) LDAC MASK REGISTER The AD5686/AD5684 DACs have double buffered interfaces Command 0101 is reserved for the software LDAC function. consisting of two banks of registers: input registers and DAC Address bits are ignored. Writing to the DAC using Command registers. The user can write to any combination of the input 0101 loads the 4-bit LDAC register (DB3 to DB0). The default registers. Updates to the DAC register are controlled by for each channel is 0; that is, the LDAC pin works normally. the LDAC pin. Setting the bits to 1 forces this DAC channel to ignore transitions on the LDAC pin, regardless of the state of the hardware LDAC OUTPUT AMPLIFIER pin. This flexibility is useful in applications where the user VREF 16-D/1A2C-BIT VOUTX wishes to select which channels respond to the LDAC pin. The LDAC register gives the user extra flexibility and control DAC over the hardware LDAC pin (see Table 13). Setting the LDAC LDAC REGISTER bits (DB3 to DB0) to 0 for a DAC channel means that this channel’s update is controlled by the hardware LDAC pin. INPUT REGISTER Table 13. LDAC Overwrite Definition Load LDAC Register SCLK SSYDNICN INTLEORGFIACCE SDO 10797-059 (LDDBA3C t Boi tDsB 0) LDAC Pin LDAC Operation Figure 42. Simplified Diagram of Input Loading Circuitry for a Single DAC 0 1 or 0 Determined by the LDAC pin. 1 X1 DAC channels are updated and Instantaneous DAC Updating (LDAC Held Low) override the LDAC pin. DAC LDAC is held low while data is clocked into the input register channels see LDAC as 1. using Command 0001. Both the addressed input register and 1 X = don’t care. the DAC register are updated on the rising edge of SYNC and the output begins to change (see Table 14). Deferred DAC Updating (LDAC Is Pulsed Low) LDAC is held high while data is clocked into the input register using Command 0001. All DAC outputs are asynchronously updated by taking LDAC low after SYNC has been taken high. The update now occurs on the falling edge of LDAC. Table 14. Write Commands and LDAC Pin Truth Table1 Hardware LDAC Input Register Command Description Pin State Contents DAC Register Contents 0001 Write to Input Register n (dependent on LDAC) VLOGIC Data update No change (no update) GND2 Data update Data update 0010 Update DAC Register n with contents of Input V No change Updated with input register contents LOGIC Register n GND No change Updated with input register contents 0011 Write to and update DAC Channel n V Data update Data update LOGIC GND Data update Data update 1 A high to low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked (blocked) by the LDAC mask register. 2 When LDAC is permanently tied low, the LDAC mask bits are ignored. Rev. C | Page 22 of 27

Data Sheet AD5686/AD5684 HARDWARE RESET (RESET) RESET SELECT PIN (RSTSEL) RESET is an active low reset that allows the outputs to be The AD5686/AD5684 contain a power-on reset circuit that controls the output voltage during power-up. By connecting cleared to either zero scale or midscale. The clear code value is the RSTSEL pin low, the output powers up to zero scale. Note user selectable via the RESET select pin. It is necessary to that this is outside the linear region of the DAC. By connecting keep RESET low for a minimum of 30 ns to complete the the RSTSEL pin high, V powers up to midscale. The output operation (see Figure 2). When the RESET signal is returned OUT remains powered up at this level until a valid write sequence high, the output remains at the cleared value until a new value is made to the DAC. is programmed. The outputs cannot be updated with a new value while the RESET pin is low. There is also a software executable reset function that resets the DAC to the power- on reset code. Command 0110 is designated for this software reset function (see Table 8). Any events on LDAC during a power-on reset are ignored. If the RESET pin is pulled low at power-up, the device does not initialize correctly until the pin is released. Rev. C | Page 23 of 27

AD5686/AD5684 Data Sheet APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING LAYOUT GUIDELINES Microprocessor interfacing to the AD5686/AD5684 is via a In any circuit where accuracy is important, careful consider- serial bus that uses a standard protocol that is compatible with ation of the power supply and ground return layout helps to DSP processors and microcontrollers. The communications ensure the rated performance. The PCB on which the AD5686/ channel requires a 3- or 4-wire interface consisting of a clock AD5684 are mounted should be designed so that the AD5686/ signal, a data signal, and a synchronization signal. The devices AD5684 lie on the analog plane. require a 24-bit data-word with data valid on the rising edge The AD5686/AD5684 should have ample supply bypassing of SYNC. of 10 µF in parallel with 0.1 µF on each supply, located as close AD5686/AD5684 TO ADSP-BF531 INTERFACE to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF The SPI interface of the AD5686/AD5684 is designed to be capacitor should have low effective series resistance (ESR) easily connected to industry-standard DSPs and micro- and low effective series inductance (ESI), such as the common controllers. Figure 43 shows the AD5686/AD5684 connected ceramic types, which provide a low impedance path to ground to the Analog Devices, Inc., Blackfin® DSP. The Blackfin has an at high frequencies to handle transient currents due to internal integrated SPI port that can be connected directly to the SPI logic switching. pins of the AD5686/AD5684. In systems where there are many devices on one board, it is AD5686/ often useful to provide some heat sinking capability to allow AD5684 the power to dissipate easily. ADSP-BF531 The AD5686/AD5684 LFCSP models have an exposed pad beneath the device. Connect this pad to the GND supply for the SPISELx SYNC SCK SCLK part. For optimum performance, use special considerations to MOSI SDIN design the motherboard and to mount the package. For PPFF98 LRDEASCET 10797-164 esonlhdaenr ctehde tehxepromseadl, pelaedc tornic athl,e a bnodt tboomar dof l ethvee lp paecrkfaogrme taon tchee, Figure 43. ADSP-BF531 Interface corresponding thermal land pad on the PCB. Design thermal vias into the PCB land pad area to further improve heat AD5686/AD5684 TO SPORT INTERFACE dissipation. The Analog Devices ADSP-BF527 has one SPORT serial The GND plane on the device can be increased (as shown in port. Figure 44 shows how one SPORT interface can be used Figure 45) to provide a natural heat sinking effect. to control theAD5686/AD5684. AD5686/ AD5686/ AD5684 AD5684 ADSP-BF527 SPORT_TFS SYNC SPORT_TSCK SCLK GND SPORT_DTO SDIN PLANE FiGGgPPuIIrOOe01 44. SPORT InteLRrDfEaAScCEeT 10797-165 BOARD 10797-166 Figure 45. Pad Connection to Board Rev. C | Page 24 of 27

Data Sheet AD5686/AD5684 GALVANICALLY ISOLATED INTERFACE CONTROLLER ADuM14001 In many process control applications, it is necessary to SERIAL VIA VOA TO provide an isolation barrier between the controller and CLOCK IN ENCODE DECODE SCLK the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may DATSAE ROIAULT VIB ENCODE DECODE VOB TSODIN occur. iCoupler® products from Analog Devices provide voltage isolation in excess of 2.5 kV. The serial loading structure of the SYNC OUT VIC ENCODE DECODE VOC TO AD5686/AD5684 makes the part ideal for isolated interfaces SYNC because the number of interface lines is kept to a minimum. Figure 46 shows a 4-channel isolated interface to the AD5686/ LOAD DOAUCT VID ENCODE DECODE VOD TLODAC AD5684 using an ADuM1400. For more information, visit http://www.analog.com/icouplers. 1ADDITIONAL PINS OMITTED FOR CLARITY. 10797-167 Figure 46. Isolated Interface Rev. C | Page 25 of 27

AD5686/AD5684 Data Sheet OUTLINE DIMENSIONS 3.10 0.30 3.00 SQ 0.23 PIN 1 2.90 0.18 INDICATOR PIN 1 0.50 13 16 INDICATOR BSC 12 1 EXPOSED 1.75 PAD 1.60 SQ 1.45 9 4 0.50 8 5 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 0.80 FOR PROPER CONNECTION OF 0.75 THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.20 REF COMPLIANTTOJEDEC STANDARDS MO-220-WEED-6. 08-16-2010-E Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 0.65 0.19 SEATING 0° 0.45 BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 48. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. C | Page 26 of 27

Data Sheet AD5686/AD5684 ORDERING GUIDE Package Package Model1, 2 Resolution Temperature Range Accuracy Description Option Branding AD5686ACPZ-RL7 16 Bits −40°C to +105°C ±8 LSB INL 16-Lead LFCSP_WQ CP-16-22 DJH AD5686BCPZ-RL7 16 Bits −40°C to +105°C ±2 LSB INL 16-Lead LFCSP_WQ CP-16-22 DJJ AD5686ARUZ 16 Bits −40°C to +105°C ±8 LSB INL 16-Lead TSSOP RU-16 AD5686ARUZ-RL7 16 Bits −40°C to +105°C ±8 LSB INL 16-Lead TSSOP RU-16 AD5686BRUZ 16 Bits −40°C to +105°C ±2 LSB INL 16-Lead TSSOP RU-16 AD5686BRUZ-RL7 16 Bits −40°C to +105°C ±2 LSB INL 16-Lead TSSOP RU-16 AD5684BCPZ-RL7 12 Bits −40°C to +105°C ±1 LSB INL 16-Lead LFCSP_WQ CP-16-22 DJP AD5684ARUZ 12 Bits −40°C to +105°C ±2 LSB INL 16-Lead TSSOP RU-16 AD5684ARUZ-RL7 12 Bits −40°C to +105°C ±2 LSB INL 16-Lead TSSOP RU-16 AD5684BRUZ 12 Bits −40°C to +105°C ±1 LSB INL 16-Lead TSSOP RU-16 AD5684BRUZ-RL7 12 Bits −40°C to +105°C ±1 LSB INL 16-Lead TSSOP RU-16 1 Z = RoHS Compliant Part. 2 The EVAL-AD5686RSDZ can be used to evaluate the AD5686/AD5684. The EVAL-AD5686RSDZ requires the EVAL-SDP-CB1Z support board for operation. ©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10797-0-6/17(C) Rev. C | Page 27 of 27