Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/°C On-Chip Reference Data Sheet AD5624R/AD5644R/AD5664R FEATURES FUNCTIONAL BLOCK DIAGRAM Low power, smallest pin-compatible, quad nanoDACs VDD GND VREFIN/VREFOUT AD5664R: 16 bits AD5624R/AD5644R/AD5664R 1.25V/2.5V REF AD5644R: 14 bits AD5624R: 12 bits REIGNPISUTTER REGDIASCTER SDTARCIN AG BUFFER VOUTA User-selectable external or internal reference SCLK External reference default On-chip 1.25 V/2.5 V, 5 ppm/°C reference REIGNPISUTTER REGDIASCTER SDTARCIN BG BUFFER VOUTB 10-lead MSOP; 10-lead, 3 mm × 3 mm LFCSP_WD; and SYNC INTLEORGFIACCE 12-ball, 1.665 mm × 2.245 mm WLCSP REIGNPISUTTER REGDIASCTER SDTARCIN CG BUFFER VOUTC 2.7 V to 5.5 V power supply DIN Guaranteed monotonic by design Power-on reset to zero scale REIGNPISUTTER REGDIASCTER SDTARCIN DG BUFFER VOUTD Per channel power-down POWER- Serial interface, up to 50 MHz POLWOEGRIC-ON DLOOGWINC 05856-001 APPLICATIONS Figure 1. Process controls Data acquisition systems Table 1. Related Devices Portable battery-powered instruments Part No. Description Digital gain and offset adjustment AD5624/AD5664 2.7 V to 5.5 V quad, 12-/16-bit DACs, external Programmable voltage and current sources reference Programmable attenuators AD5666 2.7 V to 5.5 V quad, 16-bit DAC, internal reference, LDAC, CLR pins GENERAL DESCRIPTION The AD5624R/AD5644R/AD5664R, members of the nanoDAC® 480 nA at 5 V and provides software-selectable output loads family, are low power, quad, 12-/14-/16-bit buffered voltage-out while in power-down mode. The low power consumption of DACs. All devices operate from a single 2.7 V to 5.5 V supply this part in normal operation makes it ideally suited to portable and are guaranteed monotonic by design. battery-operated equipment. The AD5624R/AD5644R/AD5664R have an on-chip reference. The AD5624R/AD5644R/AD5664R use a versatile 3-wire serial The AD56x4R-3 has a 1.25 V, 5 ppm/°C reference, giving a full- interface that operates at clock rates up to 50 MHz, and is com- scale output range of 2.5 V; the AD56x4R-5 has a 2.5 V, 5 ppm/°C patible with standard SPI, QSPI™, MICROWIRE™, and DSP reference giving a full-scale output range of 5 V. The on-chip interface standards. The on-chip precision output amplifier reference is off at power-up, allowing the use of an external enables rail-to-rail output swing. reference; all devices can be operated from a single 2.7 V to PRODUCT HIGHLIGHTS 5.5 V supply. The internal reference is enabled via a software write. 1. Quad 12-/14-/16-bit DACs. 2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference. The part incorporates a power-on reset circuit that ensures the 3. Available in 10-lead MSOP; 10-lead, 3 mm × 3 mm DAC output powers up to 0 V and remains there until a valid LFCSP_WD; and 12-ball, 1.665 mm × 2.245 mm WLCSP. write takes place. The part contains a per-channel power-down 4. Low power, typically consumes 1.32 mW at 3 V and feature that reduces the current consumption of the device to 2.25 mW at 5 V. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5624R/AD5644R/AD5664R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Internal Reference ...................................................................... 20 Applications ....................................................................................... 1 External Reference ..................................................................... 20 Functional Block Diagram .............................................................. 1 Serial Interface ............................................................................ 20 General Description ......................................................................... 1 Input Shift Register .................................................................... 21 Product Highlights ........................................................................... 1 SYNC Interrupt ........................................................................... 21 Revision History ............................................................................... 2 Power-On Reset .......................................................................... 22 Specifications ..................................................................................... 3 Software Reset ............................................................................. 22 AD5624R-5/AD5644R-5/AD5664R-5 ...................................... 3 Power-Down Modes .................................................................. 22 AD5624R-3/AD5644R-3/AD5664R-3 ...................................... 4 LDAC Function ........................................................................... 23 AC Characteristics ........................................................................ 6 Internal Reference Setup ........................................................... 23 Timing Characteristics ................................................................ 7 Microprocessor Interfacing ....................................................... 24 Timing Diagram ........................................................................... 7 Applications Information .............................................................. 25 Absolute Maximum Ratings ............................................................ 8 Using a Reference as a Power Supply for the ESD Caution .................................................................................. 8 AD5624R/AD5644R/AD5664R ............................................... 25 Pin Configurations and Function Descriptions ........................... 9 Bipolar Operation Using the AD5624R/AD5644R/AD5664R ....................................................................................................... 25 Typical Performance Characteristics ........................................... 10 Using AD5624R/AD5644R/AD5664R with a Galvanically Terminology .................................................................................... 18 Isolated Interface ........................................................................ 25 Theory of Operation ...................................................................... 20 Power Supply Bypassing and Grounding ................................ 26 Digital-to-Analog Section ......................................................... 20 Outline Dimensions ....................................................................... 27 Resistor String ............................................................................. 20 Ordering Guide .......................................................................... 28 Output Amplifier ........................................................................ 20 REVISION HISTORY 4/13—Rev. B to Rev. C 4/08—Rev. A to Rev. B Added 12-Ball WLCSP ...................................................... Universal Changes to Figure 50...................................................................... 20 Changes to Features and Product Highlights Sections ................ 1 Updated Outline Dimensions ....................................................... 27 Change to Reference TC Parameter, Table 2 ................................. 3 Changes to Ordering Guide .......................................................... 28 Added Thermal Impedance, WLCSP Package (4-Layer Board), θ Parameter, Table 6 ....................................................................... 8 11/06—Rev. 0 to Rev. A JA Added Figure 4; Renumbered Sequentially .................................. 9 Changes to Reference Output Parameter in Table 2 ..................... 3 Changes to Figure 3 Caption and Table 7...................................... 9 Changes to Reference Output Parameter in Table 3 ..................... 5 Updated Outline Dimensions ....................................................... 27 Added Note to Figure 3 .................................................................... 9 Changes to Ordering Guide .......................................................... 28 4/06—Revision 0: Initial Version Rev. C | Page 2 of 28

Data Sheet AD5624R/AD5644R/AD5664R SPECIFICATIONS AD5624R-5/AD5644R-5/AD5664R-5 V = 4.5 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; V = V ; all specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 2. B Grade1 Parameter Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE2 AD5664R Resolution 16 Bits Relative Accuracy ±8 ±16 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic by design AD5644R Resolution 14 Bits Relative Accuracy ±2 ±4 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design AD5624R Resolution 12 Bits Relative Accuracy ±0.5 ±1 LSB Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design Zero-Code Error 2 10 mV All zeroes loaded to DAC register Offset Error ±1 ±10 mV Full-Scale Error −0.1 ±1 % of FSR All ones loaded to DAC register Gain Error ±1.5 % of FSR Zero-Code Error Drift ±2 µV/°C Gain Temperature Coefficient ±2.5 ppm Of FSR/°C DC Power Supply Rejection Ratio −100 dB DAC code = midscale; V = 5 V ± 10% DD DC Crosstalk External Reference 10 µV Due to full-scale output change, R = 2 kΩ to GND or V L DD 10 µV/mA Due to load current change 5 µV Due to powering down (per channel) Internal Reference 25 µV Due to full-scale output change, R = 2 kΩ to GND or V L DD 20 µV/mA Due to load current change 10 µV Due to powering down (per channel) OUTPUT CHARACTERISTICS3 Output Voltage Range 0 V V DD Capacitive Load Stability 2 nF R = ∞ L 10 nF R = 2 kΩ L DC Output Impedance 0.5 Ω Short-Circuit Current 30 mA V = 5 V DD Power-Up Time 4 µs Coming out of power-down mode; V = 5 V DD REFERENCE INPUTS Reference Current 170 200 µA V = V = 5.5 V REF DD Reference Input Range 0.75 V V DD Reference Input Impedance 26 kΩ REFERENCE OUTPUT Output Voltage 2.495 2.505 V At ambient Reference TC3 ±5 ±10 ppm/°C MSOP package models ±10 ppm/°C LFCSP package models ±15 ppm/°C WLCSP package models Output Impedance 7.5 kΩ Rev. C | Page 3 of 28

AD5624R/AD5644R/AD5664R Data Sheet B Grade1 Parameter Min Typ Max Unit Conditions/Comments LOGIC INPUTS3 Input Current ±2 µA All digital inputs V , Input Low Voltage 0.8 V V = 5 V INL DD V , Input High Voltage 2 V V = 5 V INH DD Pin Capacitance 3 pF POWER REQUIREMENTS V 4.5 5.5 V DD I V = V , V = GND, V = 4.5 V to 5.5 V DD IH DD IL DD Normal Mode4 0.45 0.9 mA Internal reference off 0.95 1.2 mA Internal reference on All Power-Down Modes5 0.48 1 µA 1 Temperature range: B grade: −40°C to +105°C. 2 Linearity calculated using a reduced code range: AD5664R (Code 512 to Code 65,024); AD5644R (Code 128 to Code 16,256); AD5624R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All DACs powered down. AD5624R-3/AD5644R-3/AD5664R-3 V = 2.7 V to 3.6 V; R = 2 kΩ to GND; C = 200 pF to GND; V = V ; all specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 3. B Grade1 Parameter Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE2 AD5664R Resolution 16 Bits Relative Accuracy ±8 ±16 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic by design AD5644R Resolution 14 Bits Relative Accuracy ±2 ±4 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design AD5624R Resolution 12 Bits Relative Accuracy ±0.5 ±1 LSB Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design Zero-Code Error 2 10 mV All zeroes loaded to DAC register Offset Error ±1 ±10 mV Full-Scale Error −0.1 ±1 % of FSR All ones loaded to DAC register Gain Error ±1.5 % of FSR Zero-Code Error Drift ±2 µV/°C Gain Temperature Coefficient ±2.5 ppm Of FSR/°C DC Power Supply Rejection Ratio −100 dB DAC code = midscale; V = 3 V ± 10% DD DC Crosstalk External Reference 10 µV Due to full-scale output change, R = 2 kΩ to GND or V L DD 10 µV/mA Due to load current change 5 µV Due to powering down (per channel) Internal Reference 25 µV Due to full-scale output change, R = 2 kΩ to GND or V L DD 20 µV/mA Due to load current change 10 µV Due to powering down (per channel) Rev. C | Page 4 of 28

Data Sheet AD5624R/AD5644R/AD5664R B Grade1 Parameter Min Typ Max Unit Conditions/Comments OUTPUT CHARACTERISTICS3 Output Voltage Range 0 V V DD Capacitive Load Stability 2 nF R = ∞ L 10 nF R = 2 kΩ L DC Output Impedance 0.5 Ω Short-Circuit Current 30 mA V = 3 V DD Power-Up Time 4 µs Coming out of power-down mode; V = 3 V DD REFERENCE INPUTS Reference Current 170 200 µA V = V = 3.6 V REF DD Reference Input Range 0 V V DD Reference Input Impedance 26 kΩ REFERENCE OUTPUT Output Voltage 1.247 1.253 V At ambient Reference TC3 ±5 ±15 ppm/°C MSOP package models ±10 ppm/°C LFCSP package models Output Impedance 7.5 kΩ LOGIC INPUTS3 Input Current ±2 µA All digital inputs V , Input Low Voltage 0.8 V V = 3 V INL DD V , Input High Voltage 2 V V = 3 V INH DD Pin Capacitance 3 pF POWER REQUIREMENTS V 2.7 3.6 V DD I V = V , V = GND, V = 2.7 V to 3.6 V DD IH DD IL DD Normal Mode4 0.44 0.85 mA Internal reference off 0.95 1.15 mA Internal reference on All Power-Down Modes5 0.2 1 µA 1 Temperature range: B grade: −40°C to +105°C. 2 Linearity calculated using a reduced code range: AD5664R (Code 512 to Code 65,024); AD5644R (Code 128 to Code 16,256); AD5624R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All DACs powered down. Rev. C | Page 5 of 28

AD5624R/AD5644R/AD5664R Data Sheet AC CHARACTERISTICS V = 2.7 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; V = V ; all specifications T to T , unless otherwise noted.1 DD L L REFIN DD MIN MAX Table 4. Parameter2 Min Typ Max Unit Conditions/Comments3 Output Voltage Settling Time AD5624R 3 4.5 µs ¼ to ¾ scale settling to ±0.5 LSB AD5644R 3.5 5 µs ¼ to ¾ scale settling to ±0.5 LSB AD5664R 4 7 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 1.8 V/µs Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB change around major carry Digital Feedthrough 0.1 nV-s Reference Feedthrough −90 dB V = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz REF Digital Crosstalk 0.1 nV-s Analog Crosstalk 1 nV-s External reference 4 nV-s Internal reference DAC-to-DAC Crosstalk 1 nV-s External reference 4 nV-s Internal reference Multiplying Bandwidth 340 kHz V = 2 V ± 0.1 V p-p REF Total Harmonic Distortion −80 dB V = 2 V ± 0.1 V p-p, frequency = 10 kHz REF Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz 100 nV/√Hz DAC code = midscale, 10 kHz Output Noise 15 µV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization, not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical at 25°C. Rev. C | Page 6 of 28

Data Sheet AD5624R/AD5644R/AD5664R TIMING CHARACTERISTICS All input signals are specified with t = t = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2 (see Figure 2). R F DD IL IH V = 2.7 V to 5.5 V; all specifications T to T , unless otherwise noted.1 DD MIN MAX Table 5. Limit at T , T MIN MAX Parameter V = 2.7 V to 5.5 V Unit Conditions/Comments DD t 2 20 ns min SCLK cycle time 1 t 9 ns min SCLK high time 2 t 9 ns min SCLK low time 3 t4 13 ns min SYNC to SCLK falling edge setup time t 5 ns min Data setup time 5 t 5 ns min Data hold time 6 t7 0 ns min SCLK falling edge to SYNC rising edge t8 15 ns min Minimum SYNC high time t9 13 ns min SYNC rising edge to SCLK fall ignore t10 0 ns min SCLK falling edge to SYNC fall ignore 1 Guaranteed by design and characterization, not production tested. 2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. TIMING DIAGRAM t10 t1 t9 SCLK t8 t4 t3 t2 t7 SYNC t6 t5 DIN DB23 DB0 05856-002 Figure 2. Serial Write Operation Rev. C | Page 7 of 28

AD5624R/AD5644R/AD5664R Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 6. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute V to GND −0.3 V to V + 0.3 V OUT DD maximum rating conditions for extended periods may affect V /V to GND −0.3 V to V + 0.3 V REFIN REFOUT DD device reliability. Digital Input Voltage to GND −0.3 V to V + 0.3 V DD Operating Temperature Range Industrial −40°C to +105°C ESD CAUTION Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 150°C J Power Dissipation (T max − T )/θ J A JA Thermal Impedance LFCSP_WD Package (4-Layer Board) θ 61°C/W JA MSOP Package (4-Layer Board) θ 142°C/W JA θ 43.7°C/W JC WLCSP Package (4-Layer Board) θ 75°C/W JA Reflow Soldering Peak Temperature Pb-Free 260°C ± 5°C Rev. C | Page 8 of 28

Data Sheet AD5624R/AD5644R/AD5664R PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS BALLA1 INDICATOR 1 2 3 VVRREEFFOIUNT/ GND VOUTA A VDD GND VOUTB VOUTA 1 10 VREFIN/VREFOUT B AD5624R/ VOUTB 2 AD5644R/ 9 VDD DIN GND VOUTC GND 3 AD5664R 8 DIN C VVOOUUTTCD 45 (NToOt Pto V SIEcaWle) 76 SSCYNLKC 05856-003 D SCLK SYNCVOUTD GENXDP OONS ELDFCPSAPD PTAIECDKATGOE (BALNTLoO tS PtIoD V ESIE cDWaOleWN) 05856-104 Figure 3. 10-Lead LFCSP and 10-Lead MSOP Pin Configuration Figure 4. 12-Ball WLCSP Pin Configuration Table 7. Pin Function Descriptions Pin No. LFCSP MSOP WLCSP Mnemonic Description 1 1 A3 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 2 2 B3 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 3 3 A2, B2, GND Ground Reference Point for all Circuitry on the Part. C2 4 4 C3 V C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT 5 5 D3 V D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT 6 6 D2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 7 7 D1 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. 8 8 C1 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 9 9 B1 V Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be DD decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 10 10 A1 V /V The AD5624R/AD5644R/AD5664R have a common pin for reference input and reference REFIN REFOUT output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. N/A N/A EPAD Exposed Pad. The exposed pad must be tied to GND on the LFCSP package. Rev. C | Page 9 of 28

AD5624R/AD5644R/AD5664R Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 10 1.0 VDD = VREF = 5V VDD = VREF = 5V 8 TA = 25°C 0.8 TA = 25°C 6 0.6 4 0.4 INL ERROR (LSB) ––2402 DNL ERROR (LSB) ––000...4220 –6 –0.6 –1–08 05856-004 ––10..80 05856-007 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 0 10k 20k 30k 40k 50k 60k CODE CODE Figure 5. AD5664R INL, External Reference Figure 8. AD5664R DNL, External Reference 4 0.5 VDD = VREF = 5V VDD = VREF = 5V 3 TA = 25°C 0.4 TA = 25°C 0.3 2 0.2 B) B) R (LS 1 R (LS 0.1 RO 0 RO 0 R R NL E –1 NL E –0.1 I D –0.2 –2 –0.3 ––34 05856-005 ––00..54 05856-008 0 2500 5000 7500 10000 12500 15000 0 2500 5000 7500 10000 12500 15000 CODE CODE Figure 6. AD5644R INL, External Reference Figure 9. AD5644R DNL, External Reference 1.0 0.20 0.8 VTAD D= =2 5V°RCEF = 5V VTAD D= =2 5V°RCEF = 5V 0.15 0.6 0.10 0.4 INL ERROR (LSB) ––000...4202 DNL ERROR (LSB)–00..00550 –0.10 –0.6 ––01..080 500 1000 1500 2000 2500 3000 3500 400005856-006 ––00..2105 05856-009 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 7. AD5624R INL, External Reference Figure 10. AD5624R DNL, External Reference Rev. C | Page 10 of 28

Data Sheet AD5624R/AD5644R/AD5664R 10 1.0 VDD = 5V VDD=5V 8 VREFOUT = 2.5V 0.8 VREFOUT=2.5V TA = 25°C TA=25°C 6 0.6 INL ERROR (LSB) –2042 DNL ERROR (LSB) –000...2420 –4 –0.4 –6 –0.6 –1–08 ––10..08 05856-013 0 5000 10000 15000 20000 25000 30000CODE35000 40000 45000 50000 55000 60000 6500005856-010 0 5000 10000 15000 20000 25000 30000CODE35000 40000 45000 50000 55000 60000 65000 Figure 11. AD5664R-5 INL, Internal Reference Figure 14. AD5664R-5 DNL, Internal Reference 4 0.5 VDD=5V VDD = 5V 3 TVARE=FO2U5T°C=2.5V 0.4 VTAR E=F O2U5T°C = 2.5V 0.3 2 0.2 INL ERROR (LSB) –110 DNL ERROR (LSB) –00..101 –0.2 –2 –0.3 ––43 ––00..54 05856-014 0 1250 2500 3750 5000 6250 7500CODE8750 10000 11250 12500 13750 15000 1625005856-011 0 1250 2500 3750 5000 6250 7500CODE8750 10000 11250 12500 13750 15000 16250 Figure 12. AD5644R-5 INL, Internal Reference Figure 15. AD5644R-5 DNL, Internal Reference 1.0 0.20 VDD=5V VDD = 5V 0.8 VREFOUT=2.5V 0.15 VREFOUT = 2.5V TA=25°C TA = 25°C 0.6 0.10 INL ERROR (LSB) –000...2042 DNL ERROR (LSB)–00..00550 –0.4 –0.10 –0.6 ––10..08 05856-012 ––00..2105 05856-015 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 13. AD5624R-5 INL, Internal Reference Figure 16. AD5624R-5 DNL, Internal Reference Rev. C | Page 11 of 28

AD5624R/AD5644R/AD5664R Data Sheet 10 1.0 VDD = 3V VDD = 3V 8 VREFOUT = 1.25V 0.8 VREFOUT = 1.25V TA = 25°C TA = 25°C 6 0.6 4 0.4 R (LSB) 2 R (LSB) 0.2 NL ERRO –20 NL ERRO –0.20 I D –4 –0.4 –6 –0.6 –1–08 05856-016 ––01..80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 100 150 200 250 300COD350E 400 450 500 550 600 650 50 100 150 200 250 300CODE350 400 450 500 550 600 650 05856-019 Figure 17. AD5664R-3 INL, Internal Reference Figure 20. AD5664R-3 DNL, Internal Reference 4 0.5 VDD = 3V VDD = 3V 3 VREFOUT = 1.25V 0.4 VREFOUT = 1.25V TA = 25°C TA = 25°C 0.3 2 0.2 R (LSB) 1 R (LSB) 0.1 NL ERRO –10 NL ERRO –0.10 I D –0.2 –2 –0.3 ––43 05856-017 ––00..54 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 0 5 0 5 0 5 0 5 0 5 0 5 12 25 37 50 62 C75ODE87 100 112 125 137 150 162 12 25 37 50 62 C75ODE87 100 112 125 137 150 162 05856-020 Figure 18. AD5644R-3 INL, Internal Reference Figure 21. AD5644R-3 DNL, Internal Reference 1.0 0.20 VDD = 3V VDD = 3V 0.8 VREFOUT = 1.25V 0.15 VREFOUT = 1.25V TA = 25°C TA = 25°C 0.6 0.10 0.4 R (LSB) 0.2 R (LSB) 0.05 NL ERRO –0.20 NL ERRO–0.050 I D –0.4 –0.10 –0.6 –0.15 –0.8 –1.00 500 1000 1500 2C0O0D0E 2500 3000 3500 4000 05856-018 –0.200 500 1000 1500 2C0O0D0E 2500 3000 3500 4000 05856-021 Figure 19. AD5624R-3 INL, Internal Reference Figure 22. AD5624R-3 DNL, Internal Reference Rev. C | Page 12 of 28

Data Sheet AD5624R/AD5644R/AD5664R 8 0 VDD = 5V –0.02 6 MAX INL VDD = VREF = 5V –0.04 4 GAIN ERROR –0.06 B) 2 SR) –0.08 OR (LS 0 MAX DNL R (% F –0.10 ERR –2 MIN DNL RRO –0.12 E –0.14 FULL-SCALE ERROR –4 MIN INL –0.16 ––68–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 05856-022 ––00..1280–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 05856-025 Figure 23. INL Error and DNL Error vs. Temperature Figure 26. Gain Error and Full-Scale Error vs. Temperature 10 1.5 8 MAX INL 1.0 ZERO-SCALE ERROR 6 VDD = 5V 0.5 4 TA = 25°C SB) 2 mV) 0 OR (L 0 MAX DNL OR ( –0.5 ERR –2 MIN DNL ERR –1.0 –4 –1.5 –6 OFFSET ERROR MIN INL –2.0 –8 –100.75 1.25 1.75 2.25 V2.R7E5F (V3).25 3.75 4.25 4.75 05856-023 –2.5–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 05856-026 Figure 24. INL Error and DNL Error vs. VREF Figure 27. Zero-Scale Error and Offset Error vs. Temperature 8 1.0 6 MAX INL 0.5 TA = 25°C 4 GAIN ERROR R) 0 LSB) 2 MAX DNL % FS FULL-SCALE ERROR R ( 0 R ( –0.5 O O RR MIN DNL RR E –2 E –1.0 –4 MIN INL –1.5 –6 –82.7 3.2 3.7 VDD 4(V.2) 4.7 5.2 05856-024 –2.02.7 3.2 3.7 VDD 4(V.2) 4.7 5.2 05856-027 Figure 25. INL Error and DNL Error vs. Supply Figure 28. Gain Error and Full-Scale Error vs. Supply Rev. C | Page 13 of 28

AD5624R/AD5644R/AD5664R Data Sheet 1.0 TA = 25°C 8 VTAD D= =2 53°.6CV 0.5 ZERO-SCALE ERROR 7 6 0 V) CY 5 OR (m –0.5 QUEN 4 ERR –1.0 FRE 3 –1.5 2 ––22..052.7 3.2 3.7 VDD 4(V.2) O4F.F7SET ERR5O.2R 05856-028 01 0.39 0.40 0I.D4D1 (mA) 0.42 0.43 05856-060 Figure 29. Zero-Scale Error and Offset Error vs. Supply Figure 32. IDD Histogram with External Reference, 3.6 V VDD= 5.5V 8 VDD= 3.6V 6 TA = 25°C TA = 25°C 7 5 6 CY 4 CY 5 N N E E U U EQ 3 EQ 4 R R F F 3 2 2 1 0 05856-029 01 05856-061 0.41 0.42 0.43 0.44 0.45 0.90 0.92 0.94 0.96 IDD (mA) IDD (mA) Figure 30. IDD Histogram with External Reference, 5.5 V Figure 33. IDD Histogram with Internal Reference, VREFOUT = 1.25 V 0.5 6 VDD= 5.5V DAC LOADED WITH DAC LOADED WITH TA = 25°C 0.4 FULL-SCALE ZERO-SCALE SOURCING CURRENT SINKING CURRENT 5 0.3 V) 0.2 Y 4 E ( QUENC 3 OLTAG 0.01 VVDRDEF=O U3VT = 1.25V RE R V F O –0.1 R 2 R E –0.2 1 –0.3 VDD= 5V 0 0.92 0.94 IDD (m0.A96) 0.98 05856-030 ––00..54–10 –8 –6VRE–F4OUT =C– 2U2.R5RVE0NT (mA2) 4 6 8 10 05856-031 Figure 31. IDD Histogram with Internal Reference, VREFOUT = 2.5 V Figure 34. Headroom at Rails vs. Source and Sink Rev. C | Page 14 of 28

Data Sheet AD5624R/AD5644R/AD5664R 6 VDD= 5V FULL SCALE VREFOUT = 2.5V 5 TA = 25°C 4 3/4 SCALE VDD = VREF = 5V (V)UT 3 MIDSCALE TF0xUA0 L=0L 02-0S5C°TCAOL 0Ex CFFOFDFE CHANGE VO 2 OUTPUT LOADED WITH 2kΩ AND 200pFTO GND 1/4 SCALE 1 VOUT= 909mV/DIV 0 ZERO SCALE 1 –1–30 –20 –10 CURRE0NT (mA) 10 20 30 05856-046 TIME BASE = 4µs/DIV 05856-048 Figure 35. AD56x4R-5 Source and Sink Capability Figure 38. Full-Scale Settling Time, 5 V 4 VDD= 3V VDD = VREF = 5V VREFOUT = 1.25V TA = 25°C TA = 25°C 3 FULL SCALE 3/4 SCALE 2 V) (UT MIDSCALE VO VDD 1 1 1/4 SCALE MAX(C2) 0 ZERO SCALE 420.0mV 2 VOUT –1–30 –20 –10 CURRE0NT (mA) 10 20 30 05856-047 CH1 2.0V CH2 500mV MA 1C0H01µ s 1 215.M28SV/s 8.0ns/pt 05856-049 Figure 36. AD56x4R-3 Source and Sink Capability Figure 39. Power-On Reset to 0 V 0.50 VDD = VREFIN = 5V SYNC 0.45 1 0.40 SCLK VDD = VREFIN = 3V 3 0.35 0.30 A) m (D 0.25 D I 0.20 0.15 VOUT 0.10 VDD = 5V 0.050–40TA = 2–52°0C 0 TEM2P0ERATU4R0E (°C)60 80 100 05856-063 2 CCHH13 55..00VV CH2 500mV M400ns A CH1 1.4V 05856-050 Figure 37. Supply Current vs. Temperature Figure 40. Exiting Power-Down to Midscale Rev. C | Page 15 of 28

AD5624R/AD5644R/AD5664R Data Sheet 2.538 2.537 VDD= VREF = 5V VDD = VREF = 5V 2.536 T5nAs =/S 2A5M°CPLE NUMBER TDAA C= 2L5O°ACDED WITH MIDSCALE 2.535 GLITCH IMPULSE = 9.494nV 2.534 1LSB CHANGEAROUND 2.533 MIDSCALE (0x8000TO 0x7FFF) 2.532 V)2.531 (OUT22..552390 1 V2.528 2.527 2.526 2.525 2.524 222...555222123 05856-058 YXAAXXIISS == 24µs/VD/DIVIV 05856-051 0 50 100 150 200 250 300 350 400 450 512 SAMPLE NUMBER Figure 41. Digital-to-Analog Glitch Impulse (Negative) Figure 44. 0.1 Hz to 10 Hz Output Noise Plot, External Reference 2.498 VDD= VREF = 5V VDD = 5V TA = 25°C VREFOUT = 2.5V 2.497 5ns/SAMPLE NUMBER TA = 25°C ANALOG CROSSTALK = 0.424nV DAC LOADED WITH MIDSCALE 2.496 V V)2.495 DI V (OUT2.494 10µV/1 2.493 2.492 2.4910 50 100 150 200 250 300 350 400 450 51205856-059 5s/DIV 05856-052 SAMPLE NUMBER Figure 42. Analog Crosstalk, External Reference Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference 2.496 2.494 VDD = 3V 2.492 VREFOUT = 1.25V 2.490 TDAA C= L25O°ACDED WITH MIDSCALE 2.488 2.486 2.484 2.482 V (V)OUT2222....444477784680 5µV/DIV1 2.472 2.470 2.468 2.466 VDD= 5V 2.464 VREFOUT = 2.5V 2222....4444556668020 50 100 150 200 5AT2n5AN0s A=/S L2AO53M°0GC0P CLRE3O 5NS0USMTAB40LE0KR = 445.4062nV51205856-062 4s/DIV 05856-053 SAMPLE NUMBER Figure 43. Analog Crosstalk, 2.5 V Internal Reference Figure 46. 0.1 Hz to 10 Hz Output Noise Plot, 1.25 V Internal Reference Rev. C | Page 16 of 28

Data Sheet AD5624R/AD5644R/AD5664R 800 16 TA = 25°C VREF = VDD 700 MIDSCALE LOADED TA = 25°C 14 Hz) 600 VDD=3V nV/√ 500 12 NOISE ( 400 ME (µs) 10 T TI UTPU 300 VDD= 5V 8 VDD=5V O 200 VREFOUT = 2.5V 6 100 VDD= 3V VREFOUT = 1.25V 0100 1k FREQU1E0NkCY (Hz) 100k 1M 05856-054 40 1 2 3 CA4PACITA5NCE 6(nF) 7 8 9 10 05856-056 Figure 47. Noise Spectral Density, Internal Reference Figure 49. Settling Time vs. Capacitive Load –20 5 –30 VTAD D= =2 55°VC 0 TVAD D= =2 55°VC DAC LOADED WITH FULL SCALE VREF = 2V ± 0.3V p-p –5 –40 DE (dB) –50 DE (dB) ––1150 U –60 U PLIT PLIT –20 M –70 M A A –25 –80 –30 –90 –35 –100 2k F4RkEQUENCY 6(Hkz) 8k 10k 05856-055 –4010k 100kFREQUENCY (Hz)1M 10M 05856-057 Figure 48. Total Harmonic Distortion Figure 50. Multiplying Bandwidth Rev. C | Page 17 of 28

AD5624R/AD5644R/AD5664R Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Output Voltage Settling Time For the DAC, relative accuracy or integral nonlinearity is a This is the amount of time it takes for the output of a DAC to measurement of the maximum deviation, in LSBs, from a settle to a specified level for a ¼ to ¾ full-scale input change straight line passing through the endpoints of the DAC transfer and is measured from the 24th falling edge of SCLK. function. A typical INL vs. code plot can be seen in Figure 5. Digital-to-Analog Glitch Impulse Differential Nonlinearity (DNL) Digital-to-analog glitch impulse is the impulse injected into the Differential nonlinearity is the difference between the measured analog output when the input code in the DAC register changes change and the ideal 1 LSB change between any two adjacent state. It is normally specified as the area of the glitch in nV-s, codes. A specified differential nonlinearity of ±1 LSB maximum and is measured when the digital input code is changed by ensures monotonicity. This DAC is guaranteed monotonic by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see design. A typical DNL vs. code plot can be seen in Figure 8. Figure 41). Zero-Code Error Digital Feedthrough Zero-scale error is a measurement of the output error when Digital feedthrough is a measure of the impulse injected into zero code (0x0000) is loaded to the DAC register. Ideally, the the analog output of the DAC from the digital inputs of the output should be 0 V. The zero-code error is always positive in DAC, but is measured when the DAC output is not updated. It the AD5664R because the output of the DAC cannot go below is specified in nV-s, and measured with a full-scale code change 0 V due to a combination of the offset errors in the DAC and on the data bus, that is, from all 0s to all 1s and vice versa. the output amplifier. Zero-code error is expressed in mV. A plot Reference Feedthrough of zero-code error vs. temperature can be seen in Figure 27. Reference feedthrough is the ratio of the amplitude of the signal Full-Scale Error at the DAC output to the reference input when the DAC output Full-scale error is a measurement of the output error when full- is not being updated. It is expressed in dB. scale code (0xFFFF) is loaded to the DAC register. Ideally, the Noise Spectral Density output should be V − 1 LSB. Full-scale error is expressed in DD This is a measurement of the internally generated random percent of full-scale range. A plot of full-scale error vs. noise. Random noise is characterized as a spectral density temperature can be seen in Figure 26. (nV/√Hz). It is measured by loading the DAC to midscale and Gain Error measuring noise at the output. It is measured in nV/√Hz. A plot This is a measure of the span error of the DAC. It is the deviation of noise spectral density can be seen in Figure 47. in slope of the DAC transfer characteristic from the ideal DC Crosstalk expressed as % of FSR. DC crosstalk is the dc change in the output level of one DAC in Zero-Code Error Drift response to a change in the output of another DAC. It is This is a measurement of the change in zero-code error with a measured with a full-scale output change on one DAC (or soft change in temperature. It is expressed in µV/°C. power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in μV. Gain Temperature Coefficient This is a measurement of the change in gain error with changes DC crosstalk due to load current change is a measure of the in temperature. It is expressed in ppm of FSR/°C. impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in μV/mA. Offset Error Offset error is a measure of the difference between V (actual) Digital Crosstalk OUT and V (ideal) expressed in mV in the linear region of the This is the glitch impulse transferred to the output of one DAC OUT transfer function. Offset error is measured on the AD5664R at midscale in response to a full-scale code change (all 0s to all with code 512 loaded in the DAC register. It can be negative or 1s and vice versa) in the input register of another DAC. It is positive. measured in standalone mode and is expressed in nV-s. DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V to OUT a change in V for full-scale output of the DAC. It is measured DD in dB. V is held at 2 V, and V is varied by ±10%. REF DD Rev. C | Page 18 of 28

Data Sheet AD5624R/AD5644R/AD5664R Analog Crosstalk Multiplying Bandwidth This is the glitch impulse transferred to the output of one DAC The amplifiers within the DAC have a finite bandwidth. The due to a change in the output of another DAC. It is measured by multiplying bandwidth is a measure of this. A sine wave on the loading one of the input registers with a full-scale code change reference (with full-scale code loaded to the DAC) appears on (all 0s to all 1s and vice versa). Then execute a software LDAC the output. The multiplying bandwidth is the frequency at and monitor the output of the DAC whose digital code was not which the output amplitude falls to 3 dB below the input. changed. The area of the glitch is expressed in nV-s. Total Harmonic Distortion (THD) DAC-to-DAC Crosstalk This is the difference between an ideal sine wave and its This is the glitch impulse transferred to the output of one DAC attenuated version using the DAC. The sine wave is used as the due to a digital code change and subsequent analog output reference for the DAC, and the THD is a measurement of the change of another DAC. It is measured by loading the attack harmonics present on the DAC output. It is measured in dB. channel with a full-scale code change (all 0s to all 1s and vice versa) using the command write to and update while monitor- ing the output of the victim channel that is at midscale. The energy of the glitch is expressed in nV-s. Rev. C | Page 19 of 28

AD5624R/AD5644R/AD5664R Data Sheet THEORY OF OPERATION DIGITAL-TO-ANALOG SECTION R The AD5624R/AD5644R/AD5664R DACs are fabricated on a CMOS process. The architecture consists of a string DAC R followed by an output buffer amplifier. Figure 51 shows a block diagram of the DAC architecture. R TO OUTPUT VDD AMPLIFIER VREFIN OUTPUT AMPLIFIER (GAIN = +2) REF DAC REGISTER VOUT RESISTOR STRING GND 05856-032 R Figure 51. DAC Architecture R Because the input coding to the DAC is straight binary, the ideal 05856-033 output voltage when using an external reference is given by Figure 52. Resistor String  D  INTERNAL REFERENCE V =V ×  OUT REFIN 2N  The AD5624R/AD5644R/AD5664R on-chip reference is off at The ideal output voltage when using the internal reference is power-up and is enabled via a write to a control register. See the given by Internal Reference Setup section for details.  D  The AD56x4R-3 has a 1.25 V, 5 ppm/°C reference giving a full- V =2×V ×  OUT REFOUT 2N  scale output of 2.5 V. The AD56x4R-5 has a 2.5 V, 5 ppm/°C reference giving a full-scale output of 5 V. The internal reference where: associated with each part is available at the V pin. A buffer REFOUT D is the decimal equivalent of the binary code that is loaded to is required if the reference output is used to drive external loads. the DAC register: When using the internal reference, it is recommended that a 0 to 4095 for AD5624R (12 bit). 100 nF capacitor is placed between reference output and GND 0 to 16,383 for AD5644R (14 bit). for reference stability. 0 to 65,535 for AD5664R (16 bit). EXTERNAL REFERENCE N is the DAC resolution. The V pin on the AD56x4R-3 and AD56x4R-5 allows the REFIN RESISTOR STRING use of an external reference if the application requires it. The default condition of the on-chip reference is off at power-up. All The resistor string is shown in Figure 52. It is simply a string of devices (AD56x4R-3 and the AD56x4R-5) can be operated resistors, each of value R. The code loaded to the DAC register from a single 2.7 V to 5.5 V supply. determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by SERIAL INTERFACE closing one of the switches connecting the string to the The AD5624R/AD5644R/AD5664R have a 3-wire serial interface amplifier. Because it is a string of resistors, it is guaranteed (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and monotonic. MICROWIRE interface standards as well as with most DSPs. See OUTPUT AMPLIFIER Figure 2 for a timing diagram of a typical write sequence. The output buffer amplifier can generate rail-to-rail voltages on The write sequence begins by bringing the SYNC line low. Data its output, which gives an output range of 0 V to VDD. It can drive from the DIN line is clocked into the 24-bit shift register on the a load of 2 kΩ in parallel with 1000 pF to GND. The source and falling edge of SCLK. The serial clock frequency can be as high sink capabilities of the output amplifier can be seen in Figure 34 as 50 MHz, making the AD5624R/AD5644R/AD5664R compat- and Figure 35. The slew rate is 1.8 V/µs with a ¼ to ¾ full-scale ible with high speed DSPs. On the 24th falling clock edge, the settling time of 7 µs. last data bit is clocked in and the programmed function is executed, that is, a change in DAC register contents and/or a change in the mode of operation. Rev. C | Page 20 of 28

Data Sheet AD5624R/AD5644R/AD5664R At this stage, the SYNC line can be kept low or be brought high. In Table 8. Command Definition either case, it must be brought high for a minimum of 15 ns before C2 C1 C0 Command the next write sequence so that a falling edge of SYNC can initiate 0 0 0 Write to input register n the next write sequence. 0 0 1 Update DAC register n Because the SYNC buffer draws more current when V = 2 V 0 1 0 Write to input register n, update all IN (software LDAC) than it does when V = 0.8 V, SYNC should be idled low IN 0 1 1 Write to and update DAC channel n between write sequences for even lower power operation. As 1 0 0 Power down DAC (power-up) mentioned previously, it must, however, be brought high again 1 0 1 Reset just before the next write sequence. 1 1 0 LDAC register setup INPUT SHIFT REGISTER 1 1 1 Internal reference setup (on/off) The input shift register is 24 bits wide (see Figure 53). The first two bits are don’t care bits. The next three are the command Table 9. Address Command bits, C2 to C0 (see Table 8), followed by the 3-bit DAC address, A2 A1 A0 Address (n) A2 to A0 (see Table 9), and then the 16-, 14-, 12-bit data-word. 0 0 0 DAC A The data-word comprises the 16-, 14-, 12-bit input code 0 0 1 DAC B followed by 0, 2, or 4 don’t care bits, for the AD5664R, 0 1 0 DAC C AD5644R, and AD5624R, respectively (see Figure 53, Figure 54, 0 1 1 DAC D and Figure 55). These data bits are transferred to the DAC 1 1 1 All DACs register on the 24th falling edge of SCLK. SYNC INTERRUPT In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, then this acts as an interrupt to the write sequence. The input shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 56). DB23 (MSB) DB0 (LSB) X X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 COMMAND BITS ADDRESS BITS DATA BITS 05856-034 Figure 53. AD5664R Input Shift Register Contents DB23 (MSB) DB0 (LSB) X X C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X COMMAND BITS ADDRESS BITS DATA BITS 05856-035 Figure 54. AD5644R Input Shift Register Contents DB23 (MSB) DB0 (LSB) X X C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X COMMAND BITS ADDRESS BITS DATA BITS 05856-036 Figure 55. AD5624R Input Shift Register Contents SCLK SYNC DIN DB23 DB0 DB23 DB0 SYNC HINIGVHA LBIEDF WORRIET E2 4STEHQ FUAELNLCINEG: EDGE VALID WORNIT TEH SEE 2Q4UTEH NFCAEL,L OINUGT PEUDTG UEPDATES 05856-037 Figure 56. SYNC Interrupt Facility Rev. C | Page 21 of 28

AD5624R/AD5644R/AD5664R Data Sheet POWER-ON RESET By executing the same Command 100, any combination of DACs can be powered up by setting the bits (DB5 and DB4) to normal The AD5624R/AD5644R/AD5664R family contains a power-on operation mode. To select which combination of DAC channels reset circuit that controls the output voltage during power-up. to power-up, set the corresponding four bits (DB3, DB2, DB1, The output of the AD5624R/AD5644R/AD5664R DACs powers and DB0) to 1. See Table 13 for contents of the input shift register up to 0 V and the output remains there until a valid write during power-down/power-up operation. sequence is made to the DACs. This is useful in applications where it is important to know the state of the output of the Table 11. Modes of Operation for the AD5624R/AD5644R/ DACs while they are in the process of powering up. AD5664R SOFTWARE RESET DB5 DB4 Operating Mode 0 0 Normal operation The AD5624R/AD5644R/AD5664R contain a software reset 0 1 Power-down mode: 1 kΩ to GND function. Command 101 is reserved for the software reset 1 0 Power-down mode: 100 kΩ to GND function (see Table 8). The software reset command contains 1 1 Power-down mode: three-state two reset modes that are software programmable by setting bit DB0 in the control register. When Bit DB5 and Bit DB4 are set to 0, the part works normally Table 10 shows how the state of the bit corresponds to the with its normal power consumption of 450 µA at 5 V. However, software reset modes of operation of the devices. for the three power-down modes, the supply current falls to Table 12 shows the contents of the input shift register during the 480 nA at 5 V (200 nA at 3 V). Not only does the supply current software reset mode of operation. fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. Table 10. Software Reset Modes for the This allows the output impedance of the part to be known while AD5624R/AD5644R/AD5664R the part is in power-down mode. The outputs can either be DB0 Registers Reset to 0 connected internally to GND through a 1 kΩ resistor, or left 0 DAC register open-circuited (three-state) as shown in Figure 57. Input shift register 1 (Power-On Reset) DAC register RESISTOR Input shift register STRING DAC AMPLIFIER VOUT LDAC register Power-down register Internal reference setup register POWER-DOWN CIRCUITRY RESISTOR POWER-DOWN MODES NETWORK 05856-038 The AD5624R/AD5644R/AD5664R contain four separate modes Figure 57. Output Stage During Power-Down of operation. Command 100 is reserved for the power-down The bias generator, the output amplifier, the resistor string, and function (see Table 8). These modes are software programmable other associated linear circuitry are shutdown when power-down by setting two bits (DB5 and DB4) in the control register. Table 11 mode is activated. However, the contents of the DAC register are shows how the state of the bits corresponds to the mode of unaffected when in power-down. The time to exit power-down operation of the device. All DACs (DAC D to DAC A) can be is typically 4 µs for V = 5 V and for V = 3 V (see Figure 40). DD DD powered down to the selected mode by setting the correspond- ing four bits (DB3, DB2, DB1, and DB0) to 1. Table 12. 24-Bit Input Shift Register Contents for Software Reset Command DB23 to DB22 (MSB) DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0 (LSB) x 1 0 1 x x x x 1/0 Don’t care Command bits (C2 to C0) Address bits (A2 to A0) Don’t care Determines software reset mode Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation for the AD5624R/AD5644R/AD5664R DB23 to DB22 DB15 DB0 (MSB) DB21 DB20 DB19 DB18 DB17 DB16 to DB6 DB5 DB4 DB3 DB2 DB1 (LSB) x 1 0 0 x x x x PD1 PD0 DAC D DAC C DAC B DAC A Don’t Command bits (C2 to C0) Address bits (A2 to A0) Don’t Power-down Power-down/power-up channel care Don’t care care mode selection, set bit to 1 to select channel Rev. C | Page 22 of 28

Data Sheet AD5624R/AD5644R/AD5664R LDAC FUNCTION This flexibility is useful in applications where the user wants to update select channels simultaneously, while the rest of the The AD5624R/AD5644R/AD5664R DACs have double- channels update synchronously. buffered interfaces consisting of two banks of registers: input registers and DAC registers. The input registers are connected Table 14. LDAC Register Mode of Operation directly to the input shift register and the digital code is trans- LDAC Bits ferred to the relevant input register on completion of a valid (DB3 to DB0) LDAC Mode of Operation write sequence. The DAC registers contain the digital code used 0 Normal operation (default), DAC register by the resistor strings. update is controlled by write command. 1 The DAC registers are updated after new The double-buffered interface is useful if the user requires data is read in on the falling edge of the simultaneous updating of all DAC outputs. The user can write 24th SCLK pulse. to three of the input registers individually and then write to the remaining input register, updating all DAC registers simulta- INTERNAL REFERENCE SETUP neously. Command 010 is reserved for this software LDAC. The on-chip reference is off at power-up by default. This reference Access to the DAC registers is controlled by the LDAC function. can be turned on or off by setting a software programmable bit, The LDAC register contains two modes of operation for each DB0, in the control register. Table 15 shows how the state of the DAC channel. The DAC channels are selected by setting the bit corresponds to the mode of operation. Command 111 is bits of the 4-bit LDAC register (DB3, DB2, DB1, and DB0). reserved for setting up the internal reference (see Table 8). Command 110 is reserved for setting up the LDAC register. Table 16 shows how the state of the bits in the input shift When the LDAC bit register is set low, the corresponding DAC register corresponds to the mode of operation of the device registers are latched and the input registers can change state during internal reference setup. without affecting the contents of the DAC registers. When the LDAC bit register is set high, however, the DAC registers Table 15. Reference Setup Register become transparent and the contents of the input registers are Internal Reference transferred to them on the falling edge of the 24th SCLK pulse. Setup Register This is equivalent to having an LDAC hardware pin tied perma- (DB0) Action nently low for the selected DAC channel, that is, synchronous 0 Reference off (default) update mode. See Table 14 for the LDAC register mode of 1 Reference on operation. See Table 16 for contents of the input shift register during the LDAC register setup command. Table 16. 24-Bit Input Shift Register Contents for LDAC Setup Command for the AD5624R/AD5644R/AD5664R DB23 to DB22 (MSB) DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB4 DB3 DB2 DB1 DB0 (LSB) x 1 1 0 x x x x DAC D DAC C DAC B DAC A Don’t care Command bits Address bits Don’t care Set bit to 0 or 1 for required mode of (C2 to C0) (A2 to A0); don’t care operation on respective channel Table 17. 24-Bit Input Shift Register Contents for Internal Reference Setup Command DB23 to DB22 (MSB) DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0 (LSB) x 1 1 1 x x x x 1/0 Don’t care Command bits (C2 to C0) Address bits (A2 to A0) Don’t care Reference setup register Rev. C | Page 23 of 28

AD5624R/AD5644R/AD5664R Data Sheet MICROPROCESSOR INTERFACING AD5624R/AD5644R/AD5664R to 80C51/80L51 Interface AD5624R/AD5644R/AD5664R to Blackfin ADSP-BF53x Figure 60 shows a serial interface between the AD5624R/ Interface AD5644R/AD5664R and the 80C51/80L51 microcontroller. The Figure 58 shows a serial interface between the AD5624R/ setup for the interface is that the TxD of the 80C51/80L51 drives AD5644R/AD5664R and the Blackfin® ADSP-BF53x micro- SCLK of the AD5624R/AD5644R/AD5664R, while RxD drives the processor. The ADSP-BF53x processor family incorporates two serial data line of the part. The SYNC signal is derived from a bit- dual-channel synchronous serial ports, SPORT1 and SPORT0, programmable pin on the port. In this case, port line P3.3 is used. for serial and multiprocessor communications. Using SPORT0 When data is transmitted to the AD5624R/AD5644R/AD5664R, to connect to the AD5624R/AD5644R/AD5664R, the setup for P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes the interface is that the DT0PRI drives the DIN pin of the only; thus, only eight falling clock edges occur in the transmit cycle. AD5624R/AD5644R/AD5664R, while TSCLK0 drives the To load data to the DAC, P3.3 is left low after the first eight bits are SCLK of the part. The SYNC is driven from TFS0. transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of ADSP-BF53x1 AD5624R/ this cycle. The 80C51/80L51 outputs the serial data in LSB first AD5644R/ AD5664R1 format. The AD5624R/AD5644R/AD5664R must receive data with TFS0 SYNC the MSB first. The 80C51/80L51 transmit routine should take this DTOPRI DIN into account. 1ADDITIOTSNCALLK P0INS OMITTED FOSRC CLLKARITY. 05856-039 80C51/80L511 AAADDD555666624444RRR1// Figure 58. Blackfin ADSP-BF53x Interface to AD5624R/AD5644R/AD5664R P3.3 SYNC AD5624R/AD5644R/AD5664R to 68HC11/68L11 TxD SCLK Interface Figure 59 shows a serial interface between the AD5624R/ 1ADDITIONALR PxIDNS OMITTED FORD CINLARITY. 05856-041 AD5644R/AD5664R and the 68HC11/68L11 microcontroller. Figure 60. 80C51/80L51 Interface to AD5624R/AD5644R/AD5664R SCK of the 68HC11/68L11 drives the SCLK of the AD5624R/ AD5624R/AD5644R/AD5664R to MICROWIRE Interface AD5644R/AD5664R, while the MOSI output drives the serial data line of the DAC. Figure 61 shows an interface between the AD5624R/AD5644R/ AD5664R and any MICROWIRE-compatible device. Serial data The SYNC signal is derived from a port line (PC7). The setup is shifted out on the falling edge of the serial clock and is conditions for correct operation of this interface are that the clocked into the AD5624R/AD5644R/AD5664R on the rising 68HC11/68L11 is configured with its CPOL bit as 0 and its edge of the SK. CPHA bit as 1. When data is transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured MICROWIRE1 AD5624R/ AD5644R/ as described previously, data appearing on the MOSI output is AD5664R1 valid on the falling edge of SCK. Serial data from the 68HC11/ CS SYNC 68L11 is transmitted in 8-bit bytes with only eight falling clock SK SCLK edges occurring in the transmit cycle. Data is transmitted MSB fleirfst tl.o Two aloftaedr tdhaet af itros tt heieg hAtD b5it6s2 a4rRe/ AtrDan5s6fe4r4rRe/dA, Dan5d6 6a4 sRe,c PoCnd7 is 1ADDITIONAL PSIONS OMITTED FORD CINLARITY. 05856-042 serial write operation is performed to the DAC; PC7 is taken Figure 61. MICROWIRE Interface to AD5624R/AD5644R/AD5664R high at the end of this procedure. 68HC11/68L111 AD5624R/ AD5644R/ AD5664R1 PC7 SYNC SCK SCLK MOSI DIN 1ADDITIONAL PINS OMITTED FOR CLARITY. 05856-040 Figure 59. 68HC11/68L11 Interface to AD5624R/AD5644R/AD5664R Rev. C | Page 24 of 28

Data Sheet AD5624R/AD5644R/AD5664R APPLICATIONS INFORMATION USING A REFERENCE AS A POWER SUPPLY FOR R2 = 10kΩ THE AD5624R/AD5644R/AD5664R +5V +5V R1 = 10kΩ Because the supply current required by the AD5624R/AD5644R/ AD820/ AD5664R is extremely low, an alternative option is to use a ±5V OP295 voltage reference to supply the required voltage to the part (see VDD VOUT Figure 62). This is especially useful if the power supply is quite 10µF 0.1µF AD5624R/ AD5644R/ –5V noisy, or if the system supply voltages are at some value other AD5664R than 5 V or 3 V, for example, 15 V. The voltage reference outputs a steady supply voltage for the AD5624R/AD5644R/AD5664R (ssuepep Flyi g4u5r0e µ6A0) .o Iff c tuhrer elonwt tdor tohpeo AutD R5E6F2149R5/A isD u5s6e4d4, Rit/ mADus5t6 64R INTS3E-EWRRIFIRAAELCE 05856-044 Figure 63. Bipolar Operation with the AD5624R/AD5644R/AD5664R with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the USING AD5624R/AD5644R/AD5664R WITH A load. The total current required (with a 5 kΩ load on the DAC GALVANICALLY ISOLATED INTERFACE output) is In process control applications in industrial environments, it is 450 µA + (5 V/5 kΩ) = 1.45 mA often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common- The load regulation of the REF195 is typically 2 ppm/mA, mode voltages that might occur in the area where the DAC is resulting in a 2.9 ppm (14.5 µV) error for the 1.45 mA current functioning. Isocouplers provide isolation in excess of 3 kV. The drawn from it. This corresponds to a 0.191 LSB error. AD5624R/AD5644R/AD5664R use a 3-wire serial logic interface, 15V so the ADuM130x 3-channel digital isolator provides the REF195 5V required isolation (see Figure 64). The power supply to the part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides VDD S3E-WRIIRAEL SSYCNLCK AADD55662444RR// VOUT = 0V TO 5V the 5 V supply required for the AD5624R/AD5644R/AD5664R. INTERFACE DIN AD5664R 5V REGULATOR 05856-043 POWER 10µF 0.1µF Figure 62. REF195 as Power Supply to the AD5624R/AD5644R/AD5664R BIPOLAR OPERATION USING THE VDD AD5624R/AD5644R/AD5664R SCLK VIA VOA SCLK ADuM1300 The AD5624R/AD5644R/AD5664R have been designed for single-supply operation, but a bipolar output range is also SDI VIB VOB SYNC VOUT possible using the circuit in Figure 63. The circuit gives an AD5624R/ AD5644R/ output voltage range of ±5 V. Rail-to-rail operation at the AD5664R DATA VIC VOC DIN amplifier output is achievable using an AD820 or an OP295 as GND the output amplifier. 05856-045 The output voltage for any input code can be calculated as Figure 64. AD5624R/AD5644R/AD5664R with a Galvanically Isolated Interface follows:   D  R1+R2 R2 V =V × × −V ×  OUT  DD 65,536  R1  DD R1 where D represents the input code in decimal (0 to 65,536). With V = 5 V, R1 = R2 = 10 kΩ, DD 10×D V = −5V OUT 65,536 This is an output voltage range of ±5 V, with 0x0000 corre- sponding to a −5 V output, and 0xFFFF corresponding to a +5 V output. Rev. C | Page 25 of 28

AD5624R/AD5644R/AD5664R Data Sheet POWER SUPPLY BYPASSING AND GROUNDING types of capacitors. This 0.1 µF capacitor provides a low imped- ance path to ground for high frequencies caused by transient When accuracy is important in a circuit, it is helpful to carefully currents due to internal logic switching. consider the power supply and ground return layout on the board. The printed circuit board containing the AD5624R/ The power supply line itself should have as large a trace as AD5644R/AD5664R should have separate analog and digital possible to provide a low impedance path and to reduce glitch sections, each having its own area of the board. If the AD5624R/ effects on the supply line. Clocks and other fast switching AD5644R/AD5664R are in a system where other devices require digital signals should be shielded from other parts of the board an AGND-to-DGND connection, the connection should be by digital ground. Avoid crossover of digital and analog signals made at one point only. This ground point should be as close as if possible. When traces cross on opposite sides of the board, possible to the AD5624R/AD5644R/AD5664R. ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout The power supply to the AD5624R/AD5644R/AD5664R should technique is the microstrip technique where the component be bypassed with 10 µF and 0.1 µF capacitors. The capacitors side of the board is dedicated to the ground plane only and the should be located as close as possible to the device, with the signal traces are placed on the solder side. However, this is not 0.1 µF capacitor ideally right up against the device. The 10 µF always possible with a 2-layer board. capacitor is the tantalum bead type. It is important that the 0.1 µF capacitor have low effective series resistance (ESR) and effective series inductance (ESI), for example, common ceramic Rev. C | Page 26 of 28

Data Sheet AD5624R/AD5644R/AD5664R OUTLINE DIMENSIONS 2.48 2.38 3.10 2.23 3.00 SQ 2.90 0.50 BSC 6 10 PIN 1 INDEX EXPOSED 1.74 AREA PAD 1.64 0.50 1.49 0.40 0.30 5 1 0.20 MIN TOP VIEW BOTTOM VIEW PIN 1 INDICATOR (R 0.15) 0.80 FOR PROPER CONNECTION OF 0.75 0.05 MAX THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEPALTAINNGE 000...322050 0.20 REF 0.08 02-05-2013-C Figure 65. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA 091709-A Figure 66. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Rev. C | Page 27 of 28

AD5624R/AD5644R/AD5664R Data Sheet 1.705 1.665 BOTTOM VIEW 1.625 (BALL SIDE UP) 3 2 1 BALLA1 A IDENTIFIER 2.285 2.245 R1.E5F0 B 2.205 C D 0.50 BSC TOP VIEW (BALL SIDE DOWN) 1.00 0.380 REF 0.650 0.355 0.595 END VIEW 0.330 0.540 COPLANARITY 0.05 SEATING 0.270 PLANE 000...333420000 00..224100 08-31-2012-A Figure 67. 12-Ball Wafer Level Chip Scale Package [WLCSP] (CB-12-9) Dimensions shown in millimeters ORDERING GUIDE Package Package Model1 Temperature Range Accuracy Internal Reference Description Option Branding AD5624RBCPZ-3R2 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D7L AD5624RBCPZ-3REEL7 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D7L AD5624RBCPZ-5R2 −40°C to +105°C ±1 LSB INL 2.5 V 10-Lead LFCSP_WD CP-10-9 DBZ AD5624RBCPZ-5REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 10-Lead LFCSP_WD CP-10-9 DBZ AD5624RBRMZ-3 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead MSOP RM-10 D7L AD5624RBRMZ-3REEL7 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead MSOP RM-10 D7L AD5624RBRMZ-5 −40°C to +105°C ±1 LSB INL 2.5 V 10-Lead MSOP RM-10 D7V AD5624RBRMZ-5REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 10-Lead MSOP RM-10 D7V AD5644RBRMZ-3 −40°C to +105°C ±4 LSB INL 1.25 V 10-Lead MSOP RM-10 D7E AD5644RBRMZ-3REEL7 −40°C to +105°C ±4 LSB INL 1.25 V 10-Lead MSOP RM-10 D7E AD5644RBRMZ-5 −40°C to +105°C ±4 LSB INL 2.5 V 10-Lead MSOP RM-10 D7D AD5644RBRMZ-5REEL7 −40°C to +105°C ±4 LSB INL 2.5 V 10-Lead MSOP RM-10 D7D AD5664RBCBZ-3RL7 −40°C to +105°C ±16 LSB INL 1.25 V 12 Ball WLCSP CB-12-9 AD5664RBCPZ-3R2 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D73 AD5664RBCPZ-3REEL7 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D73 AD5664RBRMZ-3 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead MSOP RM-10 D73 AD5664RBRMZ-3REEL7 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead MSOP RM-10 D73 AD5664RBRMZ-5 −40°C to +105°C ±16 LSB INL 2.5 V 10-Lead MSOP RM-10 D75 AD5664RBRMZ-5REEL7 −40°C to +105°C ±16 LSB INL 2.5 V 10-Lead MSOP RM-10 D75 EVAL-AD5664REBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05856-0-4/13(C) Rev. C | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5664REBZ AD5664RBCPZ-3R2 AD5664RBCPZ-3REEL7 AD5644RBRMZ-3 AD5624RBCPZ-5R2 AD5624RBCPZ-3REEL7 AD5664RBRMZ-3 AD5644RBRMZ-3REEL7 AD5624RBRMZ-3REEL7 AD5664RBRMZ- 5REEL7 AD5624RBCPZ-3R2 AD5664RBRMZ-5 AD5624RBRMZ-3 AD5644RBRMZ-5REEL7 AD5624RBRMZ- 5REEL7 AD5644RBRMZ-5 AD5624RBRMZ-5 AD5664RBRMZ-3REEL7 AD5624RBCPZ-5REEL7 AD5664RBCBZ-3- RL7