Dual 12-/14-/16-Bit nanoDAC with 5 ppm/°C On-Chip Reference Data Sheet AD5623R/AD5643R/AD5663R FEATURES FUNCTIONAL BLOCK DIAGRAM Low power, smallest pin-compatible, dual nanoDAC VDD VREFIN/VREFOUT AD5663R: 16 bits LDAC R1E.F25EVR/E2.N5CVE AD5643R: 14 bits AD5623R: 12 bits SCLK REINGPISUTTER REGDIASCTER SDTARCIN AG BUFFER VOUTA User-selectable external or internal reference SYNC INTLEORGFIACCE External reference default DIN REINGPISUTTER REGDIASCTER SDTARCIN BG BUFFER VOUTB On-chip 1.25 V/2.5 V, 5 ppm/°C reference AD5623R/AD5643R/AD5663R 10-lead MSOP and 3 mm × 3 mm LFCSP POWER-ON POWER-DOWN 2.7 V to 5.5 V power supply RESET LOGIC Guaranteed monotonic by design LDAC CLR GND 05858-001 Power-on reset to zero scale Figure 1. Per channel power-down Table 1. Related Devices Serial interface up to 50 MHz Part No. Description Hardware LDAC and CLR functions AD5663 2.7 V to 5.5 V, dual 16-bit nanoDAC, with external APPLICATIONS reference Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION The AD5623R/AD5643R/AD5663R, members of the nanoDAC® The low power consumption of this part in normal operation family, are low power, dual 12-, 14-, and 16-bit buffered voltage- makes it ideally suited to portable, battery-operated equipment. out digital-to-analog converters (DAC) that operate from a single The AD5623R/AD5643R/AD5663R use a versatile, 3-wire serial 2.7 V to 5.5 V supply and are guaranteed monotonic by design. interface that operates at clock rates up to 50 MHz, and they are The AD5623R/AD5643R/AD5663R have an on-chip reference. compatible with standard SPI®, QSPI™, MICROWIRE™, and The AD5623R-3/AD5643R-3/AD5663R-3 have a 1.25 V, DSP interface standards. The on-chip precision output amplifier 5 ppm/°C reference, giving a full-scale output of 2.5 V; and the enables rail-to-rail output swing to be achieved. AD5623R-5/AD5643R-5/AD5663R-5 have a 2.5 V, 5 ppm/°C PRODUCT HIGHLIGHTS reference, giving a full-scale output of 5 V. The on-chip reference is off at power-up, allowing the use of an external 1.Dual 12-, 14-, and 16-bit DAC. reference; and all devices can be operated from a single 2.7 V to 2.On-chip 1.25 V/2.5 V, 5 ppm/°C reference. 5.5 V supply. The internal reference is turned on by writing to 3.Available in 10-lead MSOP and 10-lead, 3 mm × the DAC. 3 mm LFCSP. 4.Low power; typically consumes 0.6 mW at 3 V and The parts incorporate a power-on reset circuit that ensures the 1.25 mW at 5 V. DAC output powers up to 0 V and remains there until a valid 5.4.5 μs maximum settling time for the AD5623R. write takes place. The part contains a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power- down mode. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5623R/AD5643R/AD5663R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Output Amplifier ........................................................................ 21  Applications ....................................................................................... 1  Internal Reference ...................................................................... 21  Functional Block Diagram .............................................................. 1  External Reference ..................................................................... 21  General Description ......................................................................... 1  Serial Interface ............................................................................ 21  Product Highlights ........................................................................... 1  Input Shift Register .................................................................... 22  Revision History ............................................................................... 3  SYNC Interrupt .......................................................................... 22  Specifications ..................................................................................... 4  Power-On Reset .......................................................................... 23  AD5623R-5/AD5643R-5/AD5663R-5 ....................................... 4  Software Reset ............................................................................. 23  AD5623R-3/AD5643R-3/AD5663R-3 ....................................... 6  Power-Down Modes .................................................................. 23  AC Characteristics ........................................................................ 7  LDAC Function .......................................................................... 24  Timing Characteristics ................................................................ 8  Internal Reference Setup ........................................................... 25  Timing Diagram ........................................................................... 8  Microprocessor Interfacing ....................................................... 26  Absolute Maximum Ratings ............................................................ 9  Applications Information .............................................................. 27  ESD Caution .................................................................................. 9  Using a Reference as a Power Supply ....................................... 27  Pin Configuration and Function Descriptions ........................... 10  Bipolar Operation Using the AD5663R ................................... 27  Typical Performance Characteristics ........................................... 11  Using the AD5663R with a Galvanically Isolated Interface .. 27  Terminology .................................................................................... 19  Power Supply Bypassing and Grounding ................................ 28  Theory of Operation ...................................................................... 21  Outline Dimensions ....................................................................... 29  Digital-to-Analog Section ......................................................... 21  Ordering Guide .......................................................................... 30  Resistor String ............................................................................. 21  Rev. G | Page 2 of 32

Data Sheet AD5623R/AD5643R/AD5663R REVISION HISTORY 9/15—Rev. F to Rev. G 4/11—Rev. C to Rev. D Change to Figure 38 ........................................................................ 16 Changes to Ordering Guide ........................................................... 29 Changes to Software Reset Section ............................................... 23 Changes to AD5623R/AD5643R/AD5663R to Blackfin® 6/10—Rev. B to Rev. C Microprocessors Interface Section and Figure 56 ....................... 26 Changes to Ordering Guide ........................................................... 28 Changes to Using the Reference as a Power Supply Section ..... 27 Updated Outline Dimensions ........................................................ 29 4/10—Rev. A to Rev. B Updated Outline Dimensions........................................................ 28 2/13—Rev. E to Rev. F Changes to Table 14 ........................................................................ 23 12/06—Rev. 0 to Rev. A Changes to Table 2 ............................................................................ 3 4/12—Rev. D to Rev. E Changes to Table 3 ............................................................................ 5 Changes to Table 2 ............................................................................ 3 Changes to Figure 3 .......................................................................... 9 Updated Outline Dimensions ........................................................ 28 Changes to Ordering Guide ........................................................... 28 Changes to Ordering Guide ........................................................... 29 4/06—Revision 0: Initial Version Rev. G | Page 3 of 32

AD5623R/AD5643R/AD5663R Data Sheet SPECIFICATIONS AD5623R-5/AD5643R-5/AD5663R-5 V = 4.5 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; V = V ; all specifications T to T unless otherwise noted. DD L L REFIN DD MIN MAX, Table 2. A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE2 AD5663R Resolution 16 Bits Relative Accuracy ±8 ±16 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic by design AD5643R Resolution 14 Bits Relative Accuracy ±2 ±4 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design AD5623R Resolution 12 Bits Relative Accuracy ±1 ±2 ±0.5 ±1 LSB Differential Nonlinearity ±1 ±0.25 LSB Guaranteed monotonic by design Zero-Scale Error +2 +10 +2 +10 mV All 0s loaded to DAC register Offset Error ±1 ±10 ±1 ±10 mV Full-Scale Error −0.1 ±1 −0.1 ±1 % of All 1s loaded to DAC register FSR Gain Error ±1.5 ±1.5 % of FSR Zero-Scale Error Drift ±2 ±2 µV/°C Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C DC Power Supply Rejection Ratio −100 −100 dB DAC code = midscale ; V = 5 V ± DD 10% DC Crosstalk (External Reference) 10 10 µV Due to full-scale output change; R = 2 kΩ to GND or V L DD 10 10 µV/mA Due to load current change 5 5 µV Due to powering down (per channel) DC Crosstalk (Internal Reference) 25 25 µV Due to full-scale output change; R = 2 kΩ to GND or V L DD 20 20 µV/mA Due to load current change 10 10 µV Due to powering down (per channel) OUTPUT CHARACTERISTICS3 Output Voltage Range 0 V 0 V V DD DD Capacitive Load Stability 2 2 nF R = ∞ L 10 10 nF R = 2 kΩ L DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA V = 5 V DD Power-Up Time 4 4 μs Coming out of power-down mode; V = 5 V DD REFERENCE INPUTS Reference Current 170 200 170 200 µA V = V = 5.5 V REF DD Reference Input Range 0.75 V 0.75 V V DD DD Reference Input Impedance 26 26 kΩ Rev. G | Page 4 of 32

Data Sheet AD5623R/AD5643R/AD5663R A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments REFERENCE OUTPUT Output Voltage 2.495 2.505 2.495 2.505 V At ambient Reference Temperature Coefficient3 ±10 ±5 ±10 ppm/°C MSOP package models ±10 ±10 ppm/°C LFCSP package models Output Impedance 7.5 7.5 kΩ LOGIC INPUTS3 Input Current ±2 ±2 µA All digital inputs Input Low Voltage (V ) 0.8 0.8 V V = 5 V INL DD Input High Voltage (V ) 2 2 V V = 5 V INH DD Pin Capacitance 3 3 pF DIN, SCLK, and SYNC 19 19 pF LDAC and CLR POWER REQUIREMENTS V 4.5 5.5 4.5 5.5 V DD I (Normal Mode)4 V = V and V = GND DD IH DD IL V = 4.5 V to 5.5 V 0.25 0.45 0.25 0.45 mA Internal reference off DD V = 4.5 V to 5.5 V 0.8 1 0.8 1 mA Internal reference on DD I (All Power-Down Modes)5 DD V = 4.5 V to 5.5 V 0.48 1 0.48 1 µA V = V and V = GND DD IH DD IL 1 Temperature range: A, B grade = −40°C to +105°C. 2 Linearity calculated using a reduced code range: AD5663R (Code 512 to Code 65,024), AD5643R (Code 128 to Code 16,256), and AD5623R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 Both DACs powered down. Rev. G | Page 5 of 32

AD5623R/AD5643R/AD5663R Data Sheet AD5623R-3/AD5643R-3/AD5663R-3 V = 2.7 V to 3.6 V; R = 2 kΩ to GND; C = 200 pF to GND; V = V ; all specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 3. B Grade1 Parameter Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE2 AD5663R Resolution 16 Bits Relative Accuracy ±8 ±16 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic by design AD5643R Resolution 14 Bits Relative Accuracy ±2 ±4 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design AD5623R Resolution 12 Bits Relative Accuracy ±0.5 ±1 LSB Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design Zero-Scale Error +2 +10 mV All 0s loaded to DAC register Offset Error ±1 ±10 mV Full-Scale Error −0.1 ±1 % of FSR All 1s loaded to DAC register Gain Error ±1.5 % of FSR Zero-Scale Error Drift ±2 µV/°C Gain Temperature Coefficient ±2.5 ppm Of FSR/°C DC Power Supply Rejection Ratio −100 dB DAC code = midscale; V = 3 V ± 10% DD DC Crosstalk (External Reference) 10 µV Due to full-scale output change; R = 2 kΩ to GND or V L DD 10 µV/mA Due to load current change 5 µV Due to powering down (per channel) DC Crosstalk (Internal Reference) 25 µV Due to full-scale output change; R = 2 kΩ to GND or V L DD 20 µV/mA Due to load current change 10 µV Due to powering down (per channel) OUTPUT CHARACTERISTICS3 Output Voltage Range 0 V V DD Capacitive Load Stability 2 nF R = ∞ L 10 nF R = 2 kΩ L DC Output Impedance 0.5 Ω Short Circuit Current 30 mA V = 3 V DD Power-Up Time 4 µs Coming out of power-down mode; V = 3 V DD REFERENCE INPUTS Reference Current 170 200 µA V = V = 3.6 V REF DD Reference Input Range 0.75 V V DD Reference Input Impedance 26 kΩ REFERENCE OUTPUT Output Voltage 1.247 1.253 V At ambient Reference Temperature Coefficient3 ±5 ±15 ppm/°C MSOP package models ±10 ppm/°C LFCSP package models Output Impedance 7.5 kΩ Rev. G | Page 6 of 32

Data Sheet AD5623R/AD5643R/AD5663R B Grade1 Parameter Min Typ Max Unit Conditions/Comments LOGIC INPUTS3 Input Current ±2 µA All digital inputs V , Input Low Voltage 0.8 V V = 3 V INL DD V , Input High Voltage 2 V V = 3 V INH DD Pin Capacitance 3 pF DIN, SCLK, and SYNC 19 pF LDAC and CLR POWER REQUIREMENTS V 2.7 3.6 V DD I (Normal Mode)4 V = V and V = GND DD IH DD IL V = 2.7 V to 3.6 V 200 425 µA Internal reference off DD V = 2.7 V to 3.6 V 800 900 µA Internal reference on DD I (All Power-Down Modes)5 DD V = 2.7 V to 3.6 V 0.2 1 µA V = V and V = GND DD IH DD IL 1 Temperature range: B grade = −40°C to +105°C. 2 Linearity calculated using a reduced code range: AD5663R (Code 512 to Code 65,024), AD5643R (Code 128 to Code 16,256), and AD5623R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 Both DACs powered down. AC CHARACTERISTICS V = 2.7 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; V = V ; all specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 4. Parameter1, 2 Min Typ Max Unit Conditions/Comments3 Output Voltage Settling Time AD5623R 3 4.5 µs ¼ to ¾ scale settling to ±0.5 LSB AD5643R 3.5 5 µs ¼ to ¾ scale settling to ±0.5 LSB AD5663R 4 7 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 1.8 V/µs Digital-to-Analog Glitch Impulse 10 nV-sec 1 LSB change around major carry Digital Feedthrough 0.1 nV-sec Reference Feedthrough −90 dB V = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz REF Digital Crosstalk 0.1 nV-sec Analog Crosstalk 1 nV-sec External reference 4 nV-sec Internal reference DAC-to-DAC Crosstalk 1 nV-sec External reference 4 nV-sec Internal reference Multiplying Bandwidth 340 kHz V = 2 V ± 0.1 V p-p REF Total Harmonic Distortion −80 dB V = 2 V ± 0.1 V p-p, frequency = 10 kHz REF Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz 100 nV/√Hz DAC code = midscale, 10 kHz Output Noise 15 μV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization, not production tested. 2 See the Terminology section. 3 Temperature range: A, B grade = −40°C to +105°C, typical at +25°C. Rev. G | Page 7 of 32

AD5623R/AD5643R/AD5663R Data Sheet TIMING CHARACTERISTICS All input signals are specified with t = t = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2. R F DD IL IH V = 2.7 V to 5.5 V; all specifications T to T , unless otherwise noted.1 DD MIN MAX Table 5. Limit at T , T MIN MAX Parameter V = 2.7 V to 5.5 V Unit Conditions/Comments DD t2 20 ns min SCLK cycle time 1 t 9 ns min SCLK high time 2 t 9 ns min SCLK low time 3 t 13 ns min SYNC to SCLK falling edge setup time 4 t 5 ns min Data setup time 5 t 5 ns min Data hold time 6 t 0 ns min SCLK falling edge to SYNC rising edge 7 t 15 ns min Minimum SYNC high time 8 t 13 ns min SYNC rising edge to SCLK fall ignore 9 t 0 ns min SCLK falling edge to SYNC fall ignore 10 t 10 ns min LDAC pulse width low 11 t 15 ns min SCLK falling edge to LDAC rising edge 12 t 5 ns min CLR pulse width low 13 t 0 ns min SCLK falling edge to LDAC falling edge 14 t 300 ns max CLR pulse activation time 15 1 Guaranteed by design and characterization, not production tested. 2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. TIMING DIAGRAM t10 t1 t9 SCLK t8 t4 t3 t2 t7 SYNC t6 t5 DIN DB23 DB0 t14 t11 LDAC1 t12 LDAC2 CLR t13 VOUT t15 12ASYSNYNCCHHRROONNOOUUS SL DLDAACC U UPDPDAATET EM MOODDE.E. 05858-002 Figure 2. Serial Write Operation Rev. G | Page 8 of 32

Data Sheet AD5623R/AD5643R/AD5663R ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 6. Stresses at or above those listed under Absolute Maximum Parameter Rating Ratings may cause permanent damage to the product. This is a V to GND −0.3 V to +7 V stress rating only; functional operation of the product at these DD V to GND −0.3 V to V + 0.3 V or any other conditions above those indicated in the operational OUT DD V /V to GND −0.3 V to V + 0.3 V section of this specification is not implied. Operation beyond REFIN REFOUT DD Digital Input Voltage to GND −0.3 V to V + 0.3 V the maximum operating conditions for extended periods may DD Operating Temperature Range affect product reliability. Industrial −40°C to +105°C ESD CAUTION Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 150°C J Power Dissipation (T max − T )/θ J A JA LFCSP Package (4-Layer Board) θ Thermal Impedance 61°C/W JA MSOP Package (4-Layer Board) θJA Thermal Impedance 142°C/W θ Thermal Impedance 43.7°C/W JC Reflow Soldering Peak Temperature Pb-Free 260(+0/−5)°C Rev. G | Page 9 of 32

AD5623R/AD5643R/AD5663R Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VOUTA 1 10 VREFIN/VREFOUT VOUTB 2 AD5623R/ 9 VDD AD5643R/ GND 3 AD5663R 8 DIN LDAC 4 TOP VIEW 7 SCLK CLR 5 (Not to Scale) 6 SYNC N1 . O ELTXFECPSOSPS EPDA CPKAADG TEIE.D TO GND ON 05858-003 Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 2 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 3 GND Ground. Reference point for all circuitry on the part. 4 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. 5 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during a write sequence, the write is aborted. 6 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 7 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. 8 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 9 V Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with DD a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 10 V /V Common Reference Input/Reference Output. When the internal reference is selected, this is the reference output REFIN REFOUT pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input. Rev. G | Page 10 of 32

Data Sheet AD5623R/AD5643R/AD5663R TYPICAL PERFORMANCE CHARACTERISTICS 10 1.0 VDD = VREF = 5V VDD = VREF = 5V 8 TA = 25°C 0.8 TA = 25°C 6 0.6 4 0.4 INL ERROR (LSB) ––2402 DNL ERROR (LSB) ––000...4220 –6 –0.6 –8 –0.8 –100 5k 10k 15k 20k 25k 30CkOD3E5k 40k 45k 50k 55k 60k 65k 05858-005 –1.00 10k 20k 30CkODE 40k 50k 60k 05858-008 Figure 4. INL—AD5663R, External Reference Figure 7. DNL—AD5663R, External Reference 4 0.5 VDD = VREF = 5V VDD = VREF = 5V 3 TA = 25°C 0.4 TA = 25°C 0.3 2 0.2 INL ERROR (LSB) –101 DNL ERROR (LSB) –00..110 –0.2 –2 –0.3 –3 –40 2.5k 5.0k 7.C5kODE 10.0k 12.5k 15.0k 05858-006 ––00..540 2.5k 5.0k 7.C5kODE 10.0k 12.5k 15.0k 05858-009 Figure 5. INL—AD5643R, External Reference Figure 8. DNL—AD5643R, External Reference 1.0 0.20 VDD = VREF = 5V VDD = VREF = 5V 0.8 TA = 25°C TA = 25°C 0.15 0.6 0.10 0.4 B) B) LS 0.2 LS 0.05 R ( R ( RO 0 RO 0 R R NL E –0.2 NL E–0.05 I –0.4 D –0.10 –0.6 –0.8 –0.15 –1.00 0.5k 1.0k 1.5k C2.O0kDE 2.5k 3.0k 3.5k 4.0k 05858-007 –0.200 0.5k 1.0k 1.5k C2.O0kDE 2.5k 3.0k 3.5k 4.0k 05858-010 Figure 6. INL—AD5623R, External Reference Figure 9. DNL—AD5623R, External Reference Rev. G | Page 11 of 32

AD5623R/AD5643R/AD5663R Data Sheet 10 1.0 VDD = 5V VDD = 5V 8 VREFOUT = 2.5V 0.8 VREFOUT = 2.5V TA = 25°C TA = 25°C 6 0.6 4 0.4 B) B) R (LS 2 R (LS 0.2 O O R 0 R 0 R R NL E –2 NL E –0.2 I D –4 –0.4 –6 –0.6 –8 –0.8 –10 –1.0 0 5k 10k 15k 20k 25k 30CkOD35Ek 40k 45k 50k 55k 60k 65k 05858-011 0 5k 10k 15k 20k 25k 30CkOD3E5k 40k 45k 50k 55k 60k 65k 05858-014 Figure 10. INL—AD5663R-5 Figure 13. DNL—AD5663R-5 4 0.5 VDD = 5V VDD = 5V 3 VREFOUT = 2.5V 0.4 VREFOUT = 2.5V TA = 25°C TA = 25°C 0.3 2 0.2 B) B) R (LS 1 R (LS 0.1 RO 0 RO 0 R R NL E –1 NL E –0.1 I D –0.2 –2 –0.3 –3 –0.4 –4 –0.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 125 250 375 500 625 750COD875E 1000 1125 1250 1375 1500 1625 05858-012 125 250 375 500 625 750CODE875 1000 1125 1250 1375 1500 1625 05858-015 Figure 11. INL—AD5643R-5 Figure 14. DNL—AD5643R-5 1.0 0.20 VDD = 5V VDD = 5V 0.8 VREFOUT = 2.5V 0.15 VREFOUT = 2.5V TA = 25°C TA = 25°C 0.6 0.10 0.4 B) B) R (LS 0.2 R (LS 0.05 O O R 0 R 0 R R NL E –0.2 NL E–0.05 I D –0.4 –0.10 –0.6 –0.15 –0.8 –1.00 0.5k 1.0k 1.5k C2.O0kDE 2.5k 3.0k 3.5k 4.0k 05858-013 –0.200 0.5k 1.0k 1.5k C2.O0kDE 2.5k 3.0k 3.5k 4.0k 05858-016 Figure 12. INL—AD5623R-5 Figure 15. DNL—AD5623R-5 Rev. G | Page 12 of 32

Data Sheet AD5623R/AD5643R/AD5663R 10 1.0 VDD = 3V VDD = 3V 8 VREFOUT = 1.25V 0.8 VREFOUT = 1.25V TA = 25°C TA = 25°C 6 0.6 4 0.4 B) B) R (LS 2 R (LS 0.2 RO 0 RO 0 R R NL E –2 NL E –0.2 I D –4 –0.4 –6 –0.6 –8 –0.8 –10 –1.0 0 5k 10k 15k 20k 25k 30CkOD35Ek 40k 45k 50k 55k 60k 65k 05858-017 0 5k 10k 15k 20k 25k 30CkOD3E5k 40k 45k 50k 55k 60k 65k 05858-020 Figure 16. INL—AD5663R-3 Figure 19. DNL—AD5663R-3 4 0.5 VDD = 3V VDD = 3V 3 VTAR E=F O25U°TC = 1.25V 0.4 VTAR E=F O25U°TC = 1.25V 0.3 2 0.2 B) B) S 1 S L L 0.1 R ( R ( RO 0 RO 0 R R E E NL –1 NL –0.1 I D –0.2 –2 –0.3 –3 –0.4 –4 –0.5 0 1250 2500 3750 5000 6250 C7500ODE8750 10000 11250 12500 13750 15000 16250 05858-018 0 1250 2500 3750 5000 6250 C7500ODE8750 10000 11250 12500 13750 15000 16250 05858-021 Figure 17. INL—AD5643R-3 Figure 20. DNL—AD5643R-3 1.0 0.20 0.8 VTVADR DE=F =O2 5U3°TVC = 1.25V 0.15 VTVADR DE=F =O2 5U3°TVC = 1.25V 0.6 0.10 0.4 B) B) LS 0.2 LS 0.05 R ( R ( RO 0 RO 0 R R E E NL –0.2 NL –0.05 I D –0.4 –0.10 –0.6 –0.8 –0.15 –1.00 0.5k 1.0k 1.5k C2.O0kDE 2.5k 3.0k 3.5k 4.0k 05858-019 –0.200 0.5k 1.0k 1.5k C2.O0kDE 2.5k 3.0k 3.5k 4.0k 05858-022 Figure 18. INL—AD5623R-3 Figure 21. DNL—AD5623R-3 Rev. G | Page 13 of 32

AD5623R/AD5643R/AD5663R Data Sheet 8 0 6 MAX INL –0.02 VDD = 5V VDD = VREF = 5V 4 –0.04 GAIN ERROR –0.06 SB) 2 R) L MAX DNL S–0.08 R ( 0 % F RRO MIN DNL OR (–0.10 E –2 RR–0.12 E –4 –0.14 FULL-SCALE ERROR MIN INL –0.16 ––68 05858-080 –0.18 –4F0igure–2 202. INL0 Error Ta2E0nMdP DENR4LA0 TEUrrRoEr6 v(0°sC. )Tem80perat1u0r0e 120 –0.20–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 05858-023 Figure 25. Gain Error and Full-Scale Error vs. Temperature 10 1.5 8 MAX INL 6 1.0 ZERO-SCALE ERROR VDD = 5V 4 TA = 25°C 0.5 ERROR (LSB) –220 MMAINX DDNNLL RROR (mV) –0.50 E –1.0 –4 –6 –1.5 MIN INL OFFSET ERROR –1–08 05858-081 –2.0 0.75 1F.i2g5ure 12.375. INL2 E.2r5ror aV2n.R7dE5F D (NV3)L. 2E5rror3 v.7s5. VREF4 .25 4.75 –F2i.g5–u40re 26. –Z2e0ro-Sca0le ErTroErM 2aP0nEdR AOTffU4sR0eEt E(°rCro)r6 v0s. Tem8p0eratu1re0 0 05858-024 8 1.0 6 MAX INL TA = 25°C 0.5 4 GAIN ERROR R (LSB) 20 MAX DNL % FSR) 0 FULL-SCALE ERROR RRO MIN DNL OR ( –0.5 E –2 R R E –1.0 –4 MIN INL ––68 05858-082 –1.5 2.7 Figure3 .224. INL Er3ro.7r anVdD DDN 4(VL.2) Error vs4. .S7upply 5.2 –2.02.7 3.2 3.7 VDD 4(V.2) 4.7 5.2 05858-025 Figure 27. Gain Error and Full-Scale Error vs. Supply Rev. G | Page 14 of 32

Data Sheet AD5623R/AD5643R/AD5663R 1.0 0.5 TA = 25°C DAC LOADED WITH DAC LOADED WITH 0.4 FULL-SCALE ZERO-SCALE 0.5 ZERO-SCALE ERROR SOURCING CURRENT SINKING CURRENT 0.3 0 V) 0.2 R (mV) –0.5 LTAGE ( 0.1 VVDRDEF=O U3VT = 1.25V O O 0 R V ER –1.0 OR –0.1 R R –1.5 E –0.2 –0.3 VDD= 5V –2.0 OFFSET ERROR VREFOUT = 2.5V –0.4 –2.52.7 3.2 3.7 VDD 4(V.2) 4.7 5.2 05858-026 –0.5–10 –8 –6 –4 C–2URRE0NT (mA2) 4 6 8 10 05858-029 Figure 28. Zero-Scale Error and Offset Error vs. Supply Figure 31. Headroom at Rails vs. Source and Sink 6 8 VTAD D= =2 55°.5CV 5 TVVADR DE=F =O2 5U5VTC = 2.5V FULL SCALE S 4 3/4 SCALE NIT 6 U R OF (V)UT 3 MIDSCALE BE 4 VO 2 M U 1/4 SCALE N 1 2 0 ZERO SCALE 0 0.230 0.235 0.2ID4D0 (mA)0.245 0.250 0.255 05858-090 –1–30 –20 –10 CURRE0NT (mA) 10 20 30 05858-030 Figure 29. IDD Histogram with External Reference Figure 32. AD5623R-5/AD5643R-5/AD5663R-5 Source and Sink Capability 4 5 VTAD D= =2 55°.5CV TVVADR DE=F =O2 5U3°VTC = 1.25V 3 4 FULL SCALE S T MBER OF UNI 32 V (V)OUT 12 M3/I4D SSCCAALLEE U 1/4 SCALE N 1 0 ZERO SCALE 0 0.78 0.80 IDD (mA0).82 0.84 05858-091 –1–30 –20 –10 CURRE0NT (mA) 10 20 30 05858-031 Figure 30. IDD Histogram with Internal Reference Figure 33. AD5623R-3/AD5643R-3/AD5663R-3 Source and Sink Capability Rev. G | Page 15 of 32

AD5623R/AD5643R/AD5663R Data Sheet 0.30 TA = 25°C SYNC VDD = VREFIN = 5V 0.25 1 SLCK 3 0.20 VDD = VREFIN = 3V A) m (D 0.15 D I 0.10 VOUT 0.05 VDD = 5V 2 0–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 05858-044 CCHH13 55..00VV CH2 500mV M400ns A CH1 1.4V 05858-062 Figure 34. Supply Current vs. Temperature Figure 37. Exiting Power-Down to Midscale 2.538 2.537 VDD= VREF = 5V 2.536 TA = 25°C 5ns/SAMPLE NUMBER 2.535 GLITCH IMPULSE = 9.494nV-sec 2.534 1LSB CHANGE AROUND 2.533 MIDSCALE (0x8000 TO 0x7FFF) VDD = VREF = 5V 2.532 TF0OAxAUNU0 LDT=0L P022-0US50 °T0TCCp OALF LO0 TExAO FDCF EOGFDDNF EDW CITHHA 2NkGΩE V (V)OUT2222....555522338901 2.527 2.526 VOUT= 909mV/DIV 2.525 2.524 1 TIME BASE = 4µs/DIV 05858-060 222...5552221230 50 100 150 S2A00MPL2E5 0NUM30B0ER350 400 450 51205858-058 Figure 35. Full-Scale Settling Time, 5 V Figure 38. Digital-to-Analog Glitch Impulse (Negative) 2.498 VTAD D= =2 5V°RCEF = 5V 2.497 VT5nADs D=/S =2A 5VM°RCPEFL E= N5VUMBER ANALOG CROSSTALK = 0.424nV 2.496 V)2.495 (UT O VDD V2.494 1 2.493 MAX(C2)* 420.0mV 2 CH1 2.0VVOUTCH2 500mV MA 1C0H01µ s 1 215.M28SV/s 8.0ns/pt 05858-061 22..4499120 50 100 150 S2A00MPL2E5 0NUM30B0ER350 400 450 51205858-059 Figure 36. Power-On Reset to 0 V Figure 39. Analog Crosstalk, External Reference Rev. G | Page 16 of 32

Data Sheet AD5623R/AD5643R/AD5663R 2.496 2.494 2.492 VDD = 3V 2.490 VREFOUT = 1.25V 2.488 TA = 25°C DAC LOADED WITH MIDSCALE 2.486 2.484 2.482 2.480 V (V)OUT222...444777468 µV/DIV1 2.472 5 2.470 2.468 2.466 VDD= 5V 2.464 VREFOUT = 2.5V 2222....4444556668020 50 100 150 S2A00MPLT5A2En5AN 0s NA=/US L2AMO53M°0BGC0PE CLRRE3O 5NS0USMTBA40EL0RK = 445.4062nV51205858-057 4s/DIV 05858-065 Figure 40. Analog Crosstalk, Internal Reference Figure 43. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference 800 TA = 25°C MIDSCALE LOADED 700 VDD = VREF = 5V TA = 25°C DAC LOADED WITH MIDSCALE Hz) 600 √ nV/ 500 E ( S OI 400 N T 1 PU 300 UT VDD= 5V O 200 VREFOUT = 2.5V 100 VDD= 3V VREFOUT = 1.25V YX AAXXIISS == 42sµ/VD/IDVIV 05858-063 0100 1k FREQU1E0NkCY (Hz) 1M 10M 05858-066 Figure 41. 0.1 Hz to 10 Hz Output Noise Plot, External Reference Figure 44. Noise Spectral Density, Internal Reference –20 VVRDDEF =O U5TV = 2.5V –30 VTDADA DC= =2L 55O°VACDED WITH FULL SCALE TDAA C= 2L5O°ACDED WITH MIDSCALE VREF = 2V ± 0.3V p-p –40 –50 V/DIV1 (dB) –60 µ 0 1 –70 –80 –90 5s/DIV 05858-064 –100 2k F4RkEQUENCY 6(Hkz) 8k 10k 05858-067 Figure 42. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference Figure 45. Total Harmonic Distortion Rev. G | Page 17 of 32

AD5623R/AD5643R/AD5663R Data Sheet 16 VREF = VDD TA = 25°C 14 CLR 3 VDD=3V 12 VOUT A s) µ E ( 10 M TI 8 VDD=5V VOUT B 6 40 1 2 3 CA4PACITA5NCE 6(nF) 7 8 9 10 05858-068 424 CH3 5.0V CCHH42 11..00VV M200ns A CH3 1.10V 05858-050 Figure 46. Settling Time vs. Capacitive Load Figure 48. CLR Pulse Activation Time 5 VDD = 5V 0 TA = 25°C –5 –10 –15 B) d ( –20 –25 –30 –35 –4010k 100kFREQUENCY (Hz)1M 10M 05858-069 Figure 47. Multiplying Bandwidth Rev. G | Page 18 of 32

Data Sheet AD5623R/AD5643R/AD5663R TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) DC Power Supply Rejection Ratio (PSRR) For the DAC, relative accuracy or integral nonlinearity is a PSRR indicates how the output of the DAC is affected by measurement of the maximum deviation, in LSBs, from a changes in the supply voltage. PSRR is the ratio of the change in straight line passing through the endpoints of the DAC transfer VOUT to a change in VDD for full-scale output of the DAC. It function. A typical INL vs. code plot is shown in Figure 5. is measured in dB. VREF is held at 2 V, and VDD is varied by ±10%. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the Output Voltage Settling Time measured change and the ideal 1 LSB change between any two Output voltage settling time is the amount of time it takes for adjacent codes. A specified differential nonlinearity of ±1 LSB the output of a DAC to settle to a specified level for a 1/4 to 3/4 maximum ensures monotonicity. This DAC is guaranteed full-scale input change and is measured from the 24th falling monotonic by design. A typical DNL vs. code plot is shown in edge of SCLK. Figure 9. Digital-to-Analog Glitch Impulse Zero-Scale Error The impulse injected into the analog output when the input Zero-scale error is the measurement of the output error when code in the DAC register changes state. It is normally specified zero code (0x0000) is loaded to the DAC register. Ideally, the as the area of the glitch in nV-sec and is measured when the output should be 0 V. The zero-scale error is always positive in digital input code is changed by 1 LSB at the major carry the AD5623R/AD5643R/AD5663R because the output of the transition (0x7FFF to 0x8000). See Figure 38. DAC cannot go below 0 V. It is due to a combination of the Digital Feedthrough offset errors in the DAC and the output amplifier. Zero-scale A measure of the impulse injected into the analog output of the error is expressed in mV. A plot of zero-scale error vs. DAC from the digital inputs of the DAC, digital feedthrough is temperature is shown in Figure 26. measured when the DAC output is not updated. It is specified Full-Scale Error in nV-sec, and it is measured with a full-scale code change on Full-scale error is the measurement of the output error when the data bus, that is, from all 0s to all 1s and vice versa. full-scale code (0xFFFF) is loaded into the DAC register. Ideally, Reference Feedthrough the output should be V − 1 LSB. Full-scale error is expressed DD Reference feedthrough is the ratio of the amplitude of the signal in percent of full-scale range. A plot of full-scale error vs. at the DAC output to the reference input when the DAC output temperature is shown in Figure 25. is not being updated (that is, LDAC is high). It is expressed in Gain Error decibels (dB). Gain error is a measure of the span error of the DAC. It is the Noise Spectral Density deviation in slope of the DAC transfer characteristic from ideal, Noise spectral density is a measurement of the internally expressed as a percent of the full-scale range. generated random noise. Random noise is characterized as a Zero-Scale Error Drift spectral density (nV/√Hz). It is measured by loading the DAC Zero-scale error drift is the measurement of the change in zero- to midscale and measuring noise at the output. A plot of noise scale error with a change in temperature. It is expressed in spectral density is shown in Figure 44. microvolts/°C (μV/°C). DC Crosstalk Gain Temperature Coefficient DC crosstalk is the dc change in the output level of one DAC in Gain temperature coefficient is a measurement of the change in response to a change in the output of another DAC. It is gain error with changes in temperature. It is expressed in (ppm measured with a full-scale output change on one DAC (or soft of full-scale range)/°C. power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in microvolts (μV). Offset Error DC crosstalk due to load current change is a measure of the Offset error is a measure of the difference between V (actual) OUT impact that a change in load current on one DAC has to and V (ideal) expressed in mV in the linear region of the OUT another DAC kept at midscale. It is expressed in microvolts/ transfer function. Offset error is measured on the AD5623R/ milliamps (μV/mA). AD5643R/AD5663R with code 512 loaded in the DAC register. It can be negative or positive. Rev. G | Page 19 of 32

AD5623R/AD5643R/AD5663R Data Sheet Digital Crosstalk Multiplying Bandwidth Digital crosstalk is the glitch impulse transferred to the output The amplifiers within the DAC have a finite bandwidth. The of one DAC at midscale in response to a full-scale code change multiplying bandwidth is a measure of this. A sine wave on the (all 0s to all 1s and vice versa) in the input register of another reference (with full-scale code loaded to the DAC) appears on DAC. It is measured in standalone mode and is expressed the output. The multiplying bandwidth is the frequency at in nanovolts-second (nV-sec). which the output amplitude falls to 3 dB below the input. Analog Crosstalk Total Harmonic Distortion (THD) Analog crosstalk is the glitch impulse transferred to the output Total harmonic distortion is the difference between an ideal of one DAC due to a change in the output of another DAC. It is sine wave and its attenuated version using the DAC. The sine measured by loading one of the input registers with a full-scale wave is used as the reference for the DAC, and the THD is a code change (all 0s to all 1s and vice versa) while keeping LDAC measurement of the harmonics present on the DAC output. high. Then pulse LDAC low and monitor the output of the DAC It is measured in decibels (dB). whose digital code was not changed. The area of the glitch is expressed in nanovolts-second (nV-sec). DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nanovolts-second (nV-sec). Rev. G | Page 20 of 32

Data Sheet AD5623R/AD5643R/AD5663R THEORY OF OPERATION DIGITAL-TO-ANALOG SECTION R The AD5623R/AD5643R/AD5663R DAC is fabricated on a CMOS process. The architecture consists of a string DAC R followed by an output buffer amplifier. Figure 49 shows a block diagram of the DAC architecture. R TO OUTPUT AMPLIFIER VDD OUTPUT AMPLIFIER (GAIN = +2) REF (+) REGDIASCTER RSETSRISINTOGR VOUT REF (–) R GND 05858-032 R Because the input coFdiignugre t 4o9 t. hDeA CD AArcCh itiesc stturrae ight binary, the ideal 05858-033 Figure 50. Resistor String output voltage when using an external reference is given by INTERNAL REFERENCE  D  V V   The AD5623R/AD5643R/AD5663R on-chip reference is off at OUT REFIN 2N  power-up and is enabled via a write to a control register. See the The ideal output voltage when using the internal reference is Internal Reference Setup section for details. given by The AD5623R-3/AD5643R-3/AD5663R-3 has a 1.25 V,  D  5 ppm/°C reference, giving a full-scale output of 2.5 V. The V 2V   OUT REFOUT 2N  AD5623R-5/AD5643R-5/AD5663R-5 has a 2.5 V, 5 ppm/°C reference, giving a full-scale output of 5 V. The internal where: reference associated with each part is available at the V REFOUT D is the decimal equivalent of the binary code that is loaded to pin. A buffer is required if the reference output is used to drive the DAC register: external loads. When using the internal reference, it is recommended that a 100 nF capacitor be placed between 0 to 4095 for AD5623R (12-bit) reference output and GND for reference stability. 0 to 16,383 for AD5643R (14-bit) 0 to 65,535 for AD5663R (16-bit) EXTERNAL REFERENCE N is the DAC resolution. The V pins on the AD5623R-3/AD5643R-3/AD5663R-3 REFIN and the AD5623R-5/AD5643R-5/AD5663R-5 allows the use of RESISTOR STRING an external reference if the application requires it. The on-chip The resistor string section is shown in Figure 50. It is simply a reference is off at power-up, and this is the default condition. string of resistors, each of Value R. The code loaded to the DAC The AD5623R-3/AD5643R-3/AD5663R-3 and the AD5623R-5/ register determines at which node on the string the voltage is AD5643R-5/AD5663R-5 can be operated from a single 2.7 V to tapped off to be fed into the output amplifier. The voltage is 5.5 V supply. tapped off by closing one of the switches connecting the string SERIAL INTERFACE to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. The AD5623R/AD5643R/AD5663R have a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and OUTPUT AMPLIFIER MICROWIRE interface standards, as well as with most DSPs. The output buffer amplifier can generate rail-to-rail voltages on See Figure 2 for a timing diagram of a typical write sequence. its output, which gives an output range of 0 V to V . It can drive DD a load of 2 kΩ in parallel with 1000 pF to GND. The source and The write sequence begins by bringing the SYNC line low. Data sink capabilities of the output amplifier can be seen in Figure 31. from the DIN line is clocked into the 24-bit shift register on the The slew rate is 1.8 V/μs with a 1/4 to 3/4 full-scale settling time falling edge of SCLK. The serial clock frequency can be as high of 10 μs. as 50 MHz, making the AD5623R/AD5643R/AD5663R compatible with high speed DSPs. On the 24th falling clock edge, the last data bit is clocked in and the programmed function is executed, for example, a change in DAC register contents and/or a change in the mode of operation. Rev. G | Page 21 of 32

AD5623R/AD5643R/AD5663R Data Sheet At this stage, the SYNC line can be kept low or be brought high. Table 8. Command Definition In either case, it must be brought high for a minimum of 15 ns C2 C1 C0 Command before the next write sequence, so that a falling edge of SYNC 0 0 0 Write to Input Register n can initiate the next write sequence. 0 0 1 Update DAC Register n Because the SYNC buffer draws more current when V = 2 V 0 1 0 Write to Input Register n, update all IN (software LDAC) than it does when V = 0.8 V, SYNC should be idled low between IN 0 1 1 Write to and update DAC Channel n write sequences for even lower power operation. As mentioned 1 0 0 Power down DAC (power up) previously, it must, however, be brought high again just before 1 0 1 Reset the next write sequence. 1 1 0 LDAC register setup INPUT SHIFT REGISTER 1 1 1 Internal reference setup (on/off) The input shift register is 24 bits wide (see Figure 52). The first Table 9. Address Command two bits are don’t cares. The next three are Command Bit C2 to A2 A1 A0 ADDRESS (n) Command Bit C0 (see Table 8), followed by the 3-bit DAC 0 0 0 DAC A Address A2 to DAC Address A0 (see Table 9), and, finally, the 0 0 1 DAC B 16-, 14-, and 12-bit data-word. 0 1 0 Reserved The data-word comprises the 16-, 14-, and 12-bit input codes, 0 1 1 Reserved followed by zero, two, or four don’t care bits, for the AD5663R, 1 1 1 All DACs AD5643R, and AD5623R, respectively (see Figure 51, Figure 52, SYNC INTERRUPT and Figure 53). The data bits are transferred to the DAC register on the 24th falling edge of SCLK. In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, this acts as an interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 54). DB23 (MSB) DB0 (LSB) X X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 COMMAND BITS ADDRESS BITS DATA BITS 05858-034 Figure 51. AD5663R Input Shift Register Contents DB23 (MSB) DB0 (LSB) X X C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X COMMAND BITS ADDRESS BITS DATA BITS 05858-071 Figure 52. AD5643R Input Shift Register Contents DB23 (MSB) DB0 (LSB) X X C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X COMMAND BITS ADDRESS BITS DATA BITS 05858-072 Figure 53. AD5623R Input Shift Register Contents SCLK SYNC DIN DB23 DB0 DB23 DB0 SYNC HINIGVHA LBIEDF WORRIET E2 4STEHQ FUAELNLCINEG: EDGE VALID WORNIT TEH SEE 2Q4UTEHN FCAEL,L OINUGT PEUDTG UEPDATES 05858-035 Figure 54. SYNC Interrupt Facility Rev. G | Page 22 of 32

Data Sheet AD5623R/AD5643R/AD5663R POWER-ON RESET By executing the same Command 100, any combination of DACs can be powered up by setting Bit DB5 and Bit DB4 to normal The AD5623R/AD5643R/AD5663R contain a power-on reset operation mode. circuit that controls the output voltage during power-up. The AD5623R/AD5643R/AD5663R DACs output power up to 0 V, Again, to select which combination of DAC channels to power and the output remains there until a valid write sequence is up, set the corresponding bits (Bit DB1 and Bit DB0) to 1. See made to the DACs. This is useful in applications where it is Table 13 for contents of the input shift register during power- important to know the state of the output of the DACs while down/power-up operation. they are in the process of powering up. Any events on LDAC or CLR during power-on reset are ignored. The DAC output powers up to the value in the input register while LDAC is low. If LDAC is high, the DAC output powers up SOFTWARE RESET to the value held in the DAC register before power-down. The AD5623R/AD5643R/AD5663R contain a software reset function. Command 101 is reserved for the software reset Table 11. Modes of Operation function (see Table 8). The software reset command contains DB5 DB4 Operating Mode two reset modes that are software-programmable by setting bit 0 0 Normal operation DB0 in the control register. Table 10 shows how the state of the Power-down modes bit corresponds to the mode of operation of the device. Table 12 0 1 1 kΩ to GND shows the contents of the input shift register during the 1 0 100 kΩ to GND software reset mode of operation. 1 1 Three-state When both Bit DB1 and Bit DB2 are set to 0, the part works Table 10. Software Reset Modes normally, with its normal power consumption of 250 µA at 5 V. DB0 Registers Reset to Zero However, for the three power-down modes, the supply current 0 DAC register falls to 480 nA at 5 V (200 nA at 3 V). Not only does the supply Input register current fall, but the output stage is also internally switched from 1 (Power-on Reset) DAC register the output of the amplifier to a resistor network of known values. Input register This has the advantage that the output impedance of the part is LDAC register known while the part is in power-down mode. The outputs can Power-down register either be connected internally to GND through a 1 kΩ or 100 kΩ Internal reference setup register resistor or left open-circuited (three-state) (see Figure 55). After a full software reset (DB0 = 1), there must be a short time delay, approximately 5 µs, to allow the reset to complete. During the reset, a low pulse can be observed on the CLR line. If the RESISTOR STRING DAC AMPLIFIER VOUT next SPI transaction commences before the CLR line returns high, that SPI transaction is ignored. POWER-DOWN MODES POWER-DOWN CIRCUITRY RESISTOR oTfh oep AerDa5ti6o2n3.R C/AomD5m6a4n3dR /1A0D0 5is6 6re3sRe rcvoendt afoinr ftohue rp soewpearr-adteo wmno des NETWORK 05858-036 Figure 55. Output Stage During Power-Down function (see Table 8). These modes are software-programmable The bias generator, the output amplifier, the resistor string, by setting Bit DB5 and Bit DB4 in the control register. Table 11 and other associated linear circuitry are shut down when shows how the state of the bits corresponds to the mode of power-down mode is activated. However, the contents of the operation of the device. Any or all DACs (DAC B and DAC A) DAC register are unaffected when in power-down. The time can be powered down to the selected mode by setting the to exit power-down is typically 4 µs for both VDD = 5 V and corresponding two bits (Bit DB1 and Bit DB0) to 1. VDD = 3 V (see Figure 37). Table 12. 24-Bit Input Shift Register Contents for Software Reset Command MSB LSB DB23 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0 x 1 0 1 X X X X 1/0 Don’t care Command bits (C2 to C0) Address bits (A2 to A0) Don’t care Determines software reset mode Rev. G | Page 23 of 32

AD5623R/AD5643R/AD5663R Data Sheet Table 13. 24-Bit Input Shift Register Contents of Power Up/Down Function MSB LSB DB23 to DB15 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x 1 0 0 X X X X PD1 PD0 X X DAC B DAC A Don’t Command bits (C2 to C0) Address bits (A2 to A0) Don’t Power-down Don’t care Power down/Power up care Don’t care care mode channel selection; set bit to 1 to select channel Table 14. 24-Bit Input Shift Register Contents for LDAC Setup Command MSB LSB DB23 to DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB2 DB1 DB0 DB22 x 1 1 0 X X X X DAC B DAC A Don’t care Command bits (C2 to C0) Address bits (A3 to A0) Don’t care Set DAC to 0 or 1 for required Don’t care mode of operation LDAC FUNCTION Asynchronous LDAC The AD5623R/AD5643R/AD5663R DACs have double-buffered The outputs are not updated at the same time that the input interfaces consisting of two banks of registers: input registers registers are written to. When LDAC goes low, the DAC and DAC registers. The input registers are connected directly to registers are updated with the contents of the input register. the input shift register, and the digital code is transferred to the The LDAC register gives the user full flexibility and control over relevant input register on completion of a valid write sequence. The DAC registers contain the digital code used by the resistor the hardware LDAC pin. This register allows the user to select strings. which combination of channels to simultaneously update when the hardware LDAC pin is executed. Setting the LDAC bit Access to the DAC registers is controlled by the LDAC pin. register to 0 for a DAC channel means that the update of this When the LDAC pin is high, the DAC registers are latched and channel is controlled by the LDAC pin. If this bit is set to 1, this the input registers can change state without affecting the channel synchronously updates; that is, the DAC register is contents of the DAC registers. When LDAC is brought low, updated after new data is read in, regardless of the state of the however, the DAC registers become transparent and the LDAC pin. It effectively sees the LDAC pin as being pulled low. contents of the input registers are transferred to them. The See Table 15 for the LDAC register mode of operation. This double-buffered interface is useful if the user requires flexibility is useful in applications where the user wants to simultaneous updating of all DAC outputs. The user can write simultaneously update select channels while the rest of the to one of the input registers individually and then, by bringing channels are synchronously updating. LDAC low when writing to the other DAC input register, all outputs will update simultaneously. Writing to the DAC using Command 110 loads the 2-bit LDAC register [DB1:DB0]. The default for each channel is 0; that is, These parts each contain an extra feature whereby a DAC the LDAC pin works normally. Setting the bits to 1 means the register is not updated unless its input register has been updated DAC register is updated, regardless of the state of the LDAC since the last time LDAC was brought low. Normally, when LDAC pin. See Table 14 for contents of the input shift register during is brought low, the DAC registers are filled with the contents of the LDAC register setup command. the input registers. In the case of the AD5623R/AD5643R/ AD5663R, the DAC register updates only if the input register Table 15. LDAC Register Mode of Operation has changed since the last time the DAC register was updated, LDAC Bits thereby removing unnecessary digital crosstalk. (DB1 to DB0) LDAC Pin LDAC Operation The outputs of all DACs can be simultaneously updated, using 0 1/0 Determined by LDAC pin the hardware LDAC pin. 1 X = don’t care The DAC registers are updated Synchronous LDAC after new data is read in on the falling edge of the 24th SCLK The DAC registers are updated after new data is read in on the pulse. falling edge of the 24th SCLK pulse. LDAC can be permanently low or pulsed as shown in Figure 2. Rev. G | Page 24 of 32

Data Sheet AD5623R/AD5643R/AD5663R INTERNAL REFERENCE SETUP Table 16. Reference Setup Register Internal Reference The on-chip reference is off at power-up by default. This Setup Register (DB0) Action reference can be turned on or off by setting a software 0 Reference off (default) programmable bit, DB0, in the control register. Table 16 shows 1 Reference on how the state of the bit corresponds to the mode of operation. Command 111 is reserved for setting up the internal reference (see Table 8). See Table 16 for the contents of the input shift register during the internal reference setup command. Table 17. 32-Bit Input Shift Register Contents for Reference Setup Function MSB LSB DB23 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0 X 1 1 1 X X X X 1/0 Don’t care Command bits (C2 to C0) Address bits (A2 to A0) Don’t care Reference setup register Rev. G | Page 25 of 32

AD5623R/AD5643R/AD5663R Data Sheet AD5623R/AD5643R/AD5663R to 80C51/80L51 Interface MICROPROCESSOR INTERFACING AD5623R/AD5643R/AD5663R to Blackfin® Figure 58 shows a serial interface between the AD5623R/ Microprocessors Interface AD5643R/AD5663R and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/ 80L51 Figure 56 shows a serial interface between the AD5623R/ drives SCLK of the AD5623R/AD5643R/AD5663R, and RxD AD5643R/AD5663R and a Blackfin microprocessor such as the drives the serial data line of the part. The SYNC signal is again ADSP-BF531. The ADSP-BF531 incorporates two dual-channel derived from a bit-programmable pin on the port. In this case, synchronous serial ports, SPORT1 and SPORT0, for serial and Port Line P3.3 is used. When data is to be transmitted to the multiprocessor communications. Using SPORT0 to connect to AD5623R/AD5643R/AD5663R, P3.3 is taken low. The 80C51/ the AD5623R/AD5643R/AD5663R, the setup for the interface is 80L51 transmit data in 8-bit bytes only; thus, only eight falling as follows: DT0PRI drives the DIN pin of the AD5623R/ clock edges occur in the transmit cycle. To load data to the AD5643R/AD5663R, while TSCLK0 drives the SCLK of the DAC, P3.3 is left low after the first eight bits are transmitted, parts. The SYNC is driven from TFS0. and a second write cycle is initiated to transmit the second byte ADSP-BF5311 AD5643R/ of data. P3.3 is taken high following the completion of this cycle. AD5663R1 TFS0 SYNC The 80C51/80L51 output the serial data in a format that has the LSB first. The AD5623R/AD5643R/AD5663R must receive data DT0PRI DIN with the MSB first. The 80C51/80L51 transmit routine should TSCLK0 SCLK take this into account. 1ADDITIONAL PINS OMITTED FOR CLARITY. 05858-037 80C51/80L511 AD5643R/ Figure 56. AD5623R/AD5643R/AD5663R to Blackfin ADSP-BF531 Interface AD5663R1 P3.3 SYNC AD5623R/AD5643R/AD5663R to 68HC11/68L11 TxD SCLK Interface RxD DIN Figure 57 shows a serial interface between the AD5623R/ ASCDK5 6o4f3 tRh/eA 6D8H56C631R1/ a6n8dL 1t1h ed 6ri8vHesC t1h1e/ S6C8LL1K1 omf itchreo AcoDn5tr6o2l3leRr/. 1ADDITIONAL PINS OMITTED FOR CLARITY. 05858-039 Figure 58. AD5623R/AD5643R/AD5663R to 80C512/80L51 Interface AD5643R/AD5663R, and the MOSI output drives the serial data line of the DAC. AD5623R/AD5643R/AD5663R to MICROWIRE Interface Figure 59 shows an interface between the AD5623R/AD5643R/ 68HC11/68L111 AD5643R/ AD5663R1 AD5663R and any MICROWIRE-compatible device. Serial data is PC7 SYNC shifted out on the falling edge of the serial clock and is clocked into the AD5623R/AD5643R/AD5663R on the rising edge of the SK. SCK SCLK MOSI DIN MICROWIRE1 AD5643R/ 1ADDITIONAL PINS OMITTED FOR CLARITY. 05858-038 CS SAYDNC5663R1 Figure 57. AD5623R/AD5643R/AD5663R to 68HC11/68L11 Interface SK SCLK SO DIN The SYNC signal is derived from a port line (PC7). The setup cthoen d68itHioCns1 1fo/6r 8cLo1rr1e icst coopnefriagtuiorend o wf itthhi si tisn CtePrfOacLe b airte a as s0 f,o alnlodw ist:s 1ADDITIONAL PINS OMITTED FOR CLARITY. 05858-040 Figure 59. AD5623R/AD5643R/AD5663R to MICROWIRE Interface CPHA bit as 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as described previously, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5623R/ AD5643R/AD5663R, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. Rev. G | Page 26 of 32

Data Sheet AD5623R/AD5643R/AD5663R APPLICATIONS INFORMATION USING A REFERENCE AS A POWER SUPPLY This is an output voltage range of ±5 V, with 0x0000 corre- sponding to a −5 V output, and 0xFFFF corresponding to a Because the supply current required by the AD5623R/AD5643R/ +5 V output. AD5663R is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the parts (see R2 = 10kΩ Figure 60). This is especially useful if the power supply is quite +5V noisy or if the system supply voltages are at some value other +5V R1 = 10kΩ than 5 V or 3 V, for example, 15 V. The voltage reference outputs AD820/ ±5V a steady supply voltage for the AD5623R/AD5643R/AD5663R. OP295 If the low dropout REF195 is used, it must supply 500 μA of VDD VOUT 10µF 0.1µF AD5663R current to the AD5623R/AD5643R/AD5663R, with no load on –5V the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 kΩ load on the DAC output) is TINHTSREEERREFI-AWALCIREE 05858-042 500 μA + (5 V/5 kΩ) = 1.5 mA Figure 61. Bipolar Operation with the AD5663R USING THE AD5663R WITH A The load regulation of the REF195 is typically 2 ppm/mA, GALVANICALLY ISOLATED INTERFACE which results in a 3 ppm (15 μV) error for the 1.5 mA current drawn from it. This corresponds to a 0.196 LSB error for the In process control applications in industrial environments, 16-bit AD5663R. it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous 15V common-mode voltages that can occur in the area where 5V REF195 the DAC is functioning. iCoupler® provides isolation in excess of 2.5 kV. The AD5663R uses a 3-wire serial logic interface, so the ADuM1300 3-channel digital isolator provides the required VDD TIHNRTEESERE-FWRAIICRAEEL SSYCNLCK AADD55662433RR// VOUT = 0V TO 5V inseoeldatsi oton b(see ies oFliagtuerde, w62h)i.c Thh ies dpoonwee rb ysu upspinlyg tao ttrhaen spfaorrtm alesro. On DIN AD5663R 05858-041 t5h Ve DsuApCp lsyi dreeq oufi rthede tfroarn tshfeo rAmDe5r,6 a6 35R V. regulator provides the Figure 60. REF195 as Power Supply to the AD5623R/AD5643R/AD5663R 5V BIPOLAR OPERATION USING THE AD5663R REGULATOR POWER 10µF 0.1µF The AD5663R has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 61. The circuit gives an output voltage range of ±5 V. VDD Rail-to-rail operation at the amplifier output is achievable using SCLK VIA VOA SCLK an AD820 or an OP295 as the output amplifier. ADuM1300 AD5663R The output voltage for any input code can be calculated as SDI VIB VOB SYNC VOUT follows: VO VDD65,D536R1R1R2VDDRR21 DATA VIC VOC DIN GND 05858-043 where D represents the input code in decimal (0 to 65,535). Figure 62. AD5663R with a Galvanically Isolated Interface With V = 5 V, R1 = R2 = 10 kΩ, DD 10D V   5V O 65,536 Rev. G | Page 27 of 32

AD5623R/AD5643R/AD5663R Data Sheet POWER SUPPLY BYPASSING AND GROUNDING This 0.1 µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal When accuracy is important in a circuit, it is helpful to carefully logic switching. consider the power supply and ground return layout on the board. The printed circuit board containing the AD5663R The power supply line itself should have as large a trace as should have separate analog and digital sections, each having its possible to provide a low impedance path and to reduce glitch own area of the board. effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board If the AD5663R is in a system where other devices require an by digital ground. Avoid crossover of digital and analog signals, AGND-to-DGND connection, the connection should be made at if possible. When traces cross on opposite sides of the board, one point only. This ground point should be as close as possible ensure that they run at right angles to each other to reduce to the AD5663R. feedthrough effects through the board. The best board layout The power supply to the AD5663R should be bypassed with 10 µF technique is the microstrip technique, where the component and 0.1 µF capacitors. The capacitors should be located as close side of the board is dedicated to the ground plane only and the as possible to the device, with the 0.1 µF capacitor ideally right signal traces are placed on the solder side. However, this is not up against the device. The 10 µF capacitors are the tantalum always possible with a 2-layer board. bead type. It is important that the 0.1 µF capacitor have low effective series resistance (ESR) and effective series inductance (ESI), which is found, for example, in common ceramic types of capacitors. Rev. G | Page 28 of 32

Data Sheet AD5623R/AD5643R/AD5663R OUTLINE DIMENSIONS 2.48 2.38 3.10 2.23 3.00 SQ 2.90 0.50 BSC 6 10 PIN 1 INDEX EXPOSED 1.74 AREA PAD 1.64 0.50 1.49 0.40 0.30 5 1 0.20 MIN TOP VIEW BOTTOM VIEW PIN 1 INDICATOR (R 0.15) 0.80 FOR PROPER CONNECTION OF 0.75 0.05 MAX THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEPALTAINNGE Figure000 6...3223050. 10-Lead Lead Fr0a.m20e R CEhFip0 S.0c8ale Package [LFCSP_WD] 02-05-2013-C 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA 091709-A Figure 64. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Rev. G | Page 29 of 32

AD5623R/AD5643R/AD5663R Data Sheet ORDERING GUIDE Internal Package Model1 Temperature Range Accuracy Reference Package Description Option Branding AD5623RBCPZ-3R2 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D85 AD5623RBCPZ-3REEL7 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D85 AD5623RBCPZ-5REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 10-Lead LFCSP_WD CP-10-9 D86 AD5623RBRMZ-3 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead MSOP RM-10 D85 AD5623RBRMZ-3REEL7 −40°C to +105°C ±1 LSB INL 1.25 V 10-Lead MSOP RM-10 D85 AD5623RBRMZ-5 −40°C to +105°C ±1 LSB INL 2.5 V 10-Lead MSOP RM-10 D86 AD5623RBRMZ-5REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 10-Lead MSOP RM-10 D86 AD5623RACPZ-5REEL7 −40°C to +105°C ±2 LSB INL 2.5 V 10-Lead LFCSP_WD CP-10-9 DKB AD5623RARMZ-5REEL7 −40°C to +105°C ±2 LSB INL 2.5V 10-Lead MSOP RM-10 DKP AD5623RARMZ-5 −40°C to +105°C ±2 LSB INL 2.5V 10-Lead MSOP RM-10 DKP AD5643RBRMZ-3 −40°C to +105°C ±4 LSB INL 1.25 V 10-Lead MSOP RM-10 D81 AD5643RBRMZ-3REEL7 −40°C to +105°C ±4 LSB INL 1.25 V 10-Lead MSOP RM-10 D81 AD5643RBRMZ-5 −40°C to +105°C ±4 LSB INL 2.5 V 10-Lead MSOP RM-10 D7Q AD5643RBRMZ-5REEL7 −40°C to +105°C ±4 LSB INL 2.5 V 10-Lead MSOP RM-10 D7Q AD5663RBCPZ-3R2 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D7S AD5663RBCPZ-3REEL7 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead LFCSP_WD CP-10-9 D7S AD5663RBCPZ-5REEL7 −40°C to +105°C ±16 LSB INL 2.5 V 10-Lead LFCSP_WD CP-10-9 D7H AD5663RBRMZ-3 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead MSOP RM-10 D7S AD5663RBRMZ-3REEL7 −40°C to +105°C ±16 LSB INL 1.25 V 10-Lead MSOP RM-10 D7S AD5663RBRMZ-5 −40°C to +105°C ±16 LSB INL 2.5 V 10-Lead MSOP RM-10 D7H AD5663RBRMZ-5REEL7 −40°C to +105°C ±16 LSB INL 2.5 V 10-Lead MSOP RM-10 D7H EVAL-AD5663REBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. G | Page 30 of 32

Data Sheet AD5623R/AD5643R/AD5663R NOTES Rev. G | Page 31 of 32

AD5623R/AD5643R/AD5663R Data Sheet NOTES ©2006–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05858-0-9/15(G) Rev. G | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5663REBZ AD5623RBRMZ-5REEL7 AD5663RBRMZ-5 AD5643RBRMZ-3REEL7 AD5623RACPZ- 5REEL7 AD5623RBRMZ-3 AD5663RBCPZ-3R2 AD5623RBRMZ-5 AD5663RBCPZ-3REEL7 AD5623RBCPZ- 5REEL7 AD5623RBCPZ-3R2 AD5663RBRMZ-5REEL7 AD5643RBRMZ-5 AD5623RBCPZ-3REEL7 AD5643RBRMZ-3 AD5663RBRMZ-3 AD5623RBRMZ-3REEL7 AD5643RBRMZ-5REEL7 AD5663RBRMZ-3REEL7 AD5623RSRMZ-EP-5R7