2.7 V to 5.5 V, 250 μA, Rail-to-Rail Output, Dual 16-Bit nanoDAC Data Sheet AD5663 FEATURES FUNCTIONAL BLOCK DIAGRAM Low power, dual 16-bit nanoDAC VDD VREF Relative accuracy: ±12 LSBs maximum LDAC Guaranteed monotonic by design 10-lead MSOP and 3 mm × 3 mm LFCSP_WD SCLK REINGPISUTTER REGDIASCTER SDTARCIN AG BUFFER VOUTA 2.7 V to 5.5 V power supply SYNC INTLEORGFIACCE Per channel power-down DIN REINGPISUTTER REGDIASCTER SDTARCIN BG BUFFER VOUTB Power-on reset to zero scale or midscale Hardware LDAC and CLR functions AD5663 POWER-ON POWER-DOWN Serial interface; up to 50 MHz RESET LOGIC LDAC CLR GND 05855-001 APPLICATIONS Figure 1. Process control Data acquisition systems Table 1. Related Devices Portable battery-powered instruments Part No. Description Digital gain and offset adjustment AD5623R/AD5643R/AD5663R 2.7 V to 5.5 V, dual 12-/14-/16-bit DACs with internal reference Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD5663, a member of the nanoDAC® family, is a low 1. Dual 16-bit DAC; relative accuracy of ±12 LSBs maximum. power, dual, 16-bit buffered voltage-out DAC that operates from a 2. Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm single 2.7 V to 5.5 V supply and is guaranteed monotonic by LFCSP_WD packages. design. 3. Low power; typically consumes 0.6 mW at 3 V and 1.25 mW at 5 V. The AD5663 requires an external reference voltage to set the 4. 7 μs maximum settling time. output range of the DAC. The part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V or midscale (AD5663BRMZ-1) and remains there until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power- down mode. The low power consumption of this part in normal operation makes it ideally suited to portable, battery-operated equipment. The power consumption is 1.25 mW at 5 V, going down to 2.4 μW in power-down mode. The on-chip precision output amplifier of the AD5663 allows rail-to-rail output swing to be achieved. The AD5663 uses a versatile, 3-wire serial interface that operates at clock rates up to 50 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5663 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Amplifier ........................................................................ 14 Applications ....................................................................................... 1 Serial Interface ............................................................................ 14 Functional Block Diagram .............................................................. 1 Input Shift Register .................................................................... 14 General Description ......................................................................... 1 SYNC Interrupt .......................................................................... 15 Product Highlights ....................................................................... 1 Power-On Reset .......................................................................... 15 Revision History ............................................................................... 2 Software Reset ............................................................................. 15 Specifications ..................................................................................... 3 Power-Down Modes .................................................................. 16 AC Characteristics ........................................................................ 4 LDAC Function .......................................................................... 16 Timing Characteristics ................................................................ 5 Microprocessor Interfacing ....................................................... 18 Timing Diagram ........................................................................... 5 Applications ..................................................................................... 19 Absolute Maximum Ratings ............................................................ 6 Choosing a Reference for the AD5663 .................................... 19 ESD Caution .................................................................................. 6 Using a Reference as a Power Supply for the AD5663 .......... 19 Pin Configuration and Function Description .............................. 7 Bipolar Operation Using the AD5663 ..................................... 20 Typical Performance Characteristics ............................................. 8 Using the AD5663 with a Galvanically Isolated Interface .... 20 Terminology .................................................................................... 12 Power Supply Bypassing and Grounding ................................ 20 Theory of Operation ...................................................................... 14 Outline Dimensions ....................................................................... 21 D/A Section ................................................................................. 14 Ordering Guide .......................................................................... 21 Resistor String ............................................................................. 14 REVISION HISTORY 11/2016—Rev. 0 to Rev. A Changed ADSP-BF53x to ADSP-BF537 ..................... Throughout Added Figure 4; Renumbered Sequentially .................................. 7 Changes to Table 6 ............................................................................ 7 Change to Figure 28 ....................................................................... 14 Changes to Software Reset Section .............................................. 15 Changes to Figure 33 ...................................................................... 18 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21 4/2006—Revision 0: Initial Version Rev. A | Page 2 of 24

Data Sheet AD5663 SPECIFICATIONS V = 2.7 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; V = V ; all specifications T to T , unless otherwise noted. DD L L REF DD MIN MAX Table 2. A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE2 AD5663 Resolution 16 16 Bits Relative Accuracy ±8 ±16 ±6 ±12 LSB Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design Zero-Scale Error +2 +10 +2 +10 mV All 0s loaded to DAC register Offset Error ±1 ±10 ±1 ±10 mV Full-Scale Error −0.15 ±1 −0.15 ±1 % of FSR All 1s loaded to DAC register Gain Error ±1.5 ±1.5 % of FSR Zero-Scale Error Drift3 ±2 ±2 μV/°C Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C DC Power Supply Rejection Ratio −100 −100 dB DAC code = midscale, V ± 10% DD DC Crosstalk 10 10 μV Due to full-scale output change R = 2 kΩ to GND or V L DD 10 10 μV/mA Due to load current change 5 5 μV Due to powering down (per channel) OUTPUT CHARACTERISTICS2 Output Voltage Range 0 V 0 V V DD DD Capacitive Load Stability 2 2 nF R = ∞ L 10 10 nF R = 2 kΩ L DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA V = 5 V DD Power-Up Time 4 4 μs Coming out of power-down mode; V = 5 V DD REFERENCE INPUTS  Reference Current 170 200 170 200 μA V = V = 5.5 V, 3.6 V REF DD Reference Input Range 0.75 V 0.75 V V DD DD Reference Input Impedance 26 26 kΩ LOGIC INPUTS3 Input Current ±2 ±2 μA All digital inputs V , Input Low Voltage 0.8 0.8 V V = 5 V, 3 V INL DD V , Input High Voltage 2 2 V V = 5 V, 3 V INH DD Pin Capacitance 3 3 pF DIN, SCLK, and SYNC 19 19 pF LDAC and CLR POWER REQUIREMENTS V 2.7 5.5 2.7 5.5 V DD I (Normal Mode)4 V = V and V = GND DD IH DD IL V = 4.5 V to 5.5 V 250 450 250 450 μA DD V = 2.7 V to 3.6 V 200 425 200 425 μA DD I (All Power-Down Modes)5 V = V , V = GND DD IH DD IL V = 4.5 V to 5.5 V 0.48 1 0.48 1 μA DD V = 2.7 V to 3.6 V 0.2 1 0.2 1 μA DD 1 Temperature range: A grade and B grade are both equal to −40°C to +105°C. 2 Linearty calculated using a reduced code range: AD5663 (Code 512 to Code 65024). Output unloaded. 3 Guaranteed by design and characterization, not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 Both DACs powered down. Rev. A | Page 3 of 24

AD5663 Data Sheet AC CHARACTERISTICS V = 2.7 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; V = V ; all specifications T to T , unless otherwise noted.1 DD L L REF DD MIN MAX Table 3. Parameter2 Min Typ Max Unit Conditions/Comments Output Voltage Settling Time 4 7 μs 1/4 to 3/4 scale settling to ±2 LSB Slew Rate 1.8 V/μs Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB change around major carry Digital Feedthrough 0.1 nV-s Reference Feedthrough −90 dBs V = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz REF Digital Crosstalk 0.1 nV-s Analog Crosstalk 1 nV-s DAC-to-DAC Crosstalk 1 nV-s Multiplying Bandwidth 340 kHz V = 2 V ± 0.1 V p-p REF Total Harmonic Distortion −80 dB V = 2 V ± 0.1 V p-p; frequency = 10 kHz REF Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz 100 nV/√Hz DAC code = midscale, 10 kHz Output Noise 15 μV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization, not production tested. 2 See the Terminology section. Rev. A | Page 4 of 24

Data Sheet AD5663 TIMING CHARACTERISTICS All input signals are specified with t = t = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2. R F DD IL IH V = 2.7 V to 5.5 V; all specifications T to T , unless otherwise noted.1 DD MIN MAX Table 4. Limit at T , T MIN MAX Parameter V = 2.7 V to 5.5 V Unit Conditions/Comments DD t2 20 ns min SCLK cycle time 1 t 9 ns min SCLK high time 2 t 9 ns min SCLK low time 3 t 13 ns min SYNC to SCLK falling edge setup time 4 t 5 ns min Data setup time 5 t 5 ns min Data hold time 6 t 0 ns min SCLK falling edge to SYNC rising edge 7 t 15 ns min Minimum SYNC high time 8 t 13 ns min SYNC rising edge to SCLK fall ignore 9 t 0 ns min SCLK falling edge to SYNC fall ignore 10 t 10 ns min LDAC pulse width low 11 t 15 ns min SCLK falling edge to LDAC rising edge 12 t 5 ns min CLR pulse width low 13 t 0 ns min SCLK falling edge to LDAC falling edge 14 t 300 ns max CLR pulse activation time 15 1 Guaranteed by design and characterization; not production tested. 2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. TIMING DIAGRAM t10 t1 t9 SCLK t8 t4 t3 t2 t7 SYNC t6 t5 DIN DB23 DB0 t14 t11 LDAC1 t12 LDAC2 CLR t13 VOUT t15 12ASYSNYNCHCHRORONNOOUUS SL DLDAACC U UPDPDAATET EM MOODDE.E. 05855-002 Figure 2. Serial Write Operation Rev. A | Page 5 of 24

AD5663 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum A Ratings may cause permanent damage to the product. This is a Table 5. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational V to GND −0.3 V to +7 V section of this specification is not implied. Operation beyond DD V to GND −0.3 V to V + 0.3 V the maximum operating conditions for extended periods may OUT DD V to GND −0.3 V to V + 0.3 V affect product reliability. REF DD Digital Input Voltage to GND −0.3 V to V + 0.3 V DD ESD CAUTION Operating Temperature Range Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 150°C J Power Dissipation (T max − T )/θ J A JA LFCSP_WD Package (4-Layer Board) θ Thermal Impedance 61°C/W JA MSOP Package (4-Layer Board) θ Thermal Impedance 142°C/W JA θ Thermal Impedance 43.7°C/W JC Reflow Soldering Peak Temperature Pb-Free 260(+0/−5)°C Rev. A | Page 6 of 24

Data Sheet AD5663 PIN CONFIGURATION AND FUNCTION DESCRIPTION VOUTA 1 10 VREF VOUTA 1 10 VREF VOUTB 2 AD5663 9 VDD VOUTB 2 9 VDD GND 3 TOP VIEW 8 DIN GND 3 AD5663 8 DIN LDCALCR 45 (Not to Scale) 76 SSCYNLKC 05855-003 LDCALCR 45 (NToOt Pto V SIEcWale) 76 SSCYNLKC N1.O AETNXEPDSO ISS ERDECPAODM.M TEHNED EEXDPTOOS EBDE PCAODN INSE ICNTTEEDRNTAOL GLYR OFLUONADT.ING 05855-100 Figure 3. 10-Lead MSOP Pin Configuration Figure 4. 10-Lead LFCSP Pin Configuration Table 6. Pin Function Descriptions Pin No. 10-Lead 10-Lead MSOP LFCSP Mnemonic Description 1 1 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 2 2 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 3 3 GND Ground Reference Point for All Circuitry on the Device. 4 4 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. 5 5 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The device exits clear code mode on the 24th falling edge of the next write to the device. If CLR is activated during a write sequence, the write is aborted. 6 6 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the device. 7 7 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. 8 8 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 9 9 V Power Supply Input. These devices can be operated from 2.7 V to 5.5 V, and the supply must be DD decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 10 10 V Reference Voltage Input. REF N/A1 EPAD Exposed Pad. The exposed pad is internally floating and is recommended to be connected to ground. 1 N/A means not applicable. Rev. A | Page 7 of 24

AD5663 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 10 10 VDD = VREF = 5V 8 TA = 25°C 8 MAX INL 6 6 VDD = 5V B) 4 4 TA = 25°C OR (LS 02 R (LSB) 20 MAX DNL L ERR –2 ERRO –2 MIN DNL N I –4 –4 –6 –6 MIN INL –1–08 05855-004 –1–08 05855-007 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 CODE VREF (V) Figure 5. INL Figure 8. INL and DNL Error vs. VREF 1.0 8 VDD = VREF = 5V 0.8 TA = 25°C 6 MAX INL 0.6 TA = 25°C 4 0.4 ROR (LSB) 0.02 OR (LSB) 20 MAX DNL L ER –0.2 ERR –2 MIN DNL N D –0.4 –4 –0.6 MIN INL ––10..080 10k 20k 30k 40k 50k 60k 05855-005 ––682.7 3.2 3.7 4.2 4.7 5.2 05855-008 CODE VDD (V) Figure 6. DNL Figure 9. INL and DNL Error vs. Supply 8 0 VDD = 5V –0.02 6 MAX INL VDD = VREF = 5V –0.04 4 GAIN ERROR –0.06 R) LSB) 2 MAX DNL % FS –0.08 R ( 0 R ( –0.10 O O ERR –2 MIN DNL ERR –0.12 –0.14 FULL-SCALE ERROR –4 –0.16 MIN INL ––68–40 –20 0 20 40 60 80 100 120 05855-006 ––00..1280–40 –20 0 20 40 60 80 100 05855-009 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. INL Error and DNL Error vs. Temperature Figure 10. Gain Error and Full-Scale Error vs. Temperature Rev. A | Page 8 of 24

Data Sheet AD5663 1.5 VDD = 5.5V TA = 25°C 1.0 ZERO-SCALE ERROR 8 0.5 S mV) 0 F UNIT 6 ROR ( –0.5 BER O 4 R M E –1.0 U N –1.5 2 OFFSET ERROR ––22..05–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 05855-010 0 0.230 0.235 0.2ID4D0 (mA)0.245 0.250 0.255 05858-090 Figure 11. Zero-Scale and Offset Error vs. Temperature Figure 14. IDD Histogram with VDD = 5.5 V 1.0 0.20 VDD= VREF= 5V, 3V DAC LOADED WITH 0.15 TA = 25°C ZERO SCALE – 0.5 SINKING CURRENT 0.10 GAIN ERROR % FSR) 0 FULL-SCALE ERROR TAGE (V) 0.050 R ( –0.5 OL RO R V –0.05 R O E –1.0 RR –0.10 E –0.15 –1.5 DAC LOADED WITH –2.02.7 3.2 3.7 4.2 4.7 5.2 05855-011 ––00..2250–5 –4 –FS3UOLULR CS–2CINAGL EC– U1–RREN0T 1 2 3 4 505855-014 VDD (V) I (mA) Figure 12. Gain Error and Full-Scale Error vs. Supply Figure 15. Headroom at Rails vs. Source and Sink Current 1.0 0.30 TA = 25°C TA = 25°C 0.5 ZERO-SCALE ERROR VDD = VREFIN = 5V 0.25 0 0.20 R (mV) –0.5 mA) VDD = VREFIN = 3V ERRO –1.0 I (DD 0.15 0.10 –1.5 ––22..05 OFFSET ERROR 05855-012 0.050 2.7 3.2 3.7 VDD 4(V.2) 4.7 5.2 –40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 05855-044 Figure 13. Zero-Scale and Offset Error vs. Supply Figure 16. Supply Current vs. Temperature Rev. A | Page 9 of 24

AD5663 Data Sheet 2.538 2.537 VDD= VREF = 5V 2.536 TA = 25°C 5ns/SAMPLE NUMBER 2.535 GLITCH IMPULSE = 9.494nV 2.534 1LSB CHANGE AROUND VDD = VREF = 5V 2.533 MIDSCALE (0x8000 TO 0x7FFF) TA = 25°C 2.532 FULL-SCALE CODE CHANGE 2.531 0x0000 TO 0xFFFF V) OANUDT P2U0T0p LFO TAOD EGDN DWITH 2kΩ (OUT22..552390 V 2.528 2.527 VOUT= 909mV/DIV 2.526 2.525 1 2.524 05855-019 222...555222123 05855-058 TIME BASE = 4µs/DIV 0 50 100 150 200 250 300 350 400 450 512 SAMPLE NUMBER Figure 17. Full-Scale Settling Time, 5 V Figure 20. Digital-to-Analog Glitch Impulse (Negative) 2.498 TVAD D= =2 5V°RCEF = 5V 2.497 VT5nADs D=/S =2A 5VM°RCEPFL E= 5NVUMBER ANALOG CROSSTALK = 0.424nV 2.496 V) 2.495 (UT VDD VO2.494 1 2.493 MAX(C2)* 420.0mV 2 VOUT 05855-020 22..449912 05855-059 CH1 2.0V CH2 500mV M100µs 125MS/s 8.0ns/pt 0 50 100 150 200 250 300 350 400 450 512 A CH1 1.28V SAMPLE NUMBER Figure 18. Power-On Reset to 0 V Figure 21. Analog Crosstalk –20 SYNC VDD = 5V –30 TA = 25°C DAC LOADED WITH FULL SCALE 1 SLCK VREF = 2V ± 0.3V p-p 3 –40 –50 dB) –60 ( –70 VOUT –80 VDD = 5V 2 05855-021 –1–0900 05855-025 CH1 5.0V CH2 500mV M400ns A CH1 1.4V 2k 4k 6k 8k 10k CH3 5.0V FREQUENCY (Hz) Figure 19. Exiting Power-Down to Midscale Figure 22. Total Harmonic Distortion Rev. A | Page 10 of 24

Data Sheet AD5663 16 5 VTAR E=F 2=5 °VCDD 0 VTAD D= =2 55°VC 14 –5 VDD=3V 12 –10 ME (µs) 10 (dB) ––2105 TI 8 VDD=5V –25 –30 6 4 05855-026 ––4305 05855-029 0 1 2 3 4 5 6 7 8 9 10 10k 100k 1M 10M CAPACITANCE (nF) FREQUENCY (Hz) Figure 23. Settling Time vs. Capacitive Load Figure 26. Multiplying Bandwidth VDD = VREF = 5V TA = 25°C DAC LOADED WITH MIDSCALE 3 CLR VOUT A 1 VOUT B YX AAXXIISS == 42µs/VD/DIVIV 05855-027 424 CH2 1.0V M200ns A CH3 1.10V 05855-050 CH3 5.0V CH4 1.0V Figure 24. 0.1 Hz to 10 Hz Output Noise Plot Figure 27. CLR Pulse Activation Time 800 VDD = VREF = 5V 700 TA = 25°C Hz) 600 nV/ 500 E ( S OI 400 N T PU 300 T U O 200 1000 05855-028 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 25. Noise Spectral Density Rev. A | Page 11 of 24

AD5663 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Output Voltage Settling Time For the DAC, relative accuracy or integral nonlinearity is a Output voltage settling time is the amount of time it takes for measurement of the maximum deviation, in LSBs, from a the output of a DAC to settle to a specified level for a 1/4 to 3/4 straight line passing through the endpoints of the DAC transfer full-scale input change and is measured from the 24th falling function. A typical INL vs. code plot is shown in Figure 5. edge of SCLK. Differential Nonlinearity (DNL) Digital-to-Analog Glitch Impulse Differential nonlinearity is the difference between the measured Digital-to-analog glitch impulse is the impulse injected into the change and the ideal 1 LSB change between any two adjacent analog output when the input code in the DAC register changes codes. A specified differential nonlinearity of ±1 LSB maximum state. It is normally specified as the area of the glitch in nV-s, ensures monotonicity. This DAC is guaranteed monotonic by and is measured when the digital input code is changed by design. A typical DNL vs. code plot is shown in Figure 6. 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 20. Zero-Scale Error Zero-scale error is a measurement of the output error when Digital Feedthrough zero code (0x0000) is loaded to the DAC register. Ideally, the Digital feedthrough is a measure of the impulse injected into output should be 0 V. The zero-scale error is always positive in the analog output of the DAC from the digital inputs of the the AD5663 because the output of the DAC cannot go below DAC, but it is measured when the DAC output is not updated. 0 V. It is due to a combination of the offset errors in the DAC It is specified in nV-s and measured with a full-scale code change and the output amplifier. Zero-scale error is expressed in mV. on the data bus, that is, from all 0s to all 1s and vice versa. A plot of zero-scale error vs. temperature is shown in Figure 11. Total Harmonic Distortion (THD) Full-Scale Error Total harmonic distortion is the difference between an ideal Full-scale error is a measurement of the output error when full- sine wave and its attenuated version using the DAC. The sine scale code (0xFFFF) is loaded to the DAC register. Ideally, the wave is used as the reference for the DAC, and the THD is a output should be VDD − 1 LSB. Full-scale error is expressed in measurement of the harmonics present on the DAC output. percent of full-scale range. A plot of full-scale error vs. tempera- It is measured in dB. ture is shown in Figure 10. Noise Spectral Density Gain Error Noise spectral density is a measurement of the internally Gain error is a measure of the span error of the DAC. It is the generated random noise. Random noise is characterized as a deviation in slope of the DAC transfer characteristic from ideal spectral density (voltage per √Hz). It is measured by loading the expressed as a percent of the full-scale range. DAC to midscale and measuring noise at the output. It is measured in nV/√Hz. Figure 25 shows a plot of noise spectral Zero-Scale Error Drift density. Zero-scale error drift is a measurement of the change in zero- scale error with a change in temperature. It is expressed in µV/°C. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in Gain Temperature Coefficient response to a change in the output of another DAC. It is measured Gain temperature coefficient is a measurement of the change in with a full-scale output change on one DAC (or soft power-down gain error with changes in temperature. It is expressed in (ppm and power-up) while monitoring another DAC kept at midscale. of full-scale range)/°C. It is expressed in μV. Offset Error DC crosstalk due to load current change is a measure of the Offset error is a measure of the difference between V (actual) impact that a change in load current on one DAC has to another OUT and VOUT (ideal) expressed in mV in the linear region of the trans- DAC kept at midscale. It is expressed in μV/mA. fer function. Offset error is measured on the AD5663 with Digital Crosstalk Code 512 loaded in the DAC register. It can be negative or Digital crosstalk is the glitch impulse transferred to the output positive. of one DAC at midscale in response to a full-scale code change DC Power Supply Rejection Ratio (PSRR) (all 0s to all 1s and vice versa) in the input register of another PSRR indicates how the output of the DAC is affected by changes DAC. It is measured in standalone mode and is expressed in the supply voltage. PSRR is the ratio of the change in VOUT to in nV-s. a change in V for full-scale output of the DAC. It is measured DD in dB. V is held at 2 V, and V is varied by ±10%. REF DD Rev. A | Page 12 of 24

Data Sheet AD5663 Analog Crosstalk Multiplying Bandwidth Analog crosstalk is the glitch impulse transferred to the output The amplifiers within the DAC have a finite bandwidth. The of one DAC due to a change in the output of another DAC. It is multiplying bandwidth is a measure of this. A sine wave on the measured by loading one of the input registers with a full-scale reference (with full-scale code loaded to the DAC) appears on code change (all 0s to all 1s and vice versa) while keeping the output. The multiplying bandwidth is the frequency at LDAC high. Then pulse LDAC low and monitor the output of which the output amplitude falls to 3 dB below the input. the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Rev. A | Page 13 of 24

AD5663 Data Sheet THEORY OF OPERATION D/A SECTION OUTPUT AMPLIFIER The AD5663 DAC is fabricated on a CMOS process. The The output buffer amplifier can generate rail-to-rail voltages on architecture consists of a string DAC followed by an output its output, which gives an output range of 0 V to V . It can drive DD buffer amplifier. Figure 28 shows a block diagram of the DAC a load of 2 kΩ in parallel with 1000 pF to GND. architecture. The source and sink capabilities of the output amplifier can be VDD OUTPUT seen in Figure 15. The slew rate is 1.8 V/μs with a 1/4 to 3/4 AMPLIFIER (GAIN = +1) full-scale settling time of 10 μs. REF (+) REGDIASCTER RSETSRISINTOGR VOUT SERIAL INTERFACE REF (–) The AD5663 has a 3-wire serial interface (SYNC, SCLK, and GND 05855-032 DinItNer)f atchea ts tias ncdoamrdpsa,t iabsl ew welilt ahs SwPiIt,h Q mSPosI,t aDnSdP Ms. ISCeeR FOiWguIrRe E2 for Figure 28. DAC Architecture a timing diagram of a typical write sequence. Because the input coding to the DAC is straight binary, the ideal output voltage is given by The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 24-bit shift register on the  D  falling edge of SCLK. The serial clock frequency can be as high V V   OUT REF 65,536 as 50 MHz, making the AD5663 compatible with high speed DSPs. On the 24th falling clock edge, the last data bit is clocked where D is the decimal equivalent of the binary code that is in and the programmed function is executed; that is, there is a loaded to the DAC register. It can range from 0 to 65,535. change in DAC register contents and/or a change in the mode of operation. At this stage, the SYNC line can be kept low or be RESISTOR STRING brought high. In either case, it must be brought high for a mini- The resistor string section is shown in Figure 29. It is a string of mum of 15 ns before the next write sequence so that a falling edge resistors, each of Value R. The code loaded to the DAC register of SYNC can initiate the next write sequence. Because the SYNC determines at which node on the string the voltage is tapped off buffer draws more current when V = 2.0 V than it does when IN to be fed into the output amplifier. The voltage is tapped off by V = 0.10 V, SYNC should be idled low between write sequences closing one of the switches connecting the string to the amplifier. IN for even lower power operation. As mentioned previously, Because it is a string of resistors, it is guaranteed monotonic. however, it must be brought high again just before the next write sequence. R INPUT SHIFT REGISTER The input shift register is 24 bits wide (see Figure 30). The first R two bits are don’t cares. The next three are the Command Bit C2 to Command Bit C0 (see Table 7), followed by the 3-bit DAC R TAOM POLUIFTIPEURT Address A2 to DAC Address A0 (see Table 8), and, finally, the 16-bit data-word. These are transferred to the DAC register on the 24th falling edge of SCLK. Table 7. Command Definition R C2 C1 C0 Command 0 0 0 Write to input register n R 0 0 1 Update DAC register n 05855-033 0 1 0 (Wsorifttew taor ein LpDuAt Cre) gister n, update all Figure 29. Resistor String 0 1 1 Write to and update DAC channel n 1 0 0 Power down DAC (power up) 1 0 1 Reset 1 1 0 LDAC register setup 1 1 1 Reserved Rev. A | Page 14 of 24

Data Sheet AD5663 SOFTWARE RESET Table 8. Address Command A2 A1 A0 ADDRESS (n) The AD5663 contains a software reset function. Command 101 is 0 0 0 DAC A reserved for the software reset function (see Table 7). The software 0 0 1 DAC B reset command contains two reset modes that are software- 0 1 0 Reserved programmable by setting Bit DB0 in the control register. 0 1 1 Reserved Table 9 shows how the state of the bit corresponds to the mode 1 1 1 All DACs of operation of the device. Table 10 shows the contents of the input shift register during the software reset mode of operation. SYNC INTERRUPT In a normal write sequence, the SYNC line is kept low for at After a full software reset (DB0 = 1), there must be a short time delay, approximately 5 μs, to complete the reset. During the least 24 falling edges of SCLK, and the DAC is updated on the reset, a low pulse can be observed on the CLR line. If the next 24th falling edge. However, if SYNC is brought high before the SPI transaction commences before the CLR line returns high, 24th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as that SPI transaction is ignored. invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 31). Table 9. Software Reset Modes for the AD5663 DB0 Registers Reset to 0 POWER-ON RESET 0 DAC register The AD5663 family contains a power-on reset circuit that Input register controls the output voltage during power-up. The AD5663 DAC 1 (Power-On Reset) DAC register outputs power up to 0 V, the AD5663BRMZ-1 powers up to Input register midscale, and the output remains there until a valid write LDAC register sequence is made to the DAC. This is useful in applications Power-down register where it is important to know the state of the output of the DAC while it is in the process of powering up. Any events on LDAC or CLR during power-on reset are ignored. Table 10. 24-Bit Input Shift Register Contents for Software Reset Command MSB LSB DB23 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0 x 1 0 1 x x x x 1/0 Don’t care Command bits (C2 to C0) Address bits (A2 to A0) Don’t care Determines software reset mode DB23 (MSB) DB0 (LSB) X X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 COMMAND BITS ADDRESS BITS DATA BITS 05855-034 Figure 30. Input Register Contents SCLK SYNC DIN DB23 DB0 DB23 DB0 SYNC HINIGVHA LBIEDF WORRIET E2 4STEHQ FUAELNLCINEG: EDGE VALID WORNIT TEH SEE 2Q4UTEH NFCAEL,L OINUGT PEUDTG UEPDATES 05855-035 Figure 31. SYNC Interrupt Facility Rev. A | Page 15 of 24

AD5663 Data Sheet POWER-DOWN MODES The time required to exit power-down is typically 4 µs for V = 5 V and for V = 3 V (see Figure 19). DD DD The AD5663 contains four separate modes of operation. Command 100 is reserved for the power-down function Table 11. Power-Down Modes of Operation for the AD5663 (see Table 7). These modes are software-programmable by DB5 DB4 Operating Mode setting Bit DB5 and Bit DB4 in the control register. Table 11 0 0 Normal operation shows how the state of the bits corresponds to the mode of Power-Down Modes operation of the device. Any or all DACs (DAC B and DAC A) 0 1 1 kΩ to GND can be powered down to the selected mode by setting the 1 0 100 kΩ to GND corresponding two bits (Bit DB1 and Bit DB0) to 1. By 1 1 Three-state executing the same Command 100, any combination of DACs can be powered up by setting Bit DB5 and Bit DB4 to normal operation mode. Again, to select which combination of DAC LDAC FUNCTION channels to power up, set the corresponding two bits (Bit DB1 The AD5663 DAC has double-buffered interfaces consisting of and Bit DB0) to 1. See Table 12 for contents of the input shift two banks of registers: input registers and DAC registers. The register during power-down/power-up operation. input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register The DAC output powers up to the value in the input register on completion of a valid write sequence. The DAC registers while LDAC is low. If LDAC is high, the DAC output powers up contain the digital code used by the resistor strings. to the value held in the DAC register before power-down. Access to the DAC registers is controlled by the LDAC pin. When both bits are set to 0, the part works normally with its When the LDAC pin is high, the DAC registers are latched and normal power consumption of 500 µA at 5 V. However, for the the input registers can change state without affecting the three power-down modes, the supply current falls to 480 nA at 5 V (100 nA at 3 V). Not only does the supply current fall, but contents of the DAC registers. When LDAC is brought low, the output stage is also internally switched from the output of however, the DAC registers become transparent and the the amplifier to a resistor network of known values. This has the contents of the input registers are transferred to them. The advantage that the output impedance of the part is known while double-buffered interface is useful if the user requires the part is in power-down mode. The outputs can either be simultaneous updating of all DAC outputs. The user can write connected internally to GND through a 1 kΩ or 100 kΩ register to one of the input registers individually and then, by bringing or left open-circuited (three-state) (see Figure 32). LDAC low when writing to the other DAC input register, all outputs update simultaneously. These parts each contain an extra feature whereby a DAC RESISTOR STRING DAC AMPLIFIER VOUT register is not updated unless its input register has been updated since the last time LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the POCWIRECRU-IDTORWYN RESISTOR contents of the input registers. In the case of the AD5663, the NETWORK 05855-036 DsinAcCe trhege ilsatsetr tuimpdea tthese oDnAlyC i fr ethgies tienrp wuta rse ugpisdtearte hda, st hcheraenbgye d Figure 32. Output Stage During Power-Down removing unnecessary digital crosstalk. The bias generator, the output amplifier, the resistor string, and The outputs of all DACs can be updated simultaneously using other associated linear circuitry are shut down when power- the hardware LDAC pin. down mode is activated. However, the contents of the DAC register are unaffected when in power-down. Table 12. 24-Bit Input Shift Register Contents of Power-Up/Power-Down Function MSB LSB DB23 to DB15 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x 1 0 0 x x x x PD1 PD0 x x DAC B DAC A Don’t Command bits (C2 to C0) Address bits (A2 to A0); Don’t Power-down Don’t care Power down/Power up care don’t care care mode channel selection; set bit to 1 to select channel Rev. A | Page 16 of 24

Data Sheet AD5663 This flexibility is useful in applications where the user wants to Synchronous LDAC: The DAC registers are updated after new simultaneously update select channels while the rest of the data is read in on the falling edge of the 24th SCLK pulse. channels are synchronously updating LDAC can be permanently low or pulsed, as shown in Figure 2. Writing to the DAC using Command 110 loads the 2-bit LDAC Asynchronous LDAC: The outputs are not updated at the same register [DB1:DB0]. The default for each channel is 0; that is, time that the input registers are written to. When LDAC goes the LDAC pin works normally. Setting the bits to 1 means the low, the DAC registers are updated with the contents of the DAC register is updated regardless of the state of the LDAC pin. input register. See Table 14 for contents of the input shift register during the The LDAC register gives the user full flexibility and control over LDAC register setup command. the hardware LDAC pin. This register allows the user to select which combination of channels to simultaneously update when Table 13. LDAC Register Mode of Operation the hardware LDAC pin is executed. Setting the LDAC bit LDAC Bits register to 0 for a DAC channel means that the update of this (DB1 to DB0) LDAC Pin LDAC Operation channel is controlled by the LDAC pin. If this bit is set to 1, this 0 1/0 Determined by LDAC pin channel synchronously updates; that is, the DAC register is 1 x = don’t care The DAC registers are updated updated after new data is read in, regardless of the state of the after new data is read in on the falling edge of the 24th SCLK LDAC pin. It effectively sees the LDAC pin as being pulled low. pulse See Table 13 for the LDAC register mode of operation. Table 14. 24-Bit Input Shift Register Contents for LDAC Register Setup Command MSB LSB DB23 to DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB2 DB1 DB0 x 1 1 0 x x x x DAC B DAC A Don’t care Command bits (C2 to C0) Address bits (A3 to A0); Don’t care Set DAC to 0 or 1 for required mode of Don’t care operation Rev. A | Page 17 of 24

AD5663 Data Sheet MICROPROCESSOR INTERFACING 68HC11/68L111 AD56631 AD5663 to Blackfin ADSP-BF537 Interface PC7 SYNC Figure 33 shows a serial interface between the AD5663 and the SCK SCLK Blackfin ADSP-BF537 microprocessor. The ADSP-BF537 MOSI DIN incorporates two dual-channel synchronous serial ports, SPORT1 aWndh eSnP uOsRinTg0 S, PfoOr RseTr0ia tlo a ncodn mneucltti tpor othcees AsoDr 5c6o6m3m, tuhne isceattuiopn fso.r the 1ADDITIONAL PINS OMITTED FOR CLARITY. 05855-038 Figure 34. AD5663 to 68HC11/68L11 Interface interface is as follows: AD5663 to 80C51/80L51 Interface  DT0PRI drives the DIN pin of the AD5663. Figure 35 shows a serial interface between the AD5663 and the  TSCLK0 drives the SCLK of the device. 80C51/80L51 microcontroller. The setup for the interface is as follows:  The SYNC pin is driven from TFS0.  TxD of the 80C51/80L51 drives SCLK of the AD5663. ADSP-BF5371 AD56631  RxD drives the serial data line of the part. TFS0 SYNC The SYNC signal is again derived from a bit-programmable pin DT0PRI DIN on the port. In this case, Port Line P3.3 is used. When data is to be TSCLK0 SCLK transmitted to the AD5663, P3.3 is taken low. The 80C51/80L51 1ADDITIONAL PINS OMITTED FOR CLARITY. 05855-037 terdagnessm oictcs udra tina itnh e1 0tr-abnits mbyitte csy ocnlel.y T; oth luosa do ndlayt eai tgoh tt hfael DlinAgC c,l oPc3k.3 Figure 33. AD5663 to Blackfin ADSP-BF537 Interface is left low after the first eight bits are transmitted, and a second AD5663 to 68HC11/68L11 Interface write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/ Figure 34 shows a serial interface between the AD5663 and the 80L51 outputs the serial data in a format that has the LSB first. 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 The AD5663 must receive data with the MSB first. The 80C51/ drives the SCLK of the AD5663, and the MOSI output drives 80L51 transmit routine should take this into account. the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup 80C51/80L511 AD56631 conditions for correct operation of this interface are as follows: P3.3 SYNC  The 68HC11/68L11 is configured with its CPOL bit as 0. TxD SCLK RxD DIN  The 68HC11/68L11 is configured with its CPHA bit as 1. When data is being transmitted to the DAC, the SYNC line is 1ADDITIONAL PINS OMITTED FOR CLARITY. 05855-039 Figure 35. AD5663 to 80C51/80L51 Interface taken low (PC7). When the 68HC11/68L11 is configured as previously described, data appearing on the MOSI output is AD5663 to MICROWIRE Interface valid on the falling edge of SCK. Serial data from the Figure 36 shows an interface between the AD5663 and any 68HC11/68L11 is transmitted in 10-bit bytes with only eight MICROWIRE-compatible device. Serial data is shifted out on falling clock edges occurring in the transmit cycle. Data is the falling edge of the serial clock and is clocked into the AD5663 transmitted MSB first. To load data to the AD5663, PC7 is left on the rising edge of the SK. low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at MICROWIRE1 AD56631 the end of this procedure. CS SYNC SK SCLK SO DIN 1ADDITIONAL PINS OMITTED FOR CLARITY. 05855-040 Figure 36. AD5663 to MICROWIRE Interface Rev. A | Page 18 of 24

Data Sheet AD5663 APPLICATIONS CHOOSING A REFERENCE FOR THE AD5663 USING A REFERENCE AS A POWER SUPPLY FOR THE AD5663 To achieve the optimum performance from the AD5663, thought should be given to the choice of a precision voltage Because the supply current required by the AD5663 is extremely reference. The AD5663 has only one reference input, VREF. low, an alternative option is to use a voltage reference to supply The voltage on the reference input is used to supply the positive the required voltage to the part (see Figure 37). This is especially input to the DAC. Therefore, any error in the reference is useful if the power supply is quite noisy, or if the system supply reflected in the DAC. voltages are at some value other than 5 V or 3 V (for example, 15 V). The voltage reference outputs a steady supply voltage for When choosing a voltage reference for high accuracy applica- the AD5663; see Table 15 for a suitable reference. If the low drop- tions, the sources of error are initial accuracy, ppm drift, long- out REF195 is used, it must supply 250 μA of current to the term drift, and output voltage noise. Initial accuracy on the AD5663, with no load on the output of the DAC. When the output voltage of the DAC leads to a full-scale error in the DAC. DAC output is loaded, the REF195 also needs to supply the To minimize these errors, a reference with high initial accuracy current to the load. The total current required (with a 5 kΩ is preferred. Also, choosing a reference with an output trim load on the DAC output) is adjustment, such as the ADR423, allows a system designer to trim system errors out by setting a reference voltage to a voltage 250 μA + (5 V/5 kΩ) = 1.25 mA other than the nominal. The trim adjustment can also be used The load regulation of the REF195 is typically 2 ppm/mA, at temperature to trim out any error. which results in a 2.5 ppm (12.5 μV) error for the 1.25 mA Long-term drift is a measurement of how much the reference current drawn from it. This corresponds to a 0.164 LSB error. drifts over time. A reference with a tight long-term drift specifi- cation ensures that the overall solution remains relatively stable 15V during its entire lifetime. 5V REF195 500µA The temperature coefficient of a reference’s output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to THREE-WIRE SYNC VDD VREF VOUT = 0V TO 5V reduce temperature dependence of the DAC output voltage in INTESREFRAICAEL SCLK AD5663 ambient conditions. DIN 05855-041 In high accuracy applications, which have a relatively low noise Figure 37. REF195 as Power Supply to the AD5663 budget, reference output voltage noise needs to be considered. It is important to choose a reference with as low an output noise voltage as practical for the system noise resolution required. Precision voltage references, such as the ADR425, produce low output noise in the 0.1 Hz to 10 Hz range. Examples of recom- mended precision references for use as supplies to the AD5663 are shown in the Table 15. Table 15. Partial List of Precision References for Use with the AD5663 Part No. Initial Accuracy (mV Max) Temperature Drift (ppm°C Max) 0.1 Hz to 10 Hz Noise (μV p-p Typ) V (V) OUT ADR425 ±2 3 3.4 5 ADR395 ±6 25 5 5 REF195 ±2 5 50 5 AD780 ±2 3 4 2.5/3 ADR423 ±2 3 3.4 3 Rev. A | Page 19 of 24

AD5663 Data Sheet BIPOLAR OPERATION USING THE AD5663 5V REGULATOR The AD5663 has been designed for single-supply operation, POWER 10µF 0.1µF but a bipolar output range is also possible using the circuit in Figure 38. The circuit gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using VDD an AD820 or an OP295 as the output amplifier. SCLK VIA VOA SCLK ADuM1300 AD5663 The output voltage for any input code can be calculated as SDI VIB VOB SYNC VOUT   D  R1R2 R2 VO VDD  VDD   65,536  R1  R1 DATA VIC VOC DIN GND where D represents the input code in decimal (0 to 65,535). 05855-043 With V = 5 V, R1 = R2 = 10 kΩ Figure 39. AD5663 with a Galvanically Isolated Interface DD POWER SUPPLY BYPASSING AND GROUNDING 10D V  5V O 65,536 When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the This is an output voltage range of ±5 V, with 0x0000 corre- board. The printed circuit board containing the AD5663 should sponding to a −5 V output, and 0xFFFF corresponding to a have separate analog and digital sections, each having its own +5 V output. area of the board. If the AD5663 is in a system where other devices require an AGND-to-DGND connection, the connection R2 = 10kΩ should be made at one point only. This ground point should be +5V as close as possible to the AD5663. +5V R1 = 10kΩ AD820/ The power supply to the AD5663 should be bypassed with 10 μF ±5V OP295 and 0.1 μF capacitors. The capacitors should be located as close VDD VOUT 10µF 0.1µF AD5663 as possible to the device, with the 0.1 μF capacitor ideally right –5V up against the device. The 10 μF capacitors are of the tantalum bead type. It is important that the 0.1 μF capacitor have low effective series resistance (ESR) and effective series inductance TINHTSREEERREFI-AWALCIREE 05855-042 (TEhSiIs) 0 a.1s iμnF, fcoarp eaxcaitmorp pler,o cvoimdems ao nlo cwe riammpiecd taynpcees poaf tcha ptoa cgirtooursn. d Figure 38. Bipolar Operation with the AD5663 for high frequencies caused by transient currents due to internal USING THE AD5663 WITH logic switching. A GALVANICALLY ISOLATED INTERFACE The power supply line itself should have as large a trace as In process control applications in industrial environments, it possible to provide a low impedance path and to reduce glitch is often necessary to use a galvanically isolated interface to effects on the supply line. Clocks and other fast switching protect and isolate the controlling circuitry from any hazardous digital signals should be shielded from other parts of the board common-mode voltages that can occur in the area where the by digital ground. Avoid crossover of digital and analog signals DAC is functioning. iCoupler® provides isolation in excess of if possible. When traces cross on opposite sides of the board, 2.5 kV. The AD5663 use a 3-wire serial logic interface, so the ensure that they run at right angles to each other to reduce ADuM1300 three-channel digital isolator provides the required feedthrough effects through the board. The best board layout isolation (see Figure 39). The power supply to the part also technique is the microstrip technique, where the component needs to be isolated, which is done by using a transformer. On side of the board is dedicated to the ground plane only, and the the DAC side of the transformer, a 5 V regulator provides the signal traces are placed on the solder side. However, this is not 5 V supply required for the AD5663. always possible with a 2-layer board. Rev. A | Page 20 of 24

Data Sheet AD5663 OUTLINE DIMENSIONS 2.48 2.38 3.10 2.23 3.00 SQ 2.90 0.50 BSC 6 10 PIN 1 INDEX EXPOSED 1.74 AREA PAD 1.64 0.50 1.49 0.40 0.30 5 1 0.20 MIN TOP VIEW BOTTOM VIEW PIN 1 INDICATOR (R 0.15) 0.80 FOR PROPER CONNECTION OF 0.75 0.05 MAX THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEPALTAINNGE 000...322050 0.20 REF 0.08 02-05-2013-C Figure 40. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA 091709-A Figure 41. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Temperature Power-On Package Package Model1 Range Reset Code Accuracy Description Option Branding AD5663ARMZ −40°C to +105°C Zero ±16 LSB INL 10-Lead MSOP RM-10 D80 AD5663ARMZ-REEL7 −40°C to +105°C Zero ±16 LSB INL 10-Lead MSOP RM-10 D80 AD5663BRMZ −40°C to +105°C Zero ±12 LSB INL 10-Lead MSOP RM-10 D8C AD5663BRMZ-REEL7 −40°C to +105°C Zero ±12 LSB INL 10-Lead MSOP RM-10 D8C AD5663BRMZ-1 −40°C to +105°C Midscale ±12 LSB INL 10-Lead MSOP RM-10 D7J AD5663BRMZ-1REEL7 −40°C to +105°C Midscale ±12 LSB INL 10-Lead MSOP RM-10 D7J AD5663BCPZ-R2 −40°C to +105°C Zero ±12 LSB INL 10-Lead LFCSP_WD CP-10-9 D8C AD5663BCPZ-REEL7 −40°C to +105°C Zero ±12 LSB INL 10-Lead LFCSP_WD CP-10-9 D8C 1 Z = RoHS Compliant Part. Rev. A | Page 21 of 24

AD5663 Data Sheet NOTES Rev. A | Page 22 of 24

Data Sheet AD5663 NOTES Rev. A | Page 23 of 24

AD5663 Data Sheet NOTES ©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05855-0-11/16(A) Rev. A | Page 24 of 24

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5663BCPZ-REEL7 AD5663BRMZ-REEL7 AD5663ARMZ AD5663BRMZ-1REEL7 AD5663BRMZ-1 AD5663ARMZ-REEL7 AD5663BRMZ AD5663BCPZ-R2