Single, 12-/14-/16-Bit nanoDAC with 5 ppm/°C On-Chip Reference in SOT-23 Data Sheet AD5620/AD5640/AD5660 FEATURES FUNCTIONAL BLOCK DIAGRAM Low power, single nanoDACs VREFOUT GND VDD AD5660: 16 bits AD5640: 14 bits POWER-ON 1.25/2.5V AD5620/AD5640/AD5660 AD5620: 12 bits RESET REF VFB 12-bit accuracy guaranteed On-chip, 1.25 V/2.5 V, 5 ppm/°C reference REGDIASCTER REF1(6+-)BIT OBUUFTFPEURT VOUT Tiny 8-lead SOT-23, MSOP, and LFCSP packages DAC Power-down to 480 nA @ 5 V, 200 nA @ 3 V 3 V/5 V single power supply INPUT Guaranteed 16-bit monotonic by design COLNOTGRICOL CPOONWTREORL-D LOOWGNIC NREETSWISOTORRK Power-on reset to zero/midscale 3S eproiawl einr-tderofwacne f wunitcht iSocnhsm itt-triggered inputs 04539-001 SYNC SCLK DIN Rail-to-rail operation SYNC interrupt facility Figure 1. GENERAL DESCRIPTION APPLICATIONS The AD5620/AD5640/AD5660, members of the nanoDAC™ Process control family of devices, are low power, single, 12-/14-/16-bit, buffered Data acquisition systems voltage-out DACs and are guaranteed monotonic by design. Portable battery-powered instruments The AD5620/AD5640/AD5660-1 parts include an internal, Digital gain and offset adjustment 1.25 V, 5 ppm/°C reference, giving a full-scale output voltage Programmable voltage and current sources range of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include Programmable attenuators an internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output voltage range of 5 V. The reference associated with each part is PRODUCT HIGHLIGHTS available at the V pin. REFOUT 1. 12-/14-/16-bit nanoDAC—12-bit accuracy guaranteed. The parts incorporate a power-on reset circuit to ensure that the 2. On-chip, 1.25 V/2.5 V, 5 ppm/°C reference. DAC output powers up to 0 V (AD5620/AD5640/AD5660-1-2) 3. Available in 8-lead SOT-23, MSOP, and LFCSP packages. or midscale (AD5620-3 and AD5660-3) and remains there until 4. Power-on reset to 0 V or midscale. a valid write takes place. The parts contain a power-down 5. 10 µs settling time. feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads Table 1. Related Device while in power-down mode. The power consumption is Part No. Description 2.5 mW at 5 V, reducing to 1 µW in power-down mode. AD5662 2.7 V to 5.5 V, 16-bit DAC in SOT-23, LFCSP, and MSOP, external reference The AD5620/AD5640/AD5660 on-chip precision output amplifier allows rail-to-rail output swing to be achieved. For remote sensing applications, the output amplifier’s inverting input is available to the user. The AD5620/AD5640/AD5660 use a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5620/AD5640/AD5660 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Internal Reference ...................................................................... 17 Applications ....................................................................................... 1 Output Amplifier ........................................................................ 17 Product Highlights ........................................................................... 1 Serial Interface ............................................................................ 17 Functional Block Diagram .............................................................. 1 Input Shift Register .................................................................... 18 General Description ......................................................................... 1 SYNC Interrupt .......................................................................... 18 Revision History ............................................................................... 2 Power-On Reset .......................................................................... 19 Specifications ..................................................................................... 3 Power-Down Modes .................................................................. 19 AD5620/AD5640/AD5660-2-3 .................................................. 3 Microprocessor Interfacing ....................................................... 19 AD5620/AD5640/AD5660-1 ...................................................... 5 Applications Information .............................................................. 21 Timing Characteristics ................................................................ 7 Using a REF19x as a Power Supply for the AD5620/AD5640/AD5660 ....................................................... 21 Absolute Maximum Ratings ............................................................ 8 Bipolar Operation Using the AD5660 ..................................... 21 ESD Caution .................................................................................. 8 Using the AD5660 as an Isolated, Programmable, 4 mA to Pin Configurations and Function Descriptions ........................... 9 20 mA Process Controller ......................................................... 22 Typical Performance Characteristics ........................................... 10 Using the AD5620/AD5640/AD5660 with a Galvanically Terminology .................................................................................... 16 Isolated Interface ........................................................................ 22 Theory of Operation ...................................................................... 17 Power Supply Bypassing and Grounding ................................ 23 D/A Section ................................................................................. 17 Outline Dimensions ....................................................................... 24 Resistor String ............................................................................. 17 Ordering Guide .......................................................................... 26 REVISION HISTORY 10/09—Rev. B to Rev. C 8/13—Rev. F to Rev. G Changes to Ordering Guide .......................................................... 23 Added LFCSP (Throughout)........................................................... 1 5/06—Rev. A to Rev. B Added Thermal Impedance for LFCSP; Table 5 ........................... 8 Added Figure 5; Renumbered Sequentially .................................. 9 Updated Formatted ............................................................ Universal Updated Outline Dimensions ....................................................... 24 Updated Temperature Range ............................................ Universal Changes to Ordering Guide .......................................................... 26 Changes to Table 2 ............................................................................. 3 Changes to Table 5 ............................................................................. 8 12/10—Rev. E to Rev. F Replaced Figure 17, Figure 18, and Figure 19 ............................. 12 Changes to Ordering Guide .......................................................... 25 Changes to Ordering Guides .................................................. 23, 24 7/10—Rev. D to Rev. E 9/05—Rev. 0 to Rev. A Moved Using the AD5660 as an Isolated, Programmable, 4 mA Changes to Specifications ................................................................. 5 to 20 mA Process Controller Section ........................................... 22 Changes to Outline Dimensions .................................................. 23 Moved Power Supply Bypassing and Grounding Section ......... 23 7/05—Revision 0: Initial Version Changes to Ordering Guide .......................................................... 25 3/10—Rev. C to Rev. D Changes to Ordering Guide .......................................................... 24 Rev. G | Page 2 of 28

Data Sheet AD5620/AD5640/AD5660 SPECIFICATIONS AD5620/AD5640/AD5660-2-3 V = 4.5 V to 5.5 V, R = 2 kΩ to GND, C = 200 pF to GND, C = 100 nF; all specifications T to T , unless otherwise noted. DD L L REFOUT MIN MAX Table 2. Parameter A Grade1 B Grade1 C Grade1 Unit Conditions/Comments STATIC PERFORMANCE2 AD5660 Resolution 16 16 16 Bits min Relative Accuracy ±32 ±16 ±16 LSB max Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic by design AD5640 Resolution 14 14 14 Bits min Relative Accuracy ±8 ±4 ±4 LSB max Differential Nonlinearity ±0.5 ±0.5 ±0.5 LSB max Guaranteed monotonic by design AD5620 Resolution 12 12 12 Bits min Relative Accuracy ±6 ±1 ±1 LSB max Differential Nonlinearity ±0.25 ±0.25 ±0.25 LSB max Guaranteed monotonic by design Zero-Code Error 2 2 2 mV typ All 0s loaded to DAC register 10 10 10 mV max Offset Error ±10 ±10 ±10 mV max Full-Scale Error −0.15 −0.15 −0.15 % FSR typ All 1s loaded to DAC register ±1 ±1 ±1 % FSR max Gain Error ±1.5 ±1.5 ±1.5 % FSR max Zero-Code Error Drift ±2 ±2 ±2 µV/°C typ Gain Temperature Coefficient ±2.5 ±2.5 ±2.5 ppm typ Of FSR/°C DC Power Supply Rejection Ratio −75 −75 −75 dB typ DAC code = midscale; V = 5 V ± 10% DD OUTPUT CHARACTERISTICS3 Output Voltage Range 0 0 0 V min V V V V max DD DD DD Output Voltage Settling Time 8 8 8 µs typ ¼ to ¾ scale change settling to ±2 LSB 10 10 10 µs max R = 2 kΩ; 0 pF < C < 200 pF L L Slew Rate 1.5 1.5 1.5 V/µs typ ¼ to ¾ scale Capacitive Load Stability 2 2 2 nF typ R = ∞ L 10 10 10 nF typ R = 2 kΩ L Output Noise Spectral Density 80 80 80 nV/√Hz typ DAC code = midscale, 10 kHz Output Noise (0.1 Hz to 10 Hz) 45 45 45 µV p-p typ DAC code = midscale Digital-to-Analog Glitch Impulse 5 5 5 nV-s typ 1 LSB change around major carry Digital Feedthrough 0.1 0.1 0.1 nV-s typ DC Output Impedance 0.5 0.5 0.5 Ω typ Short-Circuit Current 30 30 30 mA typ V = 5 V DD Power-Up Time 5 5 5 µs typ Coming out of power-down mode; V = 5 V DD REFERENCE OUTPUT Output Voltage 2.495 2.495 2.495 V min At ambient 2.505 2.505 2.505 V max Reference TC3 ±10 ±10 ±5 ppm/°C typ ±10 ppm/°C max Output Impedance 7.5 7.5 7.5 kΩ typ Rev. G | Page 3 of 28

AD5620/AD5640/AD5660 Data Sheet Parameter A Grade1 B Grade1 C Grade1 Unit Conditions/Comments LOGIC INPUTS3 Input Current ±2 ±2 ±2 µA max All digital inputs V , Input Low Voltage 0.8 0.8 0.8 V max V = 5 V INL DD V , Input High Voltage 2 2 2 V min V = 5 V INH DD Pin Capacitance 3 3 3 pF typ POWER REQUIREMENTS V 4.5 4.5 4.5 V min All digital inputs at 0 V or V DD DD 5.5 5.5 5.5 V max DAC active and excluding load current I (Normal Mode) DD V = 4.5 V to 5.5 V 0.55 0.55 0.55 mA typ V = V and V = GND DD IH DD IL V = 4.5 V to 5.5 V 1 1 1 mA max V = V and V = GND DD IH DD IL I (All Power-Down Modes) DD V = 4.5 V to 5.5 V 0.48 0.48 0.48 µA typ V = V and V = GND DD IH DD IL V = 4.5 V to 5.5 V 1 1 1 µA max V = V and V = GND DD IH DD IL 1 Temperature range is −40°C to +105°C, typical at +25°C. 2 Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 128 to Code 16256); AD5620 (Code 32 to Code 4064). Output unloaded. Linearity tested with VDD = 5.5 V. If part is operated with a VDD < 5 V, the output is clamped to VDD. 3 Guaranteed by design and characterization; not production tested. Rev. G | Page 4 of 28

Data Sheet AD5620/AD5640/AD5660 AD5620/AD5640/AD5660-1 V 1 = 2.7 V to 3.3 V, R = 2 kΩ to GND, C = 200 pF to GND, C = 100 nF; all specifications T to T , unless otherwise noted. DD L L REFOUT MIN MAX Table 3. Parameter A Grade2 B Grade2 C Grade2 Unit Conditions/Comments STATIC PERFORMANCE3 AD5660 Resolution 16 16 16 Bits min Relative Accuracy ±32 ±16 ±16 LSB max Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic by design AD5640 Resolution 14 14 14 Bits min Relative Accuracy ±8 ±4 ±4 LSB max Differential Nonlinearity ±0.5 ±0.5 ±0.5 LSB max Guaranteed monotonic by design AD5620 Resolution 12 12 12 Bits min Relative Accuracy ±6 ±1 ±1 LSB max Differential Nonlinearity ±0.25 ±0.25 ±0.25 LSB max Guaranteed monotonic by design Zero-Code Error 2 2 2 mV typ All 0s loaded to DAC register 8 8 8 mV max Offset Error ±9 ±9 ±9 mV max Full-Scale Error ±0.15 ±0.15 ±0.15 % FSR typ All 1s loaded to DAC register ±0.85 ±0.85 ±0.85 % FSR max Gain Error ±0.85 ±0.85 ±0.85 % FSR max Zero-Code Error Drift ±2 ±2 ±2 µV/°C typ Gain Temperature Coefficient ±2.5 ±2.5 ±2.5 ppm typ Of FSR/°C DC Power Supply Rejection Ratio −60 −60 −60 dB typ DAC code = midscale; V = 3 V ± 10% DD OUTPUT CHARACTERISTICS4 Output Voltage Range 0 0 V min V V V V max DD DD DD Output Voltage Settling Time 8 8 8 µs typ ¼ to ¾ scale change settling to ±2 LSB 10 10 10 µs max R = 2 kΩ; 0 pF < C < 200 pF L L Slew Rate 1.5 1.5 1.5 V/µs typ ¼ to ¾ scale Capacitive Load Stability 2 2 2 nF typ R = ∞ L 10 10 10 nF typ R = 2 kΩ L Output Noise Spectral Density 80 80 80 nV/√Hz typ DAC code = midscale, 10 kHz Output Noise (0.1 Hz to 10 Hz) 20 20 20 µV p-p typ DAC code = midscale Digital-to-Analog Glitch Impulse 5 5 5 nV-s typ 1 LSB change around major carry Digital Feedthrough 0.1 0.1 0.1 nV-s typ DC Output Impedance 0.5 0.5 0.5 Ω typ Short-Circuit Current 30 30 30 mA typ V = 3 V DD Power-Up Time 6 6 6 µs typ Coming out of power-down mode; V = 3 V DD REFERENCE OUTPUT Output Voltage 1.247 1.247 1.247 V min At ambient 1.253 1.253 1.253 V max Reference TC4 ±10 ±10 ±5 ppm/°C typ ±15 ppm/°C max Output Impedance 7.5 7.5 7.5 kΩ typ Rev. G | Page 5 of 28

AD5620/AD5640/AD5660 Data Sheet Parameter A Grade2 B Grade2 C Grade2 Unit Conditions/Comments LOGIC INPUTS4 Input Current ±1 ±1 ±1 µA max All digital inputs V , Input Low Voltage 0.8 0.8 0.8 V max V = 3 V INL DD V , Input High Voltage 2 2 2 V min V = 3 V INH DD Pin Capacitance 3 3 3 pF max POWER REQUIREMENTS V 2.7 2.7 2.7 V min All digital inputs at 0 V or V DD DD 3.3 3.3 3.3 V max DAC active and excluding load current I (Normal Mode) DD V = 2.7 V to 3.3 V 0.55 0.55 0.55 mA typ V = V and V = GND DD IH DD IL V = 2.7 V to 3.3 V 0.65 0.65 0.65 mA max V = V and V = GND DD IH DD IL I (All Power-Down Modes) DD V = 2.7 V to 3.3 V 0.2 0.2 0.2 µA typ V = V and V = GND DD IH DD IL V = 2.7 V to 3.3 V 0.25 0.25 0.25 µA max V = V and V = GND DD IH DD IL 1 Part is functional with VDD up to 5.5 V. 2 Temperature range is −40°C to +105°C, typical at +25°C. 3 Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 128 to Code 16256); AD5620 (Code 32 to Code 4064). Output unloaded. 4 Guaranteed by design and characterization; not production tested. Rev. G | Page 6 of 28

Data Sheet AD5620/AD5640/AD5660 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2. See Figure 2. DD IL IH V = 2.7 V to 5.5 V; all specifications T to T , unless otherwise noted. DD MIN MAX Table 4. Limit at T , T MIN MAX Parameter V = 2.7 V to 3.6 V V = 3.6 V to 5.5 V Unit Conditions/Comments DD DD t1 50 33 ns min SCLK cycle time 1 t 13 13 ns min SCLK high time 2 t 13 13 ns min SCLK low time 3 t 13 13 ns min SYNC to SCLK falling edge setup time 4 t 5 5 ns min Data setup time 5 t 4.5 4.5 ns min Data hold time 6 t 0 0 ns min SCLK falling edge to SYNC rising edge 7 t 50 33 ns min Minimum SYNC high time 8 t 13 13 ns min SYNC rising edge to SCLK fall ignore 9 t 0 0 ns min SCLK falling edge to SYNC fall ignore 10 1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V. t10 t1 t 9 SCLK t8 t4 t3 t2 t7 SYNC t 6 t 5 DIN MSB LSB LMMSSSBBB === DDDBBB01253 FFOORRAADD55662600/AD5640 04539-002 Figure 2. Serial Write Operation Rev. G | Page 7 of 28

AD5620/AD5640/AD5660 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings Table 5. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any V to GND −0.3 V to +7 V DD other conditions above those indicated in the operational V to GND −0.3 V to V + 0.3 V OUT DD section of this specification is not implied. Exposure to absolute V to GND −0.3 V to V + 0.3 V FB DD maximum rating conditions for extended periods may affect V to GND −0.3 V to V + 0.3 V REFOUT DD device reliability. Digital Input Voltage to GND −0.3 V to V + 0.3 V DD Operating Temperature Range ESD CAUTION Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 150°C J Power Dissipation (T max − T )/θ J A JA SOT-23 Package (4-Layer Board) θ Thermal Impedance 119°C/W JA MSOP Package (4-Layer Board) θ Thermal Impedance 141°C/W JA θ Thermal Impedance 44°C/W JC LFCSP Package(4-Layer Board) θ Thermal Impedance 103°C/W JA θ Thermal Impedance 44.4°C/W JC Reflow Soldering Peak Temperature SnPb 240°C Pb-Free 260°C Rev. G | Page 8 of 28

Data Sheet AD5620/AD5640/AD5660 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 AD5620/ 8 GND AD5640/ VDD 1 8 GND VREFOUT 2 AD5660 7 DIN VREFOUT 2 AADD55662400// 7 DIN VVOUFBT 43 (NToOt Pto V SIEcaWle) 65 SSYCNLKC 04539-003 VVOFUBT 34 ATODP5 V6IE6W0 65 SSCYNLKC 04539-105 Figure 3. SOT-23 Pin Configuration Figure 5. LFCSP Pin Configuration VDD 1 AD5620/ 8 GND VREFOUT 2 AD5640/ 7 DIN VVOUFBT 43 (NTAoOtD Pto5 V 6SIEc6aW0le) 65 SSYCNLKC 04539-004 Figure 4. MSOP Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD Power Supply Input. These parts can operate from 2.7 V to 5.5 V. VDD should be decoupled to GND. 2 VREFOUT Reference Voltage Output. 3 VFB Feedback Connection for the Output Amplifier. VFB should be connected to VOUT for normal operation. 4 VOUT Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. 5 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle for the AD5660 and the 16th clock cycle for AD5620/AD5640 unless SYNC is taken high before this edge. In this case, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. 6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 7 DIN Serial Data Input. The AD5660 has a 24-bit shift register, and the AD5620/AD5640 have a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 8 GND Ground Reference Point for all Circuitry on the Part. Rev. G | Page 9 of 28

AD5620/AD5640/AD5660 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 10 1.0 VDD = 5V VDD = 5V 8 VREFOUT = 2.5V 0.8 VREFOUT = 2.5V TA = 25°C TA = 25°C 6 0.6 4 0.4 OR (LSB) 2 OR (LSB) 0.2 INL ERR –02 DNL ERR –0.02 –4 –0.4 –6 –0.6 –1–08 04539-005 ––10..08 04539-008 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 0 5 0 5 0 5 0 5 0 5 0 5 1 1 2 2 3 3 4 4 5 5 6 6 1 1 2 2 3 3 4 4 5 5 6 6 CODE CODE Figure 6. INL—AD5660-2/AD5660-3 Figure 9. DNL—AD5660-2/AD5660-3 4 0.5 VDD = 5V VDD = 5V 3 VTAR E=F O25U°TC = 2.5V 0.4 VTAR E=F O25U°TC = 2.5V 0.3 2 0.2 INL ERROR (LSB) –110 DNL ERROR (LSB) –00..011 –0.2 –2 –0.3 ––43 04539-006 ––00..54 04539-009 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 0 5 0 5 0 5 0 5 0 5 0 5 2 5 7 0 2 5 7 0 2 5 7 0 2 2 5 7 0 2 5 7 0 2 5 7 0 2 1 2 3 5 6 7 8 0 1 2 3 5 6 1 2 3 5 6 7 8 0 1 2 3 5 6 1 1 1 1 1 1 1 1 1 1 1 1 CODE CODE Figure 7. INL—AD5640-2/AD5640-3 Figure 10. DNL—AD5640-2/AD5640-3 1.0 0.20 VDD = 5V VDD = 5V 0.8 VREFOUT = 2.5V 0.15 VREFOUT = 2.5V TA = 25°C TA = 25°C 0.6 0.10 0.4 OR (LSB) 0.2 OR (LSB) 0.05 INL ERR –0.02 DNL ERR–0.005 –0.4 –0.10 –0.6 ––10..08 04539-007 ––00..2105 04539-010 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 8. INL—AD5620-2/AD6520-3 Figure 11. DNL—AD5620-2/AD6520-3 Rev. G | Page 10 of 28

Data Sheet AD5620/AD5640/AD5660 10 1.0 VDD = 3V VDD = 3V 8 VREFOUT = 1.25V 0.8 VREFOUT = 1.25V TA = 25°C TA = 25°C 6 0.6 4 0.4 INL ERROR (LSB) –202 DNL ERROR (LSB) –00..202 –4 –0.4 –6 –0.6 ––180 04539-017 ––01..80 04539-020 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 0 5 0 5 0 5 0 5 0 5 0 5 1 1 2 2 3 3 4 4 5 5 6 6 1 1 2 2 3 3 4 4 5 5 6 6 CODE CODE Figure 12. INL—AD5660-1 Figure 15. DNL—AD5660-1 4 0.5 VDD = 3V VDD = 3V 3 VREFOUT = 1.25V 0.4 VREFOUT = 1.25V TA = 25°C TA = 25°C 0.3 2 0.2 INL ERROR (LSB) –101 DNL ERROR (LSB) –00..011 –0.2 –2 –0.3 ––43 04539-018 ––00..54 04539-021 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 0 5 0 5 0 5 0 5 0 5 0 5 2 5 7 0 2 5 7 0 2 5 7 0 2 2 5 7 0 2 5 7 0 2 5 7 0 2 1 2 3 5 6 7 8 0 1 2 3 5 6 1 2 3 5 6 7 8 0 1 2 3 5 6 1 1 1 1 1 1 1 1 1 1 1 1 CODE CODE Figure 13. INL—AD5640-1 Figure 16. DNL—AD5640-1 1.0 0.20 VDD = 3V VDD = 3V 0.8 VREFOUT = 1.25V 0.15 VREFOUT = 1.25V TA = 25°C TA = 25°C 0.6 0.10 0.4 INL ERROR (LSB) –00..022 DNL ERROR (LSB)–00..00550 –0.4 –0.10 –0.6 ––10..08 04539-019 ––00..2105 04539-025 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 14. INL—AD5620-1 Figure 17. DNL—AD5620-1 Rev. G | Page 11 of 28

AD5620/AD5640/AD5660 Data Sheet 12 200 10 VDD=5V VDD = 5V 180 TA = 25°C 8 160 6 MAX INL ES 140 4 C R (LSB) 02 MAXDNL OF DEVI 110200 O R R E R –2 MINDNL B 80 E M –4 NU 60 –6 40 ––11–208–40 –20 0 MIN20 INL 40 60 80 100 04539-011 200 0.45VD0.46D =0.47 3.0.483V0.490.500.510.520.530.540.550.560.570.580.590.600.610.620.630.640.650.660.6704539-014 TEMPERATURE(°C) IDD (mA) Figure 18. INL Error and DNL Error vs. Temperature Figure 21. IDD Histogram 0.4 VDD=5V 0.50 DAC LOADED WITH DAC LOADED WITH 0.40 FULL-SCALE ZERO-SCALE SOURCING CURRENT SINKING CURRENT 0.2 0.30 GAINERROR R) V) 0.20 FS E ( R (% 0 TAG 0.10 VVDRDEF=O 3UVT = 1.25V ERRO FULLSCALEERROR OR VOL–0.100 R R –0.2 E–0.20 –0.30 VDD= 5V –0.4–40 –20 0 20 40 60 80 100 04539-012 ––00..5400 VREFOUT = 2.5V 04539-022 –10 –8 –6 –4 –2 0 2 4 6 8 10 TEMPERATURE(°C) CURRENT (mA) Figure 19. Gain Error and Full-Scale Error vs. Temperature Figure 22. Headroom at Rails vs. Source and Sink 1.6 VDD=5V 6.00 1.4 VDD= 5V FULL SCALE VREFOUT = 2.5V 1.2 5.00 TA = 25°C V)1.0 ZEROCODEERROR 4.00 3/4 SCALE m ROR (0.8 (V)T 3.00 MIDSCALE R U E0.6 VO 2.00 1/4 SCALE 0.4 OFFSETERROR 1.00 0.20–40 –20 0 20 40 60 80 100 04539-013 –1.000 ZERO SCALE 04539-023 –30 –20 –10 0 10 20 30 TEMPERATURE(°C) CURRENT (mA) Figure 20. Zero-Code and Offset Error vs. Temperature Figure 23. Source and Sink Capability—AD5660-2/AD5660-3 Rev. G | Page 12 of 28

Data Sheet AD5620/AD5640/AD5660 4.00 VDD= 3V VREFOUT = 1.25V TA = 25°C 3.00 FULL SCALE VDD = 5V 2.00 3/4 SCALE TA = 25°C V) FULL-SCALECODECHANGE (OUT MIDSCALE 0OxU0T0P0U0 TT OLO 0AxFDFEFDF WITH 2kΩ V AND 200pF TO GND 1.00 1/4 SCALE VOUT= 909mV/DIV 0 ZERO SCALE –1.00–30 –20 –10 0 10 20 3004539-024 1 04539-028 TIME BASE = 4µs/DIV CURRENT (mA) Figure 24. Source and Sink Capability—AD5660-1 Figure 27. Full-Scale Settling Time, 5 V 0.7 TA = 25°C VDD = 5V VDD 0.6 VDD = 3V 0.5 1 VREF A) 0.4 (mD 2 ID 0.3 0.2 VOUT 0.10 04539-015 3 04539-029 512 10512 20512 30512 40512 50512 60512 CH1 2.00V CH2 2.00V M40.0ms CH1 CODE CH3 100mV Figure 25. Supply Current vs. Code Figure 28. Power-On Reset to 0 V—AD5660-2 1400 TA = 25°C 1200 1000 VDD 1 A) 800 µ (DD VDD = 5V 2 VREF I 600 VDD = 3V 400 20000 1 2 3 4 5 04539-016 3 CH1 2.00VVOUCTH2 2.00V M20.0µs CH1 1.88V 04539-030 VLOGIC (V) CH3 200mV Figure 26. Supply Current vs. Logic Input Voltage Figure 29. Power-On Reset to Midscale—AD5660-3 Rev. G | Page 13 of 28

AD5620/AD5640/AD5660 Data Sheet 1.250800 1.250600 1.250400 VDD 1.250200 1 1.250000 E D1.249800 2 VREF LITU1.249600 P M A1.249400 1.249200 VDD = 3V VREFOUT = 1.25V VOUT 1.249000 TA = 25°C 13nS/SAMPLE NUMBER 3 CH1 1.20V CH2 1.00V M100µs CH1 1.87V 04539-031 111...222444888864000000 1 G L L(S0ITxBC7 CFHFH IFAM TNPOGU EL0S xA8ER0 =0O 00U).N28D4 nMVID-sSCALE 04539-033 0 50 100 150 200 250 300 350 400 450 500 550 CH3 100mV SAMPLE NUMBER Figure 30. Power-On Reset to 0 V—AD5660-1 Figure 33. Digital-to-Analog Glitch Impulse—AD5660-1 2.500250 SCLK VDD= 3V 2.500200 TVAD D= =2 55°VC 2.500150 20nS/SAMPLE NUMBER DAC LOADED WITH MIDSCALE 1 2.500100 DIGITAL FEEDTHROUGH = 0.06nV-s 2.500050 E2.500000 D TU2.499950 LI P2.499900 M A2.499850 2.499800 3 2.499750 CH1 2.00V M1.00µs VOUTCH2 520mV 04539-055 222...4449999997660500000 50 100 150 200 250 300 350 400 450 500 55004539-034 CH3 50.0mV SAMPLE NUMBER Figure 31. Exiting Power-Down to Midscale Figure 34. Digital Feedthrough 2.501250 16 2.501000 TA = 25°C 2.500750 14 2.500500 2.500250 VDD=3V 12 E2.500000 PLITUD22..449999755000 µME (s) 10 M TI A2.499250 2.499000 VVRDDEF =O U5VT = 2.5V 8 VDD=5V 2.498750 TA = 25°C 13nS/SAMPLE NUMBER 2.498500 1LSB CHANGE AROUND MIDSCALE 6 22..449988205000 G L(0ITxC7FHF IFM TPOU L0Sx8E0 =0 00).497nV-s 04539-032 4 04539-036 0 50 100 150 200 250 300 350 400 450 500 550 0 1 2 3 4 5 6 7 8 9 10 SAMPLE NUMBER CAPACITANCE (nF) Figure 32. Digital-to-Analog Glitch Impulse—AD5660-2/AD5660-3 Figure 35. Settling Time vs. Capacitive Load Rev. G | Page 14 of 28

Data Sheet AD5620/AD5640/AD5660 800 VDD = 5V TA = 25°C VTAR E=F O25U°TC = 2.5V 700 MIDSCALE LOADED DACLOADEDWITHMIDSCALE Hz) 600 √ nV 500 DIV SE ( V/1 OI 400 µ N 10 T U P 300 OUT 200 VVDRDEF=O 5UVT = 2.5V 04539-037 1000 VVRDDEF=O 3UVT = 1.25V 04539-038 100 1000 10000 100000 1000000 5s/DIV FREQUENCY (Hz) Figure 36. 0.1 Hz to 10 Hz Output Noise—AD5660-2/AD5660-3 Figure 38. Noise Spectral Density VDD = 3V VREFOUT = 1.25V TA = 25°C DACLOADEDWITHMIDSCALE V DI V/1 µ 5 04539-054 4s/DIV Figure 37. 0.1 Hz to 10 Hz Output Noise—AD5660-1 Rev. G | Page 15 of 28

AD5620/AD5640/AD5660 Data Sheet TERMINOLOGY Relative Accuracy Offset Error For the DAC, relative accuracy, or integral nonlinearity (INL), is Offset error is a measurement of the difference between V OUT a measurement of the maximum deviation, in LSBs, from a (actual) and V (ideal) expressed in mV in the linear region of OUT straight line passing through the endpoints of the DAC transfer the transfer function. Offset error is measured on the AD5660 function. Figure 6 through Figure 8 show typical INL vs. code. with Code 512 loaded into the DAC register. It can be negative or positive. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured DC Power Supply Rejection Ratio (PSRR) change and the ideal 1 LSB change between any two adjacent This indicates how the output of the DAC is affected by changes codes. A specified differential nonlinearity of ±1 LSB maximum in the supply voltage. PSRR is the ratio of the change in V to OUT ensures monotonicity. This DAC is guaranteed monotonic by the change in V for the full-scale output of the DAC. It is DD design. Figure 9 through Figure 11 show typical DNL vs. code. measured in dB. V is held at 2.5 V, and V is varied by ±10%. REF DD Zero-Code Error Output Voltage Settling Time Zero-code error is a measurement of the output error when This indicates the amount of time for the output of a DAC to zero code (0x0000) is loaded to the DAC register. Ideally, the settle to a specified level for a ¼ to ¾ full-scale input change. It output should be 0 V. The zero-code error is always positive in is measured from the 24th falling edge of SCLK. the AD5620/AD5640/AD5660, because the output of the DAC Digital-to-Analog Glitch Impulse cannot go below 0 V. It is due to a combination of the offset Digital-to-analog glitch impulse is the impulse injected into the errors in the DAC and the output amplifier. Zero-code error is analog output when the input code in the DAC register changes expressed in mV. Figure 20 shows a plot of zero-code error vs. state. It is normally specified as the area of the glitch in nV-s temperature. and is measured when the digital input code is changed by Full-Scale Error 1 LSB at the major carry transition (0x7FFF to 0x8000). See Full-scale error is a measurement of the output error when full- Figure 32 and Figure 33. scale code (0xFFFF) is loaded to the DAC register. Ideally, the Digital Feedthrough output should be V − 1 LSB. Full-scale error is expressed as a DD Digital feedthrough is a measurement of the impulse injected percentage of the full-scale range. Figure 19 shows a plot of full- into the analog output of the DAC from the digital inputs of the scale error vs. temperature. DAC, but is measured when the DAC output is not updated. It Gain Error is specified in nV-s and measured with a full-scale code change This is a measurement of the span error of the DAC. It is the on the data bus, that is, from all 0s to all 1s or vice versa. deviation in slope of the DAC transfer characteristic from the Noise Spectral Density ideal, expressed as a percentage of the full-scale range. This is a measurement of the internally generated random Zero-Code Error Drift noise. Random noise is characterized as a spectral density This is a measurement of the change in zero-code error with a (voltage per √Hz). It is measured by loading the DAC to change in temperature. It is expressed in µV/°C. midscale and measuring noise at the output. It is measured in nV/√Hz. Figure 38 shows a plot of noise spectral density. Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Rev. G | Page 16 of 28

Data Sheet AD5620/AD5640/AD5660 THEORY OF OPERATION D/A SECTION tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is The AD5620/AD5640/AD5660 DACs are fabricated on a CMOS guaranteed monotonic. process. The architecture consists of a string DAC followed by an output buffer amplifier. The parts include an internal 1.25 V/2.5 V, INTERNAL REFERENCE 5 ppm/°C reference that is internally gained up by 2. Figure 39 The AD5620/AD5640/AD5660-1 parts include an internal, shows a block diagram of the DAC architecture. 1.25 V, 5 ppm/°C reference, giving a full-scale output voltage of VDD R 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an VFB internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output R REF (+) voltage of 5 V. The reference associated with each part is RESISTOR DAC REGISTER STRING VOUT available at the VREFOUT pin. A buffer is required if the reference REF (�–) output is used to drive external loads. It is recommended that a OUTPUT GND AMPLIFIER 04777-022 G10N0 Dn Ffo cra rpeafceirteonrc ies sptlaabcieldit yb. etween the reference output and Figure 39. DAC Architecture OUTPUT AMPLIFIER Because the input coding to the DAC is straight binary, the ideal The output buffer amplifier can generate rail-to-rail voltages on output voltage is given by its output, which gives an output range of 0 V to VDD. This output buffer amplifier has a gain of 2 derived from a 50 kΩ resistor  D  VOUT =2×VREFOUT×2N  divider network in the feedback path. The inverting input of the output amplifier is available to the user, allowing for remote where: sensing. This V pin must be connected to V for normal FB OUT D is the decimal equivalent of the binary code that is loaded to operation. It can drive a load of 2 kΩ in parallel with 1000 pF to the DAC register. GND. Figure 22 shows the source and sink capabilities of the 0 to 4095 for AD5620 (12 bit) output amplifier. The slew rate is 1.5 V/µs with a ¼ to ¾ full- 0 to 16383 for AD5640 (14 bit) scale settling time of 10 µs. 0 to 65535 for AD5660 (16 bit) N is the DAC resolution. SERIAL INTERFACE The AD5620/AD5640/AD5660 have a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and R MICROWIRE interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence. R The write sequence begins by bringing the SYNC line low. R TO OUTPUT Data from the DIN line is clocked into the 16-bit shift register AMPLIFIER (AD5620/AD5640) or the 24-bit shift register (AD5660) on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5620/AD5640/AD5660 compatible with high speed DSPs. On the 16th falling clock edge (AD5620/ AD5640) or the 24th falling clock edge (AD5660), the last data bit is clocked in and the programmed function is executed, that R is, a change in the DAC register contents and/or a change in the mode of operation is executed. At this stage, the SYNC line can R be kept low or be brought high. In either case, it must be brought 04539-040 high for a minimum of 33 ns before the next write sequence so Figure 40. Resistor String that a falling edge of SYNC can initiate the next write sequence. Because the SYNC buffer draws more current when V = 2 V IN RESISTOR STRING than it does when V = 0.8 V, SYNC should be idled low between IN The resistor string section is shown in Figure 40. It is simply a write sequences for even lower power operation of the parts. As string of resistors, each of value R. The code loaded to the DAC is mentioned previously, however, SYNC must be brought high register determines at which node on the string the voltage is again just before the next write sequence. tapped off to be fed into the output amplifier. The voltage is Rev. G | Page 17 of 28

AD5620/AD5640/AD5660 Data Sheet INPUT SHIFT REGISTER SYNC INTERRUPT AD5620/AD5640 In a normal write sequence for the AD5660, the SYNC line is The input shift register is 16 bits wide for the AD5620/AD5640 kept low for at least 24 falling edges of SCLK, and the DAC is (see Figure 41 and Figure 42). The first two bits are control bits updated on the 24th falling edge. However, if SYNC is brought that control which mode of operation the part is in (normal high before the 24th falling edge, this acts as an interrupt to the mode or any of the three power-down modes). The next write sequence. The shift register is reset, and the write sequence 14/12 bits, respectively, are the data bits. These are transferred is seen as invalid. Neither an update of the DAC register contents to the DAC register on the 16th falling edge of SCLK. nor a change in the operating mode occurs (see Figure 44). AD5660 Similarly, in a normal write sequence for the AD5620/AD5640, the SYNC line is kept low for at least 16 falling edges of SCLK, The input shift register is 24 bits wide for the AD5660 (see and the DAC is updated on the 16th falling edge. However, if Figure 43). The first six bits are don’t care bits. The next two are SYNC is brought high before the 16th falling edge, this acts as control bits that control which mode of operation the part is in an interrupt to the write sequence. (normal mode or any of the three power-down modes). For a more complete description of the various modes, see the Power-Down Modes section. The next 16 bits are the data bits. These are transferred to the DAC register on the 24th falling edge of SCLK. DB15 (MSB) DB0 (LSB) PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 04539-041 DATA BITS Figure 41. AD5620 Input Register Contents DB15 (MSB) DB0 (LSB) PD1 PD0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 04539-042 DATA BITS Figure 42. AD5640 Input Register Contents DB23 (MSB) DB0 (LSB) X X X X X X PD1 PD0 D15 D14 D13 D12 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 04539-043 DATA BITS Figure 43. AD5660 Input Register Contents SCLK SYNC DIN MSB LSB MSB LSB SYNC HIGINHV BAELFIDO WRER I1T6ET HS/2E4QTHU FEANLCLEI:NG EDGE VALID OWNR TITHEE S 1E6QTHU/2E4NTHC FEA, OLLUITNPGU ETD UGPEDATES 04539-044 Figure 44. SYNC Interrupt Facility Rev. G | Page 18 of 28

Data Sheet AD5620/AD5640/AD5660 POWER-ON RESET The AD5620/AD5640/AD5660 family contains a power-on reset circuit that controls the output voltage during power-up. The AD5620/AD5640/AD5660-1-2 DAC output powers up to SRTERSINISGTDOARC AMPLIFIER VOUT 0 V, and the AD5620/AD5660-3 DAC output powers up to midscale. The output remains at this level until a valid write sequence is made to the DAC, which is useful in applications POWER-DOWN CIRCUITRY RESISTOR wit hise irne itth ies pimropcoerstsa onft ptoo wkenroiwng t huep .s tate of the DAC output while NETWORK 04539-045 Figure 45. Output Stage During Power-Down POWER-DOWN MODES The AD5620/AD5640/AD5660 have four separate modes of The bias generator, output amplifier, reference, resistor string, operation. These modes are software-programmable by setting and other associated linear circuitry are all shut down when two bits in the control register. Table 7 and Table 8 show how power-down mode is activated. However, the contents of the the state of the bits corresponds to the operating mode of the DAC register are unaffected when in power-down. The time to device. exit power-down is typically 5 µs for VDD = 5 V and VDD = 3 V (see Figure 31). Table 7. Modes of Operation for the AD5660 MICROPROCESSOR INTERFACING DB17 DB16 AD5660 Operating Mode AD5660-to-Blackfin® ADSP-BF53x Interface 0 0 Normal operation Power-down modes: Figure 46 shows a serial interface between the AD5660 and the 0 1 1 kΩ to GND Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x 1 0 100 kΩ to GND processor family incorporates two dual-channel synchronous 1 1 Three-state serial ports, SPORT1 and SPORT0, for serial and multi- processor communications. Using SPORT0 to connect to the AD5660, the setup for the interface is as follows: DT0PRI drives the DIN pin of the AD5660, while TSCLK0 drives the SCLK of Table 8. Modes of Operation for the AD5620/AD5640 the part and SYNC is driven from TFS0. DB15 DB14 AD5620/AD5640 Operating Mode 0 0 Normal operation ADSP-BF53x1 AD56601 Power-down modes: 0 1 1 kΩ to GND 1 0 100 kΩ to GND TFS0 SYNC 1 1 Three-state DTOPRI DIN TSCLK0 SCLK 04539-046 When both bits are set to 0, the part works normally with its 1ADDITIONAL PINS OMITTED FOR CLARITY normal power consumption of 550 µA at 5 V. However, for the Figure 46. AD5660-to-Blackfin ADSP-BF53x Interface three power-down modes, the supply current falls to 480 nA at 5 V (200 nA at 3 V). Not only does the supply current fall, but the output stage is internally switched from the output of the amplifier to a resistor network of known values. The advan- tage is that the output impedance of the part is known while the part is in power-down mode. There are three options: the out- put is connected internally to GND through a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited (three-stated). The output stage is shown in Figure 45. Rev. G | Page 19 of 28

AD5620/AD5640/AD5660 Data Sheet AD5660-to-68HC11/68L11 Interface data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left Figure 47 shows a serial interface between the AD5660 and the low after the first eight bits are transmitted, and a second write 68HC11/68L11 microcontroller. SCK of 68HC11/68L11 drives cycle is initiated to transmit the second byte of data. P3.3 is taken the SCLK of AD5660, and the MOSI output drives the serial high following the completion of this cycle. The 80C51/80L51 data line of the DAC. The SYNC signal is derived from a port output the serial data LSB first; however, the AD5660 requires line (PC7). The setup conditions for correct operation of this its data with the MSB as the first bit received. The 80C51/80L51 interface are as follows: The 68HC11/68L11 should be con- transmit routine should take this into account. figured so that its CPOL bit is 0, and its CPHA bit is 1. When data is being transmitted to the DAC, the SYNC line is taken 80C51/80L511 AD56601 low (PC7). When the 68HC11/68L11 is configured in this way, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in P3.3 SYNC 8-bit bytes with only eight falling clock edges occurring in the TxD SCLK tAraDn5s6m60it, cPyCc7le i. sD leaftta l oisw t raafntesrm thitet efdir sMt eSiBg hfti rbsitt.s T aor el otraadn dsfaetrar etod ,t ah e RxD DIN 04539-048 second serial write operation is performed to the DAC, and PC7 1ADDITIONAL PINS OMITTED FOR CLARITY is taken high at the end of this procedure. Figure 48. AD5660-to-80C51/80L51 Interface 68HC11/68L111 AD56601 AD5660-to-MICROWIRE Interface Figure 49 shows an interface between the AD5660 and any PC7 SYNC MICROWIRE-compatible device. Serial data is shifted out on SCK SCLK the falling edge of the serial clock and is clocked into the MOSI DIN 04539-047 AD5660 on the rising edge of the SK. 1ADDITIONAL PINS OMITTED FOR CLARITY MICROWIRE1 AD56601 Figure 47. AD5660-to-68HC11/68L11 Interface AD5660-to-80C51/80L51 Interface CS SYNC SK SCLK Figure 48 shows a serial interface between the AD5660 and the 80C51/80L51 microcontroller. The setup for the interface is as SO DIN 04539-049 follows: TxD of the 80C51/80L51 drives SCLK of the AD5660, 1ADDITIONAL PINS OMITTED FOR CLARITY and RxD drives the serial data line of the part. The SYNC signal Figure 49. AD5660-to-MICROWIRE Interface is again derived from a bit-programmable pin on the port. In this case, Port Line P3.3 is used. When data is to be transmitted to the AD5660, P3.3 is taken low. The 80C51/80L51 transmit Rev. G | Page 20 of 28

Data Sheet AD5620/AD5640/AD5660 APPLICATIONS INFORMATION USING A REF19x AS A POWER SUPPLY FOR THE BIPOLAR OPERATION USING THE AD5660 AD5620/AD5640/AD5660 The AD5660 is designed for single-supply operation, but a Because the supply current required by the AD5620/AD5640/ bipolar output range is also possible using the circuit in AD5660 is extremely low, an alternative option is to use a REF19x Figure 51. Figure 51 gives an output voltage range of ±5 V. voltage reference (REF195 for 5 V or REF193 for 3 V) to supply Rail-to-rail operation at the amplifier output is achievable the required voltage to the part (see Figure 50). This is especially using an AD820 or an OP295 as the output amplifier. useful if the power supply is quite noisy or if the system supply The output voltage for any input code can be calculated as voltages are at some value other than 5 V or 3 V, for example, 15 V. The REF19x outputs a steady supply voltage for the AD5620/   D  R1+R2 R2 AD5640/AD5660. If the low dropout REF195 is used, the current VO =VDD×65536× R1 −VDD×R1 it needs to supply to the AD5660 is 500 µA. This is with no load on the output of the DAC. When the DAC output is loaded, the where D represents the input code in decimal (0 to 65535). REF195 also must supply the current to the load. The total current When V = 5 V, R1 = R2 = 10 kΩ, DD required (with a 5 kΩ load on the DAC output) is 10×D 500 µA + (5 V/5 kΩ) = 1.5 mA V = −5V O 65536 The load regulation of the REF195 is typically 2 ppm/mA, This results in an output voltage range of ±5 V, with 0x0000 which results in an error of 3 ppm (15 µV) for the 1.5 mA corresponding to a −5 V output and 0xFFFF corresponding to a current drawn from it. This corresponds to a 0.197 LSB error +5 V output. for the AD5660. R2 15V 10kΩ 5V REF195 R1 +5V +5V 10kΩ AD820/ ±5V 3-WIRE SYNC VOUT = 0V TO 5V VDD VVOFUBT OP295 SERIAL SCLK AD5660 10µF 0.1µF INTERFACE DIN 04539-050 AD5660 –5V Figure 50. REF195 as the Power Supply to the AD5660 IN3TS-EEWRRIFIRAAELCE 04539-051 Figure 51. Bipolar Operation with the AD5660 Rev. G | Page 21 of 28

AD5620/AD5640/AD5660 Data Sheet ADR02 VLOOP R2 12V TO 36V 18.5kΩ P2 4mA ADJUST SELROIAADL AD5660 4.R7k1Ω 20Pm1A AD8627 Q2N13904 ADJUST 3.R3k6Ω R3 D1 4–20mA 1.5kΩ 100RΩ7 RL 04539-052 Figure 52. Programmable 4 mA to 20 mA Process Controller USING THE AD5660 AS AN ISOLATED, Without this diode, such transients could cause phase reversal PROGRAMMABLE, 4 mA TO 20 mA PROCESS of the AD8627 and possible latch-up of the controller. The loop CONTROLLER supply voltage compliance of the circuit is limited by the maximum applied input voltage to the ADR02 and is from 12 V to 40 V. In many process-control system applications, 2-wire current transmitters are used to transmit analog signals through noisy USING THE AD5620/AD5640/AD5660 WITH A environments. These current transmitters use a zero-scale signal GALVANICALLY ISOLATED INTERFACE current of 4 mA to power the signal conditioning circuitry of For process-control applications in industrial environments, it the transmitter. The full-scale output signal in these transmitters is often necessary to use a galvanically isolated interface to is 20 mA. The converse approach to process control can also be protect and isolate the controlling circuitry from hazardous used, in which a low-power, programmable current source is common-mode voltages that might occur in the area where used to control remotely located sensors or devices in the loop. the DAC is functioning. The iCoupler® provides isolation in A circuit that performs this function is shown in Figure 52. excess of 2.5 kV. The AD5620/AD5640/AD5660 use a 3-wire Using the AD5660 as the controller, the circuit provides a serial logic interface; therefore, the ADuM1300 3-channel programmable output current of 4 to 20 mA, proportional to digital isolator provides the required isolation (see Figure 53). the digital code of the DAC. Biasing for the controller is provided The power supply to the part also must be isolated, which is by the ADR02 and requires no external trim for two reasons: first, done by using a transformer. On the DAC side of the trans- the ADR02’s tight initial output voltage tolerance, and second, former, a 5 V regulator provides the 5 V supply required for the the low supply current consumption of both the AD8627 and AD5620/AD5640/AD5660. the AD5660. The entire circuit, including optocouplers, consumes less than 3 mA from the total budget of 4 mA. The AD8627 5V REGULATOR regulates the output current to satisfy the current summation POWER 10µF 0.1µF at the noninverting node of the AD8627. I = 1/R7 (V × R3/R1 + V × R3/R2) OUT DAC REF VDD For the values shown in Figure 52, SCLK V1A VOA SCLK IOUT = 0.2435 µA × D + 4 mA ADuM1300 AD56x0 where D = 0 ≤ D ≤ 65,535, giving a full-scale output current of 20 mA when the AD5660’s digital code equals 0xFFFF. Offset SDI V1B VOB SYNC VOUT trim at 4 mA is provided by P2, and P1 provides the circuit gain trim at 20 mA. These two trims do not interact because the noninverting input of the AD8627 is at virtual ground. The Schottky diode, D1, is required in this circuit to prevent loop DATA V1C VOC DIN osuf pthpely A pDow86e2r-7o mn otrraen tshieannt 3s 0fr0o mmV p ublellionwg tihtse innovneritnivnegr tininpgu itn. put GND 04539-053 Figure 53. AD5620/AD5640/AD5660 with a Galvanically Isolated Interface Rev. G | Page 22 of 28

Data Sheet AD5620/AD5640/AD5660 POWER SUPPLY BYPASSING AND GROUNDING The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch When accuracy is important in a circuit, it is helpful to carefully effects on the supply line. Clocks and other components with consider the power supply and ground return layout on the fast switching digital signals should be shielded from other board. The printed circuit board containing the AD5620/ parts of the board by digital ground. Avoid crossover of digital AD5640/AD5660 should have separate analog and digital and analog signals if possible. When traces cross on opposite sections, each having its own area of the board. If the AD5620/ sides of the board, ensure that they run at right angles to each AD5640/AD5660 are in a system where other devices require other to reduce feedthrough effects on the board. The best an AGND-to-DGND connection, the connection should be board layout technique is the microstrip technique, where the made at one point only. This ground point should be as close as component side of the board is dedicated to the ground plane possible to the AD5620/AD5640/AD5660. only and the signal traces are placed on the solder side. The power supply to the AD5620/AD5640/AD5660 should be However, this is not always possible with a 2-layer board. bypassed with 10 µF and 0.1 µF capacitors. The capacitors should be as close as physically possible to the device, with the 0.1 µF capacitor ideally right up against the device. The 10 µF capacitors are the tantalum bead type. It is important that the 0.1 µF capacitor has a low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic types of capacitors. This 0.1 µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. Rev. G | Page 23 of 28

AD5620/AD5640/AD5660 Data Sheet OUTLINE DIMENSIONS 3.00 2.90 2.80 1.70 8 7 6 5 3.00 1.60 2.80 1.50 2.60 1 2 3 4 PIN1 INDICATOR 0.65BSC 1.95 BSC 1.30 1.15 0.90 1.45MAX 0.22MAX 0.95MIN 0.08MIN 0.60 0.15MAX 8° 0.45 0.05MIN 0.38MAX SPELAATNIENG 4° B0S.6C0 0.30 0.22MIN 0° COMPLIANTTOJEDECSTANDARDSMO-178-BA 12-16-2008-A Figure 54. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN1 IDENTIFIER 0.65BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L50A.1N0ARICTOYMPLIANT0.T25OJEDECSTA0°NDARDS0M.0O9-187-AA 0.40 10-07-2009-B Figure 55. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. G | Page 24 of 28

Data Sheet AD5620/AD5640/AD5660 3.10 1.95 REF 3.00 SQ 2.90 0.65 BSC 5 8 PIN 1 INDEX AREA 0.50 PIN 1 CORNER C 0.130× 45° 0.40 0.30 4 1 TOP VIEW BOTTOM VIEW 0.80 0.75 0.05 MAX 0.70 0.00 MIN COPLANARITY SEATING 0.35 0.08 PLANE 0.30 0.203 REF 0.C2O5MPLIANTTOJEDEC STANDARDS MO-229-WEEC-2 02-23-2011-A Figure 56. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-15) Dimensions shown in millimeters Rev. G | Page 25 of 28

AD5620/AD5640/AD5660 Data Sheet ORDERING GUIDE Temperature Package Package Power-On Internal Model1 Range Description Option Branding Reset to Code Accuracy Reference AD5620ARJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6V Zero ±6 LSB INL 1.25 V AD5620ARJ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2L Zero ±6 LSB INL 2.5 V AD5620ARJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5D Zero ±6 LSB INL 2.5 V AD5620ARJ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2L Zero ±6 LSB INL 2.5 V AD5620ARJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5D Zero ±6 LSB INL 2.5 V AD5620ARMZ-2 −40°C to +105°C 8-Lead MSOP RM-8 DGY Zero ±6 LSB INL 2.5 V AD5620ARMZ-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DGY Zero ±6 LSB INL 2.5 V AD5620BCPZ-1500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DL9 Zero ±6 LSB INL 1.5 V AD5620BCPZ-1RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DL9 Zero ±6 LSB INL 1.5 V AD5620BCPZ-2500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLC Zero ±6 LSB INL 2.5 V AD5620BCPZ-2RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLC Zero ±6 LSB INL 2.5 V AD5620BRJ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2H Zero ±1 LSB INL 1.25 V AD5620BRJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D87 Zero ±1 LSB INL 1.25 V AD5620BRJ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2H Zero ±1 LSB INL 1.25 V AD5620BRJ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2J Zero ±1 LSB INL 2.5 V AD5620BRJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5C Zero ±1 LSB INL 2.5 V AD5620BRJ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2J Zero ±1 LSB INL 2.5 V AD5620BRJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5C Zero ±1 LSB INL 2.5 V AD5620CRM-1 −40°C to +105°C 8-Lead MSOP RM-8 D2M Zero ±1 LSB INL 1.25 V AD5620CRMZ-1 −40°C to +105°C 8-Lead MSOP RM-8 DGM Zero ±1 LSB INL 1.25 V AD5620CRM-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2M Zero ±1 LSB INL 1.25 V AD5620CRMZ-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DGM Zero ±1 LSB INL 1.25 V AD5620CRM-2 −40°C to +105°C 8-Lead MSOP RM-8 D2N Zero ±1 LSB INL 2.5 V AD5620CRM-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2N Zero ±1 LSB INL 2.5 V AD5620CRMZ-2 −40°C to +105°C 8-Lead MSOP RM-8 D59 Zero ±1 LSB INL 2.5 V AD5620CRMZ-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D59 Zero ±1 LSB INL 2.5 V AD5620CRM-3 −40°C to +105°C 8-Lead MSOP RM-8 D2P Midscale ±1 LSB INL 2.5 V AD5620CRMZ-3 −40°C to +105°C 8-Lead MSOP RM-8 DGN Midscale ±1 LSB INL 2.5 V AD5620CRMZ-3REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DGN Midscale ±1 LSB INL 2.5 V EVAL-AD5620EBZ Evaluation Board AD5640ARJ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2T Zero ±8 LSB INL 2.5 V AD5640ARJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC6 Zero ±8 LSB INL 2.5 V AD5640ARJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC6 Zero ±8 LSB INL 2.5 V AD5640BCPZ-1500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLV Zero ±4 LSB INL 1.25 V AD5640BCPZ-1RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLV Zero ±4 LSB INL 1.25 V AD5640BCPZ-2500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLW Zero ±4 LSB INL 2.5 V AD5640BCPZ-2RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLW Zero ±4 LSB INL 2.5 V AD5640BRJ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2Q Zero ±4 LSB INL 1.25 V AD5640BRJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC3 Zero ±4 LSB INL 1.25 V AD5640BRJ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2Q Zero ±4 LSB INL 1.25 V AD5640BRJZ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC3 Zero ±4 LSB INL 1.25 V AD5640BRJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC0 Zero ±4 LSB INL 2.5 V AD5640BRJ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2R Zero ±4 LSB INL 2.5 V AD5640BRJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC0 Zero ±4 LSB INL 2.5 V AD5640CRM-1 −40°C to +105°C 8-Lead MSOP RM-8 D2U Zero ±4 LSB INL 1.25 V AD5640CRM-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2U Zero ±4 LSB INL 1.25 V AD5640CRMZ-1 −40°C to +105°C 8-Lead MSOP RM-8 DG1 Zero ±4 LSB INL 1.25 V AD5640CRMZ-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DG1 Zero ±4 LSB INL 1.25 V AD5640CRM-2 −40°C to +105°C 8-Lead MSOP RM-8 D2V Zero ±4 LSB INL 2.5 V AD5640CRM-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2V Zero ±4 LSB INL 2.5 V AD5640CRMZ-2 −40°C to +105°C 8-Lead MSOP RM-8 DEW Zero ±4 LSB INL 2.5 V AD5640CRMZ-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DEW Zero ±4 LSB INL 2.5 V Rev. G | Page 26 of 28

Data Sheet AD5620/AD5640/AD5660 Temperature Package Package Power-On Internal Model1 Range Description Option Branding Reset to Code Accuracy Reference AD5660ACPZ-1500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLM Zero ±32 LSB INL 1.25 V AD5660ACPZ-1RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLM Zero ±32 LSB INL 1.25 V AD5660ACPZ-2500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLX Zero ±32 LSB INL 2.5 V AD5660ACPZ-2RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLX Zero ±32 LSB INL 2.5 V AD5660ACPZ-3500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLY Midscale ±32 LSB INL 2.5 V AD5660ACPZ-3RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLY Midscale ±32 LSB INL 2.5 V AD5660ARJ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D30 Zero ±32 LSB INL 1.25 V AD5660ARJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5G Zero ±32 LSB INL 1.25 V AD5660ARJ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D30 Zero ±32 LSB INL 1.25 V AD5660ARJZ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5G Zero ±32 LSB INL 1.25 V AD5660ARJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6K Zero ±32 LSB INL 2.5 V AD5660ARJ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D31 Zero ±32 LSB INL 2.5 V AD5660ARJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6K Zero ±32 LSB INL 2.5 V AD5660ARJ-3500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D32 Midscale ±32 LSB INL 2.5 V AD5660ARJZ-3500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DAV Midscale ±32 LSB INL 2.5 V AD5660ARJ-3REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D32 Midscale ±32 LSB INL 2.5 V AD5660ARJZ-3REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DAV Midscale ±32 LSB INL 2.5 V AD5660BCPZ-1500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLZ Zero ±16 LSB INL 1.25 V AD5660BCPZ-1RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLZ Zero ±16 LSB INL 1.25 V AD5660BCPZ-2500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DM0 Zero ±16 LSB INL 2.5 V AD5660BCPZ-2RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DM0 Zero ±16 LSB INL 2.5 V AD5660BCPZ-3500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DM1 Midscale ±16 LSB INL 2.5 V AD5660BCPZ-3RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DM1 Midscale ±16 LSB INL 2.5 V AD5660BRJ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2X Zero ±16 LSB INL 1.25 V AD5660BRJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6C Zero ±16 LSB INL 1.25 V AD5660BRJ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2X Zero ±16 LSB INL 1.25 V AD5660BRJZ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6C Zero ±16 LSB INL 1.25 V AD5660BRJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6L Zero ±16 LSB INL 2.5 V AD5660BRJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6L Zero ±16 LSB INL 2.5 V AD5660BRJ-3500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2Z Midscale ±16 LSB INL 2.5 V AD5660BRJZ-3500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DAN Midscale ±16 LSB INL 2.5 V AD5660BRJ-3REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2Z Midscale ±16 LSB INL 2.5 V AD5660BRJZ-3REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DAN Midscale ±16 LSB INL 2.5 V AD5660CRM-1 −40°C to +105°C 8-Lead MSOP RM-8 D33 Zero ±16 LSB INL 1.25 V AD5660CRM-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D33 Zero ±16 LSB INL 1.25 V AD5660CRMZ-1 −40°C to +105°C 8-Lead MSOP RM-8 DEX Zero ±16 LSB INL 1.25 V AD5660CRMZ-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DEX Zero ±16 LSB INL 1.25 V AD5660CRM-2 −40°C to +105°C 8-Lead MSOP RM-8 D34 Zero ±16 LSB INL 2.5 V AD5660CRM-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D34 Zero ±16 LSB INL 2.5 V AD5660CRMZ-2 −40°C to +105°C 8-Lead MSOP RM-8 DEY Zero ±16 LSB INL 2.5 V AD5660CRMZ-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DEY Zero ±16 LSB INL 2.5 V AD5660CRM-3 −40°C to +105°C 8-Lead MSOP RM-8 D35 Midscale ±16 LSB INL 2.5 V AD5660CRM-3REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D35 Midscale ±16 LSB INL 2.5 V AD5660CRMZ-3 −40°C to +105°C 8-Lead MSOP RM-8 DBY Midscale ±16 LSB INL 2.5 V AD5660CRMZ-3REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DBY Midscale ±16 LSB INL 2.5 V EVAL-AD5660EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. G | Page 27 of 28

AD5620/AD5640/AD5660 Data Sheet NOTES ©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04539-0-8/13(G) Rev. G | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5620EBZ AD5620CRMZ-2 AD5620CRMZ-3REEL7 AD5660CRMZ-2REEL7 AD5620ARJ-2REEL7 AD5640CRM-2 AD5640ARJZ-2REEL7 AD5660CRM-1REEL7 AD5620BRJ-1500RL7 AD5620ARMZ-2 AD5620CRM- 2REEL7 AD5660ARJ-2REEL7 AD5640BRJ-1500RL7 AD5620BRJ-1REEL7 AD5620CRM-2 AD5660BRJZ-3500RL7 AD5660ARJ-3REEL7 AD5660ARJZ-3500RL7 AD5620CRM-1 AD5660BRJZ-1500RL7 AD5640CRM-1 AD5620BRJZ-2500RL7 AD5620BRJ-2REEL7 AD5660CRM-3 AD5620CRMZ-1REEL7 AD5660ARJZ-2REEL7 AD5620CRMZ-3 AD5640ARJZ-2500RL7 AD5620CRM-1REEL7 AD5640BRJZ-2REEL7 AD5640BRJ-2REEL7 AD5660BRJZ-3REEL7 AD5620BRJZ-1500RL7 AD5640CRMZ-1REEL7 AD5620ARJZ-2REEL7 AD5640CRMZ-2 AD5640BRJZ-1REEL7 AD5640BRJ-1REEL7 AD5640CRMZ-2REEL7 AD5620CRMZ-1 AD5660BRJZ-2500RL7 AD5640BRJZ-2500RL7 AD5660BRJ-1REEL7 AD5660BRJZ-2REEL7 AD5660CRMZ-3REEL7 AD5660CRM-1 AD5660BRJ-1500RL7 AD5640CRM-1REEL7 AD5660ARJ-1REEL7 AD5620ARJZ-2500RL7 AD5660CRMZ-3 AD5660CRM-2 AD5660BRJ-3500RL7 AD5640BRJZ-1500RL7 AD5620ARMZ-2REEL7 AD5660CRM-2REEL7 AD5640ARJ-2500RL7 AD5620CRMZ-2REEL7 AD5620BRJ-2500RL7 AD5620ARJZ-1500RL7 AD5660CRMZ- 1REEL7 AD5660ARJZ-1500RL7 AD5660CRMZ-2 AD5620BRJZ-2REEL7 AD5640CRMZ-1 AD5660ARJ-1500RL7 AD5640CRM-2REEL7 AD5660ARJZ-3REEL7 AD5660ARJZ-1REEL7 AD5660ARJ-3500RL7 AD5660CRMZ-1 AD5620CRM-3 AD5660BRJZ-1REEL7 AD5660ARJZ-2500RL7 AD5620ARJ-2500RL7 AD5660BRJ-3REEL7 AD5620BCPZ-1RL7 AD5620BCPZ-2500RL7 AD5620BCPZ-1500RL7 AD5620BCPZ-2RL7 AD5640BCPZ-2RL7 AD5640BCPZ-1RL7 AD5640BCPZ-1500RL7 AD5640BCPZ-2500RL7