Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/°C On-Chip Reference, I2C Interface Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 FEATURES FUNCTIONAL BLOCK DIAGRAMS Low power, smallest pin-compatible, quad nanoDACs VDD GND VREFIN/VREFOUT AD5625R/AD5645R/AD5665R 12-/14-/16-bit nanoDACs AD5625R/AD5645R/AD5665R 1.25V/2.5V REF On-chip, 2.5 V, 5 ppm/°C reference in TSSOP BUFFER On-chip, 2.5 V, 10 ppm/°C reference in LFCSP ADDR1 REINGPISUTTER REGDIASCTER SDTARCIN AG VOUTA On-chip, 1.25 V, 10 ppm/°C reference in LFCSP BUFFER AD5625/AD5665 ADDR2 E REINGPISUTTER REGDIASCTER SDTARCIN BG VOUTB 3 m1Ex2mt-e /×1r 6n3-a mbl irmte nf, ea1rn0eo-nlDecaAed Co sLn FlyC SP; 14-lead TSSOP; and SCL INTERFACLOGIC REINGPISUTTER REGDIASCTER SDTARCIN CG BUFFER VOUTC 1.665 mm × 2.245 mm, 12-ball WLCSP SDA BUFFER 2.7 V to 5.5 V power supply REINGPISUTTER REGDIASCTER SDTARCIN DG VOUTD Guaranteed monotonic by design POWER-ON RESET POWER-DOWN LOGIC Power-on reset to zero scale/midscale Per channel power-down LDACCLR POR IH2Car-cdowmaprea tLiDbAleC s aenrida lC inLRte frufancceti sounps ports standard (100 kHz), N1 . O TATHDEEDS RF2O, LLLDOAWCI,N CGL RP,I NPSO RA.RE AVAILABLE ONLY ON 14-LEAD PACKAGE: 06341-001 Figure 1. AD5625R/AD5645R/AD5665R fast (400 kHz), and high speed (3.4 MHz) modes APPLICATIONS VDD GND VREFIN Process control AD5625/AD5665 Data acquisition systems BUFFER Portable battery-powered instruments ADDR1 REINGPISUTTER REGDIASCTER SDTARCIN AG VOUTA Digital gain and offset adjustment BUFFER Programmable voltage and current sources ADDR2 E REINGPISUTTER REGDIASCTER SDTARCIN BG VOUTB Programmable attenuators ACC GENERAL DESCRIPTION SCL INTERFLOGI REINGPISUTTER REGDIASCTER SDTARCIN CG BUFFER VOUTC The AD5625R/AD5645R/AD5665R and AD5625/AD5665 members of the nanoDAC® family are low power, quad, 12-/ SDA BUFFER 14-/16-bit, buffered voltage-out DACs with/without an on-chip REINGPISUTTER REGDIASCTER SDTARCIN DG VOUTD reference. All devices operate from a single 2.7 V to 5.5 V supply, POWER-ON RESET POWER-DOWN LOGIC are guaranteed monotonic by design, and have an I2C-compatible serial interface. LDACCLR POR The AD5625R/AD5645R/AD5665R have an on-chip reference. N1 . O TATHDEEDS RF2O, LLLDOAWCI,N CGL RP,I NPSO ARR.E AVAILABLE ONLY ON 14-LEAD PACKAGE: 06341-002 The LFCSP versions of the AD5625R/AD5645R/AD5665R have a Figure 2. AD5625/AD5665 1.25 V or 2.5 V, 10 ppm/°C reference, giving a full-scale output The AD5625R/AD5645R/AD5665R and AD5625/AD5665 use a range of 2.5 V or 5 V; the TSSOP versions of the AD5625R/ 2-wire I2C-compatible serial interface that operates in standard AD5645R/AD5665R have a 2.5 V, 5 ppm/°C reference, giving a (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes. full-scale output range of 5 V. The WLCSP has a 1.25 V reference. Table 1. Related Devices The on-chip reference is off at power-up, allowing the use of an Device Number Description external reference. The internal reference is enabled via a software AD5025/AD5045/AD5065 Dual 12-/14-/16-bit DACs write. The AD5625/AD5665 require an external reference AD5624R/AD5644R/AD5664R, Quad SPI 12-/14-/16-bit DACs, voltage to set the output range of the DAC. AD5624/AD5664 with/without internal reference The device incorporates a power-on reset circuit that ensures AD5627R/AD5647R/AD5667R, Dual I2C 12-/14-/16-bit DACs, AD5627/AD5667 with/without internal reference that the DAC output powers up to 0 V (POR = GND) or midscale AD5666 Quad SPI 16-bit DAC with internal (POR = V ) and remains there until a valid write occurs. The DD reference on-chip precision output amplifier enables rail-to-rail output swing. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2007-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 External Reference ..................................................................... 24 Applications ....................................................................................... 1 Serial Interface ............................................................................ 24 General Description ......................................................................... 1 Write Operation.......................................................................... 24 Functional Block Diagrams ............................................................. 1 Read Operation........................................................................... 24 Revision History ............................................................................... 2 High Speed Mode ....................................................................... 26 Specifications ..................................................................................... 3 Input Shift Register .................................................................... 26 Specifications—AD5625R/AD5645R/AD5665R ..................... 3 Multiple Byte Operation ............................................................ 26 Specifications—AD5625/AD5665 ............................................. 5 Broadcast Mode .......................................................................... 28 AC Characteristics ........................................................................ 7 LDAC Function .......................................................................... 28 I2C Timing Specifications ............................................................ 8 Power-Down Modes .................................................................. 30 Absolute Maximum Ratings .......................................................... 10 Power-On Reset and Software Reset ....................................... 31 ESD Caution ................................................................................ 10 Internal Reference Setup (R Versions) .................................... 31 Pin Configurations and Function Descriptions ......................... 11 Applications Information .............................................................. 32 Typical Performance Characteristics ........................................... 13 Using a Reference as a Power Supply for the Terminology .................................................................................... 21 AD5625R/AD5645R/AD5665R and AD5625/ AD5665 ....... 32 Theory of Operation ...................................................................... 23 Bipolar Operation Using the AD5625R/ AD5645R/AD5665R and AD5625/AD5665 ................................................................ 32 Digital-to-Analog Converter (DAC) ....................................... 23 Power Supply Bypassing and Grounding ................................ 32 Resistor String ............................................................................. 23 Outline Dimensions ....................................................................... 33 Output Amplifier ........................................................................ 23 Ordering Guide .......................................................................... 34 Internal Reference ...................................................................... 23 REVISION HISTORY 10/2018—Rev. E to Rev. F Changes to Serial Interface Section and Table 9 Title ............... 24 Changes to Serial Interface Section .............................................. 24 Changes to Figure 58 and Figure 60 Captions ............................ 25 Moved Ordering Guide Section.................................................... 34 Updated Outline Dimensions ....................................................... 33 Changes to Ordering Guide .......................................................... 35 1/2018—Rev. D to Rev. E Change to Figure 6 ......................................................................... 11 12/2009—Rev. A to Rev. B Added Figure 55; Renumbered Sequentially .............................. 20 Changes to Features Section, General Description Section, Change to Terminology Section ................................................... 21 and Table 1 ..........................................................................................1 Updated Outline Dimensions ....................................................... 33 Changes to Table 2 ............................................................................. 3 Changes to Ordering Guide .......................................................... 35 Changes to Internal Reference Section ........................................ 22 Updated Outline Dimensions ....................................................... 32 11/2015—Rev. C to Rev. D Changes to Ordering Guide .......................................................... 33 Changes to Read Operation Section ............................................ 24 6/2009—Rev. 0 to Rev. A 3/2013—Rev. B to Rev. C Changes to Features and General Description Sections .............. 1 Added 12-Ball WLCSP ...................................................... Universal Changes to Table 2 ............................................................................. 3 Change to Features and General Description Sections ............... 1 Changes to Table 3 ............................................................................. 5 Changes to Reference Output (1.25 V), Reference TC Changes to Digital-to-Analog Converter (DAC) Section, Added Parameter, Table 2 ............................................................................. 4 Figure 54 and Figure 55, Renumbered Subsequent Figures ..... 22 Added θ Thermal Impedance, WLCSP Parameter, Table 6 ... 10 Changes to Ordering Guide .......................................................... 33 JA Added Figure 8; Renumbered Sequentially ................................ 12 Added Table 8; Renumbered Sequentially .................................. 12 3/2007—Revision 0: Initial Version Changes to Internal Reference Section ........................................ 23 Rev. F | Page 2 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 SPECIFICATIONS SPECIFICATIONS—AD5625R/AD5645R/AD5665R V = 2.7 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; V = V ; all specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 2. A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments1 STATIC PERFORMANCE2 AD5665R Resolution 16 Bits Relative Accuracy ±8 ±16 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic by design AD5645R Resolution 14 Bits Relative Accuracy ±2 ±4 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design AD5625R Resolution 12 12 Bits Relative Accuracy ±1 ±4 ±0.5 ±1 LSB Differential Nonlinearity ±1 ±0.25 LSB Guaranteed monotonic by design Zero-Code Error 2 10 2 10 mV All 0s loaded to DAC register Offset Error ±1 ±10 ±1 ±10 mV Full-Scale Error −0.1 ±0.5 −0.1 ±0.5 % FSR All 1s loaded to DAC register Gain Error ±0.1 ±1.25 ±0.1 ±1 % FSR Zero-Code Error Drift ±2 ±2 µV/°C Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C DC Power Supply Rejection −100 −100 dB DAC code = midscale; Ratio V = 5 V ± 10% DD DC Crosstalk (External 15 15 µV Due to full-scale output change, Reference) R = 2 kΩ to GND or V L DD 10 10 µV/mA Due to load current change 8 8 µV Due to powering down (per channel) DC Crosstalk (Internal 25 25 µV Due to full-scale output change, Reference) R = 2 kΩ to GND or V L DD 20 20 µV/mA Due to load current change 10 10 µV Due to powering down (per channel) OUTPUT CHARACTERISTICS3 Output Voltage Range 0 V 0 V V Internal reference disabled DD DD 0 2 × V 2 × V Internal reference enabled REF REF Capacitive Load Stability 2 2 nF R = ∞ L 10 10 nF R = 2 kΩ L DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA V = 5 V DD Power-Up Time 4 4 µs Coming out of power-down mode; V = 5 V DD REFERENCE INPUTS Reference Current 210 260 210 260 µA V = V = 5.5 V REF DD Reference Input Range 0.75 V 0.75 V V DD DD Reference Input Impedance 26 26 kΩ Rev. F | Page 3 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments1 REFERENCE OUTPUT (1.25 V) Output Voltage 1.247 1.253 1.247 1.253 V At ambient Reference TC3 ±10 ±10 ppm/°C TSSOP and LFCSP ±15 ppm/°C WLCSP Output Impedance 7.5 7.5 kΩ REFERENCE OUTPUT (2.5 V) V = 4.5 V to 5.5 V DD Output Voltage 2.495 2.505 2.495 2.505 V At ambient Reference TC3 ±10 ±5 ±10 ppm/°C Output Impedance 7.5 7.5 kΩ LOGIC INPUTS (ADDRx, CLR, LDAC, POR)3 I , Input Current ±1 ±1 µA IN V , Input Low Voltage 0.15 × 0.15 × V INL V V DD DD V , Input High Voltage 0.85 × 0.85 × V INH V V DD DD C , Pin Capacitance 2 2 pF IN V , Input Hysteresis 0.1 × 0.1 × V HYST V V DD DD LOGIC INPUTS (SDA, SCL)3 I , Input Current ±1 ±1 µA IN V , Input Low Voltage 0.3 × 0.3 × V INL V V DD DD V , Input High Voltage 0.7 × 0.7 × V INH V V DD DD C , Pin Capacitance 2 2 pF IN V , Input Hysteresis 0.1 × 0.1 × V High speed mode HYST V V DD DD 0.05 × 0.05 × V Fast mode V V DD DD LOGIC OUTPUTS (SDA)3 V , Output Low Voltage 0.4 0.4 V I = 3 mA OL SINK 0.6 0.6 V I = 6 mA SINK Floating-State Leakage ±1 ±1 µA Current Floating-State Output 2 2 pF Capacitance POWER REQUIREMENTS V 2.7 5.5 2.7 5.5 V DD I (Normal Mode)4 V = V , V = GND, full-scale DD IH DD IL loaded V = 4.5 V to 5.5 V 1.0 1.16 1.0 1.16 mA Internal reference off DD V = 2.7 V to 3.6 V 0.9 1.05 0.9 1.05 mA Internal reference off DD V = 4.5 V to 5.5 V 1.9 2.14 1.9 2.14 mA Internal reference on DD V = 2.7 V to 3.6 V 1.4 1.59 1.4 1.59 mA Internal reference on DD I (All Power-Down Modes)5 DD V = 2.7 V to 5.5 V 0.48 1 0.48 1 µA V = V , V = GND (LFCSP) DD IH DD IL V = 3.6 V to 5.5 V 0.48 1 0.48 1 µA V = V , V = GND (TSSOP) DD IH DD IL 1 Temperature range of A and B grades is −40°C to +105°C. 2 Linearity calculated using a reduced code range: AD5665R (Code 512 to Code 65,024), AD5645R (Code 128 to Code 16,256), AD5625R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All DACs powered down. Power-down function is not available on 14-lead TSSOP devices when the device is powered with VDD < 3.6 V. Rev. F | Page 4 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 SPECIFICATIONS—AD5625/AD5665 V = 2.7 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; V = V ; all specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 3. B Grade Parameter Min Typ Max Unit Test Conditions/Comments1 STATIC PERFORMANCE2 AD5665 Resolution 16 Bits Relative Accuracy ±8 ±16 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic by design AD5625 Resolution 12 Bits Relative Accuracy ±0.5 ±1 LSB Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design Zero-Code Error 2 10 mV All 0s loaded to DAC register Offset Error ±1 ±10 mV Full-Scale Error −0.1 ±0.5 % FSR All 1s loaded to DAC register Gain Error ±0.1 ±1 % FSR Zero-Code Error Drift ±2 µV/°C Gain Temperature Coefficient ±2.5 ppm Of FSR/°C DC Power Supply Rejection Ratio −100 dB DAC code = midscale; V = 5 V ± 10% DD DC Crosstalk (External Reference) 15 µV Due to full-scale output change, R = 2 kΩ to GND or V L DD 10 µV/mA Due to load current change 8 µV Due to powering down (per channel) DC Crosstalk (Internal Reference) 25 µV Due to full-scale output change, R = 2 kΩ to GND or V L DD 20 µV/mA Due to load current change 10 µV Due to powering down (per channel) OUTPUT CHARACTERISTICS3 Output Voltage Range 0 V V DD Capacitive Load Stability 2 nF R = ∞ L 10 nF R = 2 kΩ L DC Output Impedance 0.5 Ω Short-Circuit Current 30 mA V = 5 V DD Power-Up Time 4 µs Coming out of power-down mode; V = 5 V DD REFERENCE INPUTS Reference Current 210 260 µA V = V = 5.5 V REF DD Reference Input Range 0.75 V V DD Reference Input Impedance 26 kΩ LOGIC INPUTS (ADDRx, CLR, LDAC, POR)3 I , Input Current ±1 µA IN V , Input Low Voltage 0.15 × V V INL DD V , Input High Voltage 0.85 × V V INH DD C , Pin Capacitance 2 pF IN V , Input Hysteresis 0.1 × V V HYST DD LOGIC INPUTS (SDA, SCL)3 I , Input Current ±1 µA IN V , Input Low Voltage 0.3 × V V INL DD V , Input High Voltage 0.7 × V V INH DD C , Pin Capacitance 2 pF IN V , Input Hysteresis 0.1 × V V High speed mode HYST DD 0.05 × V V Fast mode DD Rev. F | Page 5 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet B Grade Parameter Min Typ Max Unit Test Conditions/Comments1 LOGIC OUTPUTS (SDA)3 V , Output Low Voltage 0.4 V I = 3 mA OL SINK 0.6 V I = 6 mA SINK Floating-State Leakage Current ±1 µA Floating-State Output Capacitance 2 pF POWER REQUIREMENTS V 2.7 5.5 V DD I (Normal Mode)4 V = V , V = GND, full-scale loaded DD IH DD IL V = 4.5 V to 5.5 V 1.0 1.16 mA DD V = 2.7 V to 3.6 V 0.9 1.05 mA DD I (All Power-Down Modes)5 DD V = 2.7 V to 5.5 V 0.48 1 µA V = V , V = GND (LFCSP) DD IH DD IL V = 3.6 V to 5.5 V 0.48 1 µA V = V , V = GND (TSSOP) DD IH DD IL 1 Temperature range of B grade is −40°C to +105°C. 2 Linearity calculated using a reduced code range: AD5665 (Code 512 to Code 65,024), AD5625 (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All DACs powered down. Power-down function is not available on 14-lead TSSOP devices when the device is powered with VDD < 3.6 V. Rev. F | Page 6 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 AC CHARACTERISTICS V = 2.7 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; V = V ; all specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 4. Parameter1, 2 Min Typ Max Unit Test Conditions/Comments3 Output Voltage Settling Time AD5625R/AD5625 3 4.5 µs ¼ to ¾ scale settling to ±0.5 LSB AD5645R 3.5 5 µs ¼ to ¾ scale settling to ±0.5 LSB AD5665R/AD5665 4 7 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 1.8 V/µs Digital-to-Analog Glitch Impulse 1 LSB change around major carry 15 nV-s LFCSP 5 nV-s TSSOP Digital Feedthrough 0.1 nV-s Reference Feedthrough −90 dB V = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz REF Digital Crosstalk 0.1 nV-s Analog Crosstalk 1 nV-s External reference 4 nV-s Internal reference DAC-to-DAC Crosstalk 1 nV-s External reference 4 nV-s Internal reference Multiplying Bandwidth 340 kHz V = 2 V ± 0.1 V p-p REF Total Harmonic Distortion −80 dB V = 2 V ± 0.1 V p-p, frequency = 10 kHz REF Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz 100 nV/√Hz DAC code = midscale, 10 kHz Output Noise 15 µV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical at 25°C. Rev. F | Page 7 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet I2C TIMING SPECIFICATIONS V = 2.7 V to 5.5 V; all specifications T to T , f = 3.4 MHz, unless otherwise noted (see Figure 3; high speed mode timing DD MIN MAX SCL specification applies only to the AD5625RBRUZ-2/AD5625RBRUZ-2REEL7 and AD5665RBRUZ-2/AD5665RBRUZ-2REEL7). Table 5. Parameter Test Conditions1 Min Max Unit Description f 2 Standard mode 100 kHz Serial clock frequency SCL Fast mode 400 kHz High speed mode, C = 100 pF 3.4 MHz B High speed mode, C = 400 pF 1.7 MHz B t Standard mode 4 μs t , SCL high time 1 HIGH Fast mode 0.6 μs High speed mode, C = 100 pF 60 ns B High speed mode, C = 400 pF 120 ns B t Standard mode 4.7 μs t , SCL low time 2 LOW Fast mode 1.3 μs High speed mode, C = 100 pF 160 ns B High speed mode, C = 400 pF 320 ns B t Standard mode 250 ns t , data setup time 3 SU;DAT Fast mode 100 ns High speed mode 10 ns t Standard mode 0 3.45 μs t , data hold time 4 HD;DAT Fast mode 0 0.9 μs High speed mode, C = 100 pF 0 70 ns B High speed mode, C = 400 pF 0 150 ns B t Standard mode 4.7 μs t , setup time for a repeated start condition 5 SU;STA Fast mode 0.6 μs High speed mode 160 ns t Standard mode 4 μs t , hold time (repeated) start condition 6 HD;STA Fast mode 0.6 μs High speed mode 160 ns t Standard mode 4.7 μs t , bus-free time between a stop and a start 7 BUF condition Fast mode 1.3 μs t Standard mode 4 μs t , setup time for a stop condition 8 SU;STO Fast mode 0.6 μs High speed mode 160 ns t Standard mode 1000 ns t , rise time of SDA signal 9 RDA Fast mode 300 ns High speed mode, C = 100 pF 10 80 ns B High speed mode, C = 400 pF 20 160 ns B t Standard mode 300 ns t , fall time of SDA signal 10 FDA Fast mode 300 ns High speed mode, C = 100 pF 10 80 ns B High speed mode, C = 400 pF 20 160 ns B t Standard mode 1000 ns t , rise time of SCL signal 11 RCL Fast mode 300 ns High speed mode, C = 100 pF 10 40 ns B High speed mode, C = 400 pF 20 80 ns B t Standard mode 1000 ns t , rise time of SCL signal after a repeated start 11A RCL1 condition and after an acknowledge bit Fast mode 300 ns High speed mode, C = 100 pF 10 80 ns B High speed mode, C = 400 pF 20 160 ns B Rev. F | Page 8 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 Parameter Test Conditions1 Min Max Unit Description t Standard mode 300 ns t , fall time of SCL signal 12 FCL Fast mode 300 ns High speed mode, C = 100 pF 10 40 ns B High speed mode, C = 400 pF 20 80 ns B t Standard mode 10 ns LDAC pulse width low 13 Fast mode 10 ns High speed mode 10 ns t Standard mode 300 ns Falling edge of ninth SCL clock pulse of last byte 14 of a valid write to LDAC falling edge Fast mode 300 ns High speed mode 30 ns t Standard mode 20 ns CLR pulse width low 15 Fast mode 20 ns High speed mode 20 ns t 3 Fast mode 0 50 ns Pulse width of spike suppressed SP High speed mode 0 10 ns 1 CB refers to the capacitance on the bus line. 2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC behavior of the device. 3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode. t11 t12 t6 t 2 SCL t6 t1 t5 t8 t4 t3 t10 t9 SDA t 7 P S S t P 14 t LDAC* 13 t CLR *ASYNCHRONOUS LDAC UPDATE MODE. 15 06341-003 Figure 3. 2-Wire Serial Interface Timing Diagram Rev. F | Page 9 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 6. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Operation beyond V to GND −0.3 V to V + 0.3 V OUT DD the maximum operating conditions for extended periods may V /V to GND −0.3 V to V + 0.3 V REFIN REFOUT DD affect product reliability. Digital Input Voltage to GND −0.3 V to V + 0.3 V DD Operating Temperature Range, Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C ESD CAUTION Junction Temperature (T maximum) 150°C J Power Dissipation (T max − T )/θ J A JA θ Thermal Impedance JA LFCSP (4-Layer Board) 61°C/W TSSOP 150.4°C/W WLCSP 75°C/W Reflow Soldering Peak Temperature, 260°C ± 5°C RoHS Compliant Rev. F | Page 10 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS LDAC 1 14 SCL ADDR1 2 13 SDA VOUTA 1 10 VREFIN/VREFOUT VDD 3 AADD55662455RR// 12 GND VOUTB 2 AADD55662455RR// 9 VDD VOUTA 4 AD5665R 11 VOUTB GND 3 AD5665R 8 SDA VREFIN/VRVEOFPUOOTUCRT 675 (NToOt Pto V SIEcaWle) 1890 VCAODLRUDTRD2 06341-120 VVOOUUTTCDE45XPOSE(DNToPOtA PtDo V STIEIcEWaDle)TO GN76D.SACDLDR 06341-122 Figure 4. Pin Configuration (14-Lead TSSOP), R Suffix Version Figure 6. Pin Configuration (10-Lead LFCSP), R Suffix Version LDAC 1 14 SCL VOUTA 1 10 VREFIN ADDR1 2 13 SDA AD5625/ VDD 3 AADD55662655/ 12 GND VOGUNTDB 23 AD5665 98 VSDDDA VVVROOPEUUOFTTIACRN 4567 (NToOt Pto V SIEcaWle) 119810 VVCAOOLDRUUDTTRBD2 06341-121 VVOOUUTTCDEXP45OSE(NDTo OPt APto DV S ITEcIaWElDe) TO 76GNSADCD.LDR 06341-123 Figure 5. Pin Configuration (14-Lead TSSOP) Figure 7. Pin Configuration (10-Lead LFCSP) Table 7. Pin Function Descriptions Pin Number 14-Lead 10-Lead Mnemonic Description 1 N/A1 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. 2 N/A1 ADDR1 Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 10). 3 9 V Power Supply Input. These devices can be operated from 2.7 V to 5.5 V, and the supply should be DD decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 4 1 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 5 4 V C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT 6 N/A1 POR Power-On Reset Pin. Tying the POR pin to GND powers up the device to 0 V. Tying the POR pin to V DD powers up the device to midscale. 7 10 V /V The AD5625R/AD5645R/AD5665R have a common pin for reference input and reference output. When using REFIN REFOUT the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. (The internal reference and reference output are only available on R suffix versions.) The AD5625/AD5665 have a reference input pin only. 8 N/A1 ADDR2 Three-State Address Input. Sets Bit A3 and Bit A2 of the 7-bit slave address (see Table 10). 9 N/A1 CLR Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The device exits clear code mode on the falling edge of the ninth clock pulse of the last byte of the valid write. If CLR is activated during a write sequence, the write is aborted. If CLR is activated during high speed mode, the device exits high speed mode. 10 5 V D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT 11 2 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 12 3 GND Ground Reference Point for All Circuitry on the Device. 13 8 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull- up resistor. 14 7 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input register. N/A1 6 ADDR Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 9). EPAD For the 10-lead LFCSP, the exposed pad must be tied to GND. 1 N/A means not applicable. Rev. F | Page 11 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet BALLA1 INDICATOR 1 2 3 VVRREEFFOIUNT/ GND VOUTA A VDD GND VOUTB B SDA GND VOUTC C SCL ADDRVOUTD D (BALNTLoO tS PtIoD V ESIE cDWaOleWN) 06341-108 Figure 8. Pin Configuration (12-Ball WLCSP) Table 8. Pin Function Descriptions Pin No. Mnemonic Description A1 V /V The AD5665R has a common pin for reference input and reference output. When using the internal reference, REFIN REFOUT this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. A2, B2, C2 GND Ground Reference Point for All Circuitry on the Device. A3 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT B1 V Power Supply Input. The AD5665R can be operated from 2.7 V to 5.5 V, and the supply should be decoupled DD with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. B3 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT C1 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. C3 V C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT D1 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input register. D2 ADDR Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 9). D3 V D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT Rev. F | Page 12 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 TYPICAL PERFORMANCE CHARACTERISTICS 10 1.0 8 TVAD D= =2 5V°RCEF = 5V 0.8 TVAD D= =2 5V°RCEF = 5V 6 0.6 4 0.4 B) B) R (LS 2 R (LS 0.2 RO 0 RO 0 R R NL E –2 NL E –0.2 I –4 D –0.4 –6 –0.6 –8 –0.8 –100 5k 10k 15k 20k 25k 30CkOD3E5k 40k 45k 50k 55k 60k 65k 06341-005 –1.00 10k 20k 30CkODE 40k 50k 60k 06341-007 Figure 9. INL, AD5665, External Reference Figure 12. DNL, AD5665, External Reference 4 0.5 3 TVAD D= =2 5V°RCEF = 5V 0.4 TVAD D= =2 5V°RCEF = 5V 0.3 2 0.2 R (LSB) 1 R (LSB) 0.1 RO 0 RO 0 R R NL E –1 NL E –0.1 I D –0.2 –2 –0.3 –3 –0.4 –40 2500 5000 75C0O0DE 10000 12500 15000 06341-006 –0.50 2500 5000 75C0O0DE 10000 12500 15000 06341-008 Figure 10. INL, AD5645R, External Reference Figure 13. DNL, AD5645R, External Reference 1.0 0.20 VDD = VREF = 5V VDD = VREF = 5V 0.8 TA = 25°C 0.15 TA = 25°C 0.6 0.10 0.4 R (LSB) 0.2 R (LSB) 0.05 O 0 O 0 R R R R NL E –0.2 NL E –0.05 I –0.4 D –0.10 –0.6 –0.15 –0.8 –1.00 500 1000 1500 2C0O0D0E 2500 3000 3500 4000 06341-100 –0.200 500 1000 1500 2C0O00DE 2500 3000 3500 4000 06341-009 Figure 11. INL, AD5625, External Reference Figure 14. DNL, AD5625, External Reference Rev. F | Page 13 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet 10 1.0 VDD = 5V VDD=5V 8 VREFOUT = 2.5V 0.8 VREFOUT=2.5V TA = 25°C TA=25°C 6 0.6 B) 4 SB) 0.4 R (LS 2 OR (L 0.2 RO 0 RR 0 NL ER –2 DNL E –0.2 I –0.4 –4 –0.6 –6 –0.8 –8 –1.0 –10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5000 10000 15000 20000 25000 30000COD35000E 40000 45000 50000 55000 60000 65000 06341-010 500 1000 1500 2000 2500 3000COD3500E 4000 4500 5000 5500 6000 6500 06341-013 Figure 15. INL, AD5665R, 2.5 V Internal Reference Figure 18. DNL, AD5665R, 2.5 V Internal Reference 4 0.5 VDD=5V VDD = 5V 3 VREFOUT=2.5V 0.4 VREFOUT = 2.5V TA=25°C TA = 25°C 0.3 2 0.2 B) B) R (LS 1 R (LS 0.1 RO 0 RO 0 R R NL E –1 NL E –0.1 I D –0.2 –2 –0.3 –3 –0.4 –4 –0.5 0 1250 2500 3750 5000 6250 7500COD8750E 10000 11250 12500 13750 15000 16250 06341-011 0 1250 2500 3750 5000 6250 7500COD8750E 10000 11250 12500 13750 15000 16250 06341-014 Figure 16. INL, AD5645R, 2.5 V Internal Reference Figure 19. DNL, AD5645R, 2.5 V Internal Reference 1.0 0.20 VDD=5V VDD = 5V 0.8 VTARE=FO25U°TC=2.5V 0.15 VTAR E=F O2U5T°C = 2.5V 0.6 0.10 0.4 B) B) R (LS 0.2 R (LS 0.05 RO 0 RO 0 R R E E NL –0.2 NL –0.05 I D –0.4 –0.10 –0.6 –0.15 –0.8 –1.00 500 1000 1500 2C0O0D0E 2500 3000 3500 4000 06341-012 –0.200 500 1000 1500 2C0O0D0E 2500 3000 3500 4000 06341-015 Figure 17. INL, AD5625R, 2.5 V Internal Reference Figure 20. DNL, AD5625R, 2.5 V Internal Reference Rev. F | Page 14 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 10 1.0 VDD = 3V VDD = 3V 8 VREFOUT = 1.25V 0.8 VREFOUT = 1.25V TA = 25°C TA = 25°C 6 0.6 4 0.4 B) B) R (LS 2 R (LS 0.2 RO 0 RO 0 R R NL E –2 NL E –0.2 I D –4 –0.4 –6 –0.6 –8 –0.8 –10 –1.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 50 100 150 200 250 300COD350E 400 450 500 550 600 650 06341-016 50 100 150 200 250 300CODE350 400 450 500 550 600 650 06341-019 Figure 21. INL, AD5665R,1.25 V Internal Reference Figure 24. DNL, AD5665R,1.25 V Internal Reference 4 0.5 VDD = 3V VDD = 3V 3 VREFOUT = 1.25V 0.4 VREFOUT = 1.25V TA = 25°C TA = 25°C 0.3 2 0.2 B) B) R (LS 1 R (LS 0.1 RO 0 RO 0 R R NL E –1 NL E –0.1 I D –0.2 –2 –0.3 –3 –0.4 –4 –0.5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 0 5 0 5 0 5 0 5 0 5 0 5 12 25 37 50 62 C75ODE87 100 112 125 137 150 162 06341-017 12 25 37 50 62 C75ODE87 100 112 125 137 150 162 06341-020 Figure 22. INL, AD5645R, 1.25 V Internal Reference Figure 25. DNL, AD5645R,1.25 V Internal Reference 1.0 0.20 VDD = 3V VDD = 3V 0.8 VREFOUT = 1.25V 0.15 VREFOUT = 1.25V TA = 25°C TA = 25°C 0.6 0.10 0.4 B) B) R (LS 0.2 R (LS 0.05 RO 0 RO 0 R R NL E –0.2 NL E–0.05 I D –0.4 –0.10 –0.6 –0.15 –0.8 –1.00 500 1000 1500 2C0O0D0E 2500 3000 3500 4000 06341-018 –0.200 500 1000 1500 2C0O0D0E 2500 3000 3500 4000 06341-021 Figure 23. INL, AD5625R,1.25 V Internal Reference Figure 26. DNL, AD5625R, 1.25 V Internal Reference Rev. F | Page 15 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet 8 0 VDD = 5V –0.02 6 MAX INL VDD = VREF = 5V –0.04 4 GAIN ERROR –0.06 B) 2 SR) –0.08 OR (LS 0 MAX DNL R (% F –0.10 ERR –2 MIN DNL RRO –0.12 E –0.14 FULL-SCALE ERROR –4 MIN INL –0.16 –6 –0.18 –8–40 –20 0 TEM20PERATU4R0E (°C)60 80 100 06341-022 –0.20–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 06341-025 Figure 27. INL Error and DNL Error vs. Temperature Figure 30. Gain Error and Full-Scale Error vs. Temperature 1.5 10 8 MAX INL 1.0 ZERO-SCALE ERROR 6 0.5 VDD = 5V 4 TA = 25°C R (LSB) 20 MAX DNL OR (mV) –0.50 O R RR –2 MIN DNL ER –1.0 E –4 –1.5 OFFSET ERROR –6 MIN INL –2.0 –8 –100.75 1.25 1.75 2.25 V2.R7E5F (V3).25 3.75 4.25 4.75 06341-023 –2.5–40 –20 0 TEM2P0ERATU4R0E (°C)60 80 100 06341-026 Figure 28. INL Error and DNL Error vs. VREF Figure 31. Zero-Scale Error and Offset Error vs. Temperature 8 1.0 6 MAX INL TA = 25°C 0.5 4 GAIN ERROR B) 2 SR) 0 OR (LS 0 MAX DNL R (% F –0.5 FULL-SCALE ERROR RR MIN DNL RO E –2 R E –1.0 –4 MIN INL –1.5 –6 –8 –2.0 2.7 3.2 3.7 VDD 4(V.2) 4.7 5.2 06341-024 2.7 3.2 3.7 VDD 4(V.2) 4.7 5.2 06341-027 Figure 29. INL Error and DNL Error vs. Supply Figure 32. Gain Error and Full-Scale Error vs. Supply Rev. F | Page 16 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 1.0 2.0 TA = 25°C TA = 25°C 1.8 VDD = 5.5V 0.5 ZERO-SCALE ERROR 1.6 VREFOUT = 2.5V 0 1.4 V) 1.2 ERROR (m ––10..05 I (mA)DD 10..08 VREFIN = 5V –1.5 0.6 0.4 –2.0 OFFSET ERROR 0.2 –2.52.7 3.2 3.7 VDD 4(V.2) 4.7 5.2 06341-028 0512 10512 20512 305C1O2DE 40512 50512 60512 06341-060 Figure 33. Zero-Scale Error and Offset Error vs. Supply Figure 36. Supply Current vs. DAC Code 30 1.2 VDD= 3.6V VDD= 5.5V 25 1.0 S CE 20 0.8 VI E D A) BER OF 15 I (mDD 0.6 M U 10 0.4 N 5 0.2 TA = 25°C 0 0.880.890.900.910.920.930.940.950.96I0.97DD0.98 (m0.99A)1.001.011.021.031.041.051.061.071.08 06341-029 02.7 3.2 3.7 VDD 4(V.2) 4.7 5.2 06341-061 Figure 34. IDD Histogram with External Reference Figure 37. Supply Current vs. Supply 25 1.2 VDD= 3.6V VDD= 5.5V VDD = VREF = 5V 1.0 20 S CE 0.8 VDD = VREF = 3V DEVI 15 A) R OF VREFOUT = 1.25V VREFOUT = 2.5V (mDD 0.6 BE 10 I UM 0.4 N 5 0.2 0 1.351.371.391.411.431.451.471.491.511.531.551.571.591.611.63ID1.65D 1.67(m1.69A1.71)1.731.751.771.791.811.831.851.871.891.911.931.951.971.99 06341-030 0–40 –20 0 TEM20PERATU4R0E (°C)60 80 100 06341-063 Figure 35. IDD Histogram with Internal Reference Figure 38. Supply Current vs. Temperature Rev. F | Page 17 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet 0.5 DAC LOADED WITH DAC LOADED WITH 0.4 FULL-SCALE ZERO-SCALE SOURCING CURRENT SINKING CURRENT 0.3 V) 0.2 VDD = VREF = 5V GE ( 0.1 VDD= 3V TFAU L=L 2-5S°CCALE CODE CHANGE TA VREFOUT = 1.25V 0x0000 TO 0xFFFF OL 0 OUTPUT LOADED WITH 2kΩ R V AND 200pF TO GND O –0.1 R R E –0.2 VOUT= 909mV/DIV –0.3 VVDRDEF=O U5VT = 2.5V 1 –0.4 –0.5–10 –8 –6 –4 C–2URRE0NT (mA2) 4 6 8 10 06341-031 TIME BASE = 4µs/DIV 06341-048 Figure 39. Headroom at Rails vs. Source and Sink Figure 42. Full-Scale Settling Time, 5 V 6 5 VVTADR ED=F =O2 5U5°VTC = 2.5V FULL SCALE VTAD D= =2 5V°RCEF = 5V 4 3/4 SCALE V) 3 MIDSCALE (UT VO 2 VDD 1/4 SCALE 1 1 MAX(C2) 420.0mV 0 ZERO SCALE 2 VOUT –1–30 –20 –10 CURRE0NT (mA) 10 20 30 06341-046 CH1 2.0V CH2 500mV MA 1C0H01µ s 1 215.M28SV/s 8.0ns/pt 06341-049 Figure 40. AD5625R/AD5645R/AD5665R with 2.5 V Reference, Source and Figure 43. Power-On Reset to 0 V Sink Capability 4 VDD= 3V SYNC VREFOUT = 1.25V 3 TA = 25°C 1 FULL SCALE SLCK 3 3/4 SCALE 2 V) (UT MIDSCALE O V 1 1/4 SCALE VOUT 0 ZERO SCALE VDD = 5V 2 –1–30 –20 –10 CURRE0NT (mA) 10 20 30 06341-047 CCHH13 55..00VV CH2 500mV M400ns A CH1 1.4V 06341-050 Figure 41. AD5625R/AD5645R/AD5665R with 1.25 V Reference, Source and Figure 44. Exiting Power-Down to Midscale Sink Capability Rev. F | Page 18 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 2.538 222...555333567 TV5GnADLs DI=T/S =C2A 5VHM°R CIPEMFLP E=U N5LVSUEM B= E9R.494nV DVTADA DC= =2L 5OV°RACEDFE =D 5 WVITH MIDSCALE 2.534 1LSB CHANGE AROUND 2.533 MIDSCALE (0x8000 TO 0x7FFF) 2.532 V (V)OUT2222....555522338901 2µV/DIV1 2.527 2.526 2.525 2.524 2.523 22..5522120 50 100 150 S2A00MPL2E5 0NUM30B0ER350 400 450 512 06341-058 4s/DIV 06341-051 Figure 45. Digital-to-Analog Glitch Impulse (Negative) Figure 48. 0.1 Hz to 10 Hz Output Noise Plot, External Reference 2.498 VDD= VREF = 5V VDD = 5V TA = 25°C VREFOUT = 2.5V 2.497 5ns/SAMPLE NUMBER TA = 25°C ANALOG CROSSTALK = 0.424nV DAC LOADED WITH MIDSCALE 2.496 V (V)OUT22..449945 10µV/DIV1 2.493 2.492 2.4910 50 100 150 S2A0M0PLE25 N0UM3B0E0R 350 400 450 512 06341-059 5s/DIV 06341-052 Figure 46. Analog Crosstalk, External Reference Figure 49. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference 2.496 2.494 VDD = 3V 2.492 VREFOUT = 1.25V 2.490 TA = 25°C 2.488 DAC LOADED WITH MIDSCALE 2.486 2.484 2.482 2.480 V (V)OUT222...444777468 5µV/DIV1 2.472 2.470 2.468 2.466 VDD= 5V 2.464 VREFOUT = 2.5V 2.462 TA = 25°C 2.460 5ns/SAMPLE NUMBER 22..4455680 50 100 150 S2A00MPLA2E5N 0NAULMO30GB0E CRR3O5S0STA40L0K = 445.4062nV512 06341-062 4s/DIV 06341-053 Figure 47. Analog Crosstalk, Internal Reference Figure 50. 0.1 Hz to 10 Hz Output Noise Plot, 1.25 V Internal Reference Rev. F | Page 19 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet 800 5 700 TMAID =S 2C5A°CLE LOADED 0 VTAD D= =2 55°VC –5 Hz) 600 E (nV/√ 500 H (dB) ––1150 UTPUT NOIS 340000 VDD= 5V BANDWIDT ––2250 O 200 VREFOUT = 2.5V –30 100 VDD= 3V –35 VREFOUT = 1.25V 0100 1k FREQU1E0NkCY (Hz) 100k 1M 06341-054 –4010k 100kFREQUENCY (Hz)1M 10M 06341-057 Figure 51. Noise Spectral Density, Internal Reference Figure 54. Multiplying Bandwidth –20 0 –30 TDVADA DC= =2L 55O°VACDED WITH FULL SCALE –20 VM1T0ADI0D D=m S =2CV 53 A°p.3CL-VpE oLnOAAVDDEDD VREF = 2V ± 0.3V p-p 10µF || 100nF –40 –40 D (dB) ––5600 SRR (dB)–60 H P T C –70 A –80 –80 –100 –90 –100 2k F4RkEQUENCY 6(Hkz) 8k 10k 06341-055 –12010 100 FREQUE1NkCY (Hz) 10k 100k 06341-124 Figure 52. Total Harmonic Distortion Figure 55. AC Power Supply Rejection Ratio (AC PSRR) vs. Frequency 16 VREF = VDD TA = 25°C 14 VDD=3V 12 s) µ E ( 10 M TI 8 VDD=5V 6 40 1 2 3 CA4PACITA5NCE 6(nF) 7 8 9 10 06341-056 Figure 53. Settling Time vs. Capacitive Load Rev. F | Page 20 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Output Voltage Settling Time For the DAC, relative accuracy or integral nonlinearity is a Output voltage settling time is the amount of time it takes for measurement of the maximum deviation, in LSBs, from a the output of a DAC to settle to a specified level for a ¼ to ¾ straight line passing through the endpoints of the DAC full-scale input change, and it is measured from the rising edge transfer function. of the stop condition. Differential Nonlinearity (DNL) Digital-to-Analog Glitch Impulse Differential nonlinearity is the difference between the measured Digital-to-analog glitch impulse is the impulse injected into the change and the ideal 1 LSB change between any two adjacent analog output when the input code in the DAC register changes codes. A specified differential nonlinearity of ±1 LSB maximum state. It is normally specified as the area of the glitch in nV-s ensures monotonicity. This DAC is guaranteed monotonic and is measured when the digital input code is changed by by design. 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure 45). Zero-Code Error Zero-code error is a measurement of the output error when zero Digital Feedthrough scale (0x0000) is loaded to the DAC register. Ideally, the output Digital feedthrough is a measure of the impulse injected into the should be 0 V. The zero-code error is always positive in the analog output of the DAC from the digital inputs of the DAC AD5665R because the output of the DAC cannot go below 0 V but is measured when the DAC output is not updated. It is due to a combination of the offset errors in the DAC and the out- specified in nV-s and is measured with a full-scale code change put amplifier. Zero-code error is expressed in millivolts (mV). on the data bus, that is, from all 0s to all 1s and vice versa. Full-Scale Error Reference Feedthrough Full-scale error is a measurement of the output error when full- Reference feedthrough is the ratio of the amplitude of the signal scale code (0xFFFF) is loaded to the DAC register. Ideally, the at the DAC output to the reference input when the DAC output output should be V − 1 LSB. Full-scale error is expressed as a is not being updated. It is expressed in decibels (dB). DD percentage of full-scale range (FSR). Output Noise Spectral Density Gain Error Output noise spectral density is a measurement of the internally Gain error is a measure of the span error of the DAC. It is the generated random noise, which is characterized as a spectral deviation in slope of the DAC transfer characteristic from ideal density (nanovolts per square root of hertz frequency (nV/√Hz)). expressed as a percentage of full-scale range (FSR). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nanovolts per square root Zero-Code Error Drift of hertz frequency (nV/√Hz). A plot of noise spectral density is Zero-code error drift is a measurement of the change in shown in Figure 51. zero-code error with a change in temperature. It is expressed in microvolts per degrees Celsius (µV/°C). DC Crosstalk DC crosstalk is the dc change in the output level of one DAC Gain Temperature Coefficient in response to a change in the output of another DAC. It is Gain temperature coefficient is a measurement of the change in measured with a full-scale output change on one DAC (or soft gain error with changes in temperature. It is expressed in parts power-down and power-up) while monitoring another DAC per million (ppm) of full-scale range per degrees Celsius kept at midscale. It is expressed in microvolts (μV). (FSR/°C). DC crosstalk due to load current change is a measure of the Offset Error impact that a change in load current on one DAC has on Offset error is a measure of the difference between V (actual) OUT another DAC kept at midscale. It is expressed in microvolts per and V (ideal) expressed in mV in the linear region of the OUT milliampere (μV/mA). transfer function. Offset error is measured on the AD5665R with Code 512 loaded in the DAC register. It can be negative or Digital Crosstalk positive. This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all DC Power Supply Rejection Ratio (PSRR) 1s and vice versa) in the input register of another DAC. It is DC PSRR indicates how the output of the DAC is affected by measured in standalone mode and is expressed in nanovolts per changes in the supply voltage. PSRR is the ratio of the change in second (nV-s). V to the change in V for full-scale output of the DAC. It is OUT DD measured in decibels (dB). V is held at 2 V, and V is varied REF DD by ±10%. Rev. F | Page 21 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet Analog Crosstalk Multiplying Bandwidth Analog crosstalk is the glitch impulse transferred to the output The multiplying bandwidth is a measure of the finite bandwidth of one DAC due to a change in the output of another DAC. It is of the amplifiers within the DAC. A sine wave on the reference measured by loading one of the input registers with a full-scale (with full-scale code loaded to the DAC) appears on the output. code change (all 0s to all 1s and vice versa) and then executing The multiplying bandwidth is the frequency at which the output a software LDAC and monitoring the output of the DAC whose amplitude falls to 3 dB below the input. digital code was not changed. The area of the glitch is expressed Total Harmonic Distortion (THD) in nanovolts per second (nV-s). THD is the difference between an ideal sine wave and its DAC-to-DAC Crosstalk attenuated version using the DAC. The sine wave is used as the DAC-to-DAC crosstalk is the glitch impulse transferred to the reference for the DAC, and the THD is a measurement of the output of one DAC due to a digital code change and subsequent harmonics present on the DAC output. It is measured in analog output change of another DAC. It is measured by decibels (dB). loading the attack channel with a full-scale code change (all 0s AC Power Supply Rejection Ratio (AC PSRR) to all 1s and vice versa) with LDAC low while monitoring the AC PSRR is a measure of the rejection of the output voltage to output of the victim channel that is at midscale. The energy of ac changes in the power supplies applied to the DAC. It is the glitch is expressed in nanovolts per second (nV-s). measured for a given amplitude and frequency change in power supply voltage and is expressed in decibels. Rev. F | Page 22 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER (DAC) RESISTOR STRING The AD5625R/AD5645R/AD5665R and AD5625/AD5665 The resistor string is shown in Figure 58. It is simply a string of DACs are fabricated on a CMOS process. The AD5625/AD5665 resistors, each of value R. The code loaded to the DAC register do not have an internal reference, and the DAC architecture is determines at which node on the string the voltage is tapped off shown in Figure 56. The AD5625R/AD5645R/AD5665R do to be fed into the output amplifier. The voltage is tapped off by have an internal reference and can be configured for use with closing one of the switches connecting the string to the amplifier. either an internal or external reference (see Figure 56 and Because it is a string of resistors, it is guaranteed monotonic. Figure 57). OUTPUT AMPLIFIER Because the input coding to the DAC is straight binary, the ideal The output buffer amplifier can generate rail-to-rail voltages on its output voltage when using an external reference is given by output, which gives an output range of 0 V to V . It can drive a DD  D  load of 2 kΩ in parallel with 1000 pF to GND. The source and V V   OUT REFIN 2N  sink capabilities of the output amplifier are shown in Figure 39 and Figure 40. The slew rate is 1.8 V/μs with a ¼ to ¾ full-scale VREFIN/VREFOUT settling time of 7 μs. REF BUFFER R OUTPUT AMPLIFIER GAIN = ×2 REF (+) R REGDIASCTER RSETSRISINTOGR VOUT REF (–) R TO OUTPUT AMPLIFIER GND 06341-034 Figure 56. Internal Configuration When Using an External Reference R The ideal output voltage when using the internal reference is given by R VOUT 2VREFOUT2DN  06341-033 Figure 58. Resistor String where: INTERNAL REFERENCE D is the decimal equivalent of the binary code that is loaded to The AD5625R/AD5645R/AD5665R feature an on-chip reference. the DAC register, as follows: Versions without the R suffix require an external reference. The 0 to 4095 for AD5625R/AD5625 (12-bit). on-chip reference is off at power-up and is enabled via a write to a 0 to 16,383 for AD5645R (14-bit). control register. See the Internal Reference Setup section for details. 0 to 65,535 for AD5665R/AD5665 (16-bit). Versions packaged in a 10-lead LFCSP have a 1.25 V reference N is the DAC resolution. or a 2.5 V reference, giving a full-scale output of 2.5 V or 5 V, VREFIN/VREFOUT depending on the model selected (see the Ordering Guide). The WLCSP has an internal reference of 1.25 V. These devices can be operated with a V supply of 2.7 V to 5.5 V. Versions packaged in 1.25V INTERNAL DD REFERENCE1 OUTPUT a 14-lead TSSOP have a 2.5 V reference, giving a full-scale AMPLIFIER REF (+) GAIN = ×2 output of 5 V. Devices are functional with a VDD supply of 2.7 V to 5.5 V, but with a V supply of less than 5 V, the output is REGDIASCTER RSETSRISINTOGR VOUT clamped to V . See tDhDe Ordering Guide for a full list of models. DD REF (–) The internal reference associated with each device is available at the V pin (available on R suffix versions only). REFOUT B1CYA VNR BEFEIN O/VVREERFODURTIV.EN GND 06341-035 Aex tbeurfnfaerl lios ardesq.u Wirehde nif uthsien rge tfheree innctee ronuatlp ruetf eisr eunsceed, tito i ds rrievceo m- Figure 57. Internal Configuration When Using the Internal Reference mended that a 100 nF capacitor be placed between the reference output and GND for reference stability. Rev. F | Page 23 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet EXTERNAL REFERENCE The 2-wire serial bus protocol operates as follows: The V pin on the AD5625R/AD5645R/AD5665R allows the REFIN 1. The master initiates data transfer by establishing a start use of an external reference if the application requires it. The condition when a high-to-low transition on the SDA line default condition of the on-chip reference is off at power-up. All occurs while SCL is high. The following byte is the address devices can be operated from a single 2.7 V to 5.5 V supply. byte, which consists of the 7-bit slave address. The slave SERIAL INTERFACE address corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is The AD5625R/AD5645R/AD5665R and AD5625/AD5665 have termed the acknowledge bit). At this stage, all other devices 2-wire I2C-compatible serial interfaces. The AD5625R/AD5645R/ on the bus remain idle while the selected device waits for AD5665R and AD5625/AD5665 can be connected to an I2C bus data to be written to or read from its shift register. as a slave device, under the control of a master device. See Figure 3 2. Data is transmitted over the serial bus in sequences of nine for a timing diagram of a typical write sequence. clock pulses (eight data bits followed by an acknowledge The AD5625R/AD5645R/AD5665R and AD5625/AD5665 bit). The transitions on the SDA line must occur during the support standard (100 kHz), fast (400 kHz), and high speed low period of SCL and remain stable during the high (3.4 MHz) data transfer modes. High speed operation is only period of SCL. available on selected models. See the Ordering Guide for a full 3. When all data bits have been read or written, a stop condition list of models. Support is not provided for 10-bit addressing and is established. In write mode, the master pulls the SDA line general call addressing. high during the 10th clock pulse to establish a stop condition. The AD5625R/AD5645R/AD5665R and AD5625/AD5665 each If a stop condition is generated between the 7th and 8th clock have a 7-bit slave address. The 10-lead and 12-ball versions of pulse of the I2C address frame, a power cycle is required to the device have a slave address whose five MSBs are 00011, and recover the device. In read mode, the master issues a no the two LSBs are set by the state of the ADDR address pin, which acknowledge for the ninth clock pulse (that is, the SDA line determines the state of the A0 and A1 address bits. The 14-lead remains high). The master brings the SDA line low before versions of the device have a slave address whose three MSBs the 10th clock pulse, and then high during the 10th clock are 001, and the four LSBs are set by the ADDR1 and ADDR2 pulse to establish a stop condition. address pins, which determine the state of the A0 and A1 and WRITE OPERATION A2 and A3 address bits, respectively. When writing to the AD5625R/AD5645R/AD5665R and The facility to make hardwired changes to the ADDR pin allows AD5625/AD5665, the user must begin with a start command the user to incorporate up to three of these devices on one bus, followed by an address byte (R/W = 0), after which the DAC as outlined in Table 9. acknowledges that it is prepared to receive data by pulling SDA Table 9. ADDR Pin Settings (10-Lead and 12-Ball Packages) low. The AD5665 requires two bytes of data for the DAC and a ADDR Pin Connection A1 A0 command byte that controls various DAC functions. Three bytes V 0 0 of data must, therefore, be written to the DAC, the command DD NC 1 0 byte followed by the most significant data byte and the least GND 1 1 significant data byte, as shown in Figure 59 and Figure 60. After these data bytes are acknowledged by the AD5625R/AD5645R/ The facility to make hardwired changes to the ADDR1 and the AD5665R and AD5625/AD5665, a stop condition follows. ADDR2 pins allows the user to incorporate up to nine of these READ OPERATION devices on one bus, as outlined in Table 10. When reading data back from the AD5625R/AD5645R/AD5665R Table 10. ADDR1, ADDR2 Pin Settings (14-Lead Package) and AD5625/AD5665, the user begins with a start command ADDR2 Pin ADDR1 Pin followed by an address byte (R/W = 1), after which the DAC Connection Connection A3 A2 A1 A0 acknowledges that it is prepared to transmit data by pulling SDA V V 0 0 0 0 DD DD low. Two bytes of data are then read from the DAC, which are V NC 0 0 1 0 DD both acknowledged by the master as shown in Figure 61 and V GND 0 0 1 1 DD Figure 62. A stop condition follows. When a read operation is NC V 1 0 0 0 DD performed, the DAC shifts out the last transferred command. NC NC 1 0 1 0 NC GND 1 0 1 1 GND V 1 1 0 0 DD GND NC 1 1 1 0 GND GND 1 1 1 1 Rev. F | Page 24 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 1 9 1 9 SCL SDA 0 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 START BY ACK. BY ACK. BY MASTER AD56x5 AD56x5 FRAME 1 FRAME 2 SLAVE ADDRESS COMMAND BYTE 1 9 1 9 SCL (CONTINUED) (CONTINUSEDDA) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ACK. BY ACK. BY STOP BY AD56x5 AD56x5 MASTER MOSDTFA RSTIAAGM BNEYIF T3ICEANT LEASDTFA RTSAAIGM BNEYI FT4IECANT 06341-103 Figure 59. I2C Write Operation (10-Lead and 12-Ball Packages) 1 9 1 9 SCL SDA 0 0 1 A3 A2 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 START BY ACK. BY ACK. BY MASTER AD56x5 AD56x5 FRAME 1 FRAME 2 SLAVE ADDRESS COMMAND BYTE 1 9 1 9 SCL (CONTINUED) SDA DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (CONTINUED) ACK. BY ACK. BY STOP BY AD56x5 AD56x5 MASTER MOSDTFA RSTIAAGM NBEIYF T3ICEANT LEASDTFA RTSAAIGM BNEYI FT4IECANT 06341-104 Figure 60. I2C Write Operation (14-Lead Package) 1 9 1 9 SCL SDA 0 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 START BY ACK. BY ACK. BY MASTER AD56x5 MASTER FRAME 1 FRAME 2 SLAVE ADDRESS COMMAND BYTE 1 9 1 9 SCL (CONTINUED) (CONTINUSEDDA) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ACK. BY NO ACK. STOP BY MASTER MASTER MOSDTFA RSTIAAGM BNEYIF T3ICEANT LEASDTFA RTSAAIGM BNEYI FT4IECANT 06341-101 Figure 61. I2C Read Operation (10-Lead and 12-Ball Packages) Rev. F | Page 25 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet 1 9 1 9 SCL SDA 0 0 1 A3 A2 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 START BY ACK. BY ACK. BY MASTER AD56x5 MASTER FRAME 1 FRAME 2 SLAVE ADDRESS COMMAND BYTE 1 9 1 9 SCL (CONTINUED) (CONTINUSEDDA) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ACK. BY NO ACK. STOP BY MASTER MASTER MOSDTFA RSTIAAGM BNEYIF T3ICEANT LEASDTFA RTSAAIGM BNEYI FT4IECANT 06341-102 Figure 62. I2C Read Operation (14-Lead Package) FAST MODE HIGH-SPEED MODE 1 9 1 9 SCL SDA 0 0 0 0 1 X X X 0 0 1 A3 A2 A1 A0 R/W START BY NO ACK. SR ACK. BY MASTER MAHSST-EMRO CDOEDE ADSDERREIASLS BBUYSTE AD56x5 06341-105 Figure 63. Placing the AD5625RBRUZ-2/AD5645RBRUZ-2/AD5665RBRUZ-2/AD5625RBRUZ-2REEL7/AD5645RBRUZ-2REEL7/AD5665RBRUZ-2REEL7 in High Speed Mode HIGH SPEED MODE INPUT SHIFT REGISTER Some models offer high speed serial communication with a The input shift register is 24 bits wide. Data is loaded into the clock frequency of 3.4 MHz. See the Ordering Guide for a full device as a 24-bit word under the control of a serial clock input, list of models. SCL. The timing diagram for this operation is shown in Figure 3. The eight MSBs make up the command byte. DB23 is reserved High speed mode communication commences after the master and should always be set to 0 when writing to the device. DB22 (S) addresses all devices connected to the bus with the Master Code is used to select multiple byte operation. The next three bits are 00001XXX to indicate that a high speed mode transfer is to begin. the command bits (C2, C1, and C0) that control the mode of No device connected to the bus is permitted to acknowledge the operation of the device. See Table 11 for details. The last three high speed master code; therefore, the code is followed by a no bits of the first byte are the address bits (A2, A1, and A0). See acknowledge. Next, the master must issue a repeated start followed Table 12 for details. The rest of the bits are the 16-/14-/12-bit by the device address. The selected device then acknowledges data-word. The data-word comprises the 16-/14-/12-bit input its address. All devices continue to operate in high speed mode code followed by two or four don’t care bits for the AD5645R until the master issues a stop condition. When the stop condition and the AD5625R/AD5625, respectively (see Figure 66 through is issued, the devices return to standard/fast mode. The device Figure 68). also returns to standard/fast mode when CLR is activated while the device is in high speed mode. MULTIPLE BYTE OPERATION Multiple byte operation is supported on the AD5625R/AD5645R/ AD5665R and AD5625/AD5665. A 2-byte operation is useful for applications that require fast DAC updating and do not need to change the command byte. The S bit (DB22) in the command register can be set to 1 for 2-byte mode of operation (see Figure 65). For standard 3-byte and 4-byte operation, the S bit (DB22) in the command byte should be set to 0 (see Figure 64). Rev. F | Page 26 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 BLOCK 1 BLOCK 2 BLOCK n S = 0 S = 0 S = 0 ADSDLARVEESS COBMYMTAEND MOSDTA STIAG BNYIFTICEANTLEASDTA TSAIG BNYIFTIECANTCOBMYMTAENDMOSDTA STIAG BNYIFTICEANTLEASDTA TSAIG BNYIFTIECANT COBMYMTAENDMOSDTA STIAG BNYIFTICEANTLEASDTA TSAIG BNYIFTIECANT STOP 06341-107 Figure 64. Multiple Block Write with Command Byte in Each Block (S = 0) BLOCK 1 BLOCK 2 BLOCK n S = 1 S = 1 S = 1 ADSDLARVEESS COBMYMTAEND MOSDTA STIAG BNYIFTICEANT LEASDTA TSAIG BNYIFTIECANT MOSDTA STIAG BNYIFTICEANT LEASDTA TSAIG BNYIFTIECANT MOSDTA STIAG BNYIFTICEANT LEASDTA TSAIG BNYIFTIECANT STOP 06341-106 Figure 65. Multiple Block Write with Initial Command Byte Only (S = 1) DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R S C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D N E O RESERV BYTESELECTI CCOOMMMMAANNDD BYTE DACADDRESS DATDAA HCI GDAHT BAYTE DATDAA CLO DWAT BAYTE 06341-108 Figure 66. AD5665R/AD5665 Input Shift Register (16-Bit DAC) DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R S C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X D N E O ESERV BYTEELECTI COMMAND DACADDRESS DAC DATA DAC DATA R S COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE 06341-109 Figure 67. AD5645R Input Shift Register (14-Bit DAC) DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R S C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X D N E O RESERV BYTESELECTI CCOOMMMMAANNDD BYTE DACADDRESS DATDAA HCI GDAHT BAYTE DATDAA CLO DWAT BAYTE 06341-110 Figure 68. AD5625R/AD5625 Input Shift Register (12-Bit DAC) Rev. F | Page 27 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet BROADCAST MODE LDAC FUNCTION Broadcast addressing is supported on the AD5625R/AD5645R/ The AD5625R/AD5645R/AD5665R and AD5625/AD5665 AD5665R and AD5625/AD5665 in write mode only. Broadcast DACs have double-buffered interfaces consisting of two banks addressing can be used to synchronously update or power down of registers: input registers and DAC registers. The input registers multiple AD5625R/AD5645R/AD5665R and AD5625/AD5665 are connected directly to the input shift register, and the digital devices. When the broadcast address is used, the AD5625R/ code is transferred to the relevant input register upon completion AD5645R/AD5665R and AD5625/AD5665 respond regardless of a valid write sequence. The DAC registers contain the digital of the states of the address pins. The AD5625R/AD5645R/ code used by the resistor strings. AD5665R and AD5625/AD5665 broadcast address is 00010000. Access to the DAC registers is controlled by the LDAC pin. When Table 11. Command Definition the LDAC pin is high, the DAC registers are latched and the input C2 C1 C0 Command registers can change state without affecting the contents of the 0 0 0 Write to input Register n DAC registers. When LDAC is brought low, however, the DAC 0 0 1 Update DAC Register n registers become transparent and the contents of the input registers 0 1 0 Write to input Register n, update all are transferred to them. The double-buffered interface is useful (software LDAC) if the user requires simultaneous updating of all DAC outputs. 0 1 1 Write to and update DAC Channel n The user can write to one of the input registers individually and 1 0 0 Power up/power down then, by bringing LDAC low when writing to the other DAC 1 0 1 Reset input register, all outputs update simultaneously. 1 1 0 LDAC register setup These devices each contain an extra feature whereby a DAC register 1 1 1 Internal reference setup (on/off ) is not updated unless its input register has been updated since the last time LDAC was brought low. Normally, when LDAC is Table 12. DAC Address Command brought low, the DAC registers are filled with the contents of the A2 A1 A0 ADDRESS (n) input registers. In the case of the AD5625R/AD5645R/AD5665R 0 0 0 DAC A and AD5625/AD5665, the DAC register updates only if the 0 0 1 DAC B input register has changed since the last time the DAC register 0 1 0 DAC C was updated, thereby removing unnecessary digital crosstalk. 0 1 1 DAC D 1 1 1 All DACs The outputs of all DACs can be simultaneously updated, using the hardware LDAC pin. Rev. F | Page 28 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 Synchronous LDAC the LDAC pin. If this bit is set to 1, this channel synchronously updates; that is, the DAC register is updated after new data is The DAC registers are updated after new data is read in. LDAC read in, regardless of the state of the LDAC pin. The device can be permanently low or pulsed. effectively sees the LDAC pin as being pulled low. See Table 14 Asynchronous LDAC for the LDAC register mode of operation. This flexibility is The outputs are not updated at the same time that the input useful in applications when the user wants to simultaneously registers are written to. When LDAC goes low, the DAC registers update select channels while the rest of the channels are are updated with the contents of the input register. synchronously updating. The LDAC register gives the user full flexibility and control over Writing to the DAC using Command 110 loads the 4-bit LDAC the hardware LDAC pin (and software LDAC on the 10-lead register [DB3:DB0]. The default for each channel is 0; that is, devices that do not have the hardware LDAC pin—see Table 13). the LDAC pin works normally. Setting the bits to 1 means that This register allows the user to select which combination of the DAC register is updated, regardless of the state of the LDAC channels to simultaneously update when the hardware LDAC pin. See Figure 69 for the contents of the input shift register pin is executed. Setting the LDAC bit register to 0 for a DAC during the LDAC register setup command. channel means that the update of this channel is controlled by Table 13. LDAC Register Mode of Operation on the 10-Lead LFCSP (Load DAC Register) LDAC Bits (DB3 to DB0) LDAC Mode of Operation 0 Normal operation (default), DAC register update is controlled by the write command. 1 The DAC registers are updated after new data is read in. Table 14. LDAC Register Mode of Operation on the 14-Lead TSSOP (Load DAC Register) LDAC Bits (DB3 to DB0) LDAC Pin LDAC Operation 0 1/0 Determined by the LDAC pin. 1 X = don’t care The DAC registers are updated after new data is read in. R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 X 1 1 0 A2 A1 A0 X X X X X X X X X X X X DAC D DAC C DAC B DAC A D RVE N’TRE COMMAND DAC ADDRESS DON’T CARE DON’T CARE DAC SELECT RESE DOCA (DON’T CARE) (0 = LDAC PIN ENABLED) 06341-115 Figure 69. LDAC Setup Command Rev. F | Page 29 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet POWER-DOWN MODES Table 15. Modes of Operation for the AD5625R/AD5645R/ AD5665R and AD5625/AD5665 Command 100 is reserved for the power-up/power-down function. DB5 DB4 Operating Mode The power-up/power-down modes are programmed by setting 0 0 Normal operation Bit DB5 and Bit DB4. This defines the output state of the DAC Power-down modes amplifier, as shown in Table 15. Bit DB3 to Bit DB0 determine 0 1 1 kΩ pull-down resistor to GND to which DAC or DACs the power-up/power-down command 1 0 100 kΩ pull-down resistor to GND is applied. Setting one of these bits to 1 applies the power-up/ 1 1 Three-state, high impedance power-down state defined by DB5 and DB4 to the corresponding DAC. If a bit is 0, the state of the DAC is unchanged. Figure 71 shows the contents of the input shift register for the power-up/ RESISTOR power-down command. STRING DAC AMPLIFIER VOUT When Bit DB5 and Bit DB4 are set to 0, the device works normally with its normal power consumption of 1 mA at 5 V. However, for the three power-down modes, the supply current POWER-DOWN CIRCUITRY RESISTOR ftahlels o tuot p4u80t sntaAg ea ti s5 aVls. oN iontt eornnlayl ldyo sews itthceh esdu pfprolym c uthrere onut tfpaullt, obfu t NETWORK 06341-038 the amplifier to a resistor network of known values. This allows Figure 70. Output Stage During Power-Down the output impedance of the device to be known while the device The bias generator, output amplifier, resistor string, and other is in power-down mode. The outputs can either be connected associated linear circuitry are shut down when power-down internally to GND through a 1 kΩ or 100 kΩ resistor or be left mode is activated. However, the contents of the DAC register open-circuited (three-state) as shown in Figure 68. are unaffected when in power-down. The time to exit power- Note that the 14-lead TSSOP models offer the power-down down is typically 4 μs for VDD = 5 V or VDD = 3 V. function when the device is operated with a VDD of 3.6 V to 5.5 V. The 10-lead LFCSP models offer the power-down function when the device is powered with a V of 2.7 V to 5.5 V. DD R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 X 1 0 0 A2 A1 A0 X X X X X X X X X X PD1 PD0 DAC D DAC C DAC B DAC A D RESERVE DON’TCARE COMMAND D(DAOCN A’TD DCRAERSES) DON’T CARE DON’T CARE DOPWONW MERO-DE (1 = DDAACC SSEELLEECCTTED) 06341-116 Figure 71. Power-Up/Power-Down Command Rev. F | Page 30 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 POWER-ON RESET AND SOFTWARE RESET Table 16. Software Reset Modes for the AD5625R/AD5645R/ The AD5625R/AD5645R/AD5665R and AD5625/AD5665 AD5665R and AD5625/AD5665 contain a power-on reset circuit that controls the output voltage DB0 Registers Reset to Zero during power-up. The 10-lead version of the device powers up 0 DAC register to 0 V. The 14-lead version has a power-on reset (POR) pin that Input shift register allows the output voltage to be selected. By connecting the POR 1 (Power-On Reset) DAC register pin to GND, the AD5625R/AD5645R/AD5665R and AD5625/ Input shift register AD5665 output powers up to 0 V; by connecting the POR pin to LDAC register VDD, the AD5625R/AD5645R/AD5665R and AD5625/AD5665 Power-down register output powers up to midscale. The output remains powered up at Internal reference setup register this level until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of INTERNAL REFERENCE SETUP (R VERSIONS) the output of the DAC while it is in the process of powering up. The on-chip reference is off at power-up by default. It can be Any events on LDAC or CLR during power-on reset are ignored. turned on by sending the reference setup command (111) and setting DB0 in the input shift register. Table 17 shows how the There is also a software reset function. Command 101 is the state of the bit corresponds to the mode of operation. software reset command. The software reset command contains two reset modes that are software programmable by setting bit Table 17. Reference Setup Command DB0 in the input shift register. DB0 Action Table 16 shows how the state of the bit corresponds to the 0 Internal reference off (default) software reset modes of operation of the devices. Figure 72 1 Internal reference on shows the contents of the input shift register during the software reset mode of operation. X S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 X 1 0 1 X X X X X X X X X X X X X X X X X X RST D RESERVE DON’TCARE COMMAND D(DAOCN A’TD DCRAERSES) DON’T CARE DON’T CARE RESETMODE 06341-113 Figure 72. Reset Command R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 X 1 1 1 X X X X X X X X X X X X X X X X X X REF RESERVED DON’TCARE COMMAND D(DAOCN A’TD DCRAERSES) DON’T CARE DON’T CARE REFERENCEMODE 06341-114 Figure 73. Reference Setup Command Rev. F | Page 31 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet APPLICATIONS INFORMATION USING A REFERENCE AS A POWER SUPPLY FOR This is an output voltage range of ±5 V, with 0x0000 corresponding THE AD5625R/AD5645R/AD5665R AND AD5625/ to a −5 V output and 0xFFFF corresponding to a +5 V output. AD5665 R2 = 10kΩ Because the supply current required by the AD5625R/AD5645R/ +5V R1 = 10kΩ AD5665R and AD5625/AD5665 is extremely low, an alternative option is to use a voltage reference to supply the required voltage AD820/ VO OP295 ±5V to the device (see Figure 74). This is especially useful if the power +5V VDD VOUT supply is noisy or if the system supply voltages are at some value 10µF 0.1µF AD5625R/ AD5645R/ –5V other than 5 V or 3 V, for example, 15 V. The voltage reference AD5665R/ outputs a steady supply voltage for the AD5625R/AD5645R/ AD5625/ AD5665 AD5665R and AD5625/AD5665. If the low dropout REF195 is used, it must supply 450 μA of current to the AD5625R/AD5645R/ GND SCL SDA AD5665R and AD5625/AD5665 with no load on the output of the DAC. When the DAC output is loaded, the REF195 also must supply the current to the load. The total current required INTS2E-EWRRIFIRAAELCE 06341-044 (with a 5 kΩ load on the DAC output) is Figure 75. Bipolar Operation with the AD5625R/AD5645R/AD5665R and AD5625/AD5665 1 mA + (5 V/5 kΩ) = 2 mA POWER SUPPLY BYPASSING AND GROUNDING The load regulation of the REF195 is typically 2 ppm/mA, resulting in a 4 ppm (20 μV) error for the 2 mA current drawn When accuracy is important in a circuit, it is helpful to carefully from it. This corresponds to a 0.263 LSB error. consider the power supply and ground return layout on the board. The printed circuit board containing the AD5625R/AD5645R/ 15V AD5665R and AD5625/AD5665 should have separate analog 5V REF195 and digital sections, each having its own area of the board. If the AD5625R/AD5645R/AD5665R and AD5625/AD5665 are in a VDD system where other devices require an AGND-to-DGND 2-WIRE SCL AD5625R/ VOUT = 0V TO 5V connection, the connection should be made at one point only. SERIAL AD5645R/ INTERFACE AD5665R/ This ground point should be as close as possible to the SDA AD5625/ AD5625R/AD5645R/AD5665R and AD5625/AD5665. AD5665 GND The power supply to the AD5625R/AD5645R/AD5665R and 06341-043 AcaDpa5c6i2to5r/sA. DTh56e 6c5a pshacoiutoldr sb esh boyuplads sbeed lwocitaht e1d0 aμsF c alonsde 0 a.s1 pμoFs sible Figure 74. REF195 as Power Supply to the AD5625R/AD5645R/ AD5665R and AD5625/AD5665 to the device, with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitor is the tantalum bead type. It is BIPOLAR OPERATION USING THE AD5625R/ important that the 0.1 μF capacitor have low effective series AD5645R/AD5665R AND AD5625/AD5665 resistance (ESR) and low effective series inductance (ESI), for The AD5625R/AD5645R/AD5665R and AD5625/AD5665 have example, common ceramic types of capacitors. This 0.1 μF been designed for single-supply operation, but a bipolar output capacitor provides a low impedance path to ground for high range is also possible using the circuit shown in Figure 75. The frequencies caused by transient currents due to internal logic circuit gives an output voltage range of ±5 V. Rail-to-rail operation switching. at the amplifier output is achievable using an AD820 or an The power supply line itself should have as large a trace as OP295 as the output amplifier. possible to provide a low impedance path and to reduce glitch The output voltage for any input code can be calculated as follows: effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board VO VDD 65,D536R1R1R2VDD RR21 by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, where D represents the input code in decimal (0 to 65,535). ensure that they run at right angles to each other to reduce If V = 5 V, R1 = R2 = 10 kΩ, feedthrough effects through the board. The best board layout DD technique is the microstrip technique where the component 10D V  5V side of the board is dedicated to the ground plane only, and the O 65,536 signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. Rev. F | Page 32 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 2.48 2.38 3.10 2.23 3.00 SQ 2.90 0.50 BSC 6 10 PIN 1 INDICATOR EXPOSED 1.74 AREA PAD 1.64 0.50 1.49 0.40 0.30 0.20 MIN 5 1 TOP VIEW BOTTOM VIEW IPNIND I1CATORAREAOPTIONS (SEEDETAILA) 0.80 FOR PROPER CONNECTION OF 0.75 SIDE VIEW 0.05 MAX THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. 0.08 PKG-004362 SEPALTAINNGE 000...322050 0.20 REF 08-20-2018-C Figure 76. 10-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-10-9) Dimensions shown in millimeters 5.10 5.00 4.90 14 8 4.50 4.40 6.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.00 1M.2A0X 0.20 0.80 0.09 0.75 0.15 8° 0.60 0.05 0.30 SPELAATNIENG 0° 0.45 COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 061908-A Figure 77. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. F | Page 33 of 35

AD5625R/AD5645R/AD5665R, AD5625/AD5665 Data Sheet 1.705 1.665 BOTTOM VIEW 1.625 (BALL SIDE UP) 3 2 1 BALLA1 A IDENTIFIER 2.285 2.245 R1.E5F0 B 2.205 C D 0.50 BSC TOP VIEW (BALL SIDE DOWN) 1.00 0.380 REF 0.650 0.355 0.595 END VIEW 0.330 0.540 COPLANARITY 0.05 SEATING 0.270 PLANE 000...333420000 00..224100 08-31-2012-A Figure 78. 12-Ball Wafer Level Chip Scale Package [WLCSP] (CB-12-9) Dimensions shown in millimeters ORDERING GUIDE Temperature On-Chip Maximum Package Package Marking Model1 Range Accuracy Reference I2C Speed Description Option Code AD5625BCPZ-R2 −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead LFCSP CP-10-9 D8V AD5625BCPZ-REEL7 −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead LFCSP CP-10-9 D8V AD5625BRUZ −40°C to +105°C ±1 LSB INL None 400 kHz 14-Lead TSSOP RU-14 AD5625BRUZ-REEL7 −40°C to +105°C ±1 LSB INL None 400 kHz 14-Lead TSSOP RU-14 AD5625RBCPZ-R2 −40°C to +105°C ±1 LSB INL 1.25 V 400 kHz 10-Lead LFCSP CP-10-9 D8S AD5625RBCPZ-REEL7 −40°C to +105°C ±1 LSB INL 1.25 V 400 kHz 10-Lead LFCSP CP-10-9 D8S AD5625RACPZ-REEL7 −40°C to +105°C ±4 LSB INL 1.25 V 400 kHz 10-Lead LFCSP CP-10-9 DEU AD5625RBRUZ-1 −40°C to +105°C ±1 LSB INL 2.5 V 400 kHz 14-Lead TSSOP RU-14 AD5625RBRUZ-1REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 400 kHz 14-Lead TSSOP RU-14 AD5625RBRUZ-2 −40°C to +105°C ±1 LSB INL 2.5 V 3.4 MHz 14-Lead TSSOP RU-14 AD5625RBRUZ-2REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 3.4 MHz 14-Lead TSSOP RU-14 AD5645RBCPZ-R2 −40°C to +105°C ±4 LSB INL 1.25 V 400 kHz 10-Lead LFCSP CP-10-9 D89 AD5645RBCPZ-REEL7 −40°C to +105°C ±4 LSB INL 1.25 V 400 kHz 10-Lead LFCSP CP-10-9 D89 AD5645RBRUZ −40°C to +105°C ±4 LSB INL 2.5 V 400 kHz 14-Lead TSSOP RU-14 AD5645RBRUZ-REEL7 −40°C to +105°C ±4 LSB INL 2.5 V 400 kHz 14-Lead TSSOP RU-14 AD5665BCPZ-R2 −40°C to +105°C ±16 LSB INL None 400 kHz 10-Lead LFCSP CP-10-9 D6U AD5665BCPZ-REEL7 −40°C to +105°C ±16 LSB INL None 400 kHz 10-Lead LFCSP CP-10-9 D6U AD5665BRUZ −40°C to +105°C ±16 LSB INL None 400 kHz 14-Lead TSSOP RU-14 AD5665BRUZ-REEL7 −40°C to +105°C ±16 LSB INL None 400 kHz 14-Lead TSSOP RU-14 AD5665RBCBZ-1-RL7 −40°C to +105°C ±16 LSB INL 1.25 V 400 kHz 12-Ball WLCSP CB-12-9 AD5665RBCPZ-R2 −40°C to +105°C ±16 LSB INL 1.25 V 400 kHz 10-Lead LFCSP CP-10-9 DA2 AD5665RBCPZ-REEL7 −40°C to +105°C ±16 LSB INL 1.25 V 400 kHz 10-Lead LFCSP CP-10-9 DA2 AD5665RBRUZ-1 −40°C to +105°C ±16 LSB INL 2.5 V 400 kHz 14-Lead TSSOP RU-14 AD5665RBRUZ-1REEL7 −40°C to +105°C ±16 LSB INL 2.5 V 400 kHz 14-Lead TSSOP RU-14 AD5665RBRUZ-2 −40°C to +105°C ±16 LSB INL 2.5 V 3.4 MHz 14-Lead TSSOP RU-14 AD5665RBRUZ-2REEL7 −40°C to +105°C ±16 LSB INL 2.5 V 3.4 MHz 14-Lead TSSOP RU-14 1 Z = RoHS Compliant Part. Rev. F | Page 34 of 35

Data Sheet AD5625R/AD5645R/AD5665R, AD5625/AD5665 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2007-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06341-0-10/18(F) Rev. F | Page 35 of 35