Octal, 12-/14-/16-Bit, SPI Voltage Output denseDAC with 5 ppm/°C, On-Chip Reference Data Sheet AD5628/AD5648/AD5668 FEATURES FUNCTIONAL BLOCK DIAGRAM Low power, small footprint, pin-compatible octal DACs VDD VREFIN/VREFOUT AD5668: 16 bits AD5628/AD5648/AD5668 1.25V/2.5V REF AADD55664288:: 1142 bbiittss LDAC REINGPISUTTER REGDIASCTER SDTARCIN AG BUFFER VOUTA 14-lead/16-lead TSSOP, 16-lead LFCSP, and 16-ball WLCSP REINGPISUTTER REGDIASCTER SDTARCIN BG BUFFER VOUTB On-chip 1.25 V/2.5 V, 5 ppm/°C reference SCLK REINGPISUTTER REGDIASCTER SDTARCIN CG BUFFER VOUTC Power down to 400 nA at 5 V, 200 nA at 3 V 2.7 V to 5.5 V power supply SYNC INTLEORGFIACCE REINGPISUTTER REGDIASCTER SDTARCIN DG BUFFER VOUTD Guaranteed monotonic by design DIN REINGPISUTTER REGDIASCTER SDTARCIN EG BUFFER VOUTE Power-on reset to zero scale or midscale REINGPISUTTER REGDIASCTER SDTARCIN FG BUFFER VOUTF 3 power-down functions Hardware LDAC and LDAC override function REINGPISUTTER REGDIASCTER SDTARCIN GG BUFFER VOUTG CLR function to programmable code REINGPISUTTER REGDIASCTER SDTARCIN HG BUFFER VOUTH Rail-to-rail operation POWER-ON POWER-DOWN RESET LOGIC APPLICATIONS 1RU-16ANLDD AWCL1CSCPL RP1ACKAGE ONLY. GND 05302-001 Process control Figure 1. Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION selectable output loads while in power-down mode for any or all The AD5628/AD5648/AD5668 devices are low power, octal, DAC channels. The outputs of all DACs can be updated simul- 12-/14-/16-bit, buffered voltage-output DACs. All devices taneously using the LDAC function, with the added functionality operate from a single 2.7 V to 5.5 V supply and are guaranteed monotonic by design. The AD5668 and AD5628 are available in of user-selectable DAC channels to simultaneously update. There both a 4 mm × 4 mm LFCSP and a 16-lead TSSOP, while the is also an asynchronous CLR that updates all DACs to a user- AD5648 is available in both a 14-lead and 16-lead TSSOP. programmable code—zero scale, midscale, or full scale. The AD5628/AD5648/AD5668 utilize a versatile 3-wire serial The AD5628/AD5648/AD5668 have an on-chip reference with interface that operates at clock rates of up to 50 MHz and is an internal gain of 2. The AD5628-1/AD5648-1/AD5668-1 have compatible with standard SPI®, QSPI™, MICROWIRE™, and a 1.25 V 5 ppm/°C reference, giving a full-scale output range DSP interface standards. The on-chip precision output amplifier of 2.5 V; the AD5628-2/AD5648-2/AD5668-2 and AD5668-3 have enables rail-to-rail output swing. a 2.5 V 5 ppm/°C reference, giving a full-scale output range of 5 V. The on-board reference is off at power-up, allowing the use PRODUCT HIGHLIGHTS of an external reference. The internal reference is enabled via a 1. Octal, 12-/14-/16-bit DAC. software write. 2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference. The part incorporates a power-on reset circuit that ensures that the 3. Available in 14-lead/16-lead TSSOP, 16-lead LFCSP, and DAC output powers up to 0 V (AD5628-1/AD5648-1/AD5668-1, 16-ball WLCSP. AD5628-2/AD5648-2/AD5668-2) or midscale (AD5668-3) and 4. Power-on reset to 0 V or midscale. remains powered up at this level until a valid write takes place. 5. Power-down capability. When powered down, the DAC The part contains a power-down feature that reduces the current typically consumes 200 nA at 3 V and 400 nA at 5 V. consumption of the device to 400 nA at 5 V and provides software- Rev. J Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5628/AD5648/AD5668 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  DAC Section ................................................................................ 22  Applications ....................................................................................... 1  Resistor String ............................................................................. 22  Functional Block Diagram .............................................................. 1  Internal Reference ...................................................................... 22  General Description ......................................................................... 1  Output Amplifier ........................................................................ 23  Product Highlights ........................................................................... 1  Serial Interface ............................................................................ 23  Revision History ............................................................................... 2  Input Shift Register .................................................................... 24  Specifications ..................................................................................... 4  SYNC Interrupt .......................................................................... 24  AC Characteristics ........................................................................ 7  Internal Reference Register ....................................................... 25  Timing Characteristics ................................................................ 8  Power-On Reset .......................................................................... 25  Absolute Maximum Ratings ............................................................ 9  Power-Down Modes .................................................................. 25  Thermal Resistance ...................................................................... 9  Clear Code Register ................................................................... 25  ESD Caution .................................................................................. 9  LDAC Function .......................................................................... 27  Pin Configurations and Function Descriptions ......................... 10  Power Supply Bypassing and Grounding ................................ 27  Typical Performance Characteristics ........................................... 12  Outline Dimensions ....................................................................... 28  Terminology .................................................................................... 20  Ordering Guide .......................................................................... 30  Theory of Operation ...................................................................... 22  REVISION HISTORY 8/2011—Rev. E to Rev. F 1/2017—Rev. I to Rev. J Added 16-Ball WLCSP ...................................................... Universal Changes to Table 5 ............................................................................ 9 Added Figure 6 and Table 7; Renumbered Sequentially ........... 10 Added Thermal Resistance Section and Table 6; Renumbered Changes to Figure 32 and Figure 33............................................. 15 Sequentially ....................................................................................... 9 Updated Outline Dimensions ....................................................... 26 Changes to Figure 3 ........................................................................ 10 Changes to Ordering Guide .......................................................... 28 11/2014—Rev. H to Rev. I 1/2011—Rev. D to Rev. E Changes to Ordering Guide .......................................................... 29 Changes to AD5628 Relative Accuracy, Zero-Code Error, Offset Error, and Reference TC Parameters, Table 1 ................................ 3 2/2014—Rev. G to Rev. H Changes to AD5628 Relative Accuracy, Zero-Code Error, Offset Changes to Figure 1 .......................................................................... 1 Error, and Reference TC Parameters, Table 2 ................................ 5 Change to Figure 6 ......................................................................... 10 Changes to Output Voltage Settling Time, Table 3 ....................... 6 Change to Table 7 ........................................................................... 10 Added Figure 53; Renumbered Sequentially .............................. 17 Changes to Figure 45, Figure 46, and Figure 47 ......................... 17 Change to Output Amplifier Section ........................................... 21 Changes to Ordering Guide .......................................................... 29 Changes to Ordering Guide .......................................................... 28 1/2013—Rev. F to Rev. G Added WLCSP Reference TC of 15 ppm/°C, Table 2 .................. 5 Changes to Ordering Guide .......................................................... 29 Rev. J | Page 2 of 30

Data Sheet AD5628/AD5648/AD5668 9/2010—Rev. C to Rev. D 1/2010—Rev. B to Rev. C Change to Title .................................................................................. 1 Changes to Figure 3 ........................................................................ 10 Added 16-Lead LFCSP Throughout ................................ Universal Changes to Ordering Guide ........................................................... 28 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 5 2/2009—Rev. A to Rev. B Changes to Table 3 ............................................................................ 6 Changes to Reference Current Parameter, Table 1 and I DD Changes to Table 4 ............................................................................ 7 (Normal Mode) Parameter, Table 1 ................................................ 3 Deleted SnPb from Table 5............................................................... 8 Changes to Reference Current Parameter, Table 2 and I DD Added Figure 5; Renumbered Sequentially ................................... 9 (Normal Mode) Parameter, Table 2 ................................................ 5 Changes to Table 6 ............................................................................ 9 Replaced Typical Performance Characteristics Section ............. 10 11/2005—Rev. 0 to Rev. A Changes to Power-On Reset Section ............................................ 23 Change to Specifications .................................................................. 3 Updated Outline Dimensions ........................................................ 26 Changes to Ordering Guide ........................................................... 28 10/2005—Revision 0: Initial Version Rev. J | Page 3 of 30

AD5628/AD5648/AD5668 Data Sheet SPECIFICATIONS V = 4.5 V to 5.5 V, R = 2 kΩ to GND, C = 200 pF to GND, V = V . All specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 1. A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE2 AD5628 Resolution 12 12 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 9 Differential Nonlinearity ±0.25 ±0.25 LSB Guaranteed monotonic by design (see Figure 12) AD5648 Resolution 14 14 Bits Relative Accuracy ±2 ±8 ±2 ±4 LSB See Figure 8 Differential Nonlinearity ±0.5 ±0.5 LSB Guaranteed monotonic by design (see Figure 11) AD5668 Resolution 16 16 Bits Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 7 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 10) Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 26) Zero-Code Error Drift ±2 ±2 μV/°C Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 27) Gain Error ±1 ±1 % FSR Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C Offset Error ±6 ±19 ±6 ±19 mV DC Power Supply Rejection Ratio –80 –80 dB V ± 10% DD DC Crosstalk (External Reference) 10 10 μV Due to full-scale output change, R = 2 kΩ to GND or V L DD 5 5 μV/mA Due to load current change 10 10 μV Due to powering down (per channel) DC Crosstalk (Internal Reference) 25 25 μV Due to full-scale output change, R = 2 kΩ to GND or V L DD 10 10 μV/mA Due to load current change OUTPUT CHARACTERISTICS3 Output Voltage Range 0 V 0 V V DD DD Capacitive Load Stability 2 2 nF R = ∞ L 10 10 nF R = 2 kΩ L DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA V = 5 V DD Power-Up Time 4 4 μs Coming out of power-down mode, V = 5 V DD REFERENCE INPUTS Reference Current 40 55 40 55 μA V = V = 5.5 V (per DAC channel) REF DD Reference Input Range 0 V 0 V V DD DD Reference Input Impedance 14.6 14.6 kΩ REFERENCE OUTPUT Output Voltage AD5628-2/AD5648-2/ 2.495 2.505 2.495 2.505 V At ambient AD5668-2, AD5668-3 Reference TC3 5 10 5 10 ppm/°C TSSOP 15 5 10 ppm/°C LFCSP Reference Output Impedance 7.5 7.5 kΩ Rev. J | Page 4 of 30

Data Sheet AD5628/AD5648/AD5668 A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS3 Input Current ±3 ±3 µA All digital inputs Input Low Voltage, V 0.8 0.8 V V = 5 V INL DD Input High Voltage, V 2 2 V V = 5 V INH DD Pin Capacitance 3 3 pF POWER REQUIREMENTS V 4.5 5.5 4.5 5.5 V All digital inputs at 0 or V , DD DD DAC active, excludes load current I (Normal Mode)4 V = V and V = GND DD IH DD IL V = 4.5 V to 5.5 V 1.0 1.5 1.0 1.5 mA Internal reference off DD V = 4.5 V to 5.5 V 1.8 2.25 1.7 2.25 mA Internal reference on DD I (All Power-Down Modes)5 DD V = 4.5 V to 5.5 V 0.4 1 0.4 1 µA V = V and V = GND DD IH DD IL 1 Temperature range is −40°C to +105°C, typical at 25°C. 2 Linearity calculated using a reduced code range of AD5628 (Code 32 to Code 4064), AD5648 (Code 128 to Code 16,256), and AD5668 (Code 512 to 65,024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All eight DACs powered down. Rev. J | Page 5 of 30

AD5628/AD5648/AD5668 Data Sheet V = 2.7 V to 3.6 V, R = 2 kΩ to GND, C = 200 pF to GND, V = V . All specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 2. A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE2 AD5628 Resolution 12 12 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 9 Differential Nonlinearity ±0.25 ±0.25 LSB Guaranteed monotonic by design (see Figure 12) AD5648 Resolution 14 14 Bits Relative Accuracy ±2 ±8 ±2 ±4 LSB See Figure 8 Differential Nonlinearity ±0.5 ±0.5 LSB Guaranteed monotonic by design (see Figure 11) AD5668 Resolution 16 16 Bits Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 7 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 10) Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 26) Zero-Code Error Drift ±2 ±2 µV/°C Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 27) Gain Error ±1 ±1 % FSR Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C Offset Error ±6 ±19 ±6 ±19 mV DC Power Supply Rejection Ratio3 –80 –80 dB V ± 10% DD DC Crosstalk3 (External Reference) 10 10 µV Due to full-scale output change, R = 2 kΩ to GND or V L DD 5 5 µV/mA Due to load current change 10 10 µV Due to powering down (per channel) DC Crosstalk3 (Internal Reference) 25 25 µV Due to full-scale output change, R = 2 kΩ to GND or V L DD 10 10 µV/mA Due to load current change OUTPUT CHARACTERISTICS3 Output Voltage Range 0 V 0 V V DD DD Capacitive Load Stability 2 2 nF R = ∞ L 10 10 nF R = 2 kΩ L DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA V = 3 V DD Power-Up Time 4 4 µs Coming out of power-down mode, V = 3 V DD REFERENCE INPUTS Reference Current 40 55 40 55 µA V = V = 5.5 V (per DAC channel) REF DD Reference Input Range 0 V 0 V DD DD Reference Input Impedance 14.6 14.6 kΩ REFERENCE OUTPUT Output Voltage AD5628/AD5648/AD5668-1 1.247 1.253 1.247 1.253 V At ambient Reference TC3 5 15 5 15 ppm/°C TSSOP 15 5 15 ppm/°C LFCSP 15 ppm/°C WLCSP Reference Output Impedance 7.5 7.5 kΩ Rev. J | Page 6 of 30

Data Sheet AD5628/AD5648/AD5668 A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS3 Input Current ±3 ±3 µA All digital inputs Input Low Voltage, V 0.8 0.8 V V = 3 V INL DD Input High Voltage, V 2 2 V V = 3 V INH DD Pin Capacitance 3 3 pF POWER REQUIREMENTS V 2.7 3.6 2.7 3.6 V All digital inputs at 0 or V , DD DD DAC active, excludes load current I (Normal Mode)4 V = V and V = GND DD IH DD IL V = 2.7 V to 3.6 V 1.0 1.5 1.0 1.5 mA Internal reference off DD V = 2.7 V to 3.6 V 1.8 2.25 1.7 2.25 mA Internal reference on DD I (All Power-Down Modes)5 DD V = 2.7 V to 3.6 V 0.2 1 0.2 1 µA V = V and V = GND DD IH DD IL 1 Temperature range is −40°C to +105°C, typical at 25°C. 2 Linearity calculated using a reduced code range of AD5628 (Code 32 to Code 4064), AD5648 (Code 128 to Code 16256), and AD5668 (Code 512 to 65024). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All eight DACs powered down. AC CHARACTERISTICS V = 2.7 V to 5.5 V, R = 2 kΩ to GND, C = 200 pF to GND, V = V . All specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 3. Parameter1, 2 Min Typ Max Unit Test Conditions/Comments3 Output Voltage Settling Time 2.5 7 µs ¼ to ¾ scale settling to ±2 LSB (16-bit resolution) Slew Rate 1.2 V/µs Digital-to-Analog Glitch Impulse 4 nV-s 1 LSB (16-bit resolution) change around major carry (see Figure 42) 19 nV-s From code 0xEA00 to code 0xE9FF (16-bit resolution) Digital Feedthrough 0.1 nV-s Digital Crosstalk 0.2 nV-s Analog Crosstalk 0.4 nV-s DAC-to-DAC Crosstalk 0.8 nV-s Multiplying Bandwidth 320 kHz V = 2 V ± 0.2 V p-p REF Total Harmonic Distortion −80 dB V = 2 V ± 0.1 V p-p, frequency = 10 kHz REF Output Noise Spectral Density 120 nV/√Hz DAC code = 0x8400(16-bit resolution), 1 kHz 100 nV/√Hz DAC code = 0x8400(16-bit resolution), 10 kHz Output Noise 12 μV p-p 0.1 Hz to 10 Hz, DAC code = 0x0000 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical at 25°C. Rev. J | Page 7 of 30

AD5628/AD5648/AD5668 Data Sheet TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2. See Figure 2. DD IL IH V = 2.7 V to 5.5 V. All specifications T to T , unless otherwise noted. DD MIN MAX Table 4. Limit at T , T MIN MAX Parameter V = 2.7 V to 5.5 V Unit Test Conditions/Comments DD t 1 20 ns min SCLK cycle time 1 t 8 ns min SCLK high time 2 t 8 ns min SCLK low time 3 t4 13 ns min SYNC to SCLK falling edge set-up time t 4 ns min Data set-up time 5 t 4 ns min Data hold time 6 t7 0 ns min SCLK falling edge to SYNC rising edge t8 15 ns min Minimum SYNC high time t9 13 ns min SYNC rising edge to SCLK fall ignore t10 0 ns min SCLK falling edge to SYNC fall ignore t11 10 ns min LDAC pulse width low t12 15 ns min SCLK falling edge to LDAC rising edge t13 5 ns min CLR pulse width low t14 0 ns min SCLK falling edge to LDAC falling edge t15 300 ns typ CLR pulse activation time 1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested. t10 t1 t9 SCLK t8 t4 t3 t2 t7 SYNC t6 t5 DIN DB31 DB0 t14 t11 LDAC1 t12 LDAC2 CLR t13 VOUT t15 12ASYSNYCNHCRHORONNOOUUS SL DLDAACC U UPDPDAATET EM MOODDE.E. 05302-002 Figure 2. Serial Write Operation Rev. J | Page 8 of 30

Data Sheet AD5628/AD5648/AD5668 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. THERMAL RESISTANCE A Thermal performance is directly linked to printed circuit board Table 5. (PCB) design and operating environment. Careful attention to Parameter Rating PCB thermal design is required. V to GND −0.3 V to +7 V DD Digital Input Voltage to GND −0.3 V to VDD + 0.3 V Table 6. Thermal Resistance VOUT to GND −0.3 V to VDD + 0.3 V Package Type θJA θJC Unit V /V to GND −0.3 V to V + 0.3 V REFIN REFOUT DD RU-141 121 35 °C/W Operating Temperature Range RU-161 113.5 35 °C/W Industrial −40°C to +105°C CP-16-172 50.6 30 °C/W Storage Temperature Range −65°C to +150°C CB-16-161 45 °C/W Junction Temperature (T ) 150°C JMAX 1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test Reflow Soldering Peak Temperature board. See JEDEC JESD51. Pb Free 260°C 2 Thermal impedance simulated values are based on JEDEC 2S2P thermal test board with nine thermal vias. See JEDEC JESD51. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these ESD CAUTION or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. J | Page 9 of 30

AD5628/AD5648/AD5668 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD5628/AD5668 C C K NYS ADL LCS NID 6 5 4 3 1 1 1 1 VDD 1 12 GND VOUTA 2 TOP VIEW 11 VOUTB LDAC 1 16 SCLK VOUTC 3 (Not to Scale) 10 VOUTD SYNC 1 14 SCLK SYNC 2 15 DIN VOUTE 4 9 VOUTF VVVOOOVUUUTTDTACED 2345 (NAAToODtD Pt5o5 V 66SI2E4ca8W8l/e) 11113210 VDGVOOINNUUDTTBD VVVOOOVUUUTDTTCAED 3456 (NAAAToODDtDPt55o5V666SI24E6cWa888l//e) 11111432 VVGVOOONUUUDTTTBFD 5GVTUO 6V/TUOFERN 7RLC 8HVTUO VREFIN/VRVEOFUOTUGT 67 98 VVOOUUTTHF 05302-003 VREFIN/VRVEOFUOTUGT 78 190 CVOLURTH05302-004 N1.O ETXEPSOSED PAD MVIFERUST BE TIED TO GND. 05302-005 Figure 3. 14-Lead TSSOP (RU-14) Figure 4. 16-Lead TSSOP (RU-16) Figure 5. 16-Lead LFCSP (CP-16-17) Table 7. Pin Function Descriptions Pin No. 14-Lead 16-Lead 16-Lead TSSOP TSSOP LFCSP Mnemonic Description Not 1 15 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers applicable have new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low. 1 2 16 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 2 3 1 V Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply DD should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 3 4 2 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 11 13 11 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 4 5 3 V C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT 10 12 10 V D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT 7 8 6 V / The AD5628/AD5648/AD5668 have a common pin for reference input and reference REFIN V output. When using the internal reference, this is the reference output pin. When REFOUT using an external reference, this is the reference input pin. The default for this pin is as a reference input. Not 9 7 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all applicable LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 5 6 4 V E Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. OUT 9 11 9 V F Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. OUT 6 7 5 V G Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. OUT 8 10 8 V H Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. OUT 12 14 12 GND Ground Reference Point for All Circuitry on the Part. 13 15 13 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 14 16 14 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Not Not EPAD EPAD It is recommended that the exposed paddle be soldered to the ground plane. applicable applicable Rev. J | Page 10 of 30

Data Sheet AD5628/AD5648/AD5668 BALLA1 INDICATOR 1 2 3 4 GND SCLK DIN SYNC A VOUTB LDAC VDD VOUTA B VOUTFVOUTDVOUTEVOUTC C VOUTH CLR VREF VOUTG D (BALNTLoO tS PtIoD V ESIE cDWaOleWN) 05302-006 Figure 6. 16-Ball WLCSP (CB-16-16) Table 8. 16-Ball WLCSP Pin Function Descriptions Pin. No. Mnemonic Description B2 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low. A4 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. B3 V Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a DD 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. B4 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT B1 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT C4 V C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT C2 V D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT D3 V /V The AD5628/AD5648/AD5668 have a common pin for reference input and reference output. When using the REFIN REFOUT internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. D2 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V. C3 V E Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. OUT C1 V F Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. OUT D4 V G Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. OUT D1 V H Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. OUT A1 GND Ground Reference Point for All Circuitry on the Part. A3 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. A2 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Rev. J | Page 11 of 30

AD5628/AD5648/AD5668 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 10 1.0 VDD = 5V VDD = 5V 8 EXT REF = 5V 0.8 EXT REF = 5V TA = 25°C TA = 25°C 6 0.6 4 0.4 B) 2 B) 0.2 NL (LS 0 NL (LS 0 I –2 D –0.2 –4 –0.4 –6 –0.6 –8 –0.8 –100 10k 20k 3C0kODES 40k 50k 60k65535 05302-106 –1.00 10k 20k 3C0kODES 40k 50k 60k65535 05302-109 Figure 7. INL AD5668—External Reference Figure 10. DNL AD5668—External Reference 4 0.5 3 VETADX DT= =R2 5E5°VFC = 5V 0.4 VETADX DT= =R2 5E5°VFC = 5V 0.3 2 0.2 1 INL (LSB) –10 INL (LSB) –00..110 –0.2 –2 –0.3 –3 –0.4 –40 5k CODES 10k 15k16384 05302-107 –0.50 5k CODES 10k 15k16384 05302-110 Figure 8. INL AD5648—External Reference Figure 11. DNL AD5648—External Reference 1.0 0.20 VDD = 5V VDD = 5V 0.8 EXT REF = 5V EXT REF = 5V TA = 25°C 0.15 TA = 25°C 0.6 0.10 0.4 0.05 B) 0.2 B) S S NL (L 0 NL (L 0 I –0.2 D –0.05 –0.4 –0.10 –0.6 –0.15 –0.8 –1.00 500 1000 1500 C2O00D0ES2500 3000 3500 4095 05302-108 –0.200 500 1000 1500 C2O00D0ES2500 3000 3500 4095 05302-111 Figure 9. INL AD5628—External Reference Figure 12. DNL AD5628—External Reference Rev. J | Page 12 of 30

Data Sheet AD5628/AD5648/AD5668 10 1.0 VDD = 5V VDD = 5V INT REF = 2.5V INT REF = 2.5V TA = 25°C TA = 25°C 5 0.5 B) B) NL (LS 0 NL (LS 0 I D –5 –0.5 –100 10k 20k 3C0kODES 40k 50k 60k65535 05302-112 –1.00 10k 20k 3C0kODES 40k 50k 60k65535 05302-115 Figure 13. INL AD5668-2/AD5668-3 Figure 16. DNL AD5668-2/AD5668-3 4 0.5 VDD = 5V VDD = 5V EXT REF = 5V 0.4 EXT REF = 2.5V 3 TA = 25°C TA = 25°C 0.3 2 0.2 1 B) B) 0.1 NL (LS 0 NL (LS 0 I D –0.1 –1 –0.2 –2 –0.3 –3 –0.4 –40 5k CODES 10k 15k16383 05302-113 –0.50 5k CODES 10k 15k16383 05302-116 Figure 14. INL AD5648-2 Figure 17. DNL AD5648-2 1.0 0.20 VDD = 5V VDD = 5V INT REF = 2.5V INT REF = 2.5V TA = 25°C 0.15 TA = 25°C 0.5 0.10 0.05 INL (LSB) 0 DNL (LSB) 0 –0.05 –0.5 –0.10 –0.15 –1.00 500 1000 1500 C2O00D0ES2500 3000 3500 4095 05302-114 –0.200 500 1000 1500 C2O00D0ES2500 3000 3500 4095 05302-117 Figure 15. INL AD5628-2 Figure 18. DNL AD5628-2 Rev. J | Page 13 of 30

AD5628/AD5648/AD5668 Data Sheet 10 1.0 VDD = 3V VDD = 3V 8 INT REF = 1.25V INT REF = 1.25V TA = 25°C TA = 25°C 6 0.5 4 B) 2 B) NL (LS 0 NL (LS 0 I –2 D –4 –0.5 –6 –8 –100 10k 20k 3C0kODES 40k 50k 60k65535 05302-118 –1.00 10k 20k 3C0kODES 40k 50k 60k65535 05302-121 Figure 19. INL AD5668-1 Figure 22. DNL AD5668-1 4 0.5 VDD = 3V VDD = 3V 3 ETAX T= R25E°FC = 1.25V 0.4 ETAX T= R25E°FC = 1.25V 0.3 2 0.2 1 B) B) 0.1 S S L (L 0 L (L 0 N N I –1 D –0.1 –0.2 –2 –0.3 –3 –0.4 –40 5k CODES 10k 15k16383 05302-119 –0.50 5k CODES 10k 15k16383 05302-122 Figure 20. INL AD5648-1 Figure 23. DNL AD5648-1 1.0 0.20 VDD = 3V VDD = 3V INT REF = 1.25V INT REF = 1.25V TA = 25°C 0.15 TA = 25°C 0.5 0.10 0.05 B) B) S S NL (L 0 NL (L 0 I D –0.05 –0.5 –0.10 –0.15 –1.00 500 1000 1500 C2O00D0ES2500 3000 3500 4095 05302-120 –0.200 500 1000 1500 C2O00D0ES2500 3000 3500 4095 05302-123 Figure 21. INL AD5628-1 Figure 24. DNL AD5628-1 Rev. J | Page 14 of 30

Data Sheet AD5628/AD5648/AD5668 0 1.95 VDD = 5V TA = 25°C 1.90 –0.05 1.85 OFFSET ERROR SR)–0.10 V) 1.80 F m R (% –0.15 FULL-SCALE ERROR OR ( 1.75 O R R R ER–0.20 E 1.70 ZERO-SCALE ERROR GAIN ERROR 1.65 –0.25 1.60 –0.30–40 –25 –10 5 T2E0MPE35RATU50RE (°6C5) 80 95 110 125 05302-124 1.552.7 3.1 3.5 3.9VDD (V4).3 4.7 5.1 5.5 05302-127 Figure 25. Gain Error and Full-Scale Error vs. Temperature Figure 28. Zero-Scale Error and Offset Error vs. Supply Voltage 6 21 VDD = 5V 18 5 OFFSET ERROR 15 4 S T OR (mV) 3 ZERO-SCALE ERROR R OF HI 12 ERR MBE 9 U 2 N 6 1 3 0–40 –25 –10 5 T2E0MPE35RATU50RE (°6C5) 80 95 110 125 05302-125 00.85 IDD0 .W90ITH EXTERN0A.9L5 REFERENCE1 .(0m0A) 1.05 05302-128 Figure 26. Zero-Scale Error and Offset Error vs. Temperature Figure 29. IDD Histogram with External Reference –0.16 18 TA = 25°C –0.17 FULL-SCALE ERROR 16 –0.18 14 –0.19 R) TS 12 S–0.20 HI % F OF 10 ERROR (––00..2221 NUMBER 86 –0.23 4 –0.24 GAIN ERROR –0.25 2 –0.262.7 3.1 3.5 3.9VDD (V4).3 4.7 5.1 5.5 05302-126 10.65 1.I7D0D WITH IN1T.7E5RNAL RE1F.E8R0ENCE (m1A.8)5 1.190 05302-129 Figure 27. Gain Error and Full-Scale Error vs. Supply Voltage Figure 30. IDD Histogram with Internal Reference Rev. J | Page 15 of 30

AD5628/AD5648/AD5668 Data Sheet 0.4 1.8 TA = 25°C TA = 25°C 0.3 1.7 1.6 0.2 VDD = 5V E (V) 0.1 1.5 OR VOLTAG –0.10 VDD = 3V, INT REF = 1.25V I (mA)DD 111...234 VDD = 3V R R –0.2 E 1.1 –0.3 1.0 VDD = 5V, INT REF = 2.5V –0.4 0.9 –0.5–10 –8 –6 S–O4URC–E2/SINK0 CURR2ENT (4mA) 6 8 10 05302-130 0.80 10k 2D0IkGITAL 3C0OkDES (D4e0ckimal) 50k 60k 05302-133 Figure 31. Headroom at Rails vs. Source and Sink Figure 34. Supply Current vs. Code 6 2.0 VDD = 5V INT REF = 2.5V FULL SCALE 1.9 5 TA = 25°C 1.8 4 3/4 SCALE 1.7 V) 3 A) 1.6 VDD = 5.5V V (OUT 2 MIDSCALE I (mDD 11..45 VDD = 3.6V 1/4 SCALE 1 1.3 1.2 0 ZERO SCALE 1.1 ––10.03 –0.02 –0.01 CURRE0NT (A) 0.01 0.02 0.03 05302-131 1.0–40 –25 –10 5 T2E0MPE35RATU50RE (°6C5) 80 95 110 125 05302-134 Figure 32. AD5668-2/AD5668-3 Source and Sink Capability Figure 35. Supply Current vs. Temperature 4.0 VDD = 3V 1.48 TA = 25°C 3.5 INT REF = 1.25V TA = 25°C 1.46 3.0 FULL SCALE 1.44 2.5 (V)UT 12..50 MIDSCAL3E/4 SCALE (mA)D 1.42 VO ID 1.40 1.0 1/4 SCALE 0.5 1.38 ZERO SCALE 0 1.36 –0.5 –1.–00.03 –0.02 –0.01 CURRE0NT (A) 0.01 0.02 0.03 05302-132 1.342.7 3.1 3.5 3.9VDD (V4).3 4.7 5.1 5.5 05302-135 Figure 33. AD5668-1 Source and Sink Capability Figure 36. Supply Current vs. Supply Voltage Rev. J | Page 16 of 30

Data Sheet AD5628/AD5648/AD5668 2.3 5.5 TA = 25°C VDD = 5V 5.0 EXT REF = 5V 2.1 4.5 TA = 25°C 1.9 4.0 VDD 3.5 1.7 V) I (mA)DD 1.5 VDD =5V OLTAGE ( 232...500 VOUTA 1.3 V 1.5 1.1 1.0 VDD =3V 0.5 0.9 0 0.70 0.5 1.0 1.5 2.0VLO2G.5IC (V)3.0 3.5 4.0 4.5 5.0 05302-136 –0–.05.0010 –0.0006 –0.000T2IME (s0).0002 0.0006 0.0010 05302-139 Figure 37. Supply Current vs. Logic Input Voltage Figure 40. Power-On Reset to Midscale 6 5.5 VEDXDT =R E5VF = 5V 5.0 VEDXDT =R E5VF = 5V 24TH CLK RISING EDGE 5 TA = 25°C 4.5 TA = 25°C 4.0 4 3.5 V) (V)UT 3 AGE ( 23..50 VO LT VOUTA O 2.0 V 2 1.5 1.0 1 0.5 0 0–2 0 2 TIME (µs)4 6 8 05302-137 –0.5–10 –5 TIME0 (µs) 5 10 05302-140 Figure 38. Full-Scale Settling Time, 5 V Figure 41. Exiting Power-Down to Midscale 5.5 5.0 VEDXDT =R E5VF = 5V T EVXDDT =R E5VF = 5V 4.5 TA = 25°C TA = 25°C 4.0 VDD 3.5 V) E ( 3.0 VOUTA G A 2.5 3 T L O 2.0 V 1.5 1.0 0.5 24TH CLK RISING EDGE VOUTA 0 –0–.05.0010 –0.0006 –0.000T2IME (s0).0002 0.0006 0.0010 05302-138 4 CH3 10.0mV BW CH4 5.0V MT 4 0107n.0s% A CH4 1.50V 05302-141 Figure 39. Power-On Reset to 0 V Figure 42. Digital-to-Analog Glitch Impulse (Negative) Rev. J | Page 17 of 30

AD5628/AD5648/AD5668 Data Sheet 0.0010 VEDXDT =R E5VF = 5V 20 EDXATC RCEOFD =E 2=. 50VxFF00 TA = 25°C 15 0.0005 10 E (V) µV) TUD 0 SE ( 5 LI OI P N 0 H AM–0.0005 PUT C T –5 T U LI O G –10 –0.0010 –15 –0.00150 1 2 3 T4IME (µ5s) 6 7 8 9 05302-142 –200 1 2 3 4 TIM5E (s) 6 7 8 9 10 05302-145 Figure 43. Analog Crosstalk Figure 46. 0.1 Hz to 10 Hz Output Noise Plot, External Reference 0.0020 20 VDD = 5V INT REF = 1.25V EXT REF = 5V DAC CODE = 0xFF00 0.0015 TA = 25°C 15 V) 0.0010 10 UDE ( E (µV) 05 T 0.0005 S H AMPLI 0 PUT NOI 0 C T–05 T U LI O G–0.0005 –10 –0.0010 –15 –0.00150 1 2 3 TIME4 (µs) 5 6 7 8 05302-143 –200 1 2 3 4 TIM5E (s) 6 7 8 9 10 05302-146 Figure 44. DAC-to-DAC Crosstalk Figure 47. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference 6 VDD = 5.5V 800 EXT REF = 5V 4 DAC CODE = 0xFF00 700 µV) 2 Hz) 600 TAGE ( 0 E (nV/ 500 L S OUTPUT VO ––42 OUTPUT NOI 340000 VREF = 2.5V 200 –6 100 VREF = 1.25V –80 1 2 3 4 TIM5E (s) 6 7 8 9 10 05302-144 0100 1k FREQU1E0NkCY (Hz) 100k 1M 05302-147 Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, External Reference Figure 48. Noise Spectral Density, Internal Reference Rev. J | Page 18 of 30

Data Sheet AD5628/AD5648/AD5668 0 10 VDD = 5.5V EXT REF = 5V 0 –20 TA = 25°C VFRREEFQ =U E2VN C± Y0 .=1 V1 0pk-Hpz –10 –40 –20 B) –60 Bm) –30 THD (d –80 V (dOUT–40 CH A –50 CH B –100 CH C –120 ––7600 CCCCCHHHHH DEFGH VETAXD DT= =R2 5E5°.F5C V= 5V –3dB VREF = 2V ± 0.2V p-p –1400 2000 F40R0E0QUENCY6 (0H0z0) 8000 10,00005302-148 –8010 100 1k FR1EkQ0UENC1Y0 0(kHz) 1M 10M 100M 05302-151 Figure 49. Total Harmonic Distortion Figure 52. Multiplying Bandwidth 1.2510 9 VDD = 5.5V TA = 25°C 1.2508 8 1.2506 VDD = EXTERNAL REFERENCE = 5V 7 C) 1.2504 µs) 6 pm/° 1.2502 ME ( E (p G TI 5 ENC 1.2500 SETTLIN 34 REFER 11..22449968 VDD = EXTERNAL REFERENCE = 3V 1.2494 2 1.2492 1 00 1 2 3CAPA4CITIV5E LOA6D (nF)7 8 9 10 05302-149 1.2490 –40 TEMPERA25TURE (°C) 105 05302-152 Figure 50. Settling Time vs. Capacitive Load Figure 53. 1.25 V Reference Temperature Coefficient vs. Temperature 5.5 2.503 EXT REF = 5V 5.0 2.502 4.5 4.0 2.501 C) V) 3.5 pm/°2.500 VOLTAGE ( 223...050 VOUTA FERENCE (p22..449989 1.5 E CLR PULSE R 1.0 2.497 0.5 2.496 0 –0.5–10 –5 TIME0 (µs) 5 10 05302-150 2.495 105 TEMPERA25TURE(°C) –40 05302-154 Figure 51. Hardware CLR Figure 54. 2.5 V Reference Temperature Coefficient vs. Temperature Rev. J | Page 19 of 30

AD5628/AD5648/AD5668 Data Sheet TERMINOLOGY Relative Accuracy Digital-to-Analog Glitch Impulse For the DAC, relative accuracy, or integral nonlinearity (INL), is Digital-to-analog glitch impulse is the impulse injected into the a measure of the maximum deviation in LSBs from a straight line analog output when the input code in the DAC register changes passing through the endpoints of the DAC transfer function. state. It is normally specified as the area of the glitch in nV-s and Figure 7 to Figure 9, Figure 13 to Figure 15, and Figure 19 to is measured when the digital input code is changed by 1 LSB at Figure 21 show plots of typical INL vs. code. the major carry transition (0x7FFF to 0x8000). See Figure 42. Differential Nonlinearity DC Power Supply Rejection Ratio (PSRR) Differential nonlinearity (DNL) is the difference between the PSRR indicates how the output of the DAC is affected by changes measured change and the ideal 1 LSB change between any two in the supply voltage. PSRR is the ratio of the change in V to OUT adjacent codes. A specified differential nonlinearity of ±1 LSB a change in V for full-scale output of the DAC. It is measured DD maximum ensures monotonicity. This DAC is guaranteed mono- in decibels. V is held at 2 V, and V is varied ±10%. REF DD tonic by design. Figure 10 to Figure 12, Figure 16 to Figure 18, and Figure 22 to Figure 24 show plots of typical DNL vs. code. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in Offset Error response to a change in the output of another DAC. It is measured Offset error is a measure of the difference between the actual with a full-scale output change on one DAC (or soft power-down V and the ideal V , expressed in millivolts in the linear OUT OUT and power-up) while monitoring another DAC kept at midscale. region of the transfer function. Offset error is measured on the It is expressed in microvolts. AD5668 with Code 512 loaded into the DAC register. It can be DC crosstalk due to load current change is a measure of the negative or positive and is expressed in millivolts. impact that a change in load current on one DAC has to another Zero-Code Error DAC kept at midscale. It is expressed in microvolts per milliamp. Zero-code error is a measure of the output error when zero Reference Feedthrough code (0x0000) is loaded into the DAC register. Ideally, the Reference feedthrough is the ratio of the amplitude of the signal output should be 0 V. The zero-code error is always positive in at the DAC output to the reference input when the DAC output the AD5628/AD5648/AD5668, because the output of the DAC is not being updated (that is, LDAC is high). It is expressed in cannot go below 0 V. It is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is decibels. expressed in millivolts. Figure 28 shows a plot of typical zero- Digital Feedthrough code error vs. temperature. Digital feedthrough is a measure of the impulse injected into Gain Error the analog output of a DAC from the digital input pins of the device, but is measured when the DAC is not being written to Gain error is a measure of the span error of the DAC. It is the (SYNC held high). It is specified in nV-s and measured with a deviation in slope of the DAC transfer characteristic from the full-scale change on the digital input pins, that is, from all 0s to ideal, expressed as a percentage of the full-scale range. all 1s or vice versa. Zero-Code Error Drift Digital Crosstalk Zero-code error drift is a measure of the change in zero-code Digital crosstalk is the glitch impulse transferred to the output error with a change in temperature. It is expressed in µV/°C. of one DAC at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another DAC. Gain Error Drift It is measured in standalone mode and is expressed in nV-s. Gain error drift is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale Analog Crosstalk range)/°C. Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is Full-Scale Error measured by loading one of the input registers with a full-scale Full-scale error is a measure of the output error when full-scale code change (all 0s to all 1s or vice versa) while keeping LDAC code (0xFFFF) is loaded into the DAC register. Ideally, the high, and then pulsing LDAC low and monitoring the output of output should be V – 1 LSB. Full-scale error is expressed as a DD the DAC whose digital code has not changed. The area of the percentage of the full-scale range. Figure 25 shows a plot of glitch is expressed in nV-s. typical full-scale error vs. temperature. Rev. J | Page 20 of 30

Data Sheet AD5628/AD5648/AD5668 DAC-to-DAC Crosstalk Total Harmonic Distortion (THD) DAC-to-DAC crosstalk is the glitch impulse transferred to the Total harmonic distortion is the difference between an ideal output of one DAC due to a digital code change and subsequent sine wave and its attenuated version using the DAC. The sine output change of another DAC. This includes both digital and wave is used as the reference for the DAC, and the THD is a analog crosstalk. It is measured by loading one of the DACs measure of the harmonics present on the DAC output. It is with a full-scale code change (all 0s to all 1s or vice versa) with measured in decibels. LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Rev. J | Page 21 of 30

AD5628/AD5648/AD5668 Data Sheet THEORY OF OPERATION DAC SECTION R The AD5628/AD5648/AD5668 DACs are fabricated on a CMOS process. The architecture consists of a string of DACs followed by an output buffer amplifier. Each part includes an R internal 1.25 V/2.5 V, 5 ppm/°C reference with an internal gain of 2. Figure 55 shows a block diagram of the DAC architecture. R TO OUTPUT AMPLIFIER VDD VREFIN OUTPUT AMPLIFIER REF (GAIN = ×2) DAC REGISTER VOUT R RESISTOR STRING Figure 55. DACG NADrchitecture 05302-153 R 05302-053 Because the input coding to the DAC is straight binary, the ideal Figure 56. Resistor String output voltage when using an external reference is given by INTERNAL REFERENCE  D  VOUT VREFIN2N  The AD5628/AD5648/AD5668 have an on-chip reference with an internal gain of 2. The AD5628/AD5648/AD5668-1 have a The ideal output voltage when using the internal reference is 1.25 V, 5 ppm/°C reference, giving a full-scale output of 2.5 V; given by the AD5628/AD5648/AD5668-2, AD5668-3 have a 2.5 V, 5 ppm/°C reference, giving a full-scale output of 5 V. The on-  D  V 2V   board reference is off at power-up, allowing the use of an OUT REFOUT 2N  external reference. The internal reference is enabled via a write to the control register (see Table 9). where: D = decimal equivalent of the binary code that is loaded to the The internal reference associated with each part is available at DAC register. the V pin. A buffer is required if the reference output is REFOUT 0 to 4095 for AD5628 (12 bits). used to drive external loads. When using the internal reference, 0 to 16,383 for AD5648 (14 bits). it is recommended that a 100 nF capacitor be placed between 0 to 65,535 for AD5668 (16 bits). the reference output and GND for reference stability. N = the DAC resolution. Individual channel power-down is not supported while using RESISTOR STRING the internal reference. The resistor string section is shown in Figure 56. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. Rev. J | Page 22 of 30

Data Sheet AD5628/AD5648/AD5668 OUTPUT AMPLIFIER Table 9. Command Definitions Command The output buffer amplifier can generate rail-to-rail voltages on C3 C2 C1 C0 Description its output, which gives an output range of 0 V to V . The DD 0 0 0 0 Write to Input Register n amplifier is capable of driving a load of 2 kΩ in parallel with 0 0 0 1 Update DAC Register n 200 pF to GND. The source and sink capabilities of the output 0 0 1 0 Write to Input Register n, update all amplifier can be seen in Figure 32 and Figure 33. The slew rate (software LDAC) is 1.5 V/µs with a ¼ to ¾ scale settling time of 7 µs. 0 0 1 1 Write to and update DAC Channel n SERIAL INTERFACE 0 1 0 0 Power down/power up DAC 0 1 0 1 Load clear code register The AD5628/AD5648/AD5668 have a 3-wire serial interface 0 1 1 0 Load LDAC register (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and 0 1 1 1 Reset (power-on reset) MICROWIRE interface standards as well as most DSPs. See 1 0 0 0 Set up internal REF register Figure 2 for a timing diagram of a typical write sequence. 1 0 0 1 Reserved The write sequence begins by bringing the SYNC line low. Data – – – – Reserved from the DIN line is clocked into the 32-bit shift register on the 1 1 1 1 Reserved falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the AD5628/AD5648/AD5668 compatible with high speed DSPs. On the 32nd falling clock edge, the last Table 10. Address Commands data bit is clocked in and the programmed function is executed, Address (n) that is, a change in DAC register contents and/or a change in A3 A2 A1 A0 Selected DAC Channel the mode of operation. At this stage, the SYNC line can be kept 0 0 0 0 DAC A low or be brought high. In either case, it must be brought high 0 0 0 1 DAC B for a minimum of 15 ns before the next write sequence so that a 0 0 1 0 DAC C falling edge of SYNC can initiate the next write sequence. SYNC 0 0 1 1 DAC D should be idled low between write sequences for even lower power 0 1 0 0 DAC E operation of the part. As is mentioned previously, however, SYNC 0 1 0 1 DAC F 0 1 1 0 DAC G must be brought high again just before the next write sequence. 0 1 1 1 DAC H 1 1 1 1 All DACs Rev. J | Page 23 of 30

AD5628/AD5648/AD5668 Data Sheet INPUT SHIFT REGISTER SYNC INTERRUPT The input shift register is 32 bits wide. The first four bits are In a normal write sequence, the SYNC line is kept low for don’t cares. The next four bits are the command bits, C3 to C0 32 falling edges of SCLK, and the DAC is updated on the 32nd (see Table 9), followed by the 4-bit DAC address, A3 to A0 (see falling edge and rising edge of SYNC. However, if SYNC is brought Table 10) and finally the 16-/14-/12-bit data-word. The data- high before the 32nd falling edge, this acts as an interrupt to the word comprises the 16-/14-/12-bit input code followed by four, write sequence. The shift register is reset, and the write sequence six, or eight don’t care bits for the AD5668, AD5648, and is seen as invalid. Neither an update of the DAC register contents AD5628, respectively (see Figure 57 through Figure 59). These nor a change in the operating mode occurs (see Figure 60). data bits are transferred to the DAC register on the 32nd falling edge of SCLK. DB31(MSB) DB0(LSB) X X X X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DATABITS COMMANDBITS ADDRESSBITS 05302-054 Figure 57. AD5668 Input Register Contents DB31(MSB) DB0(LSB) X X X X C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X DATABITS COMMANDBITS ADDRESSBITS 05302-055 Figure 58. AD5648 Input Register Contents DB31(MSB) DB0(LSB) X X X X C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X DATABITS COMMANDBITS ADDRESSBITS 05302-056 Figure 59. AD5628 Input Register Contents SCLK SYNC DIN DB31 DB0 DB31 DB0 SYNCHINIGVHALBIEDFWORREITE32SNEDQFUAELNLCINEG: EDGE VALIDWORNITTEHSEE3Q2UNEDNFCAEL, LOINUGTPEUDTGUEPDATES 05302-057 Figure 60. SYNC Interrupt Facility Rev. J | Page 24 of 30

Data Sheet AD5628/AD5648/AD5668 INTERNAL REFERENCE REGISTER advantage that the output impedance of the part is known while the part is in power-down mode. There are three different The on-board reference is off at power-up by default. This allows options. The output is connected internally to GND through the use of an external reference if the application requires it. The either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited on-board reference can be turned on or off by a user-program- (three-state). The output stage is illustrated in Figure 61. mable internal REF register by setting Bit DB0 high or low (see Table 11). Command 1000 is reserved for setting the internal The bias generator of the selected DAC(s), output amplifier, REF register (see Table 9). Table 13 shows how the state of the resistor string, and other associated linear circuitry are shut bits in the input shift register corresponds to the mode of down when the power-down mode is activated. The internal operation of the device. reference is powered down only when all channels are powered POWER-ON RESET down. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically The AD5628/AD5648/AD5668 family contains a power-on 4 µs for V = 5 V and for V = 3 V. See Figure 41 for a plot. DD DD reset circuit that controls the output voltage during power-up. The AD5628/AD5648/AD5668-1, -2 DAC output powers up to Any combination of DACs can be powered up by setting PD1 0 V, and the AD5668-3 DAC output powers up to midscale. The and PD0 to 0 (normal operation). The output powers up to the output remains powered up at this level until a valid write value in the input register (LDAC low) or to the value in the sequence is made to the DAC. This is useful in applications DAC register before powering down (LDAC high). where it is important to know the state of the output of the DAC CLEAR CODE REGISTER while it is in the process of powering up. There is also a software executable reset function that resets the DAC to the power-on The AD5628/AD5648/AD5668 have a hardware CLR pin that reset code. Command 0111 is reserved for this reset function is an asynchronous clear input. The CLR input is falling edge (see Table 9). Any events on LDAC or CLR during power-on sensitive. Bringing the CLR line low clears the contents of the reset are ignored. input register and the DAC registers to the data contained in POWER-DOWN MODES the user-configurable CLR register and sets the analog outputs accordingly. This function can be used in system calibration to load The AD5628/AD5648/AD5668 contain four separate modes zero scale, midscale, or full scale to all channels together. These of operation. Command 0100 is reserved for the power-down clear code values are user-programmable by setting two bits, function (see Table 9). These modes are software-programmable Bit DB1 and Bit DB0, in the CLR control register (see Table 15). by setting two bits, Bit DB9 and Bit DB8, in the control register. The default setting clears the outputs to 0 V. Command 0101 is Table 13 shows how the state of the bits corresponds to the reserved for loading the clear code register (see Table 9). mode of operation of the device. Any or all DACs (DAC H to The part exits clear code mode on the 32nd falling edge of the next DAC A) can be powered down to the selected mode by setting write to the part. If CLR is activated during a write sequence, the the corresponding eight bits (DB7 to DB0) to 1. See Table 14 for the contents of the input shift register during power-down/power- write is aborted. up operation. When using the internal reference, only all channel The CLR pulse activation time—the falling edge of CLR to power-down to the selected modes is supported. when the output starts to change—is typically 280 ns. However, if When both bits are set to 0, the part works normally with its outside the DAC linear region, it typically takes 520 ns after normal power consumption of 1.3 mA at 5 V. However, for the executing CLR for the output to start changing (see Figure 51). three power-down modes, the supply current falls to 0.4 µA at See Table 16 for contents of the input shift register during the 5 V (0.2 µA at 3 V). Not only does the supply current fall, but loading clear code register operation. the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the Rev. J | Page 25 of 30

AD5628/AD5648/AD5668 Data Sheet Table 11. Internal Reference Register Internal REF Register (DB0) Action 0 Reference off (default) 1 Reference on Table 12. 32-Bit Input Shift Register Contents for Reference Set-Up Command MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB1 DB0 X 1 0 0 0 X X X X X 1/0 Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Internal REF register Table 13. Power-Down Modes of Operation DB9 DB8 Operating Mode 0 0 Normal operation Power-down modes 0 1 1 kΩ to GND 1 0 100 kΩ to GND 1 1 Three-state Table 14. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function MSB LSB DB31 DB19 to to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X 0 1 0 0 X X X X X PD1 PD0 DAC DAC DAC DAC DAC DAC DAC DAC H G F E D C B A Don’t Command bits (C3 to C0) Address bits (A3 to A0)— Don’t Power- Power-down/power-up channel selection—set bit to 1 to select cares don’t cares cares down mode SRTERSINISGTDOARC AMPLIFIER VOUT POWER-DOWN CIRCUITRY RESISTOR NETWORK 05302-058 Figure 61. Output Stage During Power-Down Table 15. Clear Code Register Clear Code Register DB1 DB0 CR1 CR0 Clears to Code 0 0 0x0000 0 1 0x8000 1 0 0xFFFF 1 1 No operation Table 16. 32-Bit Input Shift Register Contents for Clear Code Function MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0 X 0 1 0 1 X X X X X CR1 CR0 Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Clear code register Rev. J | Page 26 of 30

Data Sheet AD5628/AD5648/AD5668 LDAC FUNCTION pin. See Table 18 for the contents of the input shift register during the load LDAC register mode of operation. The outputs of all DACs can be updated simultaneously using the hardware LDAC pin. POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit, it is helpful to carefully Synchronous LDAC: After new data is read, the DAC registers consider the power supply and ground return layout on the board. are updated on the falling edge of the 32nd SCLK pulse. LDAC The printed circuit board containing the AD5628/AD5648/ can be permanently low or pulsed as in Figure 2. AD5668 should have separate analog and digital sections. If the AD5628/AD5648/AD5668 are in a system where other devices Asynchronous LDAC: The outputs are not updated at the same require an AGND-to-DGND connection, the connection should time that the input registers are written to. When LDAC goes be made at one point only. This ground point should be as close low, the DAC registers are updated with the contents of the as possible to the AD5628/AD5648/AD5668. input register. The power supply to the AD5628/AD5648/AD5668 should be Alternatively, the outputs of all DACs can be updated simulta- bypassed with 10 µF and 0.1 µF capacitors. The capacitors neously using the software LDAC function by writing to Input should physically be as close as possible to the device, with the Register n and updating all DAC registers. Command 0011 is 0.1 µF capacitor ideally right up against the device. The 10 µF reserved for this software LDAC function. capacitors are the tantalum bead type. It is important that the 0.1 µF capacitor has low effective series resistance (ESR) and An LDAC register gives the user extra flexibility and control low effective series inductance (ESI), such as is typical of over the hardware LDAC pin. This register allows the user to common ceramic types of capacitors. This 0.1 µF capacitor select which combination of channels to simultaneously update provides a low impedance path to ground for high frequencies when the hardware LDAC pin is executed. Setting the LDAC bit caused by transient currents due to internal logic switching. register to 0 for a DAC channel means that this channel’s update is controlled by the LDAC pin. If this bit is set to 1, this channel The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the updates synchronously; that is, the DAC register is updated supply line. Clocks and other fast switching digital signals should after new data is read, regardless of the state of the LDAC pin. It be shielded from other parts of the board by digital ground. Avoid effectively sees the LDAC pin as being tied low. (See Table 17 crossover of digital and analog signals if possible. When traces for the LDAC register mode of operation.) This flexibility is cross on opposite sides of the board, ensure that they run at right useful in applications where the user wants to simultaneously angles to each other to reduce feedthrough effects through the update select channels while the rest of the channels are board. The best board layout technique is the microstrip technique, synchronously updating. where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. Writing to the DAC using command 0110 loads the 8-bit LDAC However, this is not always possible with a 2-layer board. register (DB7 to DB0). The default for each channel is 0, that is, the LDAC pin works normally. Setting the bits to 1 means the DAC channel is updated regardless of the state of the LDAC Table 17. LDAC Register Load DAC Register LDAC Bits (DB7 to DB0) LDAC Pin LDAC Operation 0 1/0 Determined by LDAC pin. 1 X—don’t care DAC channels update, overriding the LDAC pin. DAC channels see LDAC as 0. Table 18. 32-Bit Input Shift Register Contents for LDAC Register Function MSB LSB DB31 DB19 to to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X 0 1 1 0 X X X X X DAC DAC DAC DAC DAC DAC DAC DAC H G F E D C B A Don’t Command bits (C3 to C0) Address bits (A3 to A0)— Don’t Setting LDAC bit to 1 overrides LDAC pin cares don’t cares cares Rev. J | Page 27 of 30

AD5628/AD5648/AD5668 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 6.40 4.30 BSC 1 7 PIN 1 0.65 BSC 1.05 1.00 1M.A20X 0.20 0.80 0.09 0.75 0.15 8° 0.60 0.05 0.30 SPLEAATNIENG 0° 0.45 COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 061908-A Figure 62. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0.S6C5 0.19 SPELAANTIENG 0° 0.45 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 63. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. J | Page 28 of 30

Data Sheet AD5628/AD5648/AD5668 4.10 0.35 4.00SQ 0.30 PIN1 3.90 0.25 INDICATOR PIN1 0.65 13 16 INDICATOR BSC 12 1 EXPOSED 2.70 PAD 2.60SQ 2.50 4 9 0.45 8 5 0.20MIN TOPVIEW 0.40 BOTTOMVIEW 0.35 0.80 FORPROPERCONNECTIONOF 0.75 THEEXPOSEDPAD,REFERTO 0.70 00..0052MNOAMX TFHUENCPTINIOCNODNEFSIGCURRIPATTIOIONNSAND COPLANARITY SECTIONOFTHISDATASHEET. SEATING 0.08 PLANE 0.20REF COMPLIANTTOJEDECSTANDARDSMO-220-WGGC. 08-16-2010-C Figure 64. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters 2.645 2.605 SQ 2.565 4 3 2 1 A BALLA1 IDENTIFIER 1.50 B REF C D 0.50 REF TOP VIEW BOTTOM VIEW (BALL SIDE DOWN) (BALL SIDE UP) 0.650 0.595 SIDE VIEW 0.540 COPLANARITY 0.05 SEATING 0.340 0.270 PLANE 00..332000 00..224100 10-23-2012-A Figure 65. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-16) Dimensions shown in millimeters Rev. J | Page 29 of 30

AD5628/AD5648/AD5668 Data Sheet ORDERING GUIDE Package Power-On Internal Model1 Temperature Range Package Description Option Reset to Code Accuracy Reference AD5628BRUZ-1 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±1 LSB INL 1.25 V AD5628BRUZ-1REEL7 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±1 LSB INL 1.25 V AD5628BRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 2.5 V AD5628BRUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 2.5 V AD5628ARUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±2 LSB INL 2.5 V AD5628ARUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±2 LSB INL 2.5 V AD5628ACPZ-1-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±2 LSB INL 1.25 V AD5628ACPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±2 LSB INL 2.5 V AD5628BCPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±1 LSB INL 2.5 V AD5628BCBZ-1-RL7 −40°C to +105°C 16-Ball WLCSP CB-16-16 Zero ±1 LSB INL 1.25 V AD5648BRUZ-1 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±4 LSB INL 1.25 V AD5648BRUZ-1REEL7 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±4 LSB INL 1.25 V AD5648BRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 2.5 V AD5648BRUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 2.5 V AD5648ARUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±8 LSB INL 2.5 V AD5648ARUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±8 LSB INL 2.5 V AD5668BRUZ-1 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 1.25 V AD5668BRUZ-1REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 1.25 V AD5668BRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V AD5668BRUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V AD5668BRUZ-3 −40°C to +105°C 16-Lead TSSOP RU-16 Midscale ±16 LSB INL 2.5 V AD5668BRUZ-3REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Midscale ±16 LSB INL 2.5 V AD5668ARUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 2.5 V AD5668ARUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 2.5 V AD5668ARUZ-3 −40°C to +105°C 16-Lead TSSOP RU-16 Midscale ±32 LSB INL 2.5 V AD5668ARUZ-3REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Midscale ±32 LSB INL 2.5 V AD5668BCPZ-1-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 1.25 V AD5668BCPZ-1500RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 1.25 V AD5668BCPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 2.5 V AD5668BCPZ-2500RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 2.5 V AD5668ACPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±32 LSB INL 2.5 V AD5668ACPZ-3-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Midscale ±32 LSB INL 2.5 V AD5668BCBZ-1-RL7 −40°C to +105°C 16-Ball WLCSP CB-16-16 Zero ±16 LSB INL 1.25 V AD5668BCBZ-1-500R7 −40°C to +105°C 16-Ball WLCSP CB-16-16 Zero ±16 LSB INL 1.25 V AD5668BCBZ-3-RL7 −40°C to +105°C 16-Ball WLCSP CB-16-16 Midscale ±16 LSB INL 2.5 V EVAL-AD5668SDCZ LFCSP Evaluation Board EVAL-AD5668SDRZ TSSOP Evaluation Board 1 Z = RoHS Compliant Part. ©2005–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05302-0-1/17(J) Rev. J | Page 30 of 30

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5628BRUZ-2REEL7 AD5648BRUZ-2 AD5628ARUZ-2 AD5628BCBZ-1-RL7 AD5648BRUZ-2REEL7 AD5628BRUZ-1REEL7 AD5628ACPZ-1-RL7 AD5628BCPZ-2-RL7 AD5628BRUZ-2 AD5628ARUZ-2REEL7 AD5628BRUZ-1 AD5648BRUZ-1REEL7 AD5628ACPZ-2-RL7 AD5648ARUZ-2REEL7 AD5648BRUZ-1 AD5648ARUZ-2