2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit nanoDAC, SPI Interface in LFCSP and SC70 Data Sheet AD5601/AD5611/AD5621 FEATURES FUNCTIONAL BLOCK DIAGRAM 6-lead SC70 and LFCSP packages VDD GND Micropower operation: 100 μA maximum at 5 V Power-down typically to 0.2 μA at 3 V POWER-ON AD5601/AD5611/AD5621 RESET 2.7 V to 5.5 V power supply Guaranteed monotonic by design REF(+) Power-on reset to 0 V with brownout detection REGDIASCTER 12-/1D0A-/C8-BIT OBUUFTFPEURT VOUT 3 power-down functions Low power serial interface with Schmitt-triggered inputs On-chip output buffer amplifier, rail-to-rail operation SYNC interrupt facility COINNPTURTOL CPOONWTREORL-D LOOWGNIC RESISTOR LOGIC NETWORK Minimized zero-code error AD5601 buffered 8-bit DAC B version: ±0.5 LSB INL 06853-001 AD5611 buffered 10-bit DAC SYNC SCLK SDIN B version: ±0.5 LSB INL Figure 1. A version: ±4 LSB INL Table 1. Related Devices AD5621 buffered 12-bit DAC Part Number Description B version: ±1 LSB INL AD5641 2.7 V to 5.5 V, <100 μA, 14-bit nanoDAC in A version: ±6 LSB INL SC70 and LFCSP packages APPLICATIONS They also provide software-selectable output loads while in Voltage level setting power-down mode. The parts are put into power-down mode Portable battery-powered instruments over the serial interface. Digital gain and offset adjustment Programmable voltage and current sources The low power consumption of these parts in normal operation Programmable attenuators makes them ideally suited to portable battery-operated equip- ment. The combination of small package and low power makes GENERAL DESCRIPTION these nanoDAC devices ideal for level-setting requirements, The AD5601/AD5611/AD5621, members of the nanoDAC® such as generating bias or control voltages in space-constrained family, are single, 8-/10-/12-bit, buffered voltage output DACs and power-sensitive applications. that operate from a single 2.7 V to 5.5 V supply, consuming PRODUCT HIGHLIGHTS typically 75 μA at 5 V. The parts come in tiny LFCSP and SC70 1. Available in 6-lead LFCSP and SC70 packages. packages. Their on-chip precision output amplifier allows rail- 2. Low power, single-supply operation. The AD5601/ to-rail output swing to be achieved. The AD5601/AD5611/ AD5611/AD5621 operate from a single 2.7 V to 5.5 V AD5621 utilize a versatile 3-wire serial interface that operates at supply with a maximum current consumption of 100 μA, clock rates up to 30 MHz and is compatible with SPI, QSPI™, making them ideal for battery-powered applications. MICROWIRE™, and DSP interface standards. 3. The on-chip output buffer amplifier allows the output of The reference for the AD5601/AD5611/AD5621 is derived the DAC to swing rail-to-rail with a typical slew rate of from the power supply inputs and, therefore, gives the widest 0.5 V/μs. dynamic output range. The parts incorporate a power-on reset 4. Reference is derived from the power supply. circuit, which ensures that the DAC output powers up to 0 V 5. High speed serial interface with clock speeds up to and remains there until a valid write to the device takes place. 30 MHz. Designed for very low power consumption. The AD5601/AD5611/AD5621 contain a power-down feature The interface powers up only during a write cycle. that reduces current consumption to typically 0.2 μA at 3 V. 6. Power-down capability. When powered down, the DAC typically consumes 0.2 μA at 3 V. Power-on reset with brownout detection. Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5601/AD5611/AD5621 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Output Amplifier ........................................................................ 14  Applications ....................................................................................... 1  Serial Interface ............................................................................ 14  General Description ......................................................................... 1  Input Shift Register .................................................................... 14  Functional Block Diagram .............................................................. 1  SYNC Interrupt .......................................................................... 14  Product Highlights ........................................................................... 1  Power-On Reset .......................................................................... 16  Revision History ............................................................................... 2  Power-Down Modes .................................................................. 16  Specifications ..................................................................................... 3  Microprocessor Interfacing ....................................................... 16  Timing Characteristics ................................................................ 4  Applications Information .............................................................. 18  Absolute Maximum Ratings ............................................................ 5  Choosing a Reference as Power Supply for the ESD Caution .................................................................................. 5  AD5601/AD5611/AD5621 ....................................................... 18  Pin Configurations and Function Descriptions ........................... 6  Bipolar Operation Using the AD5601/AD5611/AD5621 ..... 18  Typical Performance Characteristics ............................................. 7  Using the AD5601/AD5611/AD5621 with a Galvanically Isolated Interface ........................................................................ 19  Terminology .................................................................................... 13  Power Supply Bypassing and Grounding ................................ 19  Theory of Operation ...................................................................... 14  Outline Dimensions ....................................................................... 20  DAC Section ................................................................................ 14  Ordering Guide .......................................................................... 21  Resistor String ............................................................................. 14  REVISION HISTORY 2/16—Rev. G to Rev. H 12/07—Rev. B to Rev. C Changes to Noise Parameter, Table 2 ............................................. 3 Changes to Features .......................................................................... 1 Changes to Serial Interface Section .............................................. 14 Changes to Table 2 ............................................................................. 3 Changes to AD5601/AD5611/AD5621 to ADSP-2101 6/13—Rev. F to Rev. G Interface Section ............................................................................. 16 Change to Ordering Guide ............................................................ 21 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 20 2/12—Rev. E to Rev. F Added 6-Lead LFCSP ......................................................... Universal 7/05—Rev. A to Rev. B Changes to Features Section, General Description Section, Changes to Figure 48...................................................................... 17 Table 1, and Product Highlights Section ....................................... 1 Changes to Galvanically Isolated Interface Section ................... 19 Changes to Table 4 ............................................................................ 5 Changes to Figure 52...................................................................... 19 Added Figure 4; Renumbered Sequentially .................................. 6 Changes to Table 5 ............................................................................ 6 3/05—Rev. 0 to Rev. A Changes to Choosing a Reference as Power Supply for the Changes to Timing Characteristics ................................................. 4 AD5601/AD5611/AD5621 Section .............................................. 18 Changes to Absolute Maximum Ratings ........................................ 5 Updated Outline Dimensions ....................................................... 20 Changes to Full Scale Error Section ................................................ 7 Changes to Ordering Guide .......................................................... 21 Changes to Figure 20...................................................................... 10 Changes to Theory of Operation .................................................. 14 7/10—Rev. D to Rev. E Changes to Power Down Modes .................................................. 15 Changes to Figure 1 .......................................................................... 1 1/05—Revision 0: Initial Version 5/08—Rev. C to Rev. D Changes to General Description Section ...................................... 1 Changes to Table 2 ............................................................................ 3 Changes to Choosing a Reference as Power Supply for the AD5601/AD5611/AD5621 Section .............................................. 18 Changes to Ordering Guide .......................................................... 20 Rev. H | Page 2 of 21

Data Sheet AD5601/AD5611/AD5621 SPECIFICATIONS V = 2.7 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; all specifications T to T , unless otherwise noted. Temperature range DD L L MIN MAX for A/B grades is −40°C to +125°C, typical at 25°C. Table 2. A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE AD5601 Resolution 8 Bits Relative Accuracy1 (INL) ±0.5 LSB Differential Nonlinearity (DNL) ±0.5 LSB Guaranteed monotonic by design AD5611 Resolution 10 Bits Relative Accuracy1 (INL) ±4 ±0.5 LSB Differential Nonlinearity (DNL) ±0.5 ±0.5 LSB Guaranteed monotonic by design AD5621 Resolution 12 Bits Relative Accuracy1 (INL) ±6 ±1 LSB Differential Nonlinearity (DNL) ±0.5 ±0.5 LSB Guaranteed monotonic by design Zero-Code Error 0.5 10 0.5 10 mV All 0s loaded to DAC register Full-Scale Error ±0.5 ±0.5 mV All 1s loaded to DAC register Offset Error ±0.063 ±10 ±0.063 ±10 mV Gain Error ±0.0004 ±0.037 ±0.0004 ±0.037 %FSR Zero-Code Error Drift 5.0 5.0 μV/°C Gain Temperature Coefficient 2.0 2.0 ppm FSR/°C OUTPUT CHARACTERISTICS2 Output Voltage Range 0 V 0 V V DD DD Output Voltage Settling Time 6 10 6 10 μs Code ¼ scale to ¾ scale Slew Rate 0.5 0.5 V/μs Capacitive Load Stability 470 470 pF R = ∞ L 1000 1000 pF R = 2 kΩ L Output Noise Spectral Density 120 120 nV/Hz DAC code = midscale,1 kHz Noise 2 2 μV p-p DAC code = midscale, 0.1 Hz to 10 Hz bandwidth Digital-to-Analog Glitch Impulse 5 5 nV-s 1 LSB change around major carry Digital Feedthrough 0.2 0.2 nV-s Short-Circuit Current 15 15 mA V = 3 V/5 V DD DC Output Impedance 0.5 0.5 Ω LOGIC INPUTS Input Current3 ±2 ±2 μA Input High Voltage, V 1.8 1.8 V V = 4.7 V to 5.5 V INH DD 1.4 1.4 V V = 2.7 V to 3.6 V DD Input Low Voltage, V 0.8 0.8 V V = 4.7 V to 5.5 V INL DD 0.6 0.6 V V = 2.7 V to 3.6 V DD Pin Input Capacitance 3 3 pF Rev. H | Page 3 of 21

AD5601/AD5611/AD5621 Data Sheet A Grade B Grade Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS V 2.7 5.5 2.7 5.5 V All digital inputs at 0 V or V DD DD I for Normal Mode DAC active and excluding load DD current V = ±4.5 V to ±5.5 V 75 100 75 100 μA V = V and V = GND DD IH DD IL V = ±2.7 V to ±3.6 V 60 90 60 90 μA V = V and V = GND DD IH DD IL I for All Power-Down Modes V = V and V = GND DD IH DD IL V = ±4.5 V to ±5.5 V 0.5 0.5 μA V = V and V = GND DD IH DD IL V = ±2.7 V to ±3.6 V 0.2 0.2 μA V = V and V = GND DD IH DD IL POWER EFFICIENCY I /I 96 96 % I = 2 mA and V = ±5 V OUT DD LOAD DD 1 Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252. 2 Guaranteed by design and characterization, not production tested. 3 Total current flowing into all pins. TIMING CHARACTERISTICS V = 2.7 V to 5.5 V; all specifications T to T , unless otherwise noted. See Figure 2. DD MIN MAX Table 3. Parameter Limit1 Unit Test Conditions/Comments t2 33 ns min SCLK cycle time 1 t 5 ns min SCLK high time 2 t 5 ns min SCLK low time 3 t 10 ns min SYNC to SCLK falling edge setup time 4 t 5 ns min Data setup time 5 t 4.5 ns min Data hold time 6 t 0 ns min SCLK falling edge to SYNC rising edge 7 t 20 ns min Minimum SYNC high time 8 t 13 ns min SYNC rising edge to next SCLK falling edge ignored 9 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Maximum SCLK frequency is 30 MHz. t t t t 4 2 1 9 SCLK t8 t3 t7 SYNC t 6 SDIN D15 D14 D2 t5 D1 D0 D15 D14 06853-002 Figure 2. Timing Diagram Rev. H | Page 4 of 21

Data Sheet AD5601/AD5611/AD5621 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 4. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational V to GND −0.3 V to +7.0 V DD section of this specification is not implied. Operation beyond Digital Input Voltage to GND −0.3 V to V + 0.3 V DD the maximum operating conditions for extended periods may V to GND −0.3 V to V + 0.3 V OUT DD affect product reliability. Operating Temperature Range Industrial (A/B Grades) −40°C to +125°C Storage Temperature Range −65°C to +160°C ESD CAUTION Maximum Junction Temperature 150°C SC70 Package θ Thermal Impedance 433.34°C/W JA θ Thermal Impedance 149.47°C/W JC LFCSP Package θ Thermal Impedance 95°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD (Human Body Model) 2.0 kV Rev. H | Page 5 of 21

AD5601/AD5611/AD5621 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SYNC 1 AD5601/ 6 VOUT VDD 1 AADD55661011// 6 VOUT AD5611/ SCLK 2 AD5621 5 GND SCLK 2 AD5621 5 GND TOP VIEW SDIN 3 (Not to Scale) 4 SYNC SDIN 3 (NToOt Pto V SIEcWale) 4 VDD 06853-003 N1.O CTOENSN:ECT THE EXPOSEDPADTO GND. 06853-053 Figure 3. 6-Lead SC70 Pin Configuration Figure 4. 6-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions SC70 LFCSP Pin No. Pin No. Mnemonic Description 1 4 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the clocks that follow. The DAC is updated following the 16th clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 2 2 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 3 3 SDIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 4 1 V Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2.7 V to 5.5 V. V should be DD DD decoupled to GND. 5 5 GND Ground. Ground reference point for all circuitry on the AD5601/AD5611/AD5621. 6 6 V Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. OUT EP Exposed Pad. Connect to GND. Rev. H | Page 6 of 21

Data Sheet AD5601/AD5611/AD5621 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 2.5 VDD = VREF = 5V VDD = VREF = 5V TA = 25°C 2.0 TA = 25°C B) S 1.5 L 0.5 R ( O 1.0 B) RR S E 0.5 ERROR (L 0 DJUSTED –0.50 L A N N I –0.5 AL U–1.0 OT–1.5 T –2.0 –1.064 564 1064 1564DAC20 C6O4DE2564 3064 3564 4064 06853-004 –2.564 564 1064 1564DAC2 0C6O4DE2564 3064 3564 4064 06853-007 Figure 5. Typical AD5621 INL Figure 8. AD5621 Total Unadjusted Error (TUE) 0.5 0.6 VDD = VREF = 5V VDD = VREF = 5V 0.4 TA = 25°C TA = 25°C B) 0.4 0.3 S L B) 0.2 ROR ( 0.2 LS 0.1 ER OR ( 0 TED 0 R S R U INL E––00..21 UNADJ–0.2 L A –0.3 T O–0.4 T –0.4 –0.516 116 216 316 416DAC5 1C6ODE616 716 816 916 06853-005 –0.616 116 216 316 416DAC5 C16ODE616 716 816 916 06853-008 Figure 6. Typical AD5611 INL Figure 9. AD5611 Total Unadjusted Error (TUE) 0.100 0.20 VDD = VREF = 5V VDD = VREF = 5V 0.075 TA = 25°C 0.15 TA = 25°C B) S 0.050 R (L 0.10 O R (LSB) 0.025 ED ERR 0.05 O 0 T 0 R S R U INL E–0.025 UNADJ –0.05 –0.050 AL –0.10 T O T –0.075 –0.15 –0.1004 54 10D4AC CODE154 204 06853-006 –0.204 54 104DAC CODE154 204 06853-009 Figure 7. Typical AD5601 INL Figure 10. AD5601 Total Unadjusted Error (TUE) Rev. H | Page 7 of 21

AD5601/AD5611/AD5621 Data Sheet 0.20 12 VDD = 5V VDD = 3V VDD = 5V 0.15 TA = 25°C VVIIHL = = G DNVDDD VVIIHL = = G DNVDDD 10 TA = 25°C TA = 25°C 0.10 S R (LSB) 0.05 DEVICE 8 RO 0 0 OF 6 R R E E DNL –0.05 NUMB 4 –0.10 2 –0.15 –0.2064 564 1064 1564DAC2 0C6O4DE2564 3064 3564 06853-010 0 0.054560.05527 0.05599 0.05671 0.05742 0.05814 IDD0.05885 (m0.06648A0.06710) 0.067730.068350.068970.069600.070220.070840.071470.072090.072710.0733406853-013 Figure 11. Typical AD5621 DNL Figure 14. IDD Histogram (3 V/5 V) 0.05 VDD = 5V TA = 25°C 0.04 TA = 25°C VDD = 5V CH1 = SCLK 0.03 0.02 B) LS 0.01 R ( O 0 R R L E–0.01 N D–0.02 –0.03 CH2 = VOUT –0.04 –0.0516 116 216 316 416DAC5 1C6ODE616 716 816 916 06853-011 CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV 06853-014 Figure 12. Typical AD5611 DNL Figure 15. Full-Scale Settling Time 0.010 0.008 VTAD D= =2 55°VC CH1 = SCLK TVAD D= =2 55°VC 0.006 0.004 B) S 0.002 L R ( O 0 R ER –0.002 CH2 = VOUT L N D –0.004 –0.006 ––00..001008 4 54 10D4AC CODE154 204 06853-012 CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV 06853-015 Figure 13. Typical AD5601 DNL Figure 16. Half-Scale Settling Time Rev. H | Page 8 of 21

Data Sheet AD5601/AD5611/AD5621 VDD = 5V VDD TVAD D= =2 55°VC TA = 25°C MIDSCALE LOADED CH1 CH1 VOUT = 70mV CH2 CH1 1V, CH2 20mV, TIME BASE = 20µs/DIV 06853-016 CH1 5µV/DIV 06853-019 Figure 17. Power-On Reset to 0 V Figure 20. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth CH1 VDD VTAD D= =2 55°VC CH1 VTAD D= =2 55°VC VOUT CH2 CH2 VOUT CH1 1V, CH2 5V, TIME BASE = 50µs/DIV 06853-017 CH1 5V, CH2 1V, TIME BASE = 2µs/DIV 06853-020 Figure 18. VDD vs. VOUT Figure 21. Exiting Power-Down Mode 2.458 140 3/4 SCALE 2.456 FULL SCALE 120 2.454 MIDSCALE 2.452 100 (V)2.450 1/4 SCALE UDE2.448 80 AMPLIT22..444464 I (µA)DD 60 ZERO SCALE 2.442 40 TA = 25°C 2.440 VDD = 5V LOAD = 2kΩ AND 220pF 20 2.438 CODE 0x2000 TO 0x1FFF 10ns/SAMPLE NUMBER 2.4360 100 S2A0M0PLE NUM3B00ER 400 500 06853-018 00 5 FR10EQUENCY (1M5Hz) 20 25 06853-021 Figure 19. Digital-to-Analog Glitch Energy Figure 22. IDD vs. SCLK vs. Code Rev. H | Page 9 of 21

AD5601/AD5611/AD5621 Data Sheet 700 0.3 V/ Hz) 600 TUVADN DL= O =2 A55°DVCED OUTPUT 0.2 VDD = 5V AD5621 MAX INL ERROR n Y ( 0.1 AD5611 MAX INL ERROR AD5601 MAX INL ERROR T SI 500 EN B) 0 D S PECTRAL 340000 ERROR (L ––00..21 AD5611 MIN INL ERROR AD5601 MIN INL ERROR SE S MIDSCALE INL –0.3 OI 200 T N FULL SCALE –0.4 PU 100 AD5621 MIN INL ERROR OUT ZERO SCALE –0.5 0100 1kFREQUENCY (Hz)10k 100k 06853-022 –0.6–40 –20 0 T2E0MPERA40TURE (6°0C) 80 100 120 06853-025 Figure 23. Noise Spectral Density Figure 26. INL vs. Temperature (5 V) 70 0.08 VDD = 5V TA = 25°C 0.07 VDD = 5V 60 0.06 AD5621 MAX DNL ERROR 0.05 0.04 50 0.03 VDD = 3V SB) 0.02 AD5611 MAX DNL ERROR A)40 R (L 0.01 I (µDD30 ERRO–0.010 NL –0.02 AD5611 MIN DNL ERROR AD5601 MAX DNL ERROR D–0.03 AD5601 MIN DNL ERROR 20 –0.04 –0.05 10 –0.06 AD5621 MIN DNL ERROR –0.07 00 2000 4000 6D0I0G0ITAL8 0I0N0PUT1 0C0O00DE12000 14000 16000 06853-023 –0.08–40 10 TEM6P0ERATURE 1(°1C0) 160 06853-026 Figure 24. Supply Current vs. Digital Input Code Figure 27. DNL vs. Temperature (5 V) 0.8 0.00149 VDD = 5V VDD = 5V TA = 25°C AD5621 ZERO-CODE ERROR 0.6 DAC LOADED WITH ZERO-SCALE CODE 0.00099 0.4 V (V)OUT 0.2 OR (LSB) 0.00049 AAADDD555666010111 FZZUEELRRLOO-S--CCCOOADDLEEE EEERRRRRROOORRR ∆ 0.0 R R E –0.2 –0.00001 DAC LOADED WITH FULL-SCALE CODE –0.4 AD5611 FULL-SCALE ERROR –0.6 –15 –10 –5 I (0mA) 5 10 15 06853-024 –0.00051–40AD5–62201 FUL0L-SCA–L2T0EE EMRPR4E0ORRATU6R0E (°C8)0 100 120 14006853-027 Figure 25. Sink and Source Capability Figure 28. Zero-Code Error and Full-Scale Error vs. Temperature Rev. H | Page 10 of 21

Data Sheet AD5601/AD5611/AD5621 1.5 0.10 1.3 AD5621 MAX TUE 0.09 B) S 1.1 0.08 L ( OR 0.9 0.07 VDD = 5V R ER 0.7 0.06 D A) DJUSTE 00..35 AADD55660111 MMAAXX TTUUEE I(mDD 00..0045 VDD = 3V A N U 0.1 0.03 L A T–0.1 0.02 O T AD5601 MIN TUE –0.3 AD5611 MIN TUE 0.01 AD5621 MIN TUE –0.5–40 –20 0 20TEMP4E0RATU6R0E (°C)80 100 120 140 06853-028 0–40 –20 0 20TEMP4E0RATU6R0E (°C)80 100 120 140 06853-031 Figure 29. Total Unadjusted Error (TUE) vs. Temperature (5 V) Figure 32. Supply Current vs. Temperature (3 V/5 V Supply) 1.5 TA = 25°C 1.4 0.4 1.3 1.2 AD5621 MAX INL ERROR 1.1 0.2 mV) 1.0 VDD = 5V B) AD5611 MAX INL ERROR AD5601 MAX INL ERROR R ( 0.9 LS SET ERRO 000...678 VDD = 3V L ERROR ( –0.20 AADD55661011 MMIINN IINNLL EERRRROORR FF 0.5 IN O 0.4 0.3 –0.4 0.2 AD5621 MIN INL ERROR 0.1 0–40 –20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 06853-029 –0.62.7 3.2 S3U.7PPLY VO4L.T2AGE (V)4.7 5.2 06853-032 Figure 30. Offset Error vs. Temperature (3 V/5 V Supply) Figure 33. INL vs. Supply Voltage at 25°C 0 0.10 0.09 TA = 25°C 0.08 –0.002 0.07 VDD = 5V 0.06 –0.004 0.05 GAIN ERROR (%FSR)–––000...000100086 VDD = 3V DNL ERROR (LSB)––––00000000........00000000432112340 AADD5566A00D115 MM61AIN1XA MD DDIN5NN6L L1D E 1ENR MRLR RAEOOXRRA RRDDON56RL2 E1 RMRAOXR DNL ERROR –0.012 –0.05 –0.06 –0.07 –0.014 AD5621 MIN DNL ERROR –0.08 –0.09 –0.016–40 –20 0 20TEMP4E0RATU6R0E (°C)80 100 120 140 06853-030 –0.102.7 3.2 3.7 SU4.P2PLY V4O.7LTAG5E. 2(V) 5.7 6.2 6.7 06853-033 Figure 31. Gain Error vs. Temperature (3 V/5 V Supply) Figure 34. DNL vs. Supply Voltage at 25°C Rev. H | Page 11 of 21

AD5601/AD5611/AD5621 Data Sheet 1.5 0.10 TA = 25°C TA = 25°C 1.3 AD5621 MAX TUE 0.09 LSB) 1.1 0.08 R ( 0.07 RO 0.9 ER 0.06 D 0.7 A) USTE 0.5 m (DD 0.05 DJ AD5611 MAX TUE I 0.04 NA 0.3 U AD5621 MIN TUE 0.03 L A 0.1 T 0.02 O T –0.1 AADD55660111 MMAINX T TUUEE 0.01 –0.32.7AD5601 M3.I2N TUE S3U.7PPLY VOL4T.2AGE (V)4.7 5.2 06853-034 02.7 3.2 S3U.7PPLY VOL4.T2AGE (V)4.7 5.2 06853-036 Figure 35. Total Unadjusted Error (TUE) vs. Supply Voltage at 25°C Figure 37. Supply Current vs. Supply Voltage at 25°C 0.0010 450 TA = 25°C TA = 25°C SCLK/SDIN AD5621 ZERO-CODE ERROR 400 INCREASING SCLK/SDIN 0.0008 VDD = 5V DECREASING 350 VDD = 5V 0.0006 300 B) SCLK/SDIN LS 0.0004 AD5601 FULL-SCALE ERROR A) 250 INCREASING R ( (µ VDD = 3V RRO 0.0002 AD5611 ZERO-CODE ERROR IDD200 E AD5601 ZERO-CODE ERROR 150 0 AD5611 FULL-SCALE ERROR 100 –0.0002 AD5621 FULL-SCALE ERROR 50 –0.00042.7 3.2 3.7 SU4P.2PLY V4O.7LTAGE5. 2(V) 5.7 6.2 6.7 06853-035 00 SCLK/SD1IN DECRE2ASINGV LVODGD3IC = ( V3V) 4 5 606853-037 Figure 36. Zero-Code Error and Full-Scale Error vs. Supply Voltage at 25°C Figure 38. SCLK/SDIN vs. Logic Voltage Rev. H | Page 12 of 21

Data Sheet AD5601/AD5611/AD5621 TERMINOLOGY Relative Accuracy Total Unadjusted Error For the DAC, relative accuracy or integral nonlinearity (INL) is Total unadjusted error (TUE) is a measure of the output error, a measure of the maximum deviation, in LSBs, from a straight taking all the various errors into account. See Figure 8 to line passing through the endpoints of the DAC transfer func- Figure 10 for plots of typical TUE vs. code. tion. See Figure 5 to Figure 7 for plots of typical INL vs. code. Zero-Code Error Drift Differential Nonlinearity Zero-code error drift is a measure of the change in zero-code Differential nonlinearity (DNL) is the difference between the error with a change in temperature. It is expressed in μV/°C. measured change and the ideal 1 LSB change between any two Gain Temperature Coefficient adjacent codes. A specified differential nonlinearity of ±1 LSB Gain temperature coefficient is a measure of the change in gain maximum ensures monotonicity. This DAC is guaranteed error with changes in temperature. It is expressed in (ppm of monotonic by design. See Figure 11 to Figure 13 for plots of full-scale range)/°C. typical DNL vs. code. Digital-to-Analog Glitch Impulse Zero-Code Error Digital-to-analog glitch impulse is the impulse injected into the Zero-code error is a measure of the output error when zero analog output when the input code in the DAC register changes code (0x0000) is loaded to the DAC register. Ideally, the output state. It is normally specified as the area of the glitch in nV-s should be 0 V. The zero-code error is always positive in the and is measured when the digital input code is changed by AD5601/AD5611/AD5621 because the output of the DAC cannot 1 LSB at the major carry transition (0x2000 to 0x1FFF). See go below 0 V. Zero-code error is due to a combination of the Figure 19. offset errors in the DAC and output amplifier. Zero-code error Digital Feedthrough is expressed in mV. See Figure 28 for a plot of zero-code error Digital feedthrough is a measure of the impulse injected into vs. temperature. the analog output of the DAC from the digital inputs of the Full-Scale Error DAC, but is measured when the DAC output is not updated. Full-scale error is a measure of the output error when full-scale It is specified in nV-s and is measured with a full-scale code code (0xFFFF) is loaded to the DAC register. Ideally, the output change on the data bus—from all 0s to all 1s and vice versa. should be V − 1 LSB. Full-scale error is expressed in mV. See DD Figure 28 for a plot of full-scale error vs. temperature. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percent of the full-scale range. Rev. H | Page 13 of 21

AD5601/AD5611/AD5621 Data Sheet THEORY OF OPERATION DAC SECTION OUTPUT AMPLIFIER The AD5601/AD5611/AD5621 DACs are fabricated on a The output buffer amplifier is capable of generating rail-to-rail CMOS process. The architecture consists of a string DAC voltages on its output, giving an output range of 0 V to V . It is DD followed by an output buffer amplifier. Figure 39 is a block capable of driving a load of 2 kΩ in parallel with 1000 pF to diagram of the DAC architecture. GND. The source and sink capabilities of the output amplifier VDD are shown in Figure 25. The slew rate is 0.5 V/μs, with a half- scale settling time of 8 μs with the output loaded. REF (+) SERIAL INTERFACE RESISTOR DAC REGISTER NETWORK VOUT The AD5601/AD5611/AD5621 have a 3-wire serial interface REF (–) OUTPUT (SYNC, SCLK, and SDIN) that is compatible with SPI, QSPI, AMPLIFIER and MICROWIRE interface standards as well as most DSPs. See GND 06853-038 Figure 2 for a timing diagram of a typical write sequence. Figure 39. DAC Architecture The write sequence begins by bringing the SYNC line low. Data from the SDIN line is clocked into the 16-bit shift register on Because the input coding to the DAC is straight binary, the ideal the falling edge of SCLK. The serial clock frequency can be as output voltage is given by high as 30 MHz, making the AD5601/AD5611/AD5621 com- D patible with high speed DSPs. On the 16th falling clock edge, V V   OUT DD 2n the last data bit is clocked in and the programmed function is executed (a change in DAC register contents and/or a change where: in the mode of operation). At this stage, the SYNC line may be D is the decimal equivalent of the binary code that is loaded to kept low or brought high. In either case, it must be brought high the DAC register. n is the bit resolution of the DAC. for a minimum of 20 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. RESISTOR STRING Because the SYNC buffer draws more current when V = 1.8 V The resistor string structure is shown in Figure 40. It is simply a IN than it does when V = 0.8 V, SYNC should be idled low string of resistors, each of Value R. The code loaded to the DAC IN between write sequences for even lower power operation of the register determines at which node on the string the voltage is part, as mentioned previously. However, it must be brought tapped off to be fed into the output amplifier. The voltage is high again just before the next write sequence. tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaran- INPUT SHIFT REGISTER teed monotonic. The input shift register is 16 bits wide (see Figure 41). The first two bits are control bits, which control the operating mode of the part (normal mode or any one of three power-down R modes). For a complete description of the various modes, see the Power-Down Modes section. For the AD5621, the next R 12 bits are the data bits, which are transferred to the DAC register on the 16th falling edge of SCLK. The information in R TO OUTPUT the last two bits is ignored by the AD5621. See Figure 42 and AMPLIFIER Figure 43 for the AD5611 and AD5601 input shift register map. SYNC INTERRUPT In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th falling edge. However, if SYNC is brought high before the R 16th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a R 06853-039 change in the operating mode occurs (see Figure 44). Figure 40. Resistor String Structure Rev. H | Page 14 of 21

Data Sheet AD5601/AD5611/AD5621 DB15 (MSB) DB0 (LSB) PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X DATA BITS 0 0 NORMAL OPERATION 0 1 1kΩ TO GND 11 01 1T0H0RkEΩE T-SOT GATNED POWER-DOWN MODES 06853-040 Figure 41. AD5621 Input Register Contents DB15 (MSB) DB0 (LSB) PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DATA BITS 0 0 NORMAL OPERATION 0 1 1kΩ TO GND 11 01 1T0H0RkEΩE T-SOT GATNED POWER-DOWN MODES 06853-041 Figure 42. AD5611 Input Register Contents DB15 (MSB) DB0 (LSB) PD1 PD0 D8 D7 D6 D5 D4 D3 D2 D1 X X X X X X DATA BITS 0 0 NORMAL OPERATION 0 1 1kΩ TO GND 11 01 1T0H0RkEΩE T-SOT GATNED POWER-DOWN MODES 06853-042 Figure 43. AD5601 Input Register Contents SCLK SYNC SDIN DB15 DB0 DB15 DB0 06853-043 INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE, OUTPUT UPDATES SYNC HIGH BEFORE 16TH FALLING EDGE ON THE 16TH FALLING EDGE Figure 44. SYNC Interrupt Facility Rev. H | Page 15 of 21

AD5601/AD5611/AD5621 Data Sheet POWER-ON RESET MICROPROCESSOR INTERFACING The AD5601/AD5611/AD5621 contain a power-on reset circuit AD5601/AD5611/AD5621 to ADSP-2101 Interface that controls the output voltage during power-up. The DAC Figure 46 shows a serial interface between the AD5601/ register is filled with 0s and the output voltage is 0 V. It remains AD5611/AD5621 and the ADSP-2101. The ADSP-2101 should there until a valid write sequence is made to the DAC. This is be set up to operate in SPORT transmit alternate framing mode. useful in applications in which it is important to know the state The ADSP-2101 SPORT is programmed through the SPORT of the DAC output while it is in the process of powering up. control register and should be configured as follows: internal POWER-DOWN MODES clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register The AD5601/AD5611/AD5621 have four separate modes of after the SPORT is enabled. operation. These modes are software-programmable by setting two bits (DB15 and DB14) in the control register. Table 6 shows ADSP-2101* AD5601/AD5611/ how the state of the bits corresponds to the operating mode of AD5621* the device. TFS SYNC Table 6. Operating Modes of the AD5601/AD5611/AD5621 DT SDIN D0 B15 0D B14 NOopremraatl ionpge Mraotidoen SCLK SCLK 06853-045 Power-down modes: *ADDITIONAL PINS OMITTED FOR CLARITY Figure 46. AD5601/AD5611/AD5621 to ADSP-2101 Interface 0 1 1 kΩ to GND 1 0 100 kΩ to GND AD5601/AD5611/AD5621 to 68HC11/68L11 Interface 1 1 Three-state Figure 47 shows a serial interface between the AD5601/ AD5611/AD5621 and the 68HC11/68L11 microcontroller. SCK When both bits are set to 0, the part has normal power of the 68HC11/68L11 drives the SCLK of the AD5601/AD5611/ consumption of 100 μA maximum at 5 V. However, for the AD5621, while the MOSI output drives the serial data line of three power-down modes, the supply current falls to typically the DAC. The SYNC signal is derived from a port line (PC7). 0.2 μA at 3 V. The setup conditions for correct operation of this interface are Not only does the supply current fall, but the output stage is as follows: the 68HC11/68L11 should be configured so that the also internally switched from the output of the amplifier to a CPOL bit is 0 and the CPHA bit is 1. When data is being trans- resistor network of known values. This has the advantage that mitted to the DAC, the SYNC line is taken low (PC7). When the the output impedance of the part is known while the part is in 68HC11/68L11 are configured as indicated, data appearing on power-down mode. the MOSI output is valid on the falling edge of SCK. Serial data There are three different options: the output is connected from the 68HC11/68L11 is transmitted in 8-bit bytes with only internally to GND through a 1 kΩ resistor or a 100 kΩ resistor, eight falling clock edges occurring in the transmit cycle. Data is or the output is left open-circuited (three-stated). Figure 45 transmitted MSB first. To load data to the AD5601/AD5611/ shows the output stage. AD5621, PC7 is left low after the first eight bits are transferred and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. SRTERSINISGT DOARC AMPLIFIER VOUT 68HC11/ AD5601/AD5611/ 68L11* AD5621* PC7 SYNC POWER-DOWN CIRCUITRY NREETSWISOTORRK SCK SCLK Figure 45. Output Stage During Power-Down 06853-044 MOSI SDIN 06853-046 *ADDITIONAL PINS OMITTED FOR CLARITY The bias generator, output amplifier, resistor string, and other Figure 47. AD5601/AD5611/AD5621 to 68HC11/68L11 Interface associated linear circuitry are all shut down when power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power- down is typically 13 μs for V = 5 V and 16 μs for V = 3 V. DD DD See Figure 21 for a plot. Rev. H | Page 16 of 21

Data Sheet AD5601/AD5611/AD5621 AD5601/AD5611/AD5621 to Blackfin® ADSP-BF53x and a second write cycle is initiated to transmit the second byte Interface of data. P3.3 is taken high following the completion of this Figure 48 shows a serial interface between the AD5601/AD5611/ cycle. The 80C51/80L51 output the serial data LSB first. The AD5621 and the Blackfin ADSP-BF53x microprocessor. The AD5601/AD5611/AD5621 require data with the MSB as the ADSP-BF53x processor family incorporates two dual-channel first bit received. The 80C51/80L51 transmit routine should synchronous serial ports, SPORT1 and SPORT0, for serial and take this into account. multiprocessor communications. Using SPORT0 to connect to 80C51/80L51* AD5601/AD5611/ the AD5601/AD5611/AD5621, the setup for the interface is as AD5621* follows: DT0PRI drives the SDIN pin of the AD5601/AD5611/ AD5621, while TSCLK0 drives the SCLK of the part. The SYNC P3.3 SYNC TxD SCLK is driven from TFS0. ADSP-BF53x* AD5601/AD5611/ RxD SDIN 06853-048 AD5621* *ADDITIONAL PINS OMITTED FOR CLARITY Figure 49. AD5601/AD5611/AD5621 to 80C51/80L51 Interface DT0PRI SDIN TSCLK0 SCLK AD5601/AD5611/AD5621 to MICROWIRE Interface TFS0 SYNC 06853-047 FAiDgu5r6e2 510 a snhdo awnsy a Mn IinCtRerOfaWceI RbeEt-wcoeemnp tahteib AleD d5e6v0ic1e/.A SDer5i6al1 1d/a ta *ADDITIONAL PINS OMITTED FOR CLARITY is shifted out on the falling edge of the serial clock and is Figure 48. AD5601/AD5611/AD5621 to Blackfin ADSP-BF53x Interface clocked into the AD5601/AD5611/AD5621 on the rising edge AD5601/AD5611/AD5621 to 80C51/80L51 Interface of the SK. Figure 49 shows a serial interface between the AD5601/ MICROWIRE* AD5601/AD5611/ AD5611/AD5621 and the 80C51/80L51 microcontroller. The AD5621* setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5601/AD5611/AD5621, while RxD CS SYNC SK SCLK drives the serial data line of the part. The SYNC signal is again dPeorritv Ledin fer oPm3. 3a ibs iut sperdo.g Wramhemn adbaltea pisin t oo nbe t htrea pnosmrt.i tItne dt htois tchaes e, SO SDIN 06853-049 AD5601/AD5611/AD5621, P3.3 is taken low. The 80C51/80L51 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 50. AD5601/AD5611/AD5621 to MICROWIRE Interface transmit data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, Rev. H | Page 17 of 21

AD5601/AD5611/AD5621 Data Sheet APPLICATIONS INFORMATION CHOOSING A REFERENCE AS POWER SUPPLY FOR BIPOLAR OPERATION USING THE THE AD5601/AD5611/AD5621 AD5601/AD5611/AD5621 The AD5601/AD5611/AD5621 come in tiny LFCSP and SC70 The AD5601/AD5611/AD5621 have been designed for single- packages with less than a 100 μA supply current. Because of this, supply operation, but a bipolar output range is also possible the choice of reference depends on the application requirements. using the circuit shown in Figure 52. The circuit in Figure 52 For applications with space-saving requirements, the ADR02 gives an output voltage range of ±5 V. Rail-to-rail operation at is recommended. It is available in an SC70 package and has the amplifier output is achievable using an AD820 or OP295 as excellent drift at 9 ppm/°C (3 ppm/°C in the R-8 package) and the output amplifier. provides very good noise performance at 3.4 μV p-p in the R2 = 10kΩ 0.1 Hz to 10 Hz range. +5V Because the supply current required by the AD5601/AD5611/ +5V R1 = 10kΩ AD5621 is extremely low, the parts are ideal for low supply AD820/ +5V applications. The ADR395 voltage reference is recommended in OP295 V V this case. It requires less than 100 μA of quiescent current and DD OUT 10µF 0.1µF AD5601/AD5611/ can, therefore, drive multiple DACs in one system, if required. AD5621 –5V It also provides very good noise performance at 8 μV p-p in the 0.1 Hz to 10 Hz range. 7V INT3S-EEWRRIFIRAAELCE 06853-051 5V Figure 52. Bipolar Operation with the AD5601/AD5611/AD5621 ADR395 The output voltage for any input code can be calculated as   D  R1R2 R2 S3E-WRIIRAEL SSYCNLCK AD5601/AD5611/ VOUT = 0V TO 5V VOUT VDD2N  R1 VDDR1 INTERFACE AD5621 SDIN 06853-050 Wwhitehre V D r e=p 5re Vse, nRt1s =th Re 2in =p u1t0 c koΩde in decimal (0 – 2N). Figure 51. ADR395 as Power Supply to the AD5601/AD5611/AD5621 DD Some recommended precision references for use as supplies to 10D V  5V the AD5601/AD5611/AD5621 are listed in Table 7. OUT  2N  This is an output voltage range of ±5 V, with 0x0000 corre- Table 7. Precision References for the AD5601/AD5611/AD5621 sponding to a −5 V output and 0x3FFF corresponding to a Initial Accuracy Temp Drift 0.1 Hz to 10 Hz +5 V output. Part No. (mV max) (ppm/°C max) Noise (μV p-p typ) ADR435 ±2 3 (R-8) 8 ADR425 ±2 3 (R-8) 3.4 ADR02 ±3 3 (R-8) 10 ADR02 ±3 3 (SC70) 10 ADR395 ±5 9 (TSOT-23) 8 Rev. H | Page 18 of 21

Data Sheet AD5601/AD5611/AD5621 USING THE AD5601/AD5611/AD5621 WITH A POWER SUPPLY BYPASSING AND GROUNDING GALVANICALLY ISOLATED INTERFACE When accuracy is important in a circuit, it is helpful to carefully In process control applications in industrial environments, consider the power supply and ground return layout on the it is often necessary to use a galvanically isolated interface to board. The PCB containing the AD5601/AD5611/AD5621 protect and isolate the controlling circuitry from any hazardous should have separate analog and digital sections, each having its common-mode voltages that might occur in the area where the own area of the board. If the AD5601/AD5611/AD5621 are in a DAC is functioning. iCoupler® provides isolation in excess of system where other devices require an AGND-to-DGND 2.5 kV. Because the AD5601/AD5611/AD5621 use a 3-wire serial connection, the connection should be made at one point only. logic interface, the ADuM1300 3-channel digital isolator This ground point should be as close as possible to the provides the required isolation (see Figure 53). The power AD5601/AD5611/AD5621. supply to the part also needs to be isolated, which is done by The power supply to the AD5601/AD5611/AD5621 should be using a transformer. On the DAC side of the transformer, a 5 V bypassed with 10 μF and 0.1 μF capacitors. The capacitors regulator provides the 5 V supply required for the AD5601/ should be physically as close as possible to the device, with the AD5611/AD5621. 0.1 μF capacitor ideally right up against the device. The 10 μF 5V capacitors are the tantalum bead type. It is important that the POWER REGULATOR 10µF 0.1µF 0.1 μF capacitor have low effective series resistance (ESR) and effective series inductance (ESI), such as in common ceramic types of capacitors. This 0.1 μF capacitor provides a low imped- ance path to ground for high frequencies caused by transient VDD currents due to internal logic switching. SCLK VIA VOA SCLK The power supply line itself should have as large a trace as ADuM1300 AD5601/ possible to provide a low impedance path and reduce glitch AD5611/ effects on the supply line. Clocks and other fast switching SDI VIB VOB SYNC AD5621 VOUT digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals, if possible. When traces cross on opposite sides of the board, DATA VIC VOC SDIN GND 06853-052 efenesdutrher tohuagth t heeffye crutsn o ant trhigeh bt oaanrgdl.e Ts htoe ebaecsht boothaerdr tloay roeudtu tceec h- nique is the microstrip technique, where the component side of Figure 53. AD5601/AD5611/AD5621 with a Galvanically Isolated Interface the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a two-layer board. Rev. H | Page 19 of 21

AD5601/AD5611/AD5621 Data Sheet OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 6 5 4 2.40 1.25 2.10 1.15 1 2 3 1.80 0.65BSC 1.30BSC 1.00 1.10 0.40 0.90 0.80 0.10 0.70 0.46 0.10MAX 0.30 SPELAATNIENG 00..2028 0.36 COPLANARITY 0.15 0.26 0.10 COMPLIANTTOJEDECSTANDARDSMO-203-AB 072809-A Figure 54. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters 1.50 2.10 1.40 2.00 1.30 1.90 0.65 REF 4 6 0.20 MIN 3.10 EXPOSED 1.70 3.00 PAD 1.60 PIN 1 INDEX 2.90 0.45 1.50 AREA 0.40 0.35 3 1 PIN 1 TOP VIEW BOTTOM VIEW INDICATOR (R 0.15) 0.80 0.203 REF 0.05 MAX FTOHER EPXRPOOPSEERD C POANDN, ERCETFIEORN TOOF 0.75 0.00 MIN THE PIN CONFIGURATION AND 0.70 FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. SEATING 0.35 PLANE 0.30 C0.O08PLANARITY 0.25 COMPLIANTTOJEDEC STANDARDS MO-229 03-29-2012-B Figure 55. 6-Lead Lead Frame Chip Scale Package [LFCSP_WD] 2.00 × 3.00 mm Body, Very Very Thin, Dual Lead (CP-6-5) Dimensions shown in millimeters Rev. H | Page 20 of 21

Data Sheet AD5601/AD5611/AD5621 ORDERING GUIDE Temperature Package Model1 Range INL Package Description Option Branding AD5601BKSZ-500RL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3V AD5601BKSZ-REEL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3V AD5601BCPZ-RL7 –40°C to +125°C ±0.5 LSB 6-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-6-5 89 AD5611AKSZ-500RL7 –40°C to +125°C ±4.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3U AD5611AKSZ-REEL7 –40°C to +125°C ±4.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3U AD5611ACPZ-RL7 –40°C to +125°C ±4.0 LSB 6-Lead Lead Frame Chip Scale Package[LFCSP_WD] CP-6-5 8B AD5611BKSZ-500RL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3T AD5611BKSZ-REEL7 –40°C to +125°C ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3T AD5621AKSZ-500RL7 –40°C to +125°C ±6.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3S AD5621AKSZ-REEL7 –40°C to +125°C ±6.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3S AD5621ACPZ-RL7 –40°C to +125°C ±6.0 LSB 6-Lead Lead Frame Chip Scale Package[LFCSP_WD] CP-6-5 D3S AD5621BKSZ-500RL7 –40°C to +125°C ±1.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3R AD5621BKSZ-REEL7 –40°C to +125°C ±1.0 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 D3R EVAL-AD5621EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06853-0-2/16(H) Rev. H | Page 21 of 21