1.2 A Programmable Device Power Supply with Integrated 16-Bit Level Setting DACs Data Sheet AD5560 FEATURES On-chip comparators Gangable for higher current Programmable device power supply (DPS) Guard amplifier FV, MI, MV, FNMV functions System PMU connections 5 internal current ranges (on-chip R ) SENSE Current clamps ±5 µA, ±25 µA, ±250 µA, ±2.5 mA, ±25 mA Die temperature sensor and shutdown feature 2 external high current ranges (external R ) SENSE On-chip diode thermal array EXTFORCE1: ±1.2 A maximum Diagnostic register allows access to internal nodes EXTFORCE2: ±500 mA maximum Open-drain alarm flags (temperature, current clamp, Kelvin Integrated programmable levels alarm) All 16-bit DACs: force DAC, comparator DACs, clamp DACs, SPI-/MICROWIRE-/DSP-compatible interface offset DAC, OSD DAC, DGS DAC 64-lead (10 mm × 10 mm) TQFP with exposed pad (on top) Programmable Kelvin clamp and alarm 72-ball (8 mm × 8 mm) flip-chip BGA Offset and gain correction registers on-chip Ramp mode on force DAC for power supply slewing APPLICATIONS Programmable slew rate feature, 1 V/μs to 0.3 V/μs Automatic test equipment (ATE) DUTGND Kelvin sense and alarm Device power supply 25 V FV span with asymmetrical operation within −22 V/+25 V GENERAL DESCRIPTION The AD5560 is a high performance, highly integrated device dissipation. Current ranges in excess of ±1.2 A or at high power supply consisting of programmable force voltages and current and high voltage combinations can be achieved by measure ranges. This part includes the required DAC levels to paralleling or ganging multiple DPS devices. Open-drain set the programmable inputs for the drive amplifier, as well as alarm outputs are provided in the event of overcurrent, clamping and comparator circuitry. Offset and gain correction overtemperature, or Kelvin alarm on either the SENSE or is included on-chip for DAC functions. A number of program- DUTGND line. mable measure current ranges are available: five internal fixed The DPS functions are controlled via a simple 3-wire serial ranges and two external customer-selectable ranges (EXTFORCE1 interface compatible with SPI, QSPI™, MICROWIRE™, and DSP and EXTFORCE2) that can supply currents up to ±1.2 A and interface standards running at clock speeds of up to 50 MHz. ±500 mA, respectively. The voltage range possible at this high current level is limited by headroom and the maximum power Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5560 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Adjusting the Autocompensation Mode ................................. 39 Applications ....................................................................................... 1 Dealing with Parallel Load Capacitors .................................... 39 General Description ......................................................................... 1 DAC Levels .................................................................................. 39 Revision History ............................................................................... 3 Force and Comparator DACs ................................................... 39 Functional Block Diagram .............................................................. 4 Clamp DACs ............................................................................... 39 Specifications ..................................................................................... 5 OSD DAC .................................................................................... 40 Timing Characteristics .............................................................. 13 DUTGND DAC .......................................................................... 40 Timing Diagrams ........................................................................ 13 Offset DAC .................................................................................. 40 Absolute Maximum Ratings .......................................................... 15 Offset and Gain Registers .......................................................... 40 ESD Caution ................................................................................ 15 Reference Selection .................................................................... 41 Pin Configurations and Function Descriptions ......................... 16 Calibration................................................................................... 41 Typical Performance Characteristics ........................................... 20 Additional Calibration ............................................................... 41 Terminology .................................................................................... 28 System Level Calibration ........................................................... 41 Theory of Operation ...................................................................... 29 Choosing AV /AV Power Supply Rails ............................... 42 DD SS Force Amplifier ........................................................................... 29 Choosing HCAV x and HCAV x Supply Rails ................... 42 SS DD DAC Reference Voltage (VREF) ............................................... 29 Power Dissipation....................................................................... 42 Open-Sense Detect (OSD) Alarm and Clamp ....................... 29 Package Composition and Maximum Vertical Force ............ 43 Device Under Test Ground (DUTGND)................................. 29 Slew Rate Control ....................................................................... 43 GPO .............................................................................................. 29 Serial Interface ................................................................................ 45 Comparators ................................................................................ 30 SPI Interface ................................................................................ 45 Current Clamps .......................................................................... 30 SPI Write Mode .......................................................................... 45 Short-Circuit Protection ............................................................ 30 SDO Output ................................................................................ 45 Guard Amplifier ......................................................................... 30 RESET Function ......................................................................... 45 Compensation Capacitors ......................................................... 30 BUSY Function ........................................................................... 45 Current Range Selection ............................................................ 31 LOAD Function .......................................................................... 45 High Current Ranges ................................................................. 31 Register Update Rates ................................................................ 46 Ideal Sequence for Gang Mode ................................................. 32 Control Registers ............................................................................ 47 Compensation for Gang Mode ................................................. 32 DPS and DAC Addressing ........................................................ 47 System Force/Sense Switches .................................................... 32 Readback Mode .......................................................................... 58 Die Temperature Sensor and Thermal Shutdown.................. 33 DAC Readback............................................................................ 58 Measure Output (MEASOUT) ................................................. 33 Power-On Default ...................................................................... 58 VMID Voltage ................................................................................ 33 Using the HCAVDDx and HCAVSSx Supplies .......................... 60 Force Amplifier Stability............................................................ 36 Power Supply Sequencing ......................................................... 60 Poles and Zeros in a Typical System ........................................ 37 Required External Components ............................................... 61 Minimizing the Number of External Compensation Power Supply Decoupling ......................................................... 62 Components ................................................................................ 37 Applications Information .............................................................. 63 Extra Poles and Zeros in the AD5560 ...................................... 37 Thermal Considerations ............................................................ 63 Compensation Strategies ........................................................... 38 Temperature Contour Map on the Top of the Package ......... 64 Optimizing Performance for a Known Capacitor Using Outline Dimensions ....................................................................... 65 Autocompensation Mode .......................................................... 38 Ordering Guide .......................................................................... 66 Rev. E | Page 2 of 66

Data Sheet AD5560 REVISION HISTORY 5/2016—Rev. D to Rev. E 9/2009—Rev. A to Rev. B Changes to Figure 1........................................................................... 4 Changes to Table 1, Measure Current and Measure Voltage Changes to High Current Ranges Section ................................... 31 Parameters .......................................................................................... 6 Added Calibration Section, Reducing Zero-Scale Error Section, Changes to Die Temperature Sensor and Thermal Reducing Gain Error Section, Calibration Example Section, Shutdown Section ........................................................................... 31 Additional Calibration Section, and System Level Calibration Changes to Table 10 and Table 11 ................................................. 32 Section .............................................................................................. 41 Changes to Table 18, Bit 15 ............................................................ 45 Added Figure 58; Renumbered Sequentially ............................... 42 Changes to Table 23, Bits[15:12] ................................................... 50 Changes to Table 25 ........................................................................ 57 Changes to Table 25 ........................................................................ 54 8/2012—Rev. C to Rev. D 12/2008—Rev. 0 to Rev. A Added 72-Ball Flip-Chip BGA (Throughout) ............................... 1 Changes to Figure 1 .......................................................................... 4 Added Figure 7 and Table 5 (Renumbered Sequentially) .......... 18 Changes to Table 1 ............................................................................ 4 Added Applications Information Section .................................... 62 Changes to Table 2 .......................................................................... 13 Updated Outline Dimensions ........................................................ 64 Changes to Table 3 .......................................................................... 15 Changes to Ordering Guide ........................................................... 65 Changes to Open-Sense Detect (OSD) Alarm and Clamp ....... 27 Changes to Figure 53 ...................................................................... 30 10/2010—Rev. B to Rev. C Change to g Maximum Rating, Table 13 ................................... 34 m Changes to Force Output Voltage Parameter and Load Transient Changes to Table 19 ........................................................................ 46 Response Parameter, Table 1 ............................................................ 5 Changes to Bit 7, Bit 8 Functions, Table 21 ................................. 48 Changes to Figure 52 ...................................................................... 29 Changes to Power Supply Decoupling Section ........................... 59 Changes to Table 9 .......................................................................... 32 11/2008—Revision 0: Initial Version Rev. E | Page 3 of 66

AD5560 Data Sheet FUNCTIONAL BLOCK DIAGRAM EXTR1SENSE 100-97770 EXT2RSENSE UT D SLAVE_IN MASTER_OUT CTO CF0F4 EXTFORCE1 EXTFORCE2 CTO CF0F4 SYS_FORCE FORCE SYS_SENSE EXTMEASIH1 EXTMEASIH2 EXTMEASIL SENSE GUARD/SYS_DUTGNDDUTGND SW6 MUX UPTO ±1.2A UPTO ±500mA SW8 SW11 10kΩ SW9 SW18 HCAV2xCAV2xDDSS SW5b SW5a 25mA 20Ω2.5mA 200Ω250µA 2kΩ25µA 20kΩ5µA 100kΩ SW7 SW13 SW14 SW15 GUARDSW17AMP AD5560 HCAV1xHAV1xSSDD RSENSE NHIBIT SW4 DUTGND SENSEANDALARM ALARM BLOCKKSENSEDUTGND SENSEGUARD KELALM HC 8pFI OPENSENSEDETECT +– +– +– +– CC2C3 ΩΩkk50201 R: 200ΩPTO 1MΩ DGSDAC CCCC0C1 ΩR: 500ΩkZ6TO 1.6MΩ 40µA/V80µA/V300µA/V900µA/V gm SLEW RATECONTROL LOCAL FEEDBACKEXTFORCE1EXTFORCE2 DAC MID CODEVOLTAGETOCENTER IRANGECABISENSE+×10OR ×20–SW2 AGNDV+SENSE×1– VREFOSD16DAC 16 VREF C W1 S A B CLEN/LOADDGNDCLALMDVAVAVAGNDCCSSDD CLH16-BIT1616DAC×2 REG×1 REG16CLAMPM REG16OFFSET CONTROLC REG×1CLL16-BIT1616DAC×2 REG×1 REG16M REG16OFFSETC REG×1 RAMP REG1616×2 REG×1 REG16-BIT16FINDACM REG16C REGB×1R3R4AOFFSET DACCLH16-BIT16CLH DAC OFFSETR1R2AGNDS/W INH THERMAL SHUTDOWN161616-BIT16DAC16×2 REG×1 REGM REGC REGOFFSET×8161616-BIT16DAC16×2 REG×1 REGM REGC REGOFFSET×8 CPHSW3 CPL ISENSEVSENSESW16MUXKSENSEANDTSENSEGAINDUTGND SENSEDIE TEMP×1/×0.2DIAGNOSTIC ASENSORANDDIAGNOSTIC BTHERMALSHUTDOWN 16SERIAL SPI INTERFACE OWER-ONRESET SDISCLKSYNCBUSYSDOGPORESETTMPALM P VREF REFGND RCLK W_INH/LOAD CPOH/CPO CPOL MEASOUT H Figure 1. Rev. E | Page 4 of 66

Data Sheet AD5560 SPECIFICATIONS HCAV x ≤ (AV + 33 V), HCAV x ≤ AV , HCAV x ≥ AV , AV ≥ 8 V, AV ≤ −5 V, |AV − AV | ≥ 16 V and ≤ 33 V, DV = DD SS DD DD SS SS DD SS DD SS CC 2.3 V to 5.5 V, V = 5 V, gain (m), offset (c), and DAC offset registers are at default values; AGND = DGND = 0 V; T = 25°C to 90°C, REF J maximum specifications, unless otherwise noted. FSV is full-scale voltage, FSVR is full-scale voltage range, FSC is full-scale current, FSCR is full-scale current range. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments FORCE VOLTAGE Force Output Voltage1 EXTFORCE1 AV + 2.25 AV − 2.25 V Allow ±500 mV for external R voltage drop SS DD SENSE HCAV 1x + 1.75 HCAV 1x − 1.75 V Allow ±500 mV for external R voltage drop SS SS SENSE HCAV 1x + 1.25 HCAV 1x − 1.25 V Allow ±500 mV for external R voltage drop; SS DD SENSE reduced headroom/footroom, clamps must be enabled2 EXTFORCE2 AV + 2.25 AV − 2.25 V Allow ±500 mV for external R voltage drop SS DD SENSE HCAV 2x + 1.75 HCAV 2x − 1.75 V Allow ±500 mV for external R voltage drop SS DD SENSE HCAV 2x + 1.25 HCAV 2x − 1.25 V Allow ±500 mV for external R voltage drop; SS DD SENSE reduced headroom/footroom, clamps must be enabled2 FORCE AV + 2.75 AV − 2.75 V Internal current ranges, includes ±500 mV for SS DD internal R voltage drop SENSE Headroom/Footroom1 −2.75 +2.75 V Internal current ranges to AV /AV , includes DD SS ±500 mV for internal R voltage drop. SENSE Headroom/Footroom1 −2.25 +2.25 V External current ranges, EXTFORCE1/ EXTFORCE2 to HCAV x and HCAV x supplies; DD SS includes ±500 mV for external R voltage drop.\ SENSE Force Output Voltage Span −22 +25 V May be a skewed range but within headroom requirements and maximum power dissipation for current range Forced Voltage Linearity Error −2 +2 mV Forced Voltage Offset Error −50 +50 mV Uncalibrated, use c register to calibrate, meas- ured at midscale Forced Voltage Offset Error Tempco1 27 μV/°C Standard deviation = 23 μV/°C Forced Voltage Gain Error −25 +25 mV Uncalibrated, use m register to calibrate Forced Voltage Gain Error Tempco1 4 ppm/°C Standard deviation = 3 ppm/°C Short-Circuit Current Limit3 Clamps off EXTFORCE1 −3.5 ±2.7 +3.5 A Positive and negative dc short-circuit current EXTFORCE2 −1.25 ±0.9 +1.25 A Positive and negative dc short-circuit current FORCE −75 ±50 +75 mA ±25 mA range, positive and negative dc short- circuit current −20 ±10 +20 mA All other ranges, positive and negative dc short- circuit current Active C Buffer −64 +64 mA Fx DC Load Regulation1 −1 +1 mV EXTFORCE1 range, ±1 A load current change −0.4 +0.4 mV EXTFORCE2 range, ±0.5 A load current change Load Transient Response1 70 mV 1.2 A load step into 100 μF DUT capacitance (10 mΩ ESR), autocompensation mode 140 mV 1.2 A load step into 30 µF DUT capacitance (10 mΩ ESR), autocompensation mode NSD1 350 nV/√Hz Measured at 1 kHz, at output of FORCE MEASURE CURRENT RANGES Sense resistors are trimmed to within 1%, nominal ±500 mV V RSENSE Internal Sense Resistors1 100 kΩ ±5 µA current range 20 kΩ ±25 µA current range 2 kΩ ±250 µA current range 200 Ω ±2.5 mA current range 20 Ω ±25 mA current range Rev. E | Page 5 of 66

AD5560 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments Measure Current Ranges Specified current ranges with V = 5 V and MI REF gain = 20, or with V = 2.5 V and MI gain = 5 REF ±5 µA Set using internal sense resistor ±25 µA Set using internal sense resistor ±250 µA Set using internal sense resistor ±2.5 mA Set using internal sense resistor ±25 mA Set using internal sense resistor ±500 mA EXTFORCE2, set by user with external sense resistor, limited by headroom requirements and maximum power dissipation ±1200 mA EXTFORCE1, set by user with external sense resistor, limited by headroom requirements and maximum power dissipation MEASURE CURRENT All offset DAC/supply combinations settings, all gain settings are measure current = (I × DUT R × MI gain), unless otherwise noted SENSE Differential Input Voltage Range1 −0.64 +0.64 V Maximum voltage across R , MI gain = 20 SENSE −0.7 +0.7 V Maximum voltage across R , MI gain = 10 SENSE Output Voltage Span1 25 V Measure current block alone (internal node) Offset Error −1 +1 % FSC At 0 A, MI gain = 20, MEASOUT gain = 1 Offset Error Tempco1 −1 ppm of FSC/°C Standard deviation = 13 ppm/°C Offset Error −1.5 +1.5 % FSC At 0 A, MI gain = 10, MEASOUT gain = 1 Offset Error Tempco1 −1 ppm of FSC/°C Standard deviation = 13 ppm/°C Offset Error −1.5 +1.5 % FSC At 0 A, MI gain = 20, MEASOUT gain = 0.2 Offset Error Tempco1 3 ppm of FSC/°C Standard deviation = 13 ppm/°C Offset Error −3 +3 % FSC At 0 A, MI gain = 10, MEASOUT gain = 0.2 Offset Error Tempco1 8 ppm of FSC/°C Standard deviation = 15 ppm/°C Gain Error −2 +2 % FSC Internal current ranges, all gain settings Gain Error1 −1 +1 % FSC External current ranges, excluding R SENSE Gain Error Tempco1 20 ppm/°C Standard deviation = 5 ppm/°C MEASOUT Gain = 1 All supply conditions Linearity Error −0.01 +0.01 % FSCR MI gain = 20 and 10 MEASOUT Gain = 0.2 Nominal supply (±16.5 V, 0x8000 offset DAC) Linearity Error −0.06 +0.06 % FSCR MI gain = 20 Linearity Error −0.05 +0.05 % FSCR MI gain = 10 MEASOUT Gain = 0.2 Low supply (−25 V/+8 V, 0xD4EB offset DAC) Linearity Error −0.125 +0.125 % FSCR MI gain = 20 Linearity Error −0.175 +0.175 % FSCR MI gain = 10 MEASOUT Gain = 0.2 High supply (−5 V/+28 V, 0xD1D offset DAC) Linearity Error −0.0875 +0.0875 % FSCR MI gain = 20 Linearity Error −0.1 +0.1 % FSCR MI gain = 10 Common-Mode Error −0.005 +0.005 %FSVR/V % of FS change at measure output per volts change in DUT voltage NSD1 900 nV/√Hz MI gain = 20, MEASOUT gain = 1, measured at MEASOUT at 1 kHz, inputs grounded 550 nV/√Hz MI gain = 10, MEASOUT gain = 1, measured at MEASOUT at 1 kHz, inputs grounded 170 nV/√Hz MI gain = 20, MEASOUT gain = 0.2, measured at MEASOUT at 1 kHz, inputs grounded 110 nV/√Hz MI gain = 10, MEASOUT gain = 0.2, measured at MEASOUT at 1 kHz, inputs grounded MEASURE VOLTAGE MEASOUT Gain 1 and MEASOUT Gain 0.2 Measure Voltage Range1 AV + 2.75 AV − 2.75 V All voltage ranges SS DD Gain Error −0.1 +0.1 % FS Gain Error Tempco1 3 ppm/°C Standard deviation = 2 ppm/°C MEASOUT Gain = 1 Linearity Error −2 +2 mV Offset Error −12 +12 mV Offset Error Tempco1 2 µV/°C Standard deviation = 12 µV/°C NSD1 100 nV/√Hz At 1 kHz, at MEASOUT, inputs grounded Rev. E | Page 6 of 66

Data Sheet AD5560 Parameter Min Typ Max Unit Test Conditions/Comments MEASOUT Gain = 0.2 Linearity Error −5.5 +5.5 mV Referred to MV input, nominal supply (±16.5 V, 0x8000 offset DAC) −9 +24 mV Referred to MV input, low supply (−25 V/+8 V, 0xD4EB offset DAC) −4 +13 mV Referred to MV input, high supply (−5 V/+28 V, 0xD1D offset DAC) Offset Error −30 +20 mV Referred to MV output Offset Error Tempco1 10 µV/°C Standard deviation = 12 µV/°C, referred to MV output NSD1 50 nV/√Hz At 1 kHz, at MEASOUT, inputs grounded COMBINED LEAKAGE Includes SYS_SENSE, SYS_FORCE, EXTFORCE1, EXTFORCE2, EXTMEASIH1, EXTMEASIH2, EXTMEASIL, FORCE, and SENSE; measured with PD = 1, SW-INH = 0 (power up and tristate) Leakage Current −37.5 +37.5 nA −30 +30 nA T = 25°C to 70°C J Leakage Current Tempco1 ±0.1 ±0.4 nA/°C SENSE INPUT Leakage Current −2.5 +2.5 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.01 nA/°C Pin Capacitance1 10 pF EXTMEASIH1, EXTMEASIH2, EXTMEASIL Leakage Current −2.5 +2.5 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.01 nA/°C Pin Capacitance1 5 pF FORCE OUTPUT, FORCE Maximum Current Drive1 −30 +30 mA Leakage Current −10 +10 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.03 nA/°C Pin Capacitance1 120 pF EXTFORCE1 OUTPUTS Maximum Current Drive1 −1200 +1200 mA Set with external sense resistor, limited by headroom and power dissipation Leakage Current −7.5 +7.5 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.03 ±0.06 nA/°C Pin Capacitance1 275 pF EXTFORCE2 OUTPUTS Maximum Current Drive1 −500 +500 mA Set with external sense resistor, limited by headroom and power dissipation Leakage Current −5 +5 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) Leakage Current Tempco1 ±0.02 ±0.05 nA/°C Pin Capacitance1 100 pF SYS_SENSE Voltage Range AV AV V SS DD Leakage Current −2.5 +2.5 nA SYS_SENSE high-Z, force amplifier inhibited Leakage Current Tempco1 ±0.005 ±0.025 nA/°C Path On Resistance 280 Ω AV = 16.5 V, AV = −16.5 V DD SS Pin Capacitance1 5 pF Rev. E | Page 7 of 66

AD5560 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments SYS_FORCE Voltage Range AV AV V SS DD Current Carrying Capability1 −25 +25 mA Leakage Current −2.5 +2.5 nA SYS_FORCE high-Z, force amplifier inhibited Leakage Current Tempco1 ±0.005 ±0.025 nA/°C Path On Resistance 35 Ω AV = 16.5 V, AV = −16.5 V DD SS Pin Capacitance1 5 pF SYS_DUTGND Voltage Range AV AV V SS DD Path On Resistance 300 400 Ω AV = 16.5 V, AV = −16.5 V DD SS CURRENT CLAMP Clamp Accuracy Programmed Programmed % of FS MI gain = 20, with clamp separation of 2 V, and clamp value clamp value + 10 1 V separation from AGND/0 A Programmed Programmed % of FS MI gain = 10, with clamp separation of 2 V, and clamp value clamp value + 20 1 V separation from AGND/0 A VCLL to VCLH1 2 V 10% of FSCR (MI gain = 20), 20% of FSCR (MI gain = 10), restriction to prevent both clamps activating together VCLL to 0 A1 1 V 5% of FSCR (MI gain = 20), 10% of FSCR (MI gain = 10), restriction to avoid impinging on FV before programmed level VCLH to 0 A1 1 V 5% of FSCR (MI gain 20), 10% of FSCR (MI gain = 10), restriction to avoid impinging on FV before programmed level Clamp Activation Response Time1 20 100 μs Measured from BUSY going low to visible clamping Clamp Recovery1 2 5 μs Measured from BUSY going low to visible recovery Alarm Delay 1 50 μs Time for CLALM to flag FORCE AMPLIFER Slew Rate1 1 V/µs Fastest slew rate, controlled via serial interface 0.312 V/µs Slowest slew rate, controlled via serial interface Maximum Stable Load Capacitance1 160 µF Voltage Overshoot/Undershoot1 5 % Of programmed value (≥1 V) SETTLING TIME (FORCE AMPLIFER) Compensation Register 1 = 0x4880 (229 nF to To within 10 mV of programmed value 380 nF, ESR 74 to 140 mΩ) FV (1200 mA EXTFORCE1 Range)1 16 25 µs 3.7 V step, R = 2.4 Ω, C = 0.22 µF, full dc load DUT DUT FV (900 mA EXTFORCE1 Range)1 18 30 µs 8 V step, R = 8.8 Ω, C = 0.22 µF, full dc load DUT DUT FV (500 mA EXTFORCE2 Range)1 34 53 µs 15 V step, R = 30 Ω, C = 0.22 µF, full dc load DUT DUT FV (300 mA EXTFORCE2 Range)1 25 50 µs 10 V step, R = 33.3 Ω, C = 0.22 µF, full dc load DUT DUT FV (25 mA Range)1, 3 125 180 µs 20 V step, R = 800 Ω, C = 0.22 µF, full dc load DUT DUT FV (2.5 mA Range)1, 3 300 500 µs 10 V step, R = 4 kΩ, C = 0.22 µF, full dc load DUT DUT FV (250 µA Range)1, 3 300 500 µs 10 V step, R = 40 kΩ, C = 0.22 µF, full dc load DUT DUT FV (25 µA Range)1, 3 400 600 µs 10 V step, R = 400 kΩ, C = 0.22 µF, full dc load DUT DUT FV (5 µA Range)1, 3 20 40 µs 1 V step, R = 200 kΩ, C = 0.22 µF, full dc load DUT DUT Compensation Register 1 = 0x8880 (1.7 μF to 2.9 μF, ESR 74 to 140 mΩ) FV (180 mA EXTFORCE1 Range)1 16 25 µs 3 V step, C = 2.2 µF, full dc load DUT FV (100 mA EXTFORCE2 Range)1 60 80 µs 8 V step, C = 2.2 µF, full dc load DUT Compensation Register 1 = 0xB880 (7.9μF to 13 μF, ESR 74 to 140 mΩ) FV (180 mA EXTFORCE1 Range)1 55 70 µs 3 V step, C = 10 µF, full dc load DUT FV (100 mA EXTFORCE2 Range)1 210 260 µs 8 V step, C = 10 µF, full dc load DUT Compensation Register 1 = 0xC880 (13 μF to 22 μF, ESR 74 to 140 mΩ) FV (180 mA EXTFORCE1 Range)1 65 80 µs 3 V step, C = 20 µF, full dc load DUT FV (100 mA EXTFORCE2 Range)1 310 370 µs 8 V step, C = 20 µF, full dc load DUT Rev. E | Page 8 of 66

Data Sheet AD5560 Parameter Min Typ Max Unit Test Conditions/Comments SETTLING TIME (FV, MEASURE Compensation Register 1 = 0x4880 (229 nF to To within 10 mV of programmed value CURRENT) 380 nF, ESR 74 to 140 mΩ) MI (1200 mA EXTFORCE1 Range)1 30 40 µs 3.7 V step, R = 2.4 Ω, C = 0.22 µF, full dc load DUT DUT MI (900 mA EXTFORCE1 Range)1 32 42 µs 8 V step, R = 8.8 Ω, C = 0.22 µF, full dc load DUT DUT MI (500 mA EXTFORCE2 Range)1 69 95 µs 15 V step, R = 30 Ω, C = 0.22 µF, full dc load DUT DUT MI (300 mA EXTFORCE2 Range)1 70 100 µs 10 V step, R = 33.3 Ω, C = 0.22 µF, full dc load DUT DUT MI (25 mA Range)1, 3 650 µs 20 V step, R = 800 Ω, C = 0.22 µF, full dc load DUT DUT MI (2.5 mA Range)1, 3 6400 µs 10 V step, R = 4 kΩ, C = 0.22 µF, full dc load DUT DUT MI Buffer Alone1 10 15 µs 0.5 V step using MEASOUT high-Z to within 10 mV of final value SETTLING TIME (FV, MEASURE Compensation Register 1 = 0x4880 (229 nF to To within 10 mV of programmed value VOLTAGE) 380 nF, ESR 74 to 140 mΩ) MV (1200 mA Range)1 16 µs 3.7 V step, R = 2.4 Ω, C = 0.22 µF, full dc load DUT DUT MV (900 mA Range)1 20 µs 8 V step, R = 8.8 Ω, C = 0.22 µF, full dc load DUT DUT MV (500 mA Range)1 34 µs 15 V step, R = 30 Ω, C = 0.22 µF, full dc load DUT DUT MV (300 mA Range)1 25 µs 10 V step, R = 33.3 Ω, C = 0.22 µF, full dc load DUT DUT MV (25 mA Range)1, 3 125 180 µs 20 V step, R = 800 Ω, C = 0.22 µF, full dc load DUT DUT MV (2.5 mA Range)1, 3 300 500 µs 10 V step, R = 4 kΩ, C = 0.22 µF, full dc load DUT DUT MV (250 µA Range)1, 3 300 500 µs 10 V step, R = 40 kΩ, C = 0.22 µF, full dc load DUT DUT MV Buffer Alone1 2 5 µs 10 V step using MEASOUT high-Z to within 10 mV of final value SETTLING TIME (FV) SAFE MODE To within 100 mV of programmed value FV (1200 mA EXTFORCE1 Range1 25 µs 3.7 V step, R = 3.1 Ω, C = 0.22 µF, full dc load DUT DUT FV (180 mA EXTFORCE1 Range)1 303 µs 3 V step, R = 16 Ω, C = 0. 22 µF to 20 μF, full DUT DUT dc load FV (100 mA EXTFORCE2 Range)1 660 µs 8 V step, R = 33.3 Ω, C = 0. 22 µF to 20 μF, DUT DUT full dc load FV (25 mA Range)1, 3 760 1000 µs 20 V step, R = 400 Ω, C = 0.22 µF, full dc load DUT DUT SWITCHING TRANSIENTS Range Change Transient1 0.5 % of FV C = 10 μF, changing from higher to adjacent DUT lower ranges (except EXTFORCE1 to EXTFORCE2) 20 mV C = 10 μF, changing from lower (5 µA) to DUT higher range (EXTFORCE1) 0.5 % of FV C = 100 μF, changing between all ranges DUT DAC SPECIFICATIONS Force/Comparator/Offset DACs Resolution 16 Bits Voltage Output Span −22 +25 V V = 5 V, minimum and maximum values set REF by offset DAC Differential Nonlinearity1 −1 +1 LSB Guaranteed monotonic Offset DAC Gain Error −20 +20 mV Clamp DAC CLL < CLH Resolution 16 Bits Voltage Output Span −22 +25 V V = 5 V, minimum and maximum values set REF by offset DAC Differential Nonlinearity1 −1 +1 LSB Guaranteed monotonic OSD DAC Resolution 16 Bits Voltage Output Span 0.62 5 V V = 5 V REF Differential Nonlinearity1 −2 +2 LSB DGS DAC Resolution 16 Bits Voltage Output Span 0 5 V V = 5 V REF Differential Nonlinearity1 −2 +2 LSB Comparator DAC Dynamic Output Voltage Settling Time1 3.5 6 µs 1 V change to 1 LSB Slew Rate1 1 V/µs Digital-to-Analog Glitch 10 nV-s Energy1 Glitch Impulse Peak Amplitude1 40 mV Rev. E | Page 9 of 66

AD5560 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUT VREF DC Input Impedance 1 MΩ Typically 100 MΩ VREF Input Current −10 +10 µA Per input; typically ±30 nA VREF Range1 2 5 V COMPARATOR Measured directly at comparator; does not include measure block errors Error −7 +7 mV Uncalibrated VOLTAGE COMPARATOR With respect to the measured voltage Propagation Delay1 0.25 µs Error1 −12 +12 mV Uncalibrated CURRENT COMPARATOR Propagation Delay1 0.25 1 µs Error1 −1.5 +1.5 % Of programmed current range, uncalibrated MEASURE OUTPUT, MEASOUT Measure Output Voltage Span1 −12.81 +12.81 V MEASOUT gain = 1, V = 5 V, offset DAC = REF 0x8000 Measure Output Voltage Span1 −6.405 +6.405 V MEASOUT gain = 1, V = 2.5 V REF Measure Output Voltage Span1 0 5.125 V MEASOUT gain = 0.2, V = 5 V, offset DAC = REF 0x8000 Measure Output Voltage Span1 0 2.56 V MEASOUT gain = 0.2, V = 2.5 V REF Measure Pin Output Impedance 115 Ω Output Leakage Current −100 +100 nA When HW_INH is low Output Capacitance1 5 pF Short-Circuit Current1 −10 +10 mA OPEN-SENSE DETECT/CLAMP/ALARM Measurement Accuracy −200 +200 mV Clamp Accuracy 600 900 mV Alarm Delay1 50 μs DUTGND Voltage Range1 −1 +1 V Pull-Up Current +50 +70 μA Pull-up for purpose of detecting open circuit on DUTGND, can be disabled Leakage Current −1 +1 μA When pull-up disabled, DGS DAC = 0x3333 (1 V with V = 5 V); if DUTGND voltage is far away REF from one of comparator thresholds, more leakage may be present Trip Point Accuracy −30 +10 mV Alarm Delay1 50 μs GUARD AMPLIFIER Voltage Range1 AV + 2.25 AV − 2.25 V SS DD Voltage Span1 25 V Output Offset −10 +10 mV Short-Circuit Current1 −20 +20 mA Load Capacitance1 100 nF Output Impedance 100 Ω Alarm Delay1 200 μs If it moves 100 mV away from input level DIE TEMPERATURE SENSOR Accuracy1 −10 +10 % Relative to a temperature change Output Voltage at 25°C 1.54 V Output Scale Factor1 4.7 mV/°C Output Voltage Range1 1 2 V Rev. E | Page 10 of 66

Data Sheet AD5560 Parameter Min Typ Max Unit Test Conditions/Comments SPI INTERFACE LOGIC Logic Inputs Input High Voltage, V 1.7/2.0 V (2.3 V to 2.7 V)/(2.7 V to 5.5 V) JEDEC-compliant IH input levels Input Low Voltage, V 0.7/0.8 V (2.3 V to 2.7 V)/(2.7 V to 5.5 V) JEDEC-compliant IL input levels Input Current, I , I −1 +1 µA INH INL Input Capacitance, C 1 10 pF IN CMOS Logic Outputs SDO, CPOL, CPOH, GPO, CPO Output High Voltage, V DV − 0.4 V OH CC Output Low Voltage, V 0.4 V I = 500 µA OL OL Tristate Leakage Current −1 +1 μA SDO, CPOL, CPOH, CPO Output Capacitance1 10 10 10 pF SDO, CPOL, CPOH, CPO Open-Drain Logic Outputs BUSY, TMPALM, CLALM, KELALM Output Low Voltage, V 0.4 V I = 500 µA, C = 50 pF, R = 1 kΩ OL OL L PULLUP Output Capacitance1 10 pF POWER SUPPLIES HCAV 1x 4 28 V |HCAV x – HCAV x| < 33 V, HCAV x ≥ AV , DD DD SS SS SS HCAV x ≤ AV DD DD HCAV 1x −25 −5 V SS HCAV 2x 4 28 V |HCAV x – HCAV x| < 33 V, HCAV x ≥ AV , DD DD SS SS SS HCAV x ≤ AV DD DD HCAV 2x −25 −5 V SS AV 8 28 V |AV – AV | < 33 V DD DD SS AV −25 −5 V SS DV 2.3 5.5 V CC AI 4 30 mA All ranges DD AI 4 −30 mA All ranges SS DI 3 mA CC AI 4 27 mA Channel inhibited/tristate, HW_INH or SW-INH low DD AI 4 −27 mA Channel inhibited/tristate, HW_INH or SW-INH low SS HCAV x and HCAV x supply currents shown DD SS are excluding load currents; however, for power budget calculations, the supply currents here are consumed by the load HCAI 1 20 mA When enabled, excluding load conditions DD HCAI 1 0.5 mA When disabled DD HCAI 1 −20 mA When enabled, excluding load condition SS HCAI 1 −0.5 mA When disabled SS HCAI 2 15 mA When enabled, excluding load conditions DD HCAI 2 0.25 mA When disabled DD HCAI 2 −15 mA When enabled, excluding load conditions SS HCAI 2 −0.25 mA When disabled SS POWER-DOWN CURRENTS Supply currents on power-up or during a power-down condition HCAI 250 μA DD HCAI −250 μA SS HCAI 250 μA DD HCAI −250 μA SS AI 5 mA DD AI −5 mA SS DI 3 mA CC Maximum Power Dissipation EXTFORCE1 10 W EXTFORCE2 5 W Power-Up Overshoot1 5 % Of programmed value Rev. E | Page 11 of 66

AD5560 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments Power Supply Sensitivity1 DC to 1 kHz ΔForced Voltage/ΔAV −65 dB −30 dB at 100 kHz DD ΔForced Voltage/ΔAV −65 dB −25 dB at 100 kHz SS ΔForced Voltage/ΔHCAV x −90 dB −60 dB at 100 kHz DD ΔForced Voltage/ΔHCAV x −90 dB −62 dB at 100 kHz SS ΔMeasured Current/ΔAV −50 dB −25 dB at 100 kHz DD ΔMeasured Current/ΔAV −43 dB −20 dB at 100 kHz SS ΔMeasured Current/ΔHCAV x −90 dB −60 dB at 100 kHz DD ΔMeasured Current/ΔHCAV x −90 dB −60 dB at 100 kHz SS ΔMeasured Voltage/ΔAV −65 dB −30 dB at 100 kHz DD ΔMeasured Voltage/ΔAV −65 dB −25 dB at 100 kHz SS ΔMeasured Voltage/ΔHCAV x −90 dB −60 dB at 100 kHz DD ΔMeasured Voltage/ΔHCAV x −90 dB −65 dB at 100 kHz SS ΔForced Voltage/ΔDV −80 dB −46 dB at 100 kHz CC ΔMeasured Current/ΔDV −80 dB −36 dB at 100 kHz CC ΔMeasured Voltage/ΔDV −80 dB −46 dB at 100 kHz CC 1 Guaranteed by design and characterization, not subject to production test. 2 Programmable clamps must be enabled if taking advantage of reduced headroom/footroom. 3 Clamps disabled. 4 Not including internal pull-up current between AVDD/AVSS and HCAVDDx/HCAVSSx pins. Rev. E | Page 12 of 66

Data Sheet AD5560 TIMING CHARACTERISTICS HCAV x ≤ AV + 33 V, HCAV x ≥ AV , AV ≥ 8 V, AV ≤ −5 V, |AV − AV | ≥ 16 V and ≤ 33 V, V = 5 V (T = 25°C to 90°C, DD SS SS SS DD SS DD SS REF J maximum specifications, unless otherwise noted). Table 2. SPI Interface DV = 2.3 V DV = 2.7 V DV = 4.5 V CC CC CC Parameter1, 2, 3 to 2.7 V to 3.3 V to 5.5 V Unit Description t 600 600 600 ns max Channel update cycle time UPDATE t 25 20 20 ns min SCLK cycle time; 60/40 duty cycle 1 t 10 8 8 ns min SCLK high time 2 t 10 8 8 ns min SCLK low time 3 t 10 10 10 ns min SYNC falling edge to SCLK falling edge setup time 4 t 15 15 15 ns min Minimum SYNC high time 5 t 5 5 5 ns min 24th SCLK falling edge to SYNC rising edge 6 t 5 5 5 ns min Data setup time 7 t 4.5 4.5 4.5 ns min Data hold time 8 t4 40 35 30 ns max SYNC rising edge to BUSY falling edge 9 t 1.5 1.5 1.5 μs max BUSY pulse width low for DAC x1 write 10 280 280 280 ns max BUSY pulse width low for other register write t 25 20 10 ns min RESET pulse width low 11 t 400 400 400 µs max RESET time indicated by BUSY low 12 t 250 250 250 ns min Minimum SYNC high time in readback mode 13 t 5, 6 45 35 25 ns max SCLK rising edge to SDO valid 14 t 30 30 30 ns max SYNC rising edge to SDO high-Z 15 LOAD TIMING t 20 20 20 ns min LOAD pulse width low 16 t 150 150 150 ns min BUSY rising edge to force output response time 17 t 0 0 0 ns min BUSY rising edge to LOAD falling edge 18 t 150 150 150 ns min LOAD rising edge to FORCE output response time 19 150 150 150 ns min LOAD rising edge to current range response 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with t = t = 2 ns (10% to 90% of DV ) and timed from a voltage level of 1.2 V. R F CC 3 See Figure 4 and Figure 5. 4 This is measured with the load circuit shown in Figure 2. 5 This is measured with the load circuit shown in Figure 3. 6 Longer SCLK cycle time is required for correct operation of readback mode; consult timing diagrams and timing specifications. TIMING DIAGRAMS DVCC 200µA IOL RLOAD 2.2kΩ TO OUTPUT VOH (MIN) – VOL (MAX) PIN 2 CLOAD TO OUTPUT 50pF PIN CL5O0pAFD VOL 07779-002 200µA IOL 07779-003 Figure 2. Load Circuit for Open Drain Figure 3. Load Circuit for CMOS Rev. E | Page 13 of 66

AD5560 Data Sheet t1 SCLK 1 2 24 t3 t2 t4 t6 SYNC t5 t7 t8 SDI DB23 DB0 t9 t10 BUSY t16 LOAD1,3 EXTFFOORRCCEE1 t17 EXTFORCE21 t18 t16 LOAD2,3 FORCE EXETXFTOFROCREC2E2,13 t19 t11 RESET BUSY t12 123LLLOOOAAADDD AAFCCUTTNIICVVTEEIOADFNUT RIESINR AGBVUBAUSILYSA.YB.LE VIA CLEN OR HW_INH AS DETERMINED BY DPS REGISTER 2. 07779-004 Figure 4. SPI Write Timing SCLK 24 48 t14 t13 SYNC t15 SDI DB23 D0B DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ SDO DB23 DB0 SELECCTLEOD CRKEEGDIS OTUETR DATA 07779-005 Figure 5. SPI Read Timing Rev. E | Page 14 of 66

Data Sheet AD5560 ABSOLUTE MAXIMUM RATINGS Table 3. Stresses at or above those listed under Absolute Maximum Parameter Rating Ratings may cause permanent damage to the product. This is a AV to AV 34 V stress rating only; functional operation of the product at these DD SS AVDD to AGND −0.3 V to +34 V or any other conditions above those indicated in the operational AVSS to AGND −34 V to +0.3 V section of this specification is not implied. Operation beyond HCAV x to HCAV x 34 V DD SS the maximum operating conditions for extended periods may HCAV x to AGND −0.3 V to +34 V DD affect product reliability. HCAV x to AGND −34 V to +0.3 V SS HCAV x to AV −0.3 V to AV + 34 V DD SS SS HCAV x to AV −0.3 V to AV + 0.3 V DD DD DD ESD CAUTION HCAV x to AV +0.3 V to AV − 0.3 V SS SS SS DV to DGND −0.3 V to +7 V CC AGND to DGND −0.3 V to +0.3 V REFGND to AGND −0.3 V to +0.3 V Digital Inputs to DGND −0.3 V to DV + 0.3 V CC Analog Inputs to AGND AV − 0.3 V to AV + 0.3 V SS DD EXTFORCE1 and EXTFORCE2 to AGND1 AV − 28 V DD Storage Temperature −65°C to +125°C Operating Junction Temperature 25°C to 90°C Reflow Profile J-STD 20 (JEDEC) Junction Temperature 150°C max Power Dissipation 10 W max (EXTFORCE1 stage) 5 W max (EXTFORCE2 stage) ESD HBM 1500 V FICDM 500 V 1 When an EXTFORCE1 or EXTFORCE2 stage is enabled and the supply differ- ential |AV − AV | > 28 V, take care to ensure that these pins are not directly DD SS shorted to AV voltage at any time because this can cause damage to the device. SS Rev. E | Page 15 of 66

AD5560 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS C B B A A 1 2 1 2 1 PO C_V1CSS XTFORCE CAV1CDD CAV2BDD XTFORCE CAV2BSS CAV1BSS XTFORCE CAV1BDD CAV2ADD XTFORCE CAV2ASS CAV1ASS XTFORCE CAV1ADD G H E H H E H H E H H E H H E H 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CLALM 1 48 EXTMEASIH2 KELALM 2 PIN 1 47 EXTMEASIH1 TMPALM 3 46 AVDD CPOH/CPO 4 45 AVSS CPOL 5 44 AGND BUSY 6 43 GUARD/SYS_DUTGND SDO 7 AD5560 42 EXTMEASIL DVCC 8 TOP VIEW 41 SENSE DGND 9 (Not to Scale) 40 DUTGND SCLK 10 EXPOSED PAD ON TOP 39 CF0 SDI 11 38 CF1 SYNC 12 37 CF2 RCLK 13 36 CF3 RESET 14 35 CF4 CLEN/LOAD 15 34 NC HW_INH/LOAD 16 33 AVDD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 REFGND VREF AGND AVSS AVDD MEASOUT CC3 CC0 CC1 CC2 SLAVE_IN STER_OUT YS_SENSE AVSS YS_FORCE FORCE A S S M N12 .. O NEMTXCOEP SS=O TNS NOEE DCG OPAANTDNIV EOECN PT .TOOINPT O, AFV PSAS.CKAGE. EXPOSED PAD IS INTERNALLY CONNECTED TO 07779-006 Figure 6. TQFP_EP Pin Configuration Table 4. TQFP_EP Pin Function Descriptions Pin No. Mnemonic Description 1 CLALM Clamp Alarm Output. Open-drain output, active low; this pin can be programmed to be either latched or unlatched. 2 KELALM Kelvin Alarm Pin for SENSE and DUTGND, Open-Drain Active Low. This pin can be programmed to be either latched or unlatched. 3 TMPALM Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched or unlatched. 4 CPOH/CPO Comparator High Output (CPOH) or Window Comparator Output (CPO). 5 CPOL Comparator Low Output. 6 BUSY Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels. 7 SDO Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic purposes. 8 DV Digital Supply Voltage. CC 9 DGND Digital Ground Reference Point. 10 SCLK Clock Input, Active Falling Edge. 11 SDI Serial Data Input. 12 SYNC Frame Sync, Active Low. 13 RCLK Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied to this input to drive the ramp circuitry. Tie RCLK low if it is unused. 14 RESET Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value. 15 CLEN/LOAD Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as LOAD input (see the system control register, Address 0x1). 16 HW_INH/LOAD Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system control register, Address 0x1). 17 REFGND Accurate Ground Reference for Applied Voltage Reference. Rev. E | Page 16 of 66

Data Sheet AD5560 Pin No. Mnemonic Description 18 VREF Reference Input for DAC Channels, Input Range 2 V to 5 V. 19, 44 AGND Analog Ground. 20, 30, 45 AV Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as SS measure blocks. 21, 33, 46 AV Positive Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as DD measure blocks. 22 MEASOUT Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND. 23 C Compensation Capacitor Input 3. C3 24 C Compensation Capacitor Input 0. C0 25 C Compensation Capacitor Input 1. C1 26 C Compensation Capacitor Input 2. C2 27 SLAVE_IN Slave Input When Ganging Multiple DPS Devices. 28 MASTER_OUT Master Output When Ganging Multiple DPS Devices. 29 SYS_SENSE External Sense Signal Output. 31 SYS_FORCE External Force Signal Input. 32 FORCE Output Force Pin for Internal Current Ranges. 34 NC No Connect. 35 C Feedforward Capacitor 4. F4 36 C Feedforward Capacitor 3. F3 37 C Feedforward Capacitor 2. F2 38 C Feedforward Capacitor 1. F1 39 C Feedforward Capacitor 0. F0 40 DUTGND Device Under Test Ground. 41 SENSE Input Sense Line. 42 EXTMEASIL Low Side Measure Current Line for External High Current Ranges. 43 GUARD/SYS_DUTGND Guard Amplifier Output Pin or System Device Under Test Ground Pin. See the DPS Register 2 in Table 19 for addressing details. 47 EXTMEASIH1 Input High Measure Line for External High Current Range 1. 48 EXTMEASIH2 Input High Measure Line for External High Current Range 2. 49, 55, 61 HCAV 1A, High Current Positive Analog Supply Voltage, for EXTFORCE1 Range. DD HCAV 1B, DD HCAV 1C DD 50, 56, 62 EXTFORCE1A, Output Force. This pin is used for high Current Range 1, up to a maximum of ±1.2 A. EXTFORCE1B, EXTFORCE1C 51, 57, 63 HCAV 1A, High Current Negative Analog Supply Voltage, for EXTFORCE1 Range. SS HCAV 1B, SS HCAV 1C SS 52, 58 HCAV 2A, HCAV 2B High Current Negative Analog Supply Voltage, for EXTFORCE2 Range. SS SS 53, 59 EXTFORCE2A, Output Force. This pin is used for high Current Range 2, up to a maximum of ±500 mA. EXTFORCE2B 54, 60 HCAV 2A, High Current Positive Analog Supply Voltage, for EXTFORCE2 Range. DD HCAV 2B DD 64 GPO Extra Logic Output Bit. Ideal for external functions such as switching out a decoupling capacitor at DUT. 65 EP The exposed pad is internally connected to AV . SS Rev. E | Page 17 of 66

AD5560 Data Sheet 9 8 7 6 5 4 3 2 1 A EXTFORCE1A EXTFORCE1A EXTFORCE2A EXTFORCE1B EXTFORCE1B EXTFORCE2B EXTFORCE1C EXTFORCE1C GPO B HCAVDD1A HCAVSS1A HCAVDD2A HCAVDD1B HCAVSS1B HCAVDD2B HCAVDD1C HCAVSS1C CLALM C HCAVDD1A HCAVSS1A HCAVSS2A HCAVDD1B HCAVSS1B HCAVSS2B HCAVDD1C HCAVSS1C KELALM D AVDD EXTMEASIH1 EXTMEASIH2 CPOL CPOH/CPO TMPALM E AVSS AGND SYSG_UDAURTDG/ND 3 × 3 ARRAY IS VOID OF BALLS DVCC SDO BUSY F DUTGND EXTMEASIL SENSE SDI SCLK DGND G CF0 CF2 SYS_FORCE SYS_SENSE CC0 AVSS RESET RCLK SYNC CLEN/ H CF1 CF3 SLAVE_IN MASTER_OUT CC1 MEASOUT AVDD VREF LOAD HW_INH/ J CF4 AVDD FORCE CC2 CC3 AVSS AGND REFGND LOAD 07779-062 Figure 7. Flip-Chip BGA Pin Configuration, Bottom Side (BGA Balls Are Visible) Table 5. Flip-Chip BGA Pin Function Descriptions Pin No. Mnemonic Description A1 GPO Extra Logic Output Bit. Ideal for external functions such as switching out a decoupling capacitor at DUT. A2, A3 EXTFORCE1C Output Force. These pins are used for high Current Range 1, up to a maximum of ±1.2 A. A4 EXTFORCE2B Output Force. This pin is used for high Current Range 2, up to a maximum of ±500 mA. A5, A6 EXTFORCE1B Output Force. These pins are used for high Current Range 1, up to a maximum of ±1.2 A. A7 EXTFORCE2A Output Force. This pin is used for high Current Range 2, up to a maximum of ±500 mA. A8, A9 EXTFORCE1A Output Force. These pins are used for high Current Range 1, up to a maximum of ±1.2 A. B1 CLALM Clamp Alarm Output. Open-drain output, active low; this pin can be programmed to be either latched or unlatched. B2, C2 HCAV 1C High Current Negative Analog Supply Voltage for EXTFORCE1 Range. SS B3, C3 HCAV 1C High Current Positive Analog Supply Voltage for EXTFORCE1 Range. DD B4 HCAV 2B High Current Positive Analog Supply Voltage for EXTFORCE2 Range. DD B5, C5 HCAV 1B High Current Negative Analog Supply Voltage for EXTFORCE1 Range. SS B6, C6 HCAV 1B High Current Positive Analog Supply Voltage for EXTFORCE1 Range. DD B7 HCAV 2A High Current Positive Analog Supply Voltage for EXTFORCE2 Range. DD B8, C8 HCAV 1A High Current Negative Analog Supply Voltage for EXTFORCE1 Range. SS B9, C9 HCAV 1A High Current Positive Analog Supply Voltage for EXTFORCE1 Range. DD C1 KELALM Kelvin Alarm Pin for SENSE and DUTGND, Open-Drain Active Low. This pin can be programmed to be either latched or unlatched. C4 HCAV 2B High Current Negative Analog Supply Voltage for EXTFORCE2 Range. SS C7 HCAV 2A High Current Negative Analog Supply Voltage for EXTFORCE2 Range. SS Rev. E | Page 18 of 66

Data Sheet AD5560 Pin No. Mnemonic Description D1 TMPALM Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched or unlatched. D2 CPOH/CPO Comparator High Output (CPOH) or Window Comparator Output (CPO). D3 CPOL Comparator Low Output. D7 EXTMEASIH2 Input High Measure Line for External High Current Range 2. D8 EXTMEASIH1 Input High Measure Line for External High Current Range 1. D9,H3, J8 AV Positive Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as DD measure blocks. E1 BUSY Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels. E2 SDO Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic purposes. E3 DV Digital Supply Voltage. CC E7 GUARD/SYS_DUTGND Guard Amplifier Output Pin or System Device Under Test Ground Pin. See the DPS Register 2 in Table 19 for addressing details. E8 AGND Analog Ground. E9, G4, J4 AV Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as SS measure blocks. F1 DGND Digital Ground Reference Point. F2 SCLK Clock Input, Active Falling Edge. F3 SDI Serial Data Input. F7 SENSE Input Sense Line. F8 EXTMEASIL Low Side Measure Current Line for External High Current Ranges. F9 DUTGND Device Under Test Ground. G1 SYNC Frame Sync, Active Low. G2 RCLK Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied to this input to drive the ramp circuitry. Tie RCLK low if it is unused. G3 RESET Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value. G5 C Compensation Capacitor Input 0. C0 G6 SYS_SENSE External Sense Signal Output. G7 SYS_FORCE External Force Signal Input. G8 C Feedforward Capacitor 2. F2 G9 C Feedforward Capacitor 0. F0 H1 CLEN/LOAD Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as LOAD input (see the system control register, Address 0x1). H2 VREF Reference Input for DAC Channels, Input Range is 2 V to 5 V. H4 MEASOUT Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND. H5 C Compensation Capacitor Input 1. C1 H6 MASTER_OUT Master Output When Ganging Multiple DPS Devices. H7 SLAVE_IN Slave Input When Ganging Multiple DPS Devices. H8 C Feedforward Capacitor 3. F3 H9 C Feedforward Capacitor 1. F1 J1 HW_INH/LOAD Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system control register, Address 0x1). J2 REFGND Accurate Ground Reference for Applied Voltage Reference. J3 AGND Analog Ground. J5 C Compensation Capacitor Input 3. C3 J6 C Compensation Capacitor Input 2. C2 J7 FORCE Output Force Pin for Internal Current Ranges. J9 C Feedforward Capacitor 4. F4 Rev. E | Page 19 of 66

AD5560 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.2 12 TJ = 25°C 1.0 10 AAVVDSSD == –82V5V VREF = 5V 8 OFFSET DAC = 0xD4EB 0.8 V) RITY (mV) 0.6 ARITY (m 46 MEASOUT GAIN = 0.2 LINEA 0.4 V LINE 2 M 0.2 0 0 –2 MEASOUT GAIN = 1 –0.20 10,000 20,000 30,0C0O0DE40,000 50,000 60,000 07779-026 –40 10,000 20,000 30,0C0O0DE40,000 50,000 60,000 07779-034 Figure 8. Force Voltage Linearity vs. Code, V = 5 V, No Load Figure 11. Measure Voltage Linearity vs. Code (MEASOUT Gain 1, REF MEASOUT Gain = 0.2, Negative Skew Supply) 2.0 0.0100 TJ = 25°C HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D 1.5 AAVVDSSD == –1166.2.255VV 0.0075 LNOOWM:: AAVVDDDD /=A V5SVS, A= V±S1S6 .=2 5–V2,5 OV FOFFSFESTE DT ADCA C= 0=x 08x0D004EB VREF = 5V VREF = 5V V) 1.0 0.0050 m R ( RITY ERRO 0.50 MEASOUT GAIN = 0.2 EARITY (%) 0.00250 LOW SUPPLIES A N NE–0.5 LI–0.0025 LI MV –1.0 –0.0050 –1.5 –0.0075 NOMINAL SUPPLIES MEASOUT GAIN = 1 HIGH SUPPLIES –2.00 10,000 20,000 30,0C0O0DE40,000 50,000 60,000 07779-027 –0.01000 10,000 20,000 30,00C0OD4E0,000 50,000 60,000 70,000 07779-035 Figure 9. Measure Voltage Linearity vs. Code (MEASOUT Gain = 1, Figure 12. Measure Current Linearity vs. Code (MEASOUT Gain = 1, MEASOUT Gain = 0.2, Nominal Supplies) MI Gain = 20), T = 25°C J 5 0.010 TJ = 25°C HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D AVDD = 28V LOW: AVDD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB 4 AVSS= –5V NOM: AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000 VREF = 5V VREF = 5V OFFSET DAC = 0xD1D 0.005 3 mV) %) ARITY ( 2 MEASOUT GAIN = 0.2 ARITY ( 0 LOW SUPPLIES NE 1 NE V LI MI LI M 0 –0.005 –1 MEASOUT GAIN = 1 NOMINAL SUPPLIES HIGH SUPPLIES –20 10,000 20,000 30,0C0O0DE40,000 50,000 60,000 07779-033 –0.0100 10,000 20,000 30,00C0OD4E0,000 50,000 60,000 70,000 07779-036 Figure 10. Measure Voltage Linearity vs. Code (MEASOUT Gain = 1, Figure 13. Measure Current Linearity vs. Code (MEASOUT Gain = 1, MEASOUT Gain = 0.2, Positive Skew Supply) MI Gain = 10) Rev. E | Page 20 of 66

Data Sheet AD5560 0.0500 0.0500 0.0375 HLNV±2ORIOG5EWMmHF :::A= AAA 5RVVVVADDDDDND / G=A= EV 52SV8S,V A=, VA±SV1SS6. S2= 5 =–V 2–, 55OVVF ,O FOSFFFEFSTSE DETAT D CDA A=C C0 = x= 80 00x0xD0D41EDB 0.0375 AOAVRVVFEDSFFSDS =E== T 5–+ V1D166A..2C255 V=V 0x8000 0.0250 0.0250 MI GAIN = 20 MEASOUT GAIN = 0.2 25µA RANGE %) 0.0125 NOMINAL SUPPLIES %) 0.0125 Y ( Y ( RIT 0 LOW SUPPLIES RIT 0 A A E E N N LI–0.0125 LI–0.0125 –0.0250 –0.0250 2.5mA –0.0375 –0.0375 25mA RANGE HIGH SUPPLIES –0.05000 10,000 20,000 30,00C0OD4E0,000 50,000 60,000 70,000 07779-037 –0.05000 10,000 20,000 30,0C0O0DE40,000 50,000 60,000 07779-040 Figure 14. Measure Current Linearity vs. Code (MEASOUT Gain = 0.2, Figure 17. Measure Current Linearity vs. I (MEASOUT Gain = 0.2, RANGE MI Gain = 20) MI Gain = 20) 0.100 1.5 HLOIGWH :: AAVVDDDD == 258VV, ,A AVVSSSS = = – –255VV, OOFFFFSSEETT DDAACC == 00xxDD41EDB TJ = 25°C 0.075 NOM : AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000 1.0 VREF = 5V±25mA RANGE 0.5 0.050 A) %) 0.025 HIGH SUPPLIES NT (n 0 Y ( RE–0.5 EXTFORCE1A EARIT 0 E CUR–1.0 EFEOXXTTRFFCOOERRCCEE21BB LIN–0.025 NOMINAL SUPPLIES KAG–1.5 ESXETNMSEEASIH1 A EXTFORCE1C E –0.050 LOW SUPPLIES L–2.0 ESYXSTM_FEOARSCIHE2 EXTFORCE2A –0.075 –2.5 EXTMEASIL SYS_SENSE COMBINED LEAKAGE –0.1000 10,000 20,000 30,00C0OD4E0,000 50,000 60,000 70,000 07779-038 –3.0–10 5 STRESS VO0LTAGE (V) 5 10 07779-030 Figure 15. Measure Current Linearity vs. Code (MEASOUT Gain = 0.2, Figure 18. Leakage Current vs. Stress Voltage (Force and Combined Leakage) MI Gain = 10) 0.0100 7 AAVVDSSD == –+1166..2255VV VSTRESS = 9V 0.0075 VREF = 5V 6 OFFSET DAC = 0x8000 0.0050 MMIE GASAOINU =T 2G0AIN = 1 25µA RANGE nA) 5 %) 0.0025 NT ( EEXXTTFFOORRCCEE12BA Y ( RE 4 FORCE ARIT 0 CUR EEXXTTFMOERACSEIH11B LINE–0.0025 2.5mA KAGE 3 SEEXEXTTNFMSOEERACSEIH12C A SYS_FORCE –0.0050 LE 2 EXTFORCE2A EXTMEASIL SYS_SENSE –0.0075 25mA RANGE 1 COMBINED LEAKAGE –0.01000 10,000 20,000 30,0C0O0DE40,000 50,000 60,000 07779-039 025 35 45 TEM5P5ERATUR6E5(°C) 75 85 95 07779-031 Figure 16. Measure Current Linearity vs. I (MEASOUT Gain = 1, Figure 19. Leakage Current vs. Temperature (Force and Combined Leakage), RANGE MI Gain = 20) V = 9 V STRESS Rev. E | Page 21 of 66

AD5560 Data Sheet 0 0.15 EXTFORCE1A EXTFORCE2B TJ = 25°C 0.10 EEXXTTFMOERACSEIH11B –0.02 SENSE NT (nA) 0.05 EESEXYXXTSTTFFM_FOOEORRARCCSCEEIHE122CA R (%)–0.04 NOMINAL HIGH RRE 0 ESXYTSM_SEEANSSILE RRO–0.06 U E AGE C–0.05 GAIN –0.08 LOW K A E–0.10 L –0.10 –0.15 –0.12 –0.20–10 5 STRESS VO0LTAGE (V) 5 10 07779-032 25 35 45TEMPER55ATURE6(°5C) 75 85 07779-48 Figure 20. Leakage Current vs. Stress Voltage Figure 23. MI Positive Gain Error vs. Temperature, MI Gain = 20, MEASOUT Gain = 1 0.8 1.8 0 0.7 VSTRESS=9V 1.6 AAVVVREDSFSD === 5–±V1166..2255VV A) 0.6 mV) 1.4 OFFSET DAC = 0x8000 –0.5 mV) E CURRENT (n 00..45 EEEESEXXXXEXTTTTNTMFFFFSOOOOEERRRRACCCCSEEEEIH11121CABB GAIN ERROR ( 011...802 –1.0 GAIN ERROR ( LEAKAG 00..23 ESEESXYXXYTTTSSMMF__SFOEEOERAANRCSSSCEIIHLEE22A POSITIVE 00..46 ––21..05 NEGATIVE 0.1 0.2 025 35 45 TEM5P5ERATUR6E5(°C) 75 85 95 07779-061 025 35 45TEMPE5R5ATURE 6(5°C) 75 85 –2.5 07779-043 Figure 21. Leakage Current vs. Temperature, VSTRESS = 9 V Figure 24. FV Gain Error vs. Temperature 0.10 23.0 HIGH 0.2 LOW 0.05 22.5 NOMINAL OR (%) 0 NOMINAL 0.2 R (mV)22.0 R HIGH O ER–0.05 RR21.5 ET T E S E F S OF–0.10 FF21.0 LOW 0.2 O –0.15 HLOIGWH :: AAVVDDDD == 258VV, ,A AVVSSSS = = – –255VV, OOFFFFSSEETT DDAACC == 00xxDD41EDB 20.5 NOM : AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000 VREF = 5V LOW0.2/HIGH0.2/NOM0.2 MEAN FOR MEASOUT GAIN = 0.2 –0.2025 35 45TEMPER55ATURE6(°5C) 75 85 07779-047 20.025 35 45TEMPE5R5ATURE6(5°C) 75 85 07779-041 Figure 22. MI Offset Error vs. Temperature, MI Gain = 20, Figure 25. FV Offset Error vs. Temperature MEASOUT Gain = 1 and 0.2 Rev. E | Page 22 of 66

Data Sheet AD5560 0 5 HIGH 4 –0.001 3 –0.002 V) 2 AIN ERROR (%)––00..000043 NOMINAL LOW SET ERROR (m –101 NOMINAL G–0.005 OFF –2 HIGH –3 LOW –0.006 –4 –0.00725 35 45TEMPER55ATURE6(°5C) 75 85 07779-045 –525 35 45TEMPER55ATURE6(°5C) 75 85 07779-044 Figure 26. MV Gain Error vs. Temperature, MEASOUT Gain = 1 Figure 29. MV Offset Error vs. Temperature, MEASOUT Gain = 0.2 1.0 CH1 p-p 0.9 27mV HIGH CH1AREA 0.8 10.92µVs NOMINAL V) 0.7 R (m 0.6 LOW O FORCE R R 0.5 1 E T E 0.4 S F OF 0.3 0.2 0.0125 35 45TEMPE5R5ATURE6(5°C) 75 85 07779-042 3 CCHH31 55V0mV BBWW SYMNT 2C 0100.µ4s% A CH3 1.5V 07779-015 Figure 27. MV Offset Error vs. Temperature, MEASOUT Gain = 1 Figure 30. Range Change 2.5 mA to 25 mA, Safe Mode, 2.5 mA ILOAD, 10 μF Load 0.030 NOMINAL CH1 p-p LOW 16mV CH1AREA 0.025 –5.336µVs R (%)0.020 HIGH O FORCE RR0.015 1 E N AI G0.010 0.005 025 35 45TEMPER55ATURE6(°5C) 75 85 07779-046 3 CCHH31 55V0mV BBWW SYMTN 2C 0100.µ4s% A CH3 1.5V 07779-016 Figure 28. MV Gain Error vs. Temperature, MEASOUT Gain = 0.2 Figure 31. Range Change 25 mA to 2.5 mA, Safe Mode, 2.5 mA ILOAD, 10 μF Load Rev. E | Page 23 of 66

AD5560 Data Sheet CH1 p-p CH1 p-p 159mV 84mV CH1AREA 14.31µVs TRIGGER 2 FORCE FORCE 1 1 3 SYNC 07779-017 07779-020 CH1 50mV BW M200µs A CH3 1.5V CH1 100mV BW CH2 5V M40µs A CH2 1.6V CH3 5V BW T 10.4% T 120.4µs Figure 32. Range Change 25 mA to EXTFORCE2, Safe Mode, Figure 35. Autocompensation Mode 90% to 10% ILOAD Change, 25 mA ILOAD, 10 μF Load EXTFORCE2 Range, 10 μF Load CH1 p-p CH1 p-p 36mV TRIGGER 86mV CH1AREA –9.738µVs 2 FORCE FORCE 1 1 3 SYNC 07779-018 07779-021 CH1 50mV M200µs A CH3 1.5V CH1 100mV BW CH2 5V M40µs A CH2 4V CH3 5V T 10.4% T 120.4µs Figure 33. Range Change EXTFORCE2 to 25 mA, Safe Mode, Figure 36. Autocompensation Mode 10% to 90% ILOAD Change, 25 mA ILOAD, 10 μF Load EXTFORCE2 Range, 10 μF Load 350 10µF LOAD 30µF LOAD CH1 p-p 300 100µF LOAD 172mV 250 TRIGGER V) 2 m AK ( 200 PE FORCE TO- 150 1 K- A E P 100 50 0 MSAOEFDXEET RANCAGOUEMT OP1 MSEAOXFDETE RANCGAOUEMT 2OP MS2AO5FmDEEA RANCAGOUMETOP 07779-019 CH1 100mV BW CH2 5V MT 4 012µ0s.4µs A CH2 1.6V 07779-022 Figure 34. Kick/Droop Response vs. IRANGE, Compensation, and CLOAD,, Figure 37. Safe Mode 80% to 10%, EXTFORCE2 Range, 10 μF Load 10% to 90% to 10% ILOAD Change Rev. E | Page 24 of 66

Data Sheet AD5560 CH1 p-p TRIGGER 174mV FORCE MEASOUT – MI 2 TA = 25°C AVDD = +16.25V 1 FORCE 1 AVRVESFS == 5–V16.25V OFFSET DAC = 0x8000 IRANGE/ILOAD = 25mA 0 TO 10V STEP RLOAD = 40kΩ CLOAD = 220nF 2 AUTOCOMP MODE 0x4480 MEASOUT GAIN 1, MI GAIN 20 07779-023 43 BUSY 07779-055 CH1 100mV BW CH2 5V M40µs A CH2 4.6V CH1 5V CH2 2V BW M20µs A CH3 2.9V T 120.4µs CH3 5V CH4 10V T 1.4% Figure 38. Safe Mode 10% to 90%, EXTFORCE2 Range, 10 μF Load Figure 41. Transient Response FVMI Mode, 25 mA Range, Autocompensation Mode 2.0 AVDD = +16.5V AVSS = –16.5V FORCE 1.9 MEASOUT – MI V) E ( 1.8 G TA TA = 25°C VOL 1.7 1 AAVVDSSD == –+1166..2255VV OUT VORFEFFS =E T5 VDAC = 0x8000 EAS 1.6 0IR TANOG 1E0/IVL OSATDE =P 250µA M RLOAD = 40kΩ 2 CLOAD = 220nF 1.5 SAFE MODE BUSY MEASOUT GAIN 1, MI GAIN 20 1.425 35 FO45RCED TE5M5PERATU65RE(°C)75 85 07779-024 43 CCHH31 55VV CCHH42 120VVBW MT 1 070.2µ%s A CH3 2.9V 07779-056 Figure 39. MEASOUT TSENSE Temperature Sensor vs. Temperature Figure 42. Transient Response FVMI Mode, 25mA Range, Safe Mode (Multiple Devices) FORCE MEASOUT – MI MEASOUT – MI FORCE TA = 25°C AVDD = +16.25V 1 V0AOIR RVFTAESFNOFSGS 1=EE=0 / T5IV–L V1 DOS6AAT.2DCE5 =PV= 205x08µ0A00 1 VTAOAARVVF EDSF=FSDS 2 =E==5 T° 5–+C V1D166A..2C255 V=V 0x8000 2 RCLLOOAADD == 4202k0nΩF 0IR TANOG 3E./7ILVO SATDE =P EXTFORCE1/1.2A AMUETAOSCOOUMT PG AMIOND 1E, M0xI 4G8A8I0N 20 2 ACULOTAODC =O 1M0Pµ FM COEDREA 0MxI9C680 43 BUSY 07779-054 43 MEASOUT GAIN 1, MI GAIN 20 BUSY 07779-057 CH1 5V CH2 2V BW M400µs A CH3 2.9V CH1 5V CH2 1V BW M4µs A CH3 2.9V CH3 5V CH4 10V T 10.2% CH3 5V CH4 10V T 3% Figure 40. Transient Response FVMI Mode, ±250 μA Range, Figure 43. Transient Response FVMI Mode, EXTFORCE1 Range, Autocompensation Mode Autocompensation Mode Rev. E | Page 25 of 66

AD5560 Data Sheet 1000 PART H1 900 PART H2 PART H3 800 700 MEASOUT – MI Hz) 600 √ nV/ 500 TA = 25°C SD ( 400 1 AVDD = +16.25V N AVRVESFS == 5–V16.25V 300 OFFSET DAC = 0x8000 I0R TANOG 3E./7ILVO SATDE =P EXTFORCE1/1.2A FORCE 200 2 CLOAD = 10µF CERAMIC 100 SAFE MODE 43 CCHH13 55VV MEACCSHHO42U T11 0VGVABIWN 1, MMTI G2 04A.µ6IsN% 20 A CH3B U S 2Y.9V 07779-058 0 FVMN GAIN = 00FVMVGAIN = 10 GAIN = 00FNMVGAIN = 10 GAIN = 00 GAIN = 01FVMIGAIN = 10 GAIN = 11 07779-025 Figure 44. Transient Response FVMI Mode, EXTFORCE1 Range, Safe Mode Figure 47. NSD vs. Amplifier Stage and Gain Setting at 1 kHz 20 DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V 0 –20 1 TAVAARVV EDS=FSD 2 ===5 ° 5–+CV1166..2255VV MEASOUT – MI RR (dB) –40 OFFSET DAC = 0x8000 S I R A N G E / I L O A D = E 3X0T0FmOARCE2/ ACP FOH 0 TO 10V STEP FORCE –60 MV: GAIN 0 2 CLOAD = 220nF MMVV:: GGAAIINN 12 AUTOCOMP MODE 0x4880 MV: GAIN 3 43 MEASOUT GAIN 1, MI GAIN 20 BUSY 07779-059 –80 MMMMIIII::::G GGGAAAAIINIINNN 1 023 CCHH13 55VV CCHH42 120VVBW MT 1 09.µ8s% A CH3 2.9V –10010 100 1kFREQUE10NkCY (Hz)100k 1M 10M07779-049 Figure 45. Transient Response FVMI Mode, EXTFORCE2 Range, Figure 48. ACPSRR of AVDD vs. Frequency Autocompensation Mode 0 FORCE –20 MEASOUT – MI –40 1 TA0OIAVR ARVVFTA EDSFNO=FSDGS 2 1 =EE==50 / T° 5IV–+LC V1 DO1S66AAT..D2C2E5 5 =PV=V E0Xx8T0F0O0RCE2/300mA ACPSRR (dB) ––8600 FMMMOVVVH::: GGGAAAIIINNN 012 2 CLOAD = 220nF –100 MMVI: :G GAAININ 0 3 SAFE MODE MI:GAIN 1 43 BUSY MEASOUT GAIN 1, MI GAIN 20 07779-060 –120 DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V MMII:: GGAAIINN 23 CCHH31 55VV CCHH42 120VVBW MT 1 090.8µ%s A CH3 2.9V –14010 100 1kFREQUE10NkCY (Hz)100k 1M 10M07779-050 Figure 46. Transient Response FVMI Mode, EXTFORCE2 Range, Safe Mode Figure 49. ACPSRR of AVSS vs. Frequency Rev. E | Page 26 of 66

Data Sheet AD5560 0 0 MI: GAIN 0 –20 –20 FOH MI: GAIN 0 –40 –40 B) B) d d –60 R ( R ( R –60 R S S ACP MV: GAIN 0 ACP –80 MV: GAIN 0 –80 –100 –100 –120 FOH DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V –12010 100 1kFREQUE10NkCY (Hz)100k 1M 10M07779-051 –14010 100 1kFREQUE10NkCY (Hz)100k 1M 10M07779-053 Figure 50. ACPSRR of DV vs. Frequency Figure 52. ACPSRR of HCAV x vs. Frequency CC SS 0 1600 CABLE L = 2µH, CLAMP AT 1.2A MI: GAIN 0 CABLE L = 1µH, CLAMP AT 1.2A –20 1400 CCAABBLLEE LL == 00µ.2Hµ,H C, LCALMAPM PA TA T1. 21A.2A 1200 –40 A) CCAABBLLEE LL == 12µµHH,, CCLLAAMMPP AATT 880000mmAA R (dB) –60 MV: GAIN 0 LUE (m1000 CCAABBLLEE LL == 00µ.2Hµ,H C, LCALMAPM PA TA T80 800m0mAA R A 800 CPS –80 VMP CCAABBLLEE LL == 12µµHH,, CCLLAAMMPP AATT 440000mmAA A A600 CABLE L = 0.2µH, CLAMP AT 400mA CL CABLE L = 0µH, CLAMP AT 400mA I –100 400 CABLE L = 2µH, CLAMP AT 100mA –120 FOH 200 CCCAAABBBLLLEEE LLL === 001µ.µ2HHµ,,H CC, LLCAALMMAPMP PAA TTA T110 01000mm0mAAA DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V –14010 100 1kFREQUE10NkCY (Hz)100k 1M 10M07779-052 00.001 0.01 RLO0A.D1 (Ω) 1 10 07779-063 Figure 51. ACPSRR of HCAVDDx vs. Frequency Figure 53. ICLAMP Value vs. RLOAD – Cal at 1Ohm Rev. E | Page 27 of 66

AD5560 Data Sheet TERMINOLOGY Slew Rate Offset Error The slew rate is the rate of change of the output voltage Offset error is a measure of the difference between the actual expressed in volts per microsecond (V/μs). voltage and the ideal voltage at midscale or at zero current expressed in millivolts (mV) or percentage of full-scale range Differential Nonlinearity (DNL) (%FSR). DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified Gain Error DNL of ±1 LSB maximum ensures monotonicity. Gain error is the difference between full-scale error and zero- scale error. It is expressed in percentage of full-scale range Output Voltage Settling Time (%FSR). Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a full-scale Gain Error = Full-Scale Error − Zero-Scale Error input change. where: Digital-to-Analog Glitch Energy Full-Scale Error is the difference between the actual voltage and Digital-to-analog glitch energy is the amount of energy that is the ideal voltage at full scale. injected into the analog output at the major code transition. It Zero-Scale Error is the difference between the actual voltage and is specified as the area of the glitch in nanovolts per second the ideal voltage at zero scale. (nV-sec). It is measured by toggling the DAC register data Linearity Error between 0x7FFF and 0x8000. Linearity error, or endpoint linearity, is a measure of the AC Power Supply Rejection Ratio (ACPSRR) maximum deviation from a straight line passing through the ACPSRR is a measure of the part’s ability to avoid coupling endpoints of the full-scale range. It is measured after adjusting noise and spurious signals that appear on the supply voltage for offset error and gain error and is expressed in millivolts (mV). pin to the output of the switch. The dc voltage on the device Common-Mode (CM) Error is modulated by a sine wave of 0.2 V p-p. The ratio of the CM error is the error at the output of the amplifier due to the amplitude of the signal on the output to the amplitude of the common-mode input voltage. It is expressed in percentage of modulation is the ACPSRR. It is expressed in decibels (dB). full-scale voltage range per volt (%FSVR/V). V STRESS Clamp Limit V is the stress voltage applied to each pin during leakage STRESS Clamp limit is a measure of where the clamps begin to function testing. fully and limit the clamped voltage or current. Leakage Current Leakage current is the current measured at an output pin when the circuit connected to that pin is in high impedance state. Rev. E | Page 28 of 66

Data Sheet AD5560 THEORY OF OPERATION The AD5560 is a single-channel, device power supply for use level. This limits the maximum or minimum voltage that in semiconductor automatic test equipment. All the DAC levels can appear on the FORCE pin; it can be driven no higher required to operate the device are available on chip. than [V(F DAC) + threshold + V ] and no lower than IN BE [V(F DAC) − threshold − V ]. This device contains programmable modes to force a pin vol- IN BE • It triggers an alarm on KELALM if the force line goes more tage and measure the corresponding current (FVMI) covering a wide current measure range of up to ±1.2 A. A voltage sense than the threshold voltage away (OSD DAC level) from the amplifier allows measurement of the DUT voltage. Measured sense line. current or voltage is available on the MEASOUT pin. • It translates the V(force − sense) voltage to a level relative to AGND so that it can be measured through FORCE AMPLIFIER the MEASOUT pin. The force amplifier is a unity gain amplifier forcing voltage The open-sense detect level is programmable over the range directly to the device under test (DUT). This high bandwidth 0.62 V to 5 V (16-bit OSD DAC plus one diode drop). The 5 V amplifier allows suppression of load transient induced glitching OSD DAC can be accessed through the serial interface (see the on the amplifier output. Headroom and footroom requirements DAC register addressing portion of Table 24). There is a 10 kΩ for the amplifier are 2.25 V and an additional ±500 mV dropped resistor that can be connected between the FORCE and SENSE across the selected sense resistor with full-scale current flowing. pins by use of SW11. This 10 kΩ resistor is intended to The amplifier is designed to drive high currents up to ±1.2 A maintain a force/sense connection when a DUT is not in place. with the capability of ganging together outputs of multiple It is not intended to be connected when measurements are AD5560 devices for currents in excess of ±1.2 A. being made because this defeats the purpose of the OSD circuit The force amplifier can be compensated to ensure stability in identifying an open circuit between FORCE and SENSE. In when driving DUT capacitances of up to 160 μF. addition, the sense path has a 2.5 kΩ resistor in series; there- fore, if the 10 kΩ switch is closed, errors may become apparent The device is capable of supplying transient currents in excess when in high current ranges. of ±1.2 A when powering a DUT with a large decoupling capacitor. A clamp enable pin (CLEN) allows disabling of the DEVICE UNDER TEST GROUND (DUTGND) clamp circuitry to allow the amplifier to quickly charge this DUTGND is the ground level of the DUT. large capacitance. DUTGND Kelvin Sense An extra control bit (GPO) is available to switch out DUT KELALM flags when the voltage at the DUTGND pin moves decoupling when making low current measurements. too far away from the AGND line (>1 V default setting of the HW_INH Function DGS DAC). This alarm trigger is programmable via the serial A hardware inhibit pin (HW_INH/LOAD) allows disabling of interface. The threshold for the alarm function is program- the force amplifier, making the output high impedance. This mable using the DUTGND SENSE DAC (DGS DAC) (see function is also available through the serial interface (see the Table 24). SW-INH bit in the DPS Register 1, Address 0x2). The DUTGND pin has a 50 μA pull-up resistor that allows This pin can also be configured as a LOAD function to allow the alarm function to detect whether DUTGND is open. Setting multiple devices to be synchronized. Note that either CLEN the disable DUTALM bit high (Register 0x6, Bit 10) disables the or HW_INH can be chosen as a LOAD function. 50 μA pull-up resistor and also disables the alarm feature. The alarm feature can also be set to latched or unlatched (Register 0x6, DAC REFERENCE VOLTAGE (VREF) Bit 11). One analog reference input, VREF, supplies all DAC levels with Kelvin Alarm (KELALM) the necessary reference voltage to generate the required dc levels. The open-drain active low Kelvin alarm pin flags the user when OPEN-SENSE DETECT (OSD) ALARM AND CLAMP an open occurs in either the sense or DUTGND line; it can be The open-sense detect (OSD) circuitry protects the DUT from programmed to be either latched or unlatched (Register 0x6, overvoltage when the force and sense lines of the force Bit 13, Bit 11, Bit 7). The delay in the alarm flag is 50 μs. amplifier becoming disconnected from each other. GPO This block performs three functions related to the force and The GPO pin can be used as an extra control bit for external sense lines. switching functions, such as for switching out DUT decoupling • It clamps the sense line to within a programmable when making low current measurements. threshold level (plus a V ) of the force line, where the BE The GPO pin is also internally connected to an array of thermal programmable threshold is set by the OSD DAC voltage diodes scattered across the AD5560. The diagnostic register Rev. E | Page 29 of 66

AD5560 Data Sheet (Address 0x7) details the addressing and location of the diodes. The clamp register limits the CLL clamp to the range 0x0000 to These can be used for diagnostic purposes to determine the 0x7FFF; any code in excess of this is seen as 0x7FFF. Similarly, thermal gradients across the die and across a board containing the CLH clamp registers are limited to the range 0x8000 to many AD5560 devices. When selected, the anode of these 0xFFFF (see Table 24). diodes is connected to GPO and the cathode to AGND. The Clamp Alarm Function (CLALM) AD5560 evaluation board uses the ON Semiconductor® The CLALM open-drain output flags the user when a clamp ADT7461 temperature sensor for the purpose of analyzing the temperature at different points across the die. limit has been hit; it can be programmed to be either latched or unlatched. COMPARATORS Clamp Enable Function (CLEN/LOAD) The DUT measured value is monitored by two comparators Pin 15 (CLEN) allows the user to disable the clamping function (CPOL, CPOH). These comparators give the advantage of when powering a device with large DUT capacitance, thus allowing speed for go-no-go testing. increased current drive to the device and, therefore, speeding Table 6. Comparator Output Function up the charging time of the load capacitance. CLEN is active high. Test Condition CPOL CPOH This pin can also be configured as LOAD to allow multiple devices (V or I ) > CPH 0 DUT DUT to be synchronized. Note that either CLEN or HW_INH can be (V or I ) < CPH 1 DUT DUT chosen as a LOAD function. (V or I ) > CPL 1 DUT DUT (V or I ) < CPL 0 DUT DUT SHORT-CIRCUIT PROTECTION CPH > (V or I ) > CPL 1 1 DUT DUT The AD5560 force amplifier stage has built-in short-circuit To minimize the number of comparator output lines routed protection per stage as noted in the Specifications section. back to the controller, it is possible to change the comparator When the current clamps are disabled, the user must minimize function to a window comparator that outputs on one single the duration of time that the device is left in a short-circuit pin, CPO. This pin is shared with CPOH and, when configured condition (for all current ranges). through the serial interface, it provides information on whether GUARD AMPLIFIER the measured DUT current or voltage is inside or outside the A guard amplifier allows the user to force the shield of the window set by the CPL and CPH DAC levels (see Table 24). coaxial cable to be driven to the same forced voltage at the Table 7. Comparator Output Function in CPO Mode DUT, ensuring minimal voltage drops across the cable to Test Condition CPO Output minimize errors from cable insulation leakage. (VDUT or IDUT) > CPL and < CPH 1 The guard amplifier also has an alarm function that flags the (VDUT or IDUT) < CPL or > CPH 0 open-drain KELALM pin when the guard output is shorted. The delay in the alarm flag is 200 μs. CURRENT CLAMPS The guard amplifier output (GUARD/SYS_DUTGND, Pin 43) High and low current clamps are included on chip. These protect can also be configured to function as a SYS_DUTGND pin; to the DUT in the event of a short circuit. The CLH and CLL do this, the guard amplifier must be tristated via software (see levels are set by the 16-bit DAC levels. The clamp works to DPS Register 2, Table 19). limit the current supplied by the force amplifier to within the COMPENSATION CAPACITORS set levels. The clamp circuitry compares the voltage across the sense resistor (multiplied by an in-amp gain of 10 or 20) to The force amplifier is capable of driving DUT capacitances up compare to the programmed clamp limit and activates the to 160 μF. Four external compensation capacitor (CCx) inputs clamp circuit if either the high level or low level is exceeded, are provided to ensure stability into the maximum load capacit- thus ensuring that the DUT current can never exceed the ance while ensuring that settling time is optimized. In addition, programmed clamp limit + 10% of full-scale current. five CFx capacitor inputs are provided to switch across the sense resistors to further optimize stability and settling time perform- If a clamp level is exceeded, this is flagged via the latched open- ance. The AD5560 has three compensation modes: safe mode, drain CLALM pin, and the resulting alarm information can be autocompensation mode, and manual compensation mode, all read back via the SPI interface. of which are described in more detail in the Force Amplifier The clamp levels should not be set to the same level; instead, Stability section. they should be set a minimum of 2 V apart (irrespective of the The range of suggested compensation capacitors allows MI gain setting). This equates to 10% of FSCR (MI gain = 20) optimum performance for any capacitive load from 0 pF (20% of FSCR, MI gain of 10) apart. They should also be 1 V to 160 μF using one of the modes previously listed. away from the 0 A level. Rev. E | Page 30 of 66

Data Sheet AD5560 Although there are four compensation input pins and five feed- Master and Slaves in Force Voltage (FV) Mode forward capacitor inputs pins, all capacitor inputs may be used All devices are placed in force voltage (FV) mode. One device only if the user intends to drive large variations of DUT load acts as the master device and the other devices act as slaves. By capacitances. If the DUT load capacitance is known and does connecting in this manner, any device can be configured as the not change for all combinations of voltage ranges and test master. Here, the MASTER_OUT pin of the master device is conditions, then it is possible only one set of C and C Cx Fx connected to the output of the force amplifier, and it feeds the capacitors may be required. inputs of each slave force amplifier (via the SLAVE_IN pin ). Table 8. Suggested Compensation Capacitor Selection All devices are connected externally to the DUT. For current Capacitor Value to be shared equally, there must be good matching between C 100 pF each of the paths to the DUT. Settings for DPS Register 2 are C0 C 100 pF master = 0x0000, slave = 0x0400. Clamps should be disabled in C1 C 330 pF the slave devices. C2 C 3.3 nF C3 MASTER DPS SLAVE IN C 4.7 nF F0 SW5-a SW6 C 22 nF MASTER OUT F1 C 100 nF SW16 EXTFORCE1 F2 SW5-b C 470 nF FIN F3 DAC SW5-a EXTFORCE2 C 2.2 μF ×20 F4 FELEODCBAALCK O×WR EXTMEASIH1 The voltage range for the CCx and CFx pins is the same as the ISENSE EXTMEASIL RSENSE voltage range expected on FORCE; therefore, choice of capa- AMP SENSE citors should take this into account. CFx capacitors can have VSENSE ×1 AMP 10% tolerance; this extra variation directly affects settling times, especially when measuring current in the low current SLAVE DPS 1 SLAVE IN ranges. Selection of C should be at ≤5% tolerance. Cx SW5-a SW6 CURRENT RANGE SELECTION MASTER OUT SW16 EXTFORCE1 Integrated thin film resistors minimize external components SW5-b FIN and allow easy selection of current ranges from ±5 µA to DAC SW5-a EXTFORCE2 ×20 ±25 mA. Using external current sense resistors, two higher FELEODCBAALCK O×WR EXTMEASIH1 E current ranges are possible: EXTFORCE1 can drive currents ISENSE EXTMEASIL SENS up to ±1.2 A, while EXTFORCE2 is designed to drive currents AMP R SENSE up to ±500 mA. The voltage drop across the selected sense resistor ×1 VSENSE is ±500 mV when full-scale current is flowing through it. AMP The measure current amplifier has two gain settings, 10 and SLAVE DPS 2 SLAVE IN 20. The two gain settings allow users to achieve the quoted/ SW5-a SW6 specified current ranges with large or small voltage swings. MASTER OUT The gain of 20 setting is intended for use with a 5 V reference, SW16 EXTFORCE1 SW5-b and the gain of 10 setting is for use with a 2.5 V reference. Both FIN DAC SW5-a EXTFORCE2 combinations ensure the specified current ranges. Other ×20 VREF/gain setting combinations should only be used to FELEODCBAALCK O×WR EXTMEASIH1 SE N achieve smaller current ranges. Attempting to achieve greater ISENSE EXTMEASIL RSE AMP current ranges than the specified ranges is outside the intended SENSE ×1 operation of the AD5560. The maximum guaranteed voltage VSENSE AMP across R is ±0.64 V (gain of 20) or ±0.7 V (gain of 10). SENSE HIGH CURRENT RANGES For currents in excess of 1200 mA, a gang mode is available DUTGND DUT 07779-007 whereby multiple devices are ganged together to achieve higher Figure 54. Simplified Block Diagram of High Current Ganging Mode currents. In gang mode, the loop is controlled by the master AD5560. This loop drives a maximum capacitance of 160 µF for this mode. There are two methods of ganging channels together; these are described in the Master and Slaves in Force Voltage (FV) Mode section and the Master in FV Mode, Slaves in Force Current (FI) Mode section. Rev. E | Page 31 of 66

AD5560 Data Sheet Master in FV Mode, Slaves in Force Current (FI) Mode The EXTFORCE1, EXTFORCE2, or ±25 mA ranges can be used for the gang mode. Therefore, it is possible to gang devices The master device is placed into FV mode, and all slave devices to get a high voltage/high current combination, or a low into force current (FI) mode. The measured current of the voltage/high current combination. master device (MASTER_OUT) is applied to the input of all slave devices (SLAVE_IN), and the slaves act as followers. All For example, ganging five 25 V/25 mA devices using the 25 mA channels work to share the current equally among all devices range achieves a 25 V/625 mA range, whereas five 15 V/200 mA in the gang. Because the slaves force current, matching the devices using the EXTFORCE2 path can achieve a 15 V/1 A DUT paths is not so critical. Settings for DPS Register 2 are range. Similarly, ganging four 3.5 V/1.2 A devices using the master = 0x0200, slave = 0x0600. Clamps should be disabled in EXTFORCE1 path results in a 3.5 V/4.8 A DPS. the slave devices. IDEAL SEQUENCE FOR GANG MODE MASTER DPS SLAVE IN Use the following steps to bring devices into and out of gang mode: SW5-a SW6 MASTER OUT 1. Choose the master device and force 0 V output, corres- SW16 EXTFORCE1 ponding to zero current. SW5-b DFAINC SW5-a EXTFORCE2 2. Select slave DPS 1 and place it in slave mode (keep slaves in high-Z mode via SW-INH or HW_INH until ready to gang). SENSE 3. Select to gang in either current or voltage mode. EXTMEASIH1 MBEUAFSFOERUT ×20 EXTMEASIL RSENSE 4. Repeat Step 2 and Step 3 one at a time through the chain of AND GAIN ISENSE slaves. AMP 5. Load the required voltage to the master device. The other devices copy either voltage or current as programmed. SLAVE DPS 1 SLAVE IN To remove devices from the gang, the master device should SW5-a SW6 MASTER OUT be programmed to force 0 V out again. The procedure for SW16 EXTFORCE1 removing devices should be the reverse of Step 1 through Step 5. SW5-b FIN DAC SW5-a EXTFORCE2 Note that this may not always be possible in practice; therefore, SENSE it is also possible to gang and ungang while driving a load. Just ensure that the slave devices are in high-Z mode while confi- EXTMEASIH1 MABNEUDAF SFGOEARUINT ISENSE×20 EXTMEASIL RSENSE guring them into the required range and gang setting. AMP Gang mode extends only to the ±25 mA range and the two high current ranges, EXTFORCE1 and EXTFORCE2. Therefore, where an accurate measurement is required at a low current, the user SLAVE DPS 2 SLAVE IN should remove slaves from the gang to move to the appropriate SW5-a SW6 MASTER OUT lower current range to make the measurement. Similarly, slaves SW16 EXTFORCE1 can be brought back into the gang if needed. SW5-b FIN DAC SW5-a EXTFORCE2 COMPENSATION FOR GANG MODE SENSE When ganging, the slave devices should be set to the fastest MEASOUT EXTMEASIH1 SE response. ABNUDF FGEARIN ISENSE×20 EXTMEASIL RSEN When slaves are in FI mode, the AD5560 force amplifier over- AMP rides other compensation settings to enforce C = 0, R = 0, Fx Z and g ≤ 1. This is done internally to the force amplifier; mx therefore, readback does not show that the signals inside the DUTGND DUT 07779-008 force amplifier actually change. SYSTEM FORCE/SENSE SWITCHES Figure 55. Simplified Block Diagram of Gang Mode, Using an FV/FI Combination System force/sense switches allow easy connection of a central or system parametric measurement unit (PMU) for calibration or additional measurement purposes. The system device under test ground (SYS_DUTGND) switch is shared with the GUARD/SYS_DUTGND pin (Pin 43). See the DPS Register 2 in Table 19 for addressing details. Rev. E | Page 32 of 66

Data Sheet AD5560 DIE TEMPERATURE SENSOR AND THERMAL These diodes can be muxed out onto the GPO pin. The SHUTDOWN diagnostic register (Address 0x7) details the addressing and location of the diodes. These can be used for diagnostic There are three types of temperature sensors in the AD5560. purposes to determine the thermal gradients across the die • The first is a temperature sensor available on the MEASOUT and across a board containing many AD5560 devices. When pin and expressed in voltage terms. Nominally at 25°C, this selected, the anode of each diode is connected to GPO and sensor reads 1.54 V. It has a temperature coefficient of the cathode to AGND. The AD5560 evaluation board uses 4.7 mV/°C. This sensor is active during power-down mode. the ON Semiconductor ADT7461 temperature sensor for the purpose of analyzing the temperature at different Die Temp = (VMEASOUT − 1.54)/0.0047 + 25°C (TSENSE) points across the die. Based on typical temperature sensor output voltage at 25°C and output scaling factor. Note that, when a thermal shutdown occurs, as the force amplifier is inhibited or tristated, user intervention is required • The second type of temperature sensor is related to the to reactivate the device. It is necessary to clear the temperature thermal shutdown feature in the device. Here, there are alarm flag by issuing a read command of Register Address 0x44 sensors located in the middle of the enabled power stage, (alarm status and clear alarm status register, Table 25), and which are used to trip the thermal shutdown. The thermal then issuing a new write to the DPS Register 1 (SW-INH = 1) shutdown feature senses only the power stages, and the power to reenable the force amplifier. stage that it senses is determined by the active stage. See also the Thermal Considerations section. If ranges of <25 mA are selected, the EXTFORCE1 sensor is MEASURE OUTPUT (MEASOUT) monitored. The EXTFORCE1 power stage itself is made up of three identical stages, but the thermal shutdown is The measured DUT voltage, current (voltage representation activated by only one stage (EXTFORCE1B). Similarly, the of DUT current), K , or die temperature is available on SENSE EXTFORCE2 stage is made up of two identical output MEASOUT with respect to AGND. The default MEASOUT stages, but the thermal shutdown can be activated by only range is the forced voltage range for voltage measure and one stage (EXTFORCE2A). current measure (nominally ±12.81 V, depending on reference The thermal shutdown circuit monitors these sensors and, voltage and offset DAC) and includes overrange to allow for in the event of the die temperature exceeding the program- system error correction. mable threshold temperature (100°C, 110°C, 120°C, 130°C The serial interface allows the user to select another MEASOUT (default)), the device protects itself by inhibiting the force range of (1.025 × VREF) to AGND; this range is suitable for use amplifier stage, clearing SW-INH in DPS Register 1 and with an ADC with a smaller input range. flagging the overtemperature event via the open-drain To allow for system error correction, there is additional gain TMPALM pin, which can be programmed to be either for the force function. If this overrange is used as intended, latched or unlatched. These temperature sensors can be the output range on MEASOUT scales accordingly. read via the MEASOUT pin by selecting them in the The MEASOUT line can be tristated via the serial interface. diagnostic register (Table 23, VPTAT low and VPTAT high). They are expressed in voltage and to scale to When using low supply voltages, ensure that there is sufficient temperature. They must be referred to the VTSD reference headroom and footroom for the required force voltage range. voltage levels (see Table 23) also available on MEASOUT. V VOLTAGE MID This set of sensors is not active in power-down mode. The midcode voltage (V ) is used in the measure current MID Die Temp_y = {(VPTAT_x − VTSD_low)/[(VTSD_high − amplifier block to center the current ranges at about 0 A. VTSD_low)/(Temp_high – Temp_low)]} + Temp_low This is required to ensure that the quoted current ranges can where: be achieved when using offset DAC settings other than the x, y are (high, NPN) and (low, PNP). default. V corresponds to 0x8000 or the DAC midcode MID Temp_low = −273°C. value, that is, the middle of the voltage range set by the offset Temp_high = +130°C. DAC setting (see Table 15 and Figure 56). • The third set of temperature sensors is an array of thermal V = 5.125 × VREF × (32,768/216) − (5.125 × VREF × MID diodes scattered across the die. These diodes allow the user (OFFSET_DAC_CODE/216)) to evaluate the temperature of different parts of the die and or are of great use to determine the temperature gradients V = 5.125 × VREF × ((32,768 − Offset DAC)/216) across the die and the temperature of the accurate portions MID of the die when the device is dissipating high power. For further details on the thermal array and locations, see the diagnostic register section in Table 23. Rev. E | Page 33 of 66

AD5560 Data Sheet V is another important voltage level that is used in other approximately 2 V footroom to AV ). See the Choosing MIN SS parts of the circuit. When using a MEASOUT gain of 0.2, the AVDD/AVSS Power Supply Rails section for more V level is used to scale the voltage range; therefore, when information. MIN choosing supply rails, it is very important to ensure that there V = −5.125 × VREF × (OFFSET_DAC_CODE/216) MIN is sufficient footroom so that the V level is not impinged MIN on (the high voltage DAC amplifiers used here require Table 9. MEASOUT Output Ranges Output Voltage Range1 MEASOUT Function Offset DAC = GAIN1 = 0, MEASOUT Gain = 1 Transfer Function 0x0 Offset DAC = 0x8000 Offset DAC = 0xE000 Measure Voltage (MV) ±V 0 V to 25.62 V ±12.81 V −22.42 V to +3.2 V DUT Measure GAIN0 = 0 MI gain = 20 (I × R × 20) + V 0 V to 25.62 V ±12.81 V −22.42 V to +3.2 V DUT SENSE MID Current GAIN0 = 1 MI gain = 10 (I × R × 10) + V 0 V to 12.81 V ±6.4 V −11.2 V to +1.6 V DUT SENSE MID (MI) (V = 2.5 V) (V = 2.5 V) (V = 2.5 V) REF REF REF 1 VREF = 5 V, unless otherwise noted. Table 10. MEASOUT Function GAIN1 = 1, MEASOUT Gain = 0.2 Transfer Function Output Voltage Range1, 2 Measure Voltage (MV) MV = 0.2 × (V − V ) 0 V to 5.12 V (±2.56 V centered around 2.56 V) DUT MIN (includes overrange) Measure GAIN0 = 0 MI gain = 20 (I × R × 20 × 0.2) + 0.5125 × VREF 0 V to 5.12 V (±2.56 V centered around 2.56 V) DUT SENSE Current (includes overrange) (MI) GAIN0 = 1 MI gain = 10 (I × R × 10 × 0.2) + 0.5125 × VREF 1.28 V to 3.84 V (±1.28 V, centered around 2.56 V) DUT SENSE 0 V to 2.56 V (±1.28 V, centered around 1.28 V) (V = 2.5 V) REF 1 VREF = 5 V, unless otherwise noted. 2 The offset DAC setting has no effect on the output voltage range. Table 11. Possible ADCs and ADC Drivers for Use with AD55601 Part Sample No. Resolution Rate Channels AIN Range2 Interface ADC Driver Multiplexer3 Package AD7685 16 250 kSPS 1 0 V to VREF Serial, SPI ADA4841-1, ADG704, ADG708 MSOP, ADA4841-2, LFCSP AD7686 16 500 kSPS 1 0 V to VREF Serial, SPI ADA4841-1, ADG704, ADG708 MSOP, ADA4841-2, LFCSP AD7693 16 500 kSPS 1 −VREF to +VREF Serial, SPI ADA4841-1, ADG1404, MSOP, ADA4841-2, ADG1408, LFCSP ADA4941-1 ADG1204 AD7610 16 250 kSPS 1 Bipolar 10 V, bipolar Serial, parallel AD8021 ADG1404, LFCSP, 5 V, unipolar 10 V, ADG1408, LQFP unipolar 5 V ADG1204 AD7655 16 1 MSPS 4 0 V to 5 V Serial, SPI ADA4841-1, LQFP, ADA4841-2, LFCSP AD8021 1 Subset of the possible ADCs, ADC drivers, and multiplexers suitable for use with the AD5560. Visit http://www.analog.com for more options. 2 Do not allow the MEASOUT output range to exceed the AIN range of the ADC. 3 For the purposes of sharing ADCs among multiple DPS channels, note that the multiplexer is not absolutely necessary because the AD5560 MEASOUT path has a tristate mode. Rev. E | Page 34 of 66

Data Sheet AD5560 VREF VMID = (VTOP – VBOT)/2 VTOP VMID 2R 8.25R R LOW VOLTAGE HV DAC AMP OFFSET DAC DAC VOS = (1 + 2/8.25) × (OFFSET DAC VOLTAGE) att 8.25R 2R 2R 8.25R R VBOT VMIN 5R REFGND att MEASOUT OSD DAC IN tri R 10R MI_x10 INTERNAL MEASI LOW MEASURE CURRENT 5R INTERNAL ISENSE AMP MI_x20 1kΩ mi MEASI HIGH mi_gain R 10R 2R att 2R 5R MVEOALSTUARGEE 1kΩ mv att att 5R 5R 5R DUTGND VSENSE AMP SENSE 5R 5R - NOTES 1. att: ATTENUATION FOR EXTERNAL MEASOUT × 0.20 FOR OUTPUT VOLTAGE RANGE 0V TO 5.125V (WITH OVERRANGE) (VREF = 5V). tri: TRISTATE MODE mmmvii:_: g MMaEEinAA:S SMUUERRAEES CVUUORRELRT IE AGNGATEIN SELECTION 07779-009 Figure 56. MI, MV, and MEASOUT Block Showing Gain Settings and Offset DAC Influence Rev. E | Page 35 of 66

AD5560 Data Sheet FORCE AMPLIFIER STABILITY Table 12. External Variables There are three modes for configuring the force amplifier: safe Name Description Min Max mode, autocompensation mode, and manual compensation mode. C DUT capacitance with contributing 10 nF 160 µF R ESR Manual compensation mode has highest priority, followed by safe R ESR in series with C 1 mΩ 10 Ω mode, then autocompensation mode. C R C DUT capacitance with negligible ESR 100 pF 10 nF Safe Mode D R Loading resistance at the DUT ~2 Ω Infinity D Selected through Compensation Register 1 (see Table 20), this I Current range ±5 μA ±1.2 A R mode guarantees stability of the force amplifier under all Table 13. Internal Variables conditions. Where the load is unknown, this mode is useful but Name Description Min Max results in a slow response. This is the power-on default of the R Resistor in series with C , which 500 Ω 1.6 MΩ AD5560. Z C0 contributes a zero. Autocompensation Mode R Resistor to 8 pF to contribute an 200 Ω 1 MΩ P additional pole Using this mode, the user inputs the C and ESR values, and R C :C Capacitors to ensure 100 pF 100 nF the AD5560 decides the most appropriate compensation C0 C3 unconditional stability scheme for these load conditions. The compensation chosen C :C Capacitors to optimize ac 4.7 nF 10 μF F0 F4 is for an optimum tradeoff between ac response and stability. performance into different C, C R D Manual Compensation Mode gmx Transconductance of force 40 μA/V 900 μA/V amplifier input stage This mode allows access to all of the internal programmable parameters to configure poles/zeros, which affect the dynamic performance of the loop. These variables are outlined in Table 12 and Table 13. Figure 57 shows more details of the force amplifier block. AD5560 CF0 4.7nF FORCE VOLTAGE LOOP CF1 22nF CF2 100nF CF3 470nF CF4 2.2µF EXTFORCE2 RSENSE 2 EXTFORCE1 RSENSE 1 RP: 200Ω TO 1MΩ 20Ω 200Ω 8pF 2kΩ FORCE 20kΩ 100kΩ 5010.R6ΩMZ :TΩO 6kΩ 25kΩ 100kΩ FORCE +gm– AVGSNEDNSE ×1+ +– SENSE CD CRRC RD DAC – + – DUTGND CC0 CC1 CC2 CC3 100pF 100pF 330pF 3.3nF 07779-010 Figure 57. Block Diagram of a Force Amplifier Loop Rev. E | Page 36 of 66

Data Sheet AD5560 POLES AND ZEROS IN A TYPICAL SYSTEM Placing a capacitor in parallel with this sense resistor provides an ac feedforward path to the DUT. Therefore, at high frequen- Typical closed loop systems have one dominant pole in the cies, the DUT is driven through the C capacitor rather than feedback path, providing −20 dB/decade gain roll off and 90° Fx through the sense resistor. of phase shift so that the gain decreases to 0 dB where there is a conservative 90° of phase margin. Note that each C output has an output impedance of about Fx 3 Ω. This is very small compared to the sense resistors of the The AD5560 has compensation options to help cope with the low current ranges but not so for the highest current ranges. various load conditions that a DPS is presented with. Therefore, the C capacitors are most effective in the low current MINIMIZING THE NUMBER OF EXTERNAL Fx ranges but are of lesser benefit in higher current ranges. COMPENSATION COMPONENTS As shown in the force amplifier diagram (see Figure 57), there Note that, depending on the range of load conditions, not all is a pole at 1/( R × [C + C ]) and a zero at 1/[ R × C ]. SENSE Fx R SENSE Fx external capacitors are required. Therefore, the output impedance of each C output, at around Fx C Pins 1 Ω, limits the improvement available by using the C capacitors. Fx Fx For a large load capacitance, there is still a pole at −1/[1 Ω × CR] There are five external C pins. All five pins are used Fx above which the phase improvement is lost. If there is also a in the autocompensation mode to choose a suitable capacitor, cable resistance to the DUT, or if C has significant ESR, this depending on the load being driven. To reduce component Fx should be added to the 1 Ω to calculate the pole frequency. count, it is possible to connect just one capacitor, for instance, C to the C , C , and C pins. Therefore, when any of the If C is chosen to be bigger than the load capacitance, it can F2 F2 F1 F0 Fx smallest three external capacitors are selected, the same physical dominate the settling time and slow down the settling of the capacitor is used because it is connected to all three pins. A whole circuit. Also, it directly affects the time taken to measure disadvantage here is that the larger C capacitor should be a current (R × C ). F2 SENSE Fx bigger than optimal and may increase settling time of the The Effect of R Z whole circuit (particularly the measure current). When the load capacitance is known, R can be used to optim- Z C Pins Cx ize the response of the AD5560. Because the C buffers have Fx To make the AD5560 stable with any unknown capacitor some output impedance of about 1 Ω, there is likely to be some from 0 pF to 160 μF, all four C capacitors are required. additional resistance to the DUT. There can still be an output Cx However, if the range of load is from 0 pF to 20 µF, then pole associated with this resistance and the load capacitance, C can be omitted. Similarly, if the load range is from 0 pF to C , 1/[R × C ] (where R = the series/parallel combination of C3 R 0 R 0 2.2 µF, then C and C can be omitted. Only C is required the sense resistor, the C output impedance, the C capacitor C2 C3 C0 Fx Fx in autocompensation mode. ESR, and the cable to DUT). This is particularly significant for larger load capacitances in any current range. By programming Note that safe mode, which makes the device stable in any a zero into the loop response by setting R (in series with C ), load from 0 pF to 160 μF, simply switches in all of the four Z C0 it is possible to cancel this pole. Above the frequency 1/[C × C capacitors. Stability into 160 μF is assured only if all four C0 Cx R ], the series resistance and capacitance begin to look resistive capacitors are present; otherwise, the maximum capacitor for Z rather than capacitive, and the 90° phase shift and 20 dB/decade stability is reduced to 20 μF, 2.2 μF, or 220 nF, depending on contributed by C no longer apply. Note that, to cancel the how many capacitors are missing. C0 load pole with the R zero, the load pole must be known to EXTRA POLES AND ZEROS IN THE AD5560 Z exist. Adding a zero to cancel a pole that does not exist causes The Effect of C an oscillation (perhaps the expected load capacitor is not Cx present). Also, it is recommended to avoid creating a zero C is switched on at all times. C , C , and C can be con- C0 C3 C2 C1 frequency lower than the pole frequency; instead, allow the zero nected in addition to C to slow down the force amplifier loop. C0 frequency to be 2× or 3× higher than the calculated pole In the ±500 mA range looking into a small load capacitor, with frequency. only C connected, the ac gain vs. phase response results in C0 ~90° of phase margin and a unity gain bandwidth (UGB) of The Effect of R P ~400 kHz. R can be used to ensure circuit stability when a poor load P The Effect of C capacitor with significant ESR is present. Above the frequency, Fx 1/[C × R ], the DUT begins to look resistive. The ESR of the The output of the AD5560 passes through a sense resistor to R C DUT capacitor, R , contributes a zero at this frequency. The the DUT. Coupled with the load capacitor, this sense resistor C load capacitor, C , is counted on to stabilize the system when can act as a low-pass filter that adds phase shift and decreases R the user has cancelled the load pole with the R zero. Just as the phase margin (particularly in the low current ranges where the Z absence of C under these circumstances can cause oscillations, sense resistors are large). R the presence of ESR R while nonzero R is used can cause C Z Rev. E | Page 37 of 66

AD5560 Data Sheet stability problems. This is most likely to be the case when there settings when using the manual compensation register (this are both a large C and large R . algorithm is what the autocompensation method is based upon): R C The R resistor is intended to solve this problem. Again, it is 1. Use C (the load capacitance with a series ESR) and R (the P R C prudent not to cancel exact pole/zero cancellation with R and ESR of that load capacitance) as inputs. Z instead allow the zero to be 2× to 3× the frequency of the pole. 2. Assume that C has not been overestimated and that R has R C It is best to be very conservative when using R to cancel the not been underestimated. (Although, when the ESR R is Z C load pole. Choose a high zero frequency to avoid flat spots in shown to have a frequency dependence, the lowest R that C the gain curve that extend bandwidth, and be conservative when occurs near the resonant frequency is probably a better choosing R to create a pole. Aim to place the R zero at 5× the guide. However, do not underestimate this ESR). P Z exact cancellation frequency and the R pole at around 2× the a. C is the suggested 100 pF. P C0 exact cancellation frequency. The best solution here is to avoid b. C capacitor values are as suggested, and they extend Fx this complexity by using a high quality capacitor with low ESR. up to 2.2 µF (C ). For faster settling into small F4 COMPENSATION STRATEGIES capacitive loads, include smaller CFx values such as CF3 and C . If a capacitor is not included, then short the Ensuring Stability into an Unknown Capacitor Up to a F2 corresponding C pin to one that is. Maximum Value Fx c. There is approximately 1 Ω of parasitic resistance, R , C If the AD5560 has to be stable in a range of load capacitance from the AD5560 to the DUT (for example, the cable); from no load capacitance to an upper limit, then select manual R = 1 Ω. C compensation mode and, in Compensation Register 2, set the 3. Select g = 2, C = 000. This makes the input stage of m[1:0] C[3:1] parameters according to the maximum load capacitance listed the force amplifier; have g = 300 µA/V; deselect the mx in Table 14. compensation capacitors, C , C , C so that only C is C1 C2 C3, C0 active. Table 14. Suggested Compensation Settings for Load Capa- 4. Choose a C value from 0 to 4 to select the largest C citance Range of Unknown Value to Some Maximum Value F[2:0] Fx capacitor that is smaller than C . Capacitor R 5. If C < 100 nF, then set R = 0, R = 0. This ends the Min Max g R R C C R Z[2:0] P[2:0] m[1:0] P[2:0] Z[2:0] C[3:1] F[2:0] algorithm. 0 0.22 μF 2 0 0 000 2 6. Calculate R, the resistive impedance to the DUT, using the 0 2.2 μF 2 0 0 001 3 0 following steps: 0 10 μF 2 0 0 010 4 a. Calculate R, the sense resistor, from the selected 0 20 μF 2 0 0 011 4 S current range using R = 0.5 V/I . 0 160 μF 2 0 0 111 4 S RANGE b. Calculate R, the output impedance, through the C F Fx Table 14 assumes that the C and C capacitor values are those capacitor, by using Cx Fx suggested in Table 8. R = 1.2 Ω + (ESR of C capacitor) F Fx Making a circuit stable over a range of load capacitances for c. Calculate R , a modified version of R, which takes FM F no load capacitance or greater means that the circuit is over- account of frequency dependent peaking, through the compensated for small load capacitances, undercompensated C buffers into a large capacitive load, by using Fx for high load capacitances, or both. The previous choice settings, along with the suggested capacitor values, is a compromise RFM = RF/(1 + [2 × (CFx/2.2 μF)]) between both. By compromising phase margin into the largest That is, R is up to 3× smaller than R, when the FM F load capacitors, the system bandwidth can be increased, which selected C capacitor is large compared to 2.2 μF. Fx means better performance under load current transient condi- Then calculate tions. The disadvantage is that there is more overshoot during a R = R + (R ||R ) large DAC step. To reduce this at the expense of settling time, it 0 C S FM may be desirable to temporarily switch a capacitor range 5× or where R takes its value from the assumptions in Step 2. C 10× larger before making a large DAC step. 7. If R > (R/5), then the ESR is large enough to make the C 0 DUT look resistive. Choose R = 0, R = 0. This ends OPTIMIZING PERFORMANCE FOR A KNOWN Z[2:0] P[2:0] the algorithm CAPACITOR USING AUTOCOMPENSATION MODE 8. Calculate the unity gain frequency (Fug), the ideal unity The autocompensation mode decides what values of gmx, CCx gain frequency of the force amplifier, from Fug = CFx, RZ, and RP should be chosen for good performance in a gmx/2πCC0. Using the previously suggested values (gm[1:0] = 2 particular capacitor. Both the capacitance and its ESR need to gives g = 300 µA/V and C = 100 pF), Fug calculates to mx C0 be known. To avoid creating an oscillator, the capacitance should 480 kHz. not be overestimated and the ESR should not be underesti- 9. Calculate F , the load pole frequency, using F = P P mated. Use the following steps to determine compensation 1/(2πRC ). 0 C0 Rev. E | Page 38 of 66

Data Sheet AD5560 10. Calculate F , the ESR zero frequency, using F = A more complex alternative is to calculate the overall impedance Z Z 1/(2πRcCr). at the expected unity gain bandwidth and use this to calculate 11. If F > Fug, the load pole is above the bandwidth of the an equivalent series C and R that have the same complex P R C AD5560. Ignore it with R = 0, R = 0. This ends the impedance at that particular frequency. Z[2:0] P[2:0] algorithm DAC LEVELS 12. If R < (R/25), then the ESR is negligible. Attempt to C 0 This device contains all the dedicated DAC levels necessary cancel the load pole with R zero. Choose an ideal zero Z for operation: a 16-bit DAC for the force amplifier, two 16-bit frequency of 2 × F for some safety margin and then P DACs for the clamp high and low levels, two 16-bit DACs for choose the R value that gives the closest frequency on a Z[2:0] the comparator high and low levels, a 16-bit DAC to set a logarithmic scale. This ends the algorithm programmable open sense voltage, and a 16-bit offset DAC 13. Otherwise, this is a troublesome window in which a load to bias or offset a number of DACs on chip (FORCE, CLL, pole and a load zero cannot be ignored. Use the following CLH, CPL, CPH). steps: • To cancel the load pole at F , choose an ideal zero FORCE AND COMPARATOR DACS P frequency of 6 × F (this is more conservative than the P The architecture of the main force amplifier DAC consists of 2 × F suggested earlier, but there is more that can go P a 16-bit R-2R DAC, whereas the comparator DACs are resistor- wrong with miscalculation). Then choose the R Z[2:0] string DACs followed by an output buffer amplifier. This value that gives the closest zero to this ideal frequency resistor-string architecture guarantees DAC monotonicity. of 6 × F on a logarithmic scale. P The 16-bit binary digital code loaded to the DAC register • To cancel the ESR zero at F , choose an ideal pole Z determines at what node on the string the voltage is tapped frequency of 2 × F . Z off before being fed to the output amplifier. • Then choose the R value that gives the closest pole P[2:0] The comparator DAC is similarly arranged. The force and to this ideal frequency of 2 × F on a logarithmic scale. Z comparator DACs have a 25.62 V span, including overrange This ends the algorithm to enable offset and gain errors to be calibrated out. ADJUSTING THE AUTOCOMPENSATION MODE The transfer function for these 16-bit DACs is The autocompensation algorithm assumes that there is 1 Ω of DACCODE resistance (RC) from the AD5560 to the DUT. If a particular VOUT =5.125×VREF× 216 −5.125×VREF× application has resistance that differs greatly from this, then OFFSET_DAC_CODE it is likely that the autocompensation algorithm is nonoptimal.  +DUTGND  216  If using the autocompensation algorithm as a starting point, where DAC CODE is X2 (see the Offset and Gain Registers consider that overstating the C capacitance and understating R section). the ESR R is likely to give a faster response but could cause C CLAMP DACS oscillations. Understating C and overstating R is more likely R C to slow things down and reduce phase margin but not create The architecture of the clamp DAC consists of a 16-bit resistor- an oscillator. string DAC followed by an output buffer amplifier. This resistor- string architecture guarantees DAC monotonicity. The 16-bit It is often advisable to err on the side of simplicity. Rather than binary digital code loaded to the DAC register determines at insert a pole and zero at similar frequencies, it may be better to what node on the string the voltage is tapped off before being add none at all. Set R = R = 0 to push them beyond the P[2:0] Z[2:0] fed to the output amplifier. AD5560 bandwidth. DEALING WITH PARALLEL LOAD CAPACITORS The clamp DACs have a 25.62 V span, including overrange, to enable offset and gain errors to be calibrated out. In the event that the load capacitance consists of two parallel capacitors with different ESRs, it is highly likely that the overall complex impedance at the unity gain bandwidth is dominated by the larger capacitor and its ESR. Assuming that the smaller capacitor does not exist normally is a safer simplifying assump- tion. Rev. E | Page 39 of 66

AD5560 Data Sheet The transfer function for these 16-bit DACs is Table 15. Offset DAC Relationship with Other DACs, V = 5 V REF Offset DAC Code DAC Code1 DAC Output Voltage Range DACCODE VCLH,VCLL=5.125×VREF× 216 −5.125×VREF× 0 0 0.00 0 32,768 12.81 OFFSET_DAC_CODE  +DUTGND  216  0 65,535 25.62 … … … The transfer function for the clamp current value is 32,768 0 −12.81 ICLL,ICLH=5.125×VREF×DACCO2D1E6 −32768 3322,,776688 3625,,756385 01.20.081 R ×MI_AMP_GAIN SENSE … … … where: 57,344 0 −22.42 R is the sense resistor. 57,344 32,768 −9.61 SENSE MI_AMP_GAIN is the gain of the MI amp (either 10 or 20). 57,344 65,535 3.20 OSD DAC … … … 65,355 … Footroom limitations The OSD DAC is a 16-bit DAC function, again a resistor string 1 DAC code shown for 16-bit force DAC. DAC guaranteeing monotonicity. The 16-bit binary digital code loaded to the DAC register determines at what node on OFFSET AND GAIN REGISTERS the string the voltage is tapped off before being fed to the output amplifier. The OSD function is used to program the Each DAC level contains independent offset and gain control voltage difference needed between the force and sense lines registers that allow the user to digitally trim offset and gain. before the alarm circuit flags an error. The OSD DAC has a These registers give the user the ability to calibrate out errors range of 0.62 V to 5 V. The transfer function is as follows: in the complete signal chain (including the DAC) using the internal m and c registers, which hold the correction factors. DACCODE (1) V =VREF×  OUT  216  The digital input transfer function for the DACs can be represented as The offset DAC does not affect the OSD DAC output range. x2 = [x1 × (m + 1)/2n] + (c – 2n – 1) DUTGND DAC where: Similarly, the DUTGND DAC (DGS) is a 16-bit DAC and uses x2 is the data-word loaded to the resistor string DAC. a resistor string DAC to guarantee monotonicity. The 16-bit x1 is the 16-bit data-word written to the DAC input register. binary digital code loaded to the DAC register determines at m is the code in the gain register (default code = 216 – 1). what node on the string the voltage is tapped off before being n is the DAC resolution (n = 16). fed to the output amplifier. This function is used to program c is the code in the offset register (default code = 215). the voltage difference needed between the DUTGND and Offset and Gain Registers for the Force Amplifier DAC AGND lines before the alarm circuit flags an error. The force amplifier input (F ) DAC level contains independent The DUTGND DAC has a range of 0 V to 5 V. The transfer IN offset and gain control registers that allow the user to digitally function for this 16-bit DAC is shown in Equation 1. trim offset and gain. There is one set of registers for the force The offset DAC does not affect the OSD DAC output range. voltage range: x1, m, and c. OFFSET DAC Offset and Gain Registers for the Comparator DACs In addition to the offset and gain trim, there is also a 16-bit The comparator DAC levels contain independent offset and offset DAC that offsets the output of each DAC on chip. There- gain control registers that allow the user to digitally trim offset fore, depending on headroom available, the input to the force and gain. There are seven sets of registers consisting of a combi- amplifier can be arranged either symmetrically or asymmetrically nation of x1, m, and c, one set each for the five internal force about DUTGND but always within a voltage span of 25 V. Some current ranges and one set each for the two external high extra gain is included to allow for system error correction using current ranges. the m (gain) and c (offset) registers. Offset and Gain Registers for the Clamp DACs The usable voltage range is −22 V to +25 V. Full scale loaded The clamp DAC levels contain independent offset and gain to the offset DAC does not give a useful output voltage range control registers that allow the user to digitally trim offset because the output amplifiers are limited by available footroom. and gain. One set of registers covers the V range, the five Table 15 shows the effect of the offset DAC on other DACs in SENSE internal force current ranges, and the two external high current the device (clamp, comparator, and force DACs). ranges. Both clamp DAC x1 registers and their associated offset and gain registers are 16 bit. Rev. E | Page 40 of 66

Data Sheet AD5560 REFERENCE SELECTION Calibration Example The voltage applied to the VREF pin determines the output Nominal offset coefficient = 32,768 (0x8000) voltage range and span applied to the force amplifier, clamp, Nominal gain coefficient = 65,535 (0xFFFF) and comparator inputs and the current ranges. For example, the gain error = 0.5%, and the offset error = 100 mV. This device can be used with a reference input ranging from Gain error (0.5%) calibration is as follows: 2 V to 5 V. However, for most applications, a reference input of 5 V is able to meet all voltage range requirements. The DAC 65,535 × 0.995 = 65,207 amplifier gain is 5.125, which gives a DAC output span of Therefore, load Code 1111 1110 1011 0111 (0xFEB7) to the 25.625 V. The DACs have gain and offset registers that can m register. be used to calibrate out system errors. In addition, the gain Offset error (100 mV) calibration is as follows: register can be used to reduce the DAC output range to the desired force voltage range. LSB size = 10.25/65,535 = 156 µV Using a 5 V reference and setting the m (gain) register to one- Offset coefficient for 100 mV offset = 100/0.156 = 641 LSBs fourth scale or 0x4000 gives an output voltage span of 6.25 V. Therefore, load Code 0111 1101 0111 1111 (0x7D7F) to the Because the force DAC has 18 bits of resolution even with only c register. one-fourth of the output voltage span, it is still possible to ADDITIONAL CALIBRATION achieve 16-bit resolution in this 6.25 V range. The techniques described in the Calibration section are usually The measure current amplifier has two gain settings, 10 and 20. sufficient to reduce the zero-scale and gain errors. However, The two gain settings allow users to achieve the quoted/speci- there are limitations whereby the errors may not be sufficiently fied current ranges with large or small voltage swings. The 20 reduced. For example, the offset (c) register can only be used to gain setting is intended for use with a 5 V reference, and the 10 reduce the offset caused by negative zero-scale error. A positive gain setting is for use with a 2.5 V reference. Both combinations offset cannot be reduced. Likewise, if the maximum voltage is ensure the specified current ranges. Other VREF/gain setting below the ideal value, that is, a negative gain error, the gain (m) combinations should be used only to achieve smaller current register cannot be used to increase the gain to compensate for ranges. See Table 27 for suggested references for use with the the error. These limitations can be overcome by increasing the AD5560. reference value. CALIBRATION SYSTEM LEVEL CALIBRATION Calibration involves determining the gain and offset of each There are many ways to calibrate the device on power-on. channel in each mode and overwriting the default values in the Following is an example of how to calibrate the FIN DAC m and c registers of the individual DACs. registers (Register 0x8 to Register 0xA) of the device without a Reducing Zero-Scale Error DUT or DUT board connected. The calibration procedure for Zero-scale error can be reduced as follows: the force and measure circuitry is as follows: 1. Set the output to the lowest possible value. 1. Calibrate the force voltage (two-point calibration). a. Write zero scale to the FIN DAC registers 2. Measure the actual output voltage and compare it to the (Register 0x8 to Register 0xA). required value. This is the zero-scale error. b. Connect SYS_FORCE to FORCE (via SW8) and 3. Calculate the number of LSBs equivalent to the zero-scale SYS_SENSE to SENSE (via SW9), and close the internal error, and add or subtract this number to the default value force/sense switch (SW11). of the c register. c. Using the system PMU, measure the error between the Reducing Gain Error voltage at FORCE/SENSE and the desired value. d. Similarly, load full scale to the FIN DAC registers Gain error can be reduced as follows: (Register 0x8 to Register 0xA) and measure the error 1. Measure the zero-scale error. between the voltage at FORCE/SENSE and the desired 2. Set the output to the highest possible value. value. 3. Measure the actual output voltage and compare it to the e. Calculate the m and c values. required value. This is the gain error. f. Load these values to the appropriate FIN DAC m and 4. Calculate the number of LSBs equivalent to the gain error FIN DAC c registers (Register 0x9 and Register 0xA). and subtract this number from the default value of the m 2. Calibrate the measure voltage (two-point calibration). register. Note that only positive gain error can be reduced. a. Connect SYS_FORCE to FORCE (via SW8) and SYS_SENSE to SENSE (via SW9), and close the internal force/sense switch (via SW11). Rev. E | Page 41 of 66

AD5560 Data Sheet b. Force the voltage on FORCE via SYS_FORCE and where: measure the voltage at MEASOUT. The AV _Headroom is the 2.75 V headroom (includes the R SS SENSE difference is the error between the actual forced voltage drop). voltage and the voltage at MEASOUT. V is the voltage range anticipated at DUTGND. DUTGND 3. Calibrate the measure current (two-point calibration). RCABLE is the cable/path resistance. a. In FV mode, write zero scale to the FIN DAC registers ILOAD is the maximum load current. (Register 0x8 to Register 0xA). When choosing AV , remember to take into account the DD b. Disconnect the FORCE pin and the SENSE pin. specified current ranges. The measure current block has either Connect SYS_FORCE to FORCE (via SW8) and a gain of 20 or 10 and must have sufficient headroom/ SYS_SENSE to SENSE (via SW9). footroom to operate correctly. c. Connect the SYS_FORCE pin to an external ammeter As the nominal, V is ±0.5 V for the full-scale specified and its other terminal to the SYS_SENSE pin. RSENSE current flowing for all ranges. If this is gained by 20, the d. Connect the SYS_SENSE pin to a precision resistor measure current amplifier output (internal node) voltage (R ), where R = R × 20 of the current range, DUT DUT SENSE range is ±10 V with full-scale current and the default offset and connect its other terminal to ground (see Figure 58). DAC setting. The measure current block needs ±2.25 V e. Measure the error between the ammeter reading and footroom/headroom for correct operation in addition to the MEASOUT reading by forcing ±10 V to the FIN the ±0.5 V V . DAC registers (Register 0x8 to Register 0xA). RSENSE f. Repeat Step 3a through Step3e across all current For simplicity, when VREF = 5 V, minimum |AVDD − AVSS| = ranges. 31.125 V (VREF × 5.125 + headroom + footroom); otherwise, 4. Similarly, calibrate the comparator and clamp DACs, and there can be unanticipated effects resulting from headroom/ load the appropriate gain and offset registers. Calibrating footroom issues. This does not take into account cable loss or these DACs requires some successive approximation to DUTGND contributions. determine where the comparator trips or the clamps Similarly, when V = 2.5 V, minimum |AV − AV | = 18.3 V REF DD SS engage. and, when V = 2 V, minimum |AV − AV | = 16 V. REF DD SS SYS_FORCE The AD5560 is designed to settle fast into large capacitive loads; DFAINC RSENSE SW8 therefore, when slewing, the device draws 2× to 3× the current FORCE range from the AVDD/AVSS supplies. When supply rails are chosen, they should be capable of supplying each DPS channel ISENSE EAXMTMERENTEARL with sufficient current to slew. MEASOUT CHOOSING HCAV x AND HCAV x SUPPLY RAILS SYS_SENSE SS DD VSENSE SW9 Selection of HCAVSSx and HCAVDDx supplies is determined by SENSE RDUT the EXTFORCE1 and EXTFORCE2 output ranges. The supply AD5560 WRDHUETR =E R:SENSE × 20 07779-100 rDaUilsT cGhNosDen v moltuasgte t arkane gine,t oca abclceo luonsst, hsueapdprloyo tmole arnand cfeo,o atnrodo m, Figure 58. Measure Current Calibration VRSENSE. If diodes are used in series with the HCAVSSx and HCAV x supplies pins (shown in Figure 60), the diode voltage CHOOSING AV /AV POWER SUPPLY RAILS DD DD SS drop should also be factored into the supply rail calculation. As noted in the Specifications section, the minimum supply The AD5560 is designed to settle fast into large capacitive loads variation across the part is |AV − AV | ≥ 16 V and ≤ 33 V, DD SS in high current ranges; therefore, when slewing, the device draws AV ≥ 8 V, and AV ≤ −5 V. For the AD5560 circuits to DD SS 2× to 3× the current range from the HCAV x and HCAV x operate correctly, the supply rails must take into account not SS DD supplies. When choosing supply rails, ensure that they are only the force voltage range but also the internal DAC capable of supplying each DPS channel with sufficient current minimum voltage level, as well as headroom/footroom. to slew. The DAC amplifier gains VREF by 5.125, and the offset DAC All output stages of the AD5560 are symmetrical; they can centers that range about some chosen point. Because the DAC source and sink the rated current. Supply design/bypassing minimum voltage (V ) is used in other parts of the circuit MIN should account for this. (MEASOUT gain of 0.2), it is important that AV be chosen SS based on the following: POWER DISSIPATION AV ≤ −5.125 × (VREF × (OFFSET_DAC_CODE/216)) − The maximum power dissipation allowed in the EXTFORCE1 SS AV _Headroom − V − (R × I ) stage is 10 W, whereas in the EXTFORCE2 stage, it is 5 W. SS DUTGND CABLE LOAD Take care to ensure that the device is adequately cooled to remove the heat. The quiescent current is ~0.8 W with an Rev. E | Page 42 of 66

Data Sheet AD5560 internal current range enabled and ~1 W with external current step size value is added to or subtracted from FIN DAC x1, ranges, EXTFORCE1 or EXTFORCE2, enabled. This device is calibrated and stored. The user must supply a clock to the RCLK specified for performance up to 90°C junction temperature (T). pin to load the new code to the DAC. The output settles in 1.2 µs J PACKAGE COMPOSITION AND MAXIMUM for a step of 10 mV with CDUT in the lowest range of <0.2 µF. VERTICAL FORCE While the output is settling, the next step is calculated to be ready for the next ramp clock. The calibration engine is used The exposed pad and leads of the TQFP package have a 100% here; therefore, there is a calibration delay of 1.2 µs. tin finish. The exposed paddle is connected internally to AV . SS The simulated maximum allowable force for a single lead is The ramp timing is controlled in two ways: by a user-supplied 0.18 lbs; total allowable force for the package is 11.5 lbs. The clock (RCLK) and by a clock divider register. This gives the quoted maximum force may cause permanent lead bending. user much flexibility over the frequency of the ramp steps. The Other package failure (die, mold, board) may occur first at ramp typically starts after (2 × clock divider + 2) clocks, lower forces. although there can be a ±1 clock delay due to the asynchronous nature of RCLK. The external clock can be a maximum of 833 SLEW RATE CONTROL kHz when using clock divider = 1. Faster RCLK speeds can be There are two methods of achieving different slew rates using used, but the fastest ramp rate is linked into the DAC the AD5560. One method is using the programmable slew rate calibration engine. feature that gives eight programmable rates. The second For slower ramp rates, an even slower RCLK can be used. method is using the ramp feature and an external clock. The step sizes are in multiples of 16 LSBs. If the code previous Programmable Slew Rate to the end code is not a multiple of this step size, the last step is Eight programmable modes of slew rates are available to choose smaller. If the ramp function must be interrupted at any stage from through the serial interface, enabling the user to choose during the ramp, write the interrupt ramp command. The FIN different rates to power up the DUT. The different slew rates DAC x1 stops ramping at the current value and returns to are achieved by variation in the internal compensation of the normal operation. force DAC output amplifier. The slew rates available are The fastest ramp rate is 0.775 V/µs (for a 5 V reference and an 1.000 V/µs, 0.875 V/µs, 0.750 V/µs, 0.625 V/µs, 0.5 V/µs, 833 kHz clock using a 2032 LSB step size and divider = 1). 0.4375 V/µs, 0.35V µs, and 0.313 V/µs. The slowest ramp rate is 24 µV/µs (for a 5 V reference and an Ramp Function 833 kHz clock using a 16 LSB step size and divider = 255). Included in the AD5560 is a ramp function that enables the Even slower ramps can be achieved with slower SCLK. The user to apply a rising or falling voltage ramp to the DUT. The ramp continues until any of the following occurs: user supplies a clock, RCLK, to control the timing. • It reaches the end code. This function is controlled via the serial interface and requires • An interrupt ramp is received from the user. programming of a number of registers to determine the end • If any enabled alarm triggers, the ramp stops to allow value, the ramp size, and the clock divider register to determine the user to service the activated alarm. the update rate. While the device is in ramp mode, the only command that the The contents of the FIN DAC x1 register are the ramp start interface accepts is an interrupt ramp. No other commands should value. The user must load the end code register and the step be written to the device while ramping because they are ignored. size register. The sign is now generated from the difference between the FIN DAC x1 register and the end code; then the Rev. E | Page 43 of 66

AD5560 Data Sheet NEW RAMP SCTEHPA NSGIZEE? YES SELECT RAMP SIZE NO CHANGE YES PROGRAM DICVLISOICOKN? CLOCK DIVIDER NO CHANGE RAMP YES WRITE NEW START? FIN ×1 DACVALUE NO WRITE RAMP END CODE RAMP MODE ENABLE RAMP UPDCAOTDEE D?AC YES NECXATL DCAUCL ACTOEDE LOAD DAC NO INTERRUPT YES DO NOT LOAD DAC. RAMP? RETAIN PREVIOUS ALARM? VALUE NO NO RAMP COMPLETE? YES NORREMTUARLN MTOODE TERMINATE RAMP 07779-011 Figure 59. Flow Chart for Ramp Function Rev. E | Page 44 of 66

Data Sheet AD5560 SERIAL INTERFACE BUSY FUNCTION The AD5560 contains an SPI-compatible interface operating at clock frequencies of up to 50 MHz. To minimize both the BUSY is a digital open-drain output that indicates the status of power consumption of the device and on-chip digital noise, the the AD5560. All writes drive the BUSY output low for some interface powers up fully only when the device is being written period of time; however, events that use the calibration engine, to, that is, on the falling edge of SYNC. such as all DAC x1 writes, drive it lower for a longer period of SPI INTERFACE time while the calculations are completed. The serial interface is 2.5 V LVTTL-compatible when operating For the DACs, the value of the internal data (x2) loaded to the from a 2.3 V to 3.6 V DV supply. It is controlled by the DAC data register is calculated each time the user writes new CC following four pins: data to the corresponding x1 register. During the calculation of x2, the BUSY output goes low and x2 writes are pipelined; • SYNC (frame synchronization input) therefore, x2 writes can still be presented to the device while • SDI (serial data input pin) BUSY is still low (see the Register Update Rates section). The • SCLK (clocks data in and out of the device) DAC outputs update immediately after BUSY goes high. • SDO (serial data output pin for data readback) Writes to other registers must be handled differently and SPI WRITE MODE should either watch the BUSY pin or be timed. While BUSY The AD5560 allows writing of data via the serial interface to is low, the user can continue writing new data to any control every register directly accessible to the serial interface, which register, m register, or c register but should not complete the is all registers except the DAC registers. writing process (SYNC returning high) until the BUSY signal has returned high. The serial word is 24 bits long. The serial interface works with both a continuous and a burst (gated) serial clock. Serial data BUSY also goes low during power-on reset, as well as when a applied to SDI is clocked into the AD5560 by clock pulses applied low level is detected on the RESET pin. to SCLK. The first falling edge of SYNC starts the write cycle. BUSY writes to the system control register, compensation At least 24 falling clock edges must be applied to SCLK to clock register, alarm register, and diagnostic register; m or c registers in 24 bits of data before SYNC is taken high again. do not involve the calibration engine, thus speeding up writing The input register addressed is updated on the rising edge of to the device. SYNC. For another serial transfer to take place, SYNC must be LOAD FUNCTION taken low again. The AD5560 device contains a function with which updates SDO OUTPUT to multiple devices can be synchronized using the LOAD The SDO output in the AD5560 is a weak/slow output driver. function. There is not a dedicated pin available for this If using readback or the daisy-chain function, the frequency of function; however, either the CLEN or HW_INH pin can SCLK must be reduced so that SDO can operate properly. The be used as a LOAD input (selection is made in the system SCLK frequency is dependent on the DV supply voltage used; CC control register, Address 0x1, Bits[8:7]). see Table 2 for details and the following example: When selected as the LOAD function, the pin no longer Maximum SCLK = 12 MHz, then DV = 2.3 V to 2.7 V CC operates in its previous function (power-on default for each Maximum SCLK = 15 MHz, then DVCC = 2.7 V to 3.3 V of these pins is a CLEN or HW_INH function). Maximum SCLK = 20 MHz, then DVCC = 4.5 V to 5.5 V The LOAD function controls the following registers: RESET FUNCTION • 0x8 FIN DAC x2 register RESET is a level-sensitive input. Bringing the RESET line low • 0xD CLL DAC x2 register resets the contents of all internal registers to their power-on • 0x10 CLH DAC x2 register reset state. The falling edge of RESET initiates the reset process; • 0x4 Compensation Register 1 BUSY goes low for the duration, returning high when the • 0x5 Compensation Register2 RESET process is complete. This sequence takes 300 µs • 0x2 DPS Register1 (only current ranges, Bits[13:11]) maximum. Do not write to the serial interface while BUSY There is, however, an alternate method for updating and using is low handling a RESET command. When BUSY returns high, the CLEN and HW_INH pins in their normal function. normal operation resumes, and the status of the RESET pin is ignored until it goes low again. Rev. E | Page 45 of 66

AD5560 Data Sheet If Bits[8:7] of the system control register (Address 0x1) are corresponding x1 register. The calculation is performed by a high, then the CLEN and HW_INH operate as normal, and the three stage process. The first two stages take 600 ns each, and update waits until BUSY goes high (this way multiple channels the third stage takes 300 ns. When the write to one of the x1 can still be synchronized by simply tying BUSY pins together). registers is complete, the calculation process begins. The user is free to write to another register provided that the write REGISTER UPDATE RATES operation does not finish until the first stage calculation is As mentioned previously, the value of the x2 register is complete, that is, 600 ns after the completion of the first write calculated each time the user writes new data to the operation. Rev. E | Page 46 of 66

Data Sheet AD5560 CONTROL REGISTERS DPS AND DAC ADDRESSING A no operation (NOP) command performs no function within the device. This code may be useful when performing a The serial word assignment consists of 24 bits, as shown in readback function where a change of DAC or DPS register is Table 16. All write-to registers can be read back. There are not required. some read-only registers (Address 0x43 and Address 0x44). DAC x2 registers are not available for readback. Table 16. Serial Word Assignment B23 [B22:B16] [B15:B0] R/W Address bits Data bits Table 17. Read or Write Register Addressing Address Register Default Data Bits, MSB First 0x0 NOP 0x0000 NOP command; performs no operation. 0x1 System 0x0000 Bit Name Function control 15 TMP[1:0] Thermal shutdown bits. TMP1, TMP0 allow the user to program the thermal register 14 shutdown temperature of operation. TMP Action 0 Shutdown at a T of 130°C (power-on default) J 1 Shutdown at a T of 120°C J 2 Shutdown at a T of 110°C J 3 Shutdown at a T of 100°C J 13 Gain[1:0] MEASOUT output range. The MEASOUT range defaults to the voltage force span for 12 voltage and current measurements (this is ±12.81 V), which includes some overrange to allow for error correction. The MEASOUT range can be reduced by using the gain bits. This allows for use of asymmetrical supplies or for use of a smaller input range ADC. MEASOUT gain settings do not translate the low voltage temperature sensor signal (TSENSE). Gain MEASOUT Gain MI Gain 0 1 20 1 1 10 2 0.2 20 3 0.2 10 To allow for system error correction, there is an additional gain of 0.125 for the force function if this error correction is used as intended; then the output range on MEASOUT scales accordingly (see Table 9). 11 FINGND Writing a 1 to FINGND switches the positive input of the force amplifier to GND; when 0, the input of the force amplifier is connected to the output of the force DAC. 10 CPO Write a 1 to the CPO bit to enable a simple window comparator function. In this mode, only one comparator output is available (CPOH/CPO). This provides two bits of information. The compared value is either inside or outside the window and enables the user to bring only one line back to the controller per DPS device. 9 PD This bit powers down the force amplifier block. Note that the amplifier must be powered up but inhibited (SW-INH or HW_INH), to meet leakage specifications. A 0 powers this block down (default). 8 LOAD Updates to registers listed in the following LOAD function column do not occur until 7 the active LOAD pin is brought low (or in the case of LOAD 3, until BUSY goes high). LOAD LOAD Function 0 Default operation, CLEN and HW_INH function normally. 1 The CLEN pin is a LOAD input. 2 The HW_INH pin is a LOAD input. 3 The device senses the BUSY open-drain pin and doesn't update until that goes high. No LOAD hardware pin. CLEN and HW_INH function normally. 6:0 Unused Set to 0. Rev. E | Page 47 of 66

AD5560 Data Sheet Table 18. DPS Register 1 Address Default Data Bits, MSB First 0x2 0x0000 Bit Name Function 15 SW-INH This bit enables the force amplifier when high and disables the amplifier when low. This bit is AND’d with the HW_INH hardware inhibit pin. 14 Reserved Reserved, set to 0. 13 I[2:0] Current range addressing. These bits allow selection of the required current range. 12 11 I Action 0 ±5 µA current range. 1 ±25 µA current range. 2 ±250 µA current range. 3 ±2.5 mA current range. 4 ±25 mA current range. 5 External Range 2. 6 External Range 1. 7 Reserved. 10 CMP[1:0] Comparator function. CMP1 acts as a comparator output enable, whereas CMP0 selects between a comparing DUT current or voltage; by default, the comparators are high-Z on power-on. 9 CMP Action 0 Comparator outputs high-Z. 1 Comparator outputs high-Z. 2 Compare DUT current. 3 Compare DUT voltage. 8 ME[3:0] Bits ME[3:0] allow selection of the required measure mode, allowing the MEASOUT line to be disabled; 7 connect to the temperature sensor or enable it for measurement. ME[3] is MEASOUT enable/disable; when high, MEASOUT is enabled, and ME[2:0] can be used to preselect the measuring parameter. Where a 6 number of MEASOUT lines are connected together and passed to a common ADC, this function can allow 5 for much faster measurement time between channels because the slew time of the measurement buffer is reduced. For details on diagnostic functions, see Address 0x7, the diagnostic register. ME[2:0] Action 0 MEASOUT high-Z. 1 Connect MEASOUT to I SENSE. 2 Connect MEASOUT to V SENSE. 3 Connect MEASOUT to K SENSE. 4 Connect MEASOUT to TSENSE. 5 Connect MEASOUT to DUTGND SENSE. 6 Connect MEASOUT to diagnostic functions: DIAG A (see Address 0x7). 7 Connect MEASOUT to diagnostic functions: DIAG B (see Address 0x7). 4 CLEN Clamp enable; set high to enable the clamp; set low to disable the clamp. This bit is OR’d with the hardware CLEN pin. 3:0 Unused Set to 0. Rev. E | Page 48 of 66

Data Sheet AD5560 Table 19. DPS Register 2 Address Default Data Bits, MSB First 0x3 0x0000 Bit Name Function 15 SF0 System force and sense line addressing, SF0. Bit SF0 addresses each of the different combinations of switching the system force and sense lines to the force and sense pins at the DUT. Guard High-Z (Bit 7) SFO SYS_SENSE Pin SYS_FORCE Pin GUARD/SYS_DUTGND Pin 0 0 Open Open Guard 0 1 Sense Force Guard 1 0 Open Open Open 1 1 Sense Force DUTGND 14 SR[2:0] Slew rate control, SR2, SR1, SR0. Selects the slew rate for the main DAC output amp. 13 SR Action 12 0 1 V/μs 1 0.875 V/μs 2 0.75 V/μs 3 0.62 V/μs 4 0.5 V/μs 5 0.43 V/μs 6 0.35 V/μs 7 0.3125 V/μs 11 GPO General purpose output bit. The GPO bit can be used for any function, such as disconnecting the decoupling capacitor to help speed up low current testing. 10 SLAVE, Ganging multiple devices increases the current drive available. Use these bits to enable 9 GANGIMODE selection of the ganging mode and place the device in slave or master mode. In default operation, each device is a master (gang of one). Figure 54 shows how the device is configured in this mode. SLAVE Action 0 Master: MASTER_OUT = internally connects to active EXTFORCE1/ EXTFORCE2 output 1 Master: MASTER_OUT = master MI 2 SLAVE FV to EXTFORCE1/EXTFORCE2 connected internally to close the FVAMP loop 3 SLAVE FI 8 INT10K Setting this bit high allows the user to connect an internal sense short resistor of 10 kΩ between the force and the sense lines (closes SW11). This resistor is actually made up of series 4 kΩ resistors followed by a 2 kΩ switch and another 4 kΩ resistor. There is a 10 kΩ resistor that can be connected between the FORCE and SENSE pins by use of SW11. This 10 kΩ resistor is intended to maintain a force/sense connection when a DUT is not in place. It is not intended to be connected when measurements are being made because this defeats the purpose of the OSD circuit in identifying an open circuit between FORCE and SENSE. In addition, the sense path has a 2.5 kΩ resistor in series; therefore, if the 10 kΩ switch is closed, errors may become apparent when in high current ranges. 7 Guard high-Z Set this bit high to high-Z the guard amplifier. This is required if using the GUARD/ SYS_DUTGND pin in the SYS_DUTGND function. 6:0 Unused Set to 0. Rev. E | Page 49 of 66

AD5560 Data Sheet The AD5560 has three compensation modes. The power-on default mode is SAFEMODE enabled. This ensures that the device is stable into any load. Use Compensation Register 1 to configure the device for autocompensation, where the user inputs the CDUT and ESR bits, and the AD5560 chooses the most appropriate compensation scheme for these load conditions. Table 20. Compensation Register 1 Address Default Data Bits, MSB First 0x4 0x0000 Bit Name Function 15 CDUT[3:0] Use these control bits to tell the device how much capacitive load there is so that the device can 14 optimize the compensation used. Do not overestimate CDUT because this can cause oscillations. 13 Underestimating CDUT gives suboptimal but stable performance. 12 CDUT CDUT Min CDUT Max 0 0 nF 50 nF 1 50 nF 83 nF 2 83 nF 138 nF 3 138 nF 229 nF 4 229 nF 380 nF 5 380 nF 630 nF 6 630 nF 1.1 µF 7 1.1 µF 1.7 µF 8 1.7 µF 2.9 µF 9 2.9 µF 4.8 µF 10 4.8 µF 7.9 µF 11 7.9 µF 13 µF 12 13 µF 22 µF 13 22 µF 36 µF 14 36 µF 60 µF 15 60 µF 160 µF 11 ESR[3:0] Use these control bits to tell the device how much ESR there is in series with CDUT so that the device can 10 optimize the compensation used. Do not underestimate ESR because this can cause oscillations. 9 Overestimating ESR gives suboptimal but stable performance. 8 ESR ESR Min ESR Max 0 0 mΩ 1 mΩ 1 1 mΩ 1.8 mΩ 2 1.8 mΩ 3.4 mΩ 3 3.4 mΩ 6.3 mΩ 4 6.3 mΩ 12 mΩ 5 12 mΩ 21 mΩ 6 21 mΩ 40 mΩ 7 40 mΩ 74 mΩ 8 74 mΩ 140 mΩ 9 140 mΩ 250 mΩ 10 250 mΩ 460 mΩ 11 460 mΩ 860 mΩ 12 860 mΩ 1500 mΩ 13 1500 mΩ 2900 mΩ 14 2900 mΩ 5400 mΩ 15 6400 mΩ 10,000 mΩ 7 SAFEMODE SAFEMODE = 0 overrides values in Compensation Register 1 to make the force amplifier stable under most load conditions. This mode is useful if it is unknown what the DPS is driving, but it does result in an extremely slow response. The default operation on power-on or reset is SAFEMODE. SAFEMODE settings are always g = 2, R = 0, R = 0, C = 111, C = 5, and C = 1. m[1:0] P[2:0] Z[2:0] C[3:1] F[2:0] C0 Set this bit high to enable autocompensation. 6:0 Reserved Set to 0. Rev. E | Page 50 of 66

Data Sheet AD5560 Table 21. Compensation Register 2 Address Default Data Bits, MSB First 0x5 0x0110 Bit Name Function 15 Manual The AD5560 can be manually configured to compensate the force amplifier into a wide range of load compensation conditions. When this bit is high, manual compensation mode is active, and it overrides the settings of Compensation Register 1. Readback when in manual compensation mode returns the compensation settings loaded to the force amplifier and loaded to this register. Similarly, when in autocompensation mode, readback of this register address returns the compensation settings of the force amplifier. However, readback of this register address when in safe mode does not reflect SAFEMODE settings. SAFEMODE settings are g = 2, R[2:0] = 0, R = 0, C ] = 111, C = 5, and C = 1. m[1:0] P Z[2:0] C[3:1 F[2:0] C0 14 R Set the value of R to add a zero at the following frequencies. This calculation assumes that C = 100 pF. Z[2:0] Z C0 13 R R (Ω) F (Hz) Z Zx Z 12 01 500 3.2 M 1 1.6 k 1 M 2 5 k 320 k 3 16 k 100 k 4 50 k 32 k 5 160 k 10 k 6 500 k 3.2 k 7 1.6 M 1 k 11 R Set the value of R to add an additional pole. There is an internal 8 pF capacitor to provide an RC filter, P[2:0] P 10 creating a pole at one of the following frequencies. 9 R R (Ω) F (Hz) P[2:0] P P 01 200 100 M 1 675 29 M 2 2280 8.7 M 3 7700 2.6 M 4 26 k 760 k 5 88 k 220 k 6 296 k 67 k 7 1 M 20 k 8 g Set the transconductance of the force amplifiers input stage. The gain bandwidth (GBW) of the force m[1:0] 7 voltage loop is equal to gmx/CC0. The following values assume CC0 = 100 pF. g g (µA/V) GBW (Hz) mx mx 0 40 64 k 1 80 130 k 21 300 480 k (default) 3 900 1.3 M 6 C These bits determine which feedforward capacitor C is switched in. F[2:0] Fx 5 C Action Fx 4 0 None 1 C F0 2 C F1 3 C F2 4 C F3 51 CF4 6 None 7 None 3 CC3 Connect CC3 in series with 100 kΩ1 2 CC2 Connect CC2 in series with 25 kΩ1 1 CC1 Connect CC1 in series with 6 kΩ1 0 Reserved 0 1 This item corresponds to a SAFEMODE setting (SAFEMODE is the power-on default setting). Rev. E | Page 51 of 66

AD5560 Data Sheet Register 0x6 allows the user to enable or disable any of the alarm flags that are not required. If disabled, that particular alarm no longer flags on the appropriate open-drain pin; however, the alarm status is still available in both of the alarm status registers (Address 0x43 and Address 0x44). Table 22. Alarm Setup Register Address Default Data Bits, MSB First 0x6 0x0000 Bit Name Function 15 Latched Set this latched bit high to program the open-drain TMPALM alarm pin as a latched output; TMPALM leave low for an unlatched alarm pin (default). 14 Disable Set this bit high to disable the open-drain TMPALM alarm pin; leave low to leave enabled (default). TMPALM 13 Latched Set this latched bit high to program the OSALM as a latched alarm on the open-drain KELALM OSALM pin; leave low for an unlatched alarm pin (default). 12 Disable Set this bit high to disable the OSALM alarm function flagging the open-drain KELALM pin; OSALM leave low to remain enabled (default). The disable GRDALM, DUTALM, and OSALM alarm functions share one open-drain KELALM alarm pin. These bits allow users to choose if they wish to have all or selected information flagged to the alarm pin. 11 Latched Set this latched bit high to program the DUTALM as a latched alarm on the open-drain KELALM DUTALM pin; leave low for an unlatched alarm pin (default). 10 Disable Set this bit high to disable the DUTALM alarm function flagging the open-drain KELALM pin. DUTALM Leave low to leave enabled (default). The disable GRDALM, DUTALM, and OSALM alarm functions share one open drain KELALM alarm pin. These bits allow users to choose if they wish to have all or any information flagged to the alarm pin. The DUTGND pin has a 50 µA pull-up to allow for detection of an error in the DUTGND path. Setting this bit high also disables the 50 µA pull-up. 9 Latched Set this latched bit high to program the open-drain CLALM clamp alarm pin as a latched CLALM output; leave low for an unlatched alarm pin (default). 8 Disable Set this bit high to disable the open drain CLALM alarm pin; leave low to leave enabled (default). CLALM 7 Latched Set this latched bit high to program the GRDALM as a latched alarm on the open-drain KELALM GRDALM pin; leave low for an unlatched alarm pin (default). 6 Disable Set this bit high to disable the GRDALM alarm function flagging the open-drain KELALM pin; GRDALM leave low to leave enabled (default). The disable GRDALM, DUTALM and OSALM alarm functions share one open-drain KELALM alarm pin. These bits allow users to choose if they wish to have all or any information flagged to the KELALM alarm pin. 5:0 Unused Set to 0. Rev. E | Page 52 of 66

Data Sheet AD5560 Table 23. Diagnostic Register Address Default Data Bits, MSB First 0x7 0x0000 Bit Name Function 15 DIAG DIAG select selects the set of diagnostic signals that can be made available on MEASOUT. First, use MEASOUT 14 select[3:0] addressing (DPS Register 1) to select either the DIAG A or the DIAG B node to be made available on MEASOUT. 13 Selected 12 DIAG Select Measure Block DIAG A DIAG B 0:3 Disabled Disabled Disabled 4 Force amplifier Disabled Disabled 5 EXTFORCE1A EXTFORCE2A 6 FINP FINM 7 Output 2.5 mA Output 25 mA 8 Measure block VPTAT low VPTAT high 9 VTSD low (ref V VTSD high (ref V for +130°C) for −273°C) 10 MI VMID Code 11 MV VMIN Code 12 DAC block FORCE DAC VOS DAC 13 CLL DAC CLH DAC 14 CPL DAC CPH DAC 15 OSD DAC DGS DAC VPTAT low/VPTAT high are temperature sensor devices in the middle of the enabled power stage, which gives a voltage level that can be mapped back to the VTSD low and VTSD high reference points to get a temperature value. These sensors are used in the thermal shutdown feature. See the Die Temperature Sensor and Thermal Shutdown section. VMID code is the midscale voltage of the DACs; the offset DAC has a direct effect on this voltage level. VMIN code is the zero-scale voltage of the DACs; again the offset DAC has a direct effect. 11 TSENSE The following codes allow selection of one of three sets of eight thermal diodes. The D+ of the selected thermal 10 select[3:0] diode is available on the GPO pin; the D− is on the AGND. 9 These thermal diodes are located across the die, in the cool parts and in the power stages. Diodes [16:23] are located 8 in the force amplifier NPNs (power output devices for supplying current). Similarly, Diodes [24:31] are located in the force amplifier PNP devices (output devices for sinking current). 7 Selected TSENSE Select Thermal Block Connected Sensor 0:7 N/A—normal No sensor connected GPO operation 8 Cool block Cool end of high current drivers, hot side of digital block 9 25 mA output stage 10 Hottest part of sensitive measurement circuitry and cool part of force amplifier 11 Coolest end of force amplifier block 12 Coolest end of DACs 13 Beside TSENSE available on MEASOUT 14 Hottest part of DACs 15 Cool side of digital block 16 Force amplifier 1A-1 17 PNPs 1A-2 18 2A (similar location to VPTAT low for EXTFORCE2 range) 19 1B-1 (similar location to VPTAT low for EXTFORCE1 range) 20 1B-2 21 2B 22 1C-1 23 1C-2 Rev. E | Page 53 of 66

AD5560 Data Sheet Address Default Data Bits, MSB First 0x7 0x0000 Bit Name Function 24 Force amplifier 1A-1 25 NPNs 1A-2 26 2A (similar location to VPTAT high for EXTFORCE2 range) 27 1B-1 (similar location to VPTAT high for EXTFORCE1 range) 28 1B-2 29 2B 30 1C-1 31 1C-2 6 Test Force These register bits allow disabling of stages of the force amplifier. They can be used to ensure connectivity in 5 AMP[1:0] each parallel stage. The enabled stage depends also on which current range is selected. Test Force Current Range Amplifier Enabled Stage EXTFORCE1 0 All stages EXTFORCE1 1 EXTFORCE1C EXTFORCE1 2 EXTFORCE1B EXTFORCE1 3 EXTFORCE1A EXTFORCE2 0 All stages EXTFORCE2 1 Reserved EXTFORCE2 2 EXTFORCE2B EXTFORCE2 3 EXTFORCE2A 4:0 Reserved Set to 0. Rev. E | Page 54 of 66

Data Sheet AD5560 Table 24. Other Registers Address Register Default Data Bits, MSB First 0x8 FIN DAC x1 0x8000 x1 DAC register; D15 to D0, MSB first. 0x9 FIN DAC m 0xFFFF m register; D15 to D0, MSB first. 0xA FIN DAC c 0x8000 c register; D15 to D0, MSB first. 0xB Offset DAC x 0x8000 D15 to D0. 0xC OSD DAC x 0x1FFF D15 to D0. 0xD CLL DAC x1 0x0000 D15 to D0; the low clamp level can only be negative; the MSB is always 0 to ensure this. 0xE CLL DAC m 0xFFFF D15 to D0. 0xF CLL DAC c 0x8000 D15 to D0. 0x10 CLH DAC x1 0xFFFF D15 to D0; the high clamp level can only be positive; the MSB is always 1 to ensure this. 0x11 CLH DAC m 0xFFFF D15 to D0. 0x12 CLH DAC c 0x8000 D15 to D0. 0x13 CPL DAC x1 5 μA range 0x0000 D15 to D0. 0x14 CPL DAC m 5 μA range 0xFFFF D15 to D0. 0x15 CPL DAC c 5 μA range 0x8000 D15 to D0. 0x16 CPL DAC x1 25 μA range 0x0000 D15 to D0. 0x17 CPL DAC m 25 μA range 0xFFFF D15 to D0. 0x18 CPL DAC c 25 μA range 0x8000 D15 to D0. 0x19 CPL DAC x1 250 μA range 0x0000 D15 to D0. 0x1A CPL DAC m 250 μA range 0xFFFF D15 to D0. 0x1B CPL DAC c 250 μA range 0x8000 D15 to D0. 0x1C CPL DAC x1 2.5 mA range 0x0000 D15 to D0. 0x1D CPL DAC m 2.5 mA range 0xFFFF D15 to D0. 0x1E CPL DAC c 2.5 mA range 0x8000 D15 to D0. 0x1F CPL DAC x1 25 mA range 0x0000 D15 to D0. 0x20 CPL DAC m 25 mA range 0xFFFF D15 to D0. 0x21 CPL DAC c 25 mA range 0x8000 D15 to D0. 0x22 CPL DAC x1 EXT Range 2 0x0000 D15 to D0. 0x23 CPL DAC m EXT Range 2 0xFFFF D15 to D0. 0x24 CPL DAC c EXT Range 2 0x8000 D15 to D0. 0x25 CPL DAC x1 EXT Range 1 0x0000 D15 to D0. 0x26 CPL DAC m EXT Range 1 0xFFFF D15 to D0. 0x27 CPL DAC c EXT Range 1 0x8000 D15 to D0. 0x28 CPH DAC x 1 5 μA range 0xFFFF D15 to D0. 0x29 CPH DAC m 5 μA range 0xFFFF D15 to D0. 0x2A CPH DAC c 5 μA range 0x8000 D15 to D0. 0x2B CPH DAC x1 25 μA range 0xFFFF D15 to D0. 0x2C CPH DAC m 25 mA range 0xFFFF D15 to D0. 0x2D CPH DAC c 25 μA range 0x8000 D15 to D0. 0x2E CPH DAC x1 250 μA range 0xFFFF D15 to D0. 0x2F CPH DAC m 250 μA range 0xFFFF D15 to D0. 0x30 CPH DAC c 250 μA range 0x8000 D15 to D0. 0x31 CPH DAC x1 2.5 mA range 0x0000 D15 to D0. 0x32 CPH DAC m 2.5 mA range 0xFFFF D15 to D0. 0x33 CPH DAC c 2.5 mA range 0x8000 D15 to D0. 0x34 CPH DAC x1 25 mA range 0xFFFF D15 to D0. 0x35 CPH DAC m 25 mA range 0xFFFF D15 to D0. 0x36 CPH DAC c 25 mA range 0x8000 D15 to D0. 0x37 CPH DAC x1 EXT Range 2 0xFFFF D15 to D0. 0x38 CPH DAC m EXT Range 2 0xFFFF D15 to D0. 0x39 CPH DAC c EXT Range 2 0x8000 D15 to D0. 0x3A CPH DAC x1 EXT Range 1 0xFFFF D15 to D0. 0x3B CPH DAC m EXT Range 1 0xFFFF D15 to D0. Rev. E | Page 55 of 66

AD5560 Data Sheet Address Register Default Data Bits, MSB First 0x3C CPH DAC c EXT Range 1 0x8000 D15 to D0. 0x3D DGS DAC 0x3333 D15 to D0 DUTGND SENSE DAC, 0 V to 5 V range. 0x3E Ramp end code 0x0000 D15 to D0; this is the ramp end code. The ramp start code is the code that is in the FIN DAC register. 0x3F Ramp step size 0x0001 0000 0000 D6 to D0. D6:D0 set the ramp step size in increments of 16 LSB per code, with a 5 V reference, 16 LSB = 6.1 mV. For example, 000 0000 = 16 LSBs (6.1 mV) step 000 0001 = 16 LSBs (6.1 mV) step … 111 1111 = 2032 LSBs (775 mV) step. 0x40 RCLK divider 0x0001 0000 0000 D7 to D0. D7:D0 set the RCLK divider. 0000 0000 = ÷ 1 0000 0001 = ÷ 1 0000 0010 = ÷ 2 0000 0011 = ÷ 3 … 1111 1111 = ÷ 255 0x41 Enable ramp 0x0000 0xFFFF to enable. 0x42 Interrupt ramp 0x0000 0x0000 to interrupt. Rev. E | Page 56 of 66

Data Sheet AD5560 Table 25. Alarm Status and Clear Alarm Status Register Address Register Default Data Bits, MSB first 0x43 Alarm status 0x0000 This register is a read-only register providing information on the status of the alarm functions and the comparator outputs. Bit Name Function 15 LTMPALM Latched temperature alarm bit; if low, this bit indicates that an alarm event has occurred. 14 TMPALM Unlatched alarm bit; if low, these bit indicates that an alarm event is still present. 13 LOSALM Latched open-sense alarm bit; if low, indicates that an alarm event has occurred. 12 OSALM Unlatched open-sense alarm bit; if low, indicates that an alarm event is still present. 11 LDUTALM Latched DUTGND Kelvin sense alarm; if low, indicates that an alarm event has occurred. 10 DUTALM Unlatched DUTGND Kelvin sense alarm; if low, indicates that an alarm event is still present. 9 LCLALM Latched clamp alarm; if low, indicates that an alarm event has occurred. 8 CLALM Unlatched clamp alarm; if low, indicates that an alarm event is still present. 7 LGRDALM Latched guard alarm; if low, indicates that an alarm event has occurred. 6 GRDALM Unlatched guard alarm; if low, indicates that an alarm event is still present. 5 CPOL Comparator output low condition as per the comparator output pin. 4 CPOH Comparator output high condition as per the comparator output pin. 3:0 Unused Must be zeros. 0x44 Alarm status 0x0000 This register is a read-only register providing information on the status of the alarm functions and and clear alarm the comparator outputs. Reading this register also automatically clears any latched alarm pins or bits. Bit Name Function 15 LTMPALM Latched temperature alarm bit; if low, this bit indicates that an alarm event has occurred. 14 TMPALM Unlatched alarm bit; if low, these bit indicates that an alarm event is still present. 13 LOSALM Latched open-sense alarm bit; if low, indicates that an alarm event has occurred. 12 OSALM Unlatched open-sense alarm bit; if low, indicates that an alarm event is still present. 11 LDUTALM Latched DUTGND Kelvin sense alarm; if low, indicates that an alarm event has occurred. 10 DUTALM Unlatched DUTGND Kelvin sense alarm; if low, indicates that an alarm event is still present. 9 LCLALM Latched clamp alarm; if low, indicates that an alarm event has occurred. 8 CLALM Unlatched clamp alarm; if low, indicates that an alarm event is still present. 7 LGRDALM Latched guard alarm; if low, indicates that an alarm event has occurred. 6 GRDALM Unlatched guard alarm; if low, indicates that an alarm event is still present. 5 CPOL Comparator output low condition as per the comparator output pin. 4 CPOH Comparator output high condition as per the comparator output pin. 3:0 Unused Must be zeros. 0x45 CPL DAC x1 0x0000 D15 to D0. V comparator low threshold. SENSE 0x46 CPL DAC m 0xFFFF D15 to D0. V comparator low gain. SENSE 0x47 CPL DAC c 0x8000 D15 to D0. V comparator low offset. SENSE 0x48 CPH DAC x1 0xFFFF D15 to D0. V comparator high threshold. SENSE 0x49 CPH DAC m 0xFFFF D15 to D0. V comparator high gain. SENSE 0x4A CPH DAC c 0x8000 D15 to D0. V comparator high offset. SENSE 0x4B to Reserved Reserved. 0x7F Rev. E | Page 57 of 66

AD5560 Data Sheet READBACK MODE DAC READBACK The AD5560 allows data readback via the serial interface from The DAC x1, DAC m, and DAC c registers are available to read every register directly accessible to the serial interface, which is back via the serial interface. Access to the calibrated x2 register all registers except the DAC register (x2 calibrated register). To is not available. read back contents of a register, it is necessary to write a 1 to POWER-ON DEFAULT the R/W bit, address the appropriate register, and fill the data During power-on, the power-on state machine resets all internal bits with all zeros. registers to their default values, and BUSY goes low. A rising After the write command has been written, data from the edge on BUSY indicates that the power-on event is complete selected register is loaded to the internal shift register and is and that the interface is enabled. The RESET pin has no available on the SDO pin during the next SPI operation. function in the power-on event. Address 0x43 and Address 0x44 are the only registers that are During power-on, all DAC x1 registers corresponding to 0 V read only. The read function gives the user details of the alarm are cleared; the calibration register default corresponds to m at status and the comparator output result. full scale and to c at zero scale. Alarm flags on latched alarm pins (Pin 1, Pin 2, Pin 3) and bits The default conditions of the DPS and the system control are cleared after a read command of Register 0x44 (alarm status registers are as shown in the relevant tables (see Table 17 and clear alarm register (see Table 25)). through Table 26). SCLK frequency for readback does not operate at the full speed During a RESET function, all registers are reset to the power-on of the SPI interface. See the Timing Characteristics section for default. further details. Rev. E | Page 58 of 66

Data Sheet AD5560 Table 26. AD5560 Truth Table of Switches1 Reg Bit Name Bit SW1 SW2 SW3 SW4 SW7 SW13 SW14 SW15 SW5 SW6 SW8 SW9 SW11 SW16 System Gain0, X X X X X X X X X X X X X X Control Gain1 Register FINGND 0 B X X X X X X X X X X X X X 1 A X X X X X X X X X X X X X CPO X X X X X X X X X X X X X X PD2, 3 X X X X X X X X X X X X X On DPS Register 1 SW-INH2 04 X c X X X X X X X X X X X X 15 X a X X X X X X X X X X X X I2, I1, I0 000 X X X On On Off Off Off X X X X X X 001 X X X On On Off Off Off X X X X X X 010 X X X On On Off Off Off X X X X X X 011 X X X On On Off Off Off X X X X X X 100 X X X On On Off Off Off X X X X X X 101 X X X Off Off Off On On X X X X X X 110 X X X Off Off On Off On X X X X X X CMP1, CMP0 00 X X X X X X X X X X X X X X 01 X X X X X X X X X X X X X X 10 X X a X X X X X X X X X X X 11 X X b X X X X X X X X X X X ME3, ME2, 000 X X X X X X X X X X X X X Off ME1, ME0 001 X X X X X X X X X X X X X On 010 X X X X X X X X X X X X X On 011 X X X X X X X X X X X X X On 100 X X X X X X X X X X X X X On 101 X X X X X X X X X X X X X On 110 X X X X X X X X X X X X X On 111 X X X X X X X X X X X X X On DPS Register 2 SF0 0 X X X X X X X X X X Off Off X X 1 X X X X X X X X X X On On X X Slave, 006 b a X X X X X X a Off X X X X GANGIMODE 017 b a X X X X X X b Off X X X X 108 c c X X X X X X Off On X X X X 119 c b X X X X X X Off On X X X X INT10K 0 X X X X X X X X X X X X Off X 1 X X X X X X X X X X X X On X Hardware Pins HW_INH2 X c X X X X X X X X X X X X CLEN X X X X X X X X X X X X X X 1 X = don’t care; the switch is unaffected by the particular bit condition. 2 Active low. 3 Power-down mode; used for low power consumption. 4 Force amplifier outputs tristate, low leakage mode; feedback made around amplifier. 5 FV mode. 6 Master: MASTER_OUT = internally connects to active EXTFORCE1/EXTFORCE2/25 mA output. 7 Master: MASTER_OUT = master MI. 8 Slave FV: EXTFORCE1/EXTFORCE2/25 mA connected internally to close the FVAMP loop. 9 Slave FI. Rev. E | Page 59 of 66

AD5560 Data Sheet USING THE HCAV x AND HCAV x SUPPLIES internal pull-up resistors between the supplies (see Figure 60). DD SS Using diodes here allows a more flexible use of supplies and The first set of power supplies, AV and AV , provide power DD SS can minimize the amount of supply switching required. In the to the DAC levels and associated circuitry. They also supply the example, the AV and AV supplies can support the high force amplifier stage for the low current ranges (ranges using DD SS voltage needs, whereas the HCAV x and HCAV x supplies internal sense resistors up to 25 mA maximum). DD SS support the low voltage, higher current ranges. Diode selection The second set of power supplies, HCAV 1 and HCAV 1, SS DD should take into account the current carrying requirements. are intended to be used to minimize power consumption in Supply selection for HCAV x and HCAV x supplies must DD SS the AD5560 device for the EXTFORCE1 range (up to ±1.2 A). allow for this extra voltage drop. Similarly, the HCAV 2 and HCAV 2 supplies are used for the SS DD POWER SUPPLY SEQUENCING EXTFORCE2 range (up to ±500 mA). These supplies must be less than or equal to the AV and AV supplies. When driving When the supplies are connected to the AD5560, it is important DD SS high currents at low voltages, power can be greatly minimized that the AGND and DGND pins be connected to the relevant by ensuring that the supplies are at the lowest voltages. ground plane before the positive or negative supplies are applied. In most applications, this is not an issue because the ground Therefore, HCAV x and HCAV x can be switched externally SS DD pins for the power supplies are connected to the ground pins of to different power rails as required by the set voltage range. the AD5560 via ground planes. The AV and AV supplies However, the design of the high current output stage means DD SS must be applied to the device either before or at the same time that these supplies always have to be at a higher voltage than as the HCAV x and HCAV x supplies, as indicated in Table 3. the forced voltage, irrespective of the current range being used. DD SS There are no known supply sequences surrounding the DV Therefore, depending on the level of supply switching, external CC supply, although it is recommended that it be applied as diodes may be required in series with each of the HCAV x DD indicated by the absolute maximum ratings (see Table 3). and HCAV x supplies, as shown in Figure 60. There are SS AVSS = –5V HCAVSS1 = –5V HCAVSS2 = –5V AVDD = +28V HCAVDD1 = +6V HCAVDD2 = +9V 10µF 10µF DVCC = 3V/5V 10µF 10µF 10µF 10µF + + + + + + 0.1µF + 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF + + + + + + 33kΩ 100kΩ 100kΩ 33kΩ 3. MIDCURRENT RANGE 500mA ALLOW ±0.5V RANGE FOR EXT RSENSE EXTFORCE2 2. HIGHEST CURRENT DUT RANGE RANGE 0V TO +6V OUTPUT RANGE –0.2V TO +6.5V 1200mA RANGE ALLOW ±0.5V FOR EXT RSENSE EXTFORCE1 DUT RANGE –2V TO +3V OUTPUT RANGE –2.5V TO +3.5V 1. LOW CURRENT, HIGH VOLTAGE INTERNAL RANGE SELECT (5µA, 25µA, 250µA, 2.5mA, 25mA) FORCE OUTPUT RANGE DUT RANGE INTERNAL RSENSE 0V TO +25V 0V TO +25V ±0.5V AT FULL CURRENT AD5560 07779-012 Figure 60. Example of Using the Extra Supply Rails Within the AD5560 to Achieve Multiple Voltage/Current Ranges Rev. E | Page 60 of 66

Data Sheet AD5560 REQUIRED EXTERNAL COMPONENTS five feedforward capacitor input pins, all capacitor inputs may be used only if the user intends to drive large variations of DUT The minimum required external components are shown in the load capacitances. If the DUT load capacitance is known and block diagram in Figure 61. Decoupling is very dependent on does not change for all combinations of voltage ranges and test the type of supplies used, the board layout, and the noise in the conditions, then it is possible only one set of C and C is system. It is possible that less decoupling may be required as a Cx Fx required. result. Although there are four compensation input pins and AVSS HCAVSS1 HCAVSS2 AVDD HCAVDD1 HCAVDD2 SHARED 10µF 10µF REFERENCE 10µF 10µF 10µF 10µF + + + + + + DVCC REF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF + + + + + + + + DVCC OR AVSS AVDD DVCC VREF CC0CC1 CC2CC3 OTHER DIGITAL SUPPLY RPULLUP EXTFORCE1 CLALM EXTFORCE2 KELALM CF0 TMPALM CF1 DVCC OR CF2 OTHER CF3 DIGITAL SUPPLY CF4 RPULLUP RESET FORCE SENSE EXTMEASHI1 EXTMEASHI2 RSENSE 1 EXTMEASIL RSENSE 2 VREF MEASOUT ADC ADC DRIVER DUT SHARED DUTGND ADC 07779-013 Figure 61. External Components Required for Use with the DPS Table 27. References Suggested for Use with the AD55601 Ref Out Tempco Initial (ppm/°C max) Ref Output Supply Voltage Part No. Voltage (V) Accuracy % A/B Grade Current (mA) Range (V) Package ADR431 2.5 ±0.04 10/3 30 4.5 to 18 MSOP, SOIC ADR435 5 ±0.04 10/3 30 7 to 18 MSOP, SOIC ADR441 2.5 ±0.04 10/3 10 3 to 18 MSOP, SOIC ADR445 5 ±0.04 10/3 10 5.5 to 18 MSOP, SOIC 1 Subset of the possible references suitable for use with the AD5560. See http://www.analog.com/references for more options. Rev. E | Page 61 of 66

AD5560 Data Sheet POWER SUPPLY DECOUPLING Digital lines running under the device should be avoided because these couple noise onto the device. The analog ground plane In any circuit where accuracy is important, careful consid- should be allowed to run under the AD5560 to avoid noise eration of the power supply and ground return layout helps coupling. The power supply lines of the AD5560 should use as to ensure the rated performance. The printed circuit board large a trace as possible to provide low impedance paths and on which the AD5560 is mounted should be designed so that reduce the effects of glitches on the power supply line. Fast the analog and digital sections are separated and confined to switching digital signals should be shielded with digital ground certain areas of the board. If the AD5560 is in a system where to avoid radiating noise to other parts of the board and should multiple devices require an AGND-to-DGND connection, the never be run near the reference inputs. It is essential to connection should be made at one point only. The star ground minimize noise on all VREF lines. Avoid crossover of digital point should be established as close as possible to the device. and analog signals. Traces on opposite sides of the board The DGND connection in the AD5560 should be treated as should run at right angles to each other. This reduces the effects AGND and returned to the AGND plane. For more detail on of feedthrough throughout the board. As is the case for all thin decoupling for mixed signal applications, refer to Analog packages, care must be taken to avoid flexing the package and Devices Tutorial MT 031. to avoid a point load on the surface of this package during the For supplies with multiple pins (AV , AV , DV ), it is SS DD CC assembly process. recommended to tie these pins together and to decouple Also note that the exposed paddle of the AD5560 is internally each supply once. connected to the negative supply AV . SS The AD5560 should have ample supply decoupling of 10 µF in parallel with 0.1 µF on each supply located as close to the part as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESL), such as the common ceramic capaci- tors that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Rev. E | Page 62 of 66

Data Sheet AD5560 APPLICATIONS INFORMATION THERMAL CONSIDERATIONS Table 28. Thermal Resistance for TQFP_EP1 θ 4 θ θ JC (Local) JC (Local) JCP Cooling Airflow (LFPM) θ 2 θ 3 Ideal TIM6 w/TIM6 w/TIM5 Unit JA JC (Uniform) No Heat Sink 0 39 N/A °C/W 200 37.2 °C/W 500 35.7 °C/W Heat Sink7 0 12.2 N/A °C/W 200 11.1 1.0 2.8 4.91 °C/W 500 9.5 °C/W Cold Plate8 N/A N/A 1.0 2.8 4.91 7.5 °C/W 1 All numbers are simulated and assume a JEDEC 4-layer test board. 2 θ is the thermal resistance from hottest junction to ambient air. JA 3 θ is the thermal resistance from junction to the package top, assuming total power is uniformly distributed. JC(Uniform) 4 θ is the thermal resistance from junction to the center of package top, assuming total power = 8.5 W (1 W uniformly distributed, 7.5 W in power stages—local JC (Local) heating). 5 θ is the thermal resistance from hottest junction to infinite cold plate with consideration of thermal interface material (TIM). JCP 6 Ideal TIM is assuming top of package in perfect contact with an infinite cold plate. w/TIM is assuming TIM is 0.5 mm thick, with thermal conductivity of 2.56 W/m/k. 7 Heat sink with a rated performance of θ ~5.3°C/W under forced convection, gives ~T = 111°C at 500 LFM. Thermal performance of the package depends on the heat CA J sink and environmental conditions. 8 Attached infinite cold plate should be ≤26°C to maintain T < 90°C, given total power = 8.5 W. Thermal performance of the package depends on the heat sink and J environmental conditions. 9 To estimate junction temperature, the following equations can be used: T = T + θ × Power J amb JA T = T + θ × Power J cold plate JCP T = T + θ × Power J top JC Table 29. Thermal Resistance for Flip Chip BGA1 θ 4 θ θ 5 JC (Local) JC (Local) JCP Cooling Airflow (LFPM) θ 2 θ 3 Ideal TIM6 w/TIM6 w/TIM Unit JA JC (Uniform) No Heat Sink 0 40.8 N/A °C/W 200 38.1 °C/W 500 36 °C/W Heat Sink8 0 18 N/A °C/W 200 11.8 0.05 1.6 4.6 °C/W 500 9 °C/W Cold Plate9 N/A N/A 0.05 1.6 4.6 6.5 °C/W 1 All numbers are simulated and assume a JEDEC 4-layer test board. 2 θ is the thermal resistance from hottest junction to ambient air. JA 3 θ is the thermal resistance from junction to the package top, assuming total power is uniformly distributed. JC (Uniform) 4 θ is the thermal resistance from junction to the center of package top, assuming total power = 8.5 W (1 W uniformly distributed, 7.5 W in power stages—local JC (Local) heating). 5 θ is the thermal resistance from hottest junction to infinite cold plate with consideration of thermal interface material (TIM). JCP 6 Ideal TIM is assuming top of package in perfect contact with an infinite cold plate. w/TIM is assuming TIM is 0.4 mm thick, with thermal conductivity of 3.57 W/m/k. 7 Heat sink with a rated performance of θ ~4.9°C/W under forced convection, gives ~T = 112°C at 500 LFM. Thermal performance of the package depends on the heat CA J sink and environmental conditions. 8 Attached infinite cold plate should be ≤30°C to maintain T < 90°C, given total power = 8.5 W. Thermal performance of the package depends on the heat sink and J environmental conditions. 9 To estimate junction temperature, the following equations can be used: T = T + θ × Power J amb JA T = T + θ × Power J cold plate JCP T = T + θ × Power J top JC Rev. E | Page 63 of 66

AD5560 Data Sheet TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package Due to localized heating, temperature at the top surface of Due to localized heating, temperature at the top surface of the package has steep gradient. Thus, the θJC value is highly the package has steep gradient. Thus, the θJC value is highly dependent on where the case temperature is measured. dependent on where the case temperature is measured. Figure 62 shows the top of the die temperature contour map Figure 63 shows the top of the die temperature contour map for the TQFP_EP. for the flip chip BGA. 07779-064 Figure 62. Temperature Contour Map for 64-Lead TQFP_EP 07779-065 Figure 63. Temperature Contour Map for the Flip Chip BGA Rev. E | Page 64 of 66

Data Sheet AD5560 OUTLINE DIMENSIONS 1.20 0.675 12.20 MAX 12.00 SQ 0.75 0.872 5.95 BSC 11.80 0.60 0.45 64 49 49 64 1.00 REF 1 48 48 1 SEATING PLANE 10.20 5.95 EXPPOADSED B7.S8C5 1 90..8000 SQ BSC TOP VIEW (PINS DOWN) 1.05 BOTTOM VIEW 1.00 0.20 16 33 33 (PINS UP) 16 0.95 0.09 17 32 32 17 0.15 7° VIEW A B7.S8C5 0.27 0.05 COPLANAR0I.T0Y8 30.5°° FTOHER EPXRPOOPSEERD C POANDN, ERCETFIEORN TOOF LEABD0.S 5PC0ITCH 00..2127 THE PIN CONFIGURATION AND ROTAVTIEEDW 9 0A° CCW COMPLIANTTO JEDECFS UESNCTCTAITNOIDONAN OR DFDE STS HMCISSR -ID0P2AT6TI-OAAN CSSDH-EHEUT. 10-19-2011-C Figure 64. 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-64-3) Dimensions shown in millimeters 8.10 8.00 SQ 7.90 5.720 REF A1 BALL 0.40 REF A1 BALL CORNER (DIE OFFSET) CORNER 9 8 7 6 5 4 3 2 1 A B C 6.40 6.865 REF BSC SQ D E F 0.80 G BSC H J TOP VIEW 0.80 BOTTOM VIEW REF *1.20 DETAIL A 0.81 1.08 DETAIL A 0.76 1.00 R0.E3F6 0.71 0.39 0.34 0.29 0.50 COPLANARITY 0.45 0.12 SEATING 0.40 PLANE BALL DIAMETER *CEXOCMEPPLTIAIONNT TTOO PJAEDCEKCA GSET AHNEDIGAHRTD.S MO-225 WITH 04-19-2012-B Figure 65. 72-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-72-2) Dimensions shown in millimeters Rev. E | Page 65 of 66

AD5560 Data Sheet ORDERING GUIDE Model1 Temperature Range2 Package Description Package Option AD5560JSVUZ T = 25°C to +90oC 64-Lead Thin Quad Flat Pack with Exposed Pad (TQFP_EP) SV-64-3 J AD5560JSVUZ-REEL T = 25°C to +90oC 64-Lead Thin Quad Flat Pack with Exposed Pad (TQFP_EP) SV-64-3 J AD5560JBCZ T = 25°C to +90oC 72-Ball Chip Scale Package Ball Grid Array (CSP-BGA) BC-72-2 J AD5560JBCZ-REEL T = 25°C to +90oC 72-Ball Chip Scale Package Ball Grid Array (CSP-BGA) BC-72-2 J EVAL-AD5560EBUZ Evaluation Kit 1 Z = RoHS Compliant Part. 2 TJ = junction temperature. ©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07779-0-5/16(E) Rev. E | Page 66 of 66

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5560JBCZ-REEL AD5560JSVUZ-REEL AD5560JBCZ EVAL-AD5560EBUZ AD5560JSVUZ