2.7 V to 5.5 V, Serial-Input, Voltage-Output, 14-Bit DACs AD5551/AD5552 FEATURES FUNCTIONAL BLOCK DIAGRAMS Full 14-bit performance VDD 8 3 V and 5 V single supply operation AD5551 Low 0.625 mW power dissipation VREF 3 14-BIT DAC 1 VOUT 1 μs settling time 2 AGND Unbuffered voltage output capable of driving 60 kΩ loads directly CS 4 14-BIT DATA LATCH SPI/QSPI/MICROWIRE-compatible interface standards DIN 6 CONTROL LOGIC Power-on reset clears DAC output to 0 V (unipolar mode) SCLK 5 SERIAL INPUT REGISITER 5 kV HBM ESD classification APPLICATIONS DG7ND 01943-001 Digital gain and offset adjustment Figure 1. Automatic test equipment VDD Data acquisition systems 14 Industrial process control AD5552 RFB 1 RFB RINV 13 INV VREFF 6 GENERAL DESCRIPTION 14-BIT DAC 2 VOUT The AD5551/AD5552 are single, 14-bit, serial-input, voltage- VREFS 5 3 AGNDF output DACs that operate from a single 2.7 V to 5.5 V supply. The DAC output range extends from 0 V to VREF. CS 7 14-BIT DATA LATCH These DACs provide 14-bit performance without any adjust- LSDCALCK 181 COLNOTGRICOL 4 AGNDS ments. The DAC output is unbuffered, which reduces power DIN 10 SERIAL INPUT REGISITER cWonitshu amnp etxiotenr nanald o opf fasmetp e,r trhoer sA cDon5t5r5ib2u ctaend bbey oapne orauttepdu ti nb uffer. DG12ND 01943-002 Figure 2. bipolar mode generating a ±V output swing. The AD5552 REF also includes Kelvin sense connections for the reference and PRODUCT HIGHLIGHTS analog ground pins to reduce layout sensitivity. For higher precision applications, refer to 16-bit DACs AD5541, AD5542, 1. Single Supply Operation. and AD5544. The AD5551 and AD5552 are fully specified and The AD5551/AD5552 utilize a versatile 3-wire interface that is guaranteed for a single 2.7 V to 5.5 V supply. compatible with SPI, QSPI™, MICROWIRE™, and DSP interface 2. Low Power Consumption. standards. The AD5551 and AD5552 are available in 8-lead and Typically 0.625 mW with a 5 V supply. 14-lead SOIC packages. 3. 3-Wire Serial Interface. 4. Unbuffered output capable of driving 60 kΩ loads, which reduces power consumption as there is no internal buffer to drive. 5. Power-On Reset Circuitry. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2000–2010 Analog Devices, Inc. All rights reserved.

AD5551/AD5552 TABLE OF CONTENTS Features .............................................................................................. 1 Bipolar Output Operation ......................................................... 12 Applications ....................................................................................... 1 Output Amplifier Selection ....................................................... 12 General Description ......................................................................... 1 Force Sense Buffer Amplifier Selection ................................... 12 Functional Block Diagrams ............................................................. 1 Reference and Ground ............................................................... 13 Product Highlights ........................................................................... 1 Power-On Reset .......................................................................... 13 Revision History ............................................................................... 2 Power Supply and Reference Bypassing .................................. 13 Specifications ..................................................................................... 3 Microprocessor Interfacing ........................................................... 14 Timing Characteristics ................................................................ 4 ADSP-21xx to AD5551/AD5552 Interface ............................. 14 Absolute Maximum Ratings ............................................................ 5 68HC11 to AD5551/AD5552 Interface ................................... 14 ESD Caution .................................................................................. 5 MICROWIRE to AD5551/AD5552 Interface ........................ 14 Pin Configurations and Function Descriptions ........................... 6 80C51/80L51 to AD5551/AD5552 Interface .......................... 14 Typical Performance Characteristics ............................................. 7 Applications Information .............................................................. 15 Terminology .................................................................................... 10 Optocoupler Interface ................................................................ 15 Theory of Operation ...................................................................... 11 Decoding Multiple AD5551/AD5552s .................................... 15 Digital-to-Analog Section ......................................................... 11 Outline Dimensions ....................................................................... 16 Serial Interface ............................................................................ 11 Ordering Guide .......................................................................... 16 Unipolar Output Operation ...................................................... 11 REVISION HISTORY 5/10—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Data Sheet Title, Features Section, General Description Section, and Product Highlights Section ................. 1 Changes to Specifications Section .................................................. 3 Changes to Table 3 ............................................................................ 5 Changes to Pin V Description in Table 4 and Table 5 ............. 6 DD Changes to Typical Performance Characteristics Section ........... 7 Changes to First Paragraph in Theory of Operation Section ... 11 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 16 7/00—Revision 0: Initial Version Rev. A | Page 2 of 16

AD5551/AD5552 SPECIFICATIONS V = 2.7 V to 5.5 V, 2.5 V ≤ V ≤ V , AGND = DGND = 0 V. All specifications T = T to T , unless otherwise noted. DD REF DD A MIN MAX Table 1. Parameter1 Min Typ Max Unit Test Condition STATIC PERFORMANCE Resolution 14 Bits Relative Accuracy, INL ±0.15 ±1.0 LSB B grade Differential Nonlinearity ±0.15 ±0.8 LSB Guaranteed monotonic Gain Error −1.5 −0.3 +0.5 LSB Gain Error Temperature Coefficient ±0.1 ppm/°C Zero-Code Error 0.1 ±1 LSB Zero-Code Temperature Coefficient ±0.05 ppm/°C AD5552 Bipolar Resistor Matching 1.000 Ω/Ω RFB/RINV, typically RFB = RINV = 28 kΩ ±0.0015 ±0.0152 % Ratio error Bipolar Zero Offset Error ±0.25 ±1 LSB Bipolar Zero Temperature Coefficient ±0.2 ppm/°C Bipolar Zero-Code Error −0.3 ±1.2 LSB Bipolar Gain Error −0.3 ±1.2 LSB OUTPUT CHARACTERISTICS2 Output Voltage Range 0 V − 1 LSB V Unipolar operation REF −V V − 1 LSB V AD5552 bipolar operation REF REF Output Voltage Settling Time 1 μs To ½ LSB of FS, C = 10 pF L Slew Rate 17 V/μs C = 10 pF, measured from 0% to 63% L Digital-to-Analog Glitch Impulse 1.1 nV-sec 1 LSB change around the major carry Digital Feedthrough 0.2 nV-sec All 1s loaded to DAC, V = 2.5 V REF DAC Output Impedance 6.25 kΩ Tolerance typically 20% Power Supply Rejection Ratio ±1.0 LSB ΔV ± 10% DD DAC REFERENCE INPUT Reference Input Range 2.0 V V DD Reference Input Resistance3 9 kΩ Unipolar operation 7.5 kΩ AD5552, bipolar operation LOGIC INPUTS Input Current ±1 μA V , Input Low Voltage 0.8 V INL V , Input High Voltage 2.4 V INH Input Capacitance2 10 pF Hysteresis Voltage2 0.15 V REFERENCE2 Reference −3 dB Bandwidth 2.2 MHz All 1s loaded Reference Feedthrough 1 mV p-p All 0s loaded, V = 1 V p-p at 100 kHz REF Signal-to-Noise Ratio 92 dB Reference Input Capacitance 26 pF Code 0000 H 26 pF Code 3FFF H POWER REQUIREMENTS Digital inputs at rails V 2.7 5.5 V DD IDD 125 150 μA Power Dissipation 0.625 0.825 mW 1 Temperature range is as follows: B version: −40°C to +85°C; 2 Guaranteed by design, not subject to production test. 3 Reference input resistance is code-dependent, minimum at 2555H. Rev. A | Page 3 of 16

AD5551/AD5552 TIMING CHARACTERISTICS V = 2.7 V to 5.5 V, 2.5 V ≤ V ≤ 5.5 V, AGND = DGND = 0 V. All specifications −40°C ≤ T ≤ +85°C, unless otherwise noted. DD REF A Table 2. Limit at T , T MIN MAX Parameter1, 2 All Versions Unit Description f 25 MHz max SCLK cycle frequency SCLK t 40 ns min SCLK cycle time 1 t 20 ns min SCLK high time 2 t 20 ns min SCLK low time 3 t 15 ns min CS low to SCLK high setup 4 t 15 ns min CS high to SCLK high setup 5 t 35 ns min SCLK high to CS low hold time 6 t 20 ns min SCLK high to CS high hold time 7 t 15 ns min Data setup time 8 t 0 ns min Data hold time 9 t 30 ns min LDAC pulse width 10 t 30 ns min CS high to LDAC low setup 11 t 30 ns min CS high time between active periods 12 1 Guaranteed by design, not production tested. 2 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90% of +3 V and timed from a voltage level of +1.6 V). t 1 SCLK t6 t2 t3 t5 t4 t7 CS t 12 t 8 t 9 DIN DB13 DB0 t 11 t 10 LDAC* *AD5552 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED. 01943-003 Figure 3. Timing Diagram Rev. A | Page 4 of 16

AD5551/AD5552 ABSOLUTE MAXIMUM RATINGS T = 25°C unless otherwise noted A Stresses above those listed under Absolute Maximum Ratings Table 3. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any VDD to AGND –0.3 V to +6 V other conditions above those listed in the operational sections Digital Input Voltage to DGND –0.3 V to VDD + 0.3 V of this specification is not implied. Exposure to absolute VOUT to AGND –0.3 V to VDD + 0.3 V maximum rating conditions for extended periods may affect AGND, AGNDF, AGNDS to DGND –0.3 V to +0.3 V device reliability. Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range Industrial (B Version) −40°C to +85°C ESD CAUTION Storage Temperature Range −65°C to +150°C Maximum Junction Temperature, (T max) 150°C J Package Power Dissipation (T max – T )/θ J A JA Thermal Impedance θ JA SOIC (R-8) 149.5°C/W SOIC (R-14) 104.5°C/W Lead Temperature, Soldering Peak Temperature1 260°C ESD2 5 kV 1 As per JEDEC Standard 20. 2 HBM classification. Rev. A | Page 5 of 16

AD5551/AD5552 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS RFB 1 14 VDD VOUT 2 13 INV AGNDF 3 AD5552 12 DGND AGNDS 4 TOP VIEW 11 LDAC (Not to Scale) VOUT 1 8 VDD VREFS 5 10 DIN AGND 2 AD5551 7 DGND VREFF 6 9 NC VRCESF 34 (NToOt Pto V SIEcaWle) 65 DSCINLK 01943-004 CS N7C = NO CONNECN8T SCLK 01943-005 Figure 4. AD5551 Pin Configuration Figure 5. AD5552 Pin Configuration Table 4. AD5551 Pin Function Descriptions Pin No. Mnemonic Description 1 V Analog Output Voltage from the DAC. OUT 2 AGND Ground Reference Point for Analog Circuitry. 3 V This is the voltage reference input for the DAC. Connect to external reference ranges from 2 V to V . REF DD 4 CS This is an active low-logic input signal. The chip select signal is used to frame the serial data input. 5 SCLK Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. 6 DIN Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK. 7 DGND Digital Ground. Ground reference for digital circuitry. 8 V Analog Supply Voltage, 2.7 V to 5.5 V ± 10%. DD Table 5. AD5552 Pin Function Descriptions Pin No. Mnemonic Description 1 RFB Feedback Resistor. In bipolar mode, connect this pin to external op amp output. 2 V Analog Output Voltage from the DAC. OUT 3 AGNDF Ground Reference Point for Analog Circuitry (Force). 4 AGNDS Ground Reference Point for Analog Circuitry (Sense). 5 V This is the voltage reference input (sense) for the DAC. Connect to external reference ranges from 2 V to V . REFS DD 6 V This is the voltage reference input (force) for the DAC. Connect to external reference ranges from 2 V to V . REFF DD 7 CS This is an active low-logic input signal. The chip select signal is used to frame the serial data input. 8 SCLK Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. 9 NC No Connect. 10 DIN Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK. 11 LDAC LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the input register. 12 DGND Digital Ground. Ground reference for digital circuitry. 13 INV Connected to the internal scaling resistors of the DAC. Connect the INV pin to external op amps inverting input in bipolar mode. 14 V Analog Supply Voltage, 2.7 V to 5.5 V ± 10%. DD Rev. A | Page 6 of 16

AD5551/AD5552 TYPICAL PERFORMANCE CHARACTERISTICS 0.125 0.125 VDD = 5V VDD = 5V VREF = 2.5V B) VREF = 2.5V TY (LSB) 0.062 RITY (LS 0.062 NEARI 0 LINEA NONLI–0.062 L NON 0 AL TIA R N INTEG–0.125 DIFFERE–0.062 –0.187 –0.125 0 8192 16,384 24,576 3C2O,7D6E8 40,960 49,152 57,344 65,536 01943-006 0 8192 16,384 24,576 3C2O,7D6E8 40,960 49,152 57,344 65,536 01943-009 Figure 6. Integral Nonlinearity vs. Code Figure 9. Differential Nonlinearity vs. Code 0.062 0.187 VDD = 5V VDD = 5V VREF = 2.5V B) VREF = 2.5V TY (LSB) 0 RITY (LS 0.125 NEARI–0.062 LINEA 0.062 NONLI–0.125 L NON 0 AL TIA R N INTEG–0.187 DIFFERE–0.062 –0.250 –0.125 –60 –40 –20 0 TEM20PERA4T0URE6 (0°C) 80 100 120 140 01943-007 –60 –40 –20 0 TEM20PERA4T0URE6 (0°C) 80 100 120 140 01943-010 Figure 7. Integral Nonlinearity vs. Temperature Figure 10. Differential Nonlinearity vs. Temperature 0.125 0.187 VREF = 2.5V VDD = 5V TA = 25°C TA = 25°C 0.062 0.125 B) DNL B) DNL S S L L R ( 0 R ( 0.062 O O R R R R E E Y Y RIT–0.062 RIT 0 A A E E INL N N LI LI –0.125 –0.062 INL –0.187 –0.125 2 3 SUPP4LY VOLTAG5E (V) 6 7 01943-008 0 1 RE2FERENCE 3VOLTAGE4 (V) 5 6 01943-011 Figure 8. Linearity Error vs. Supply Voltage Figure 11. Linearity Error vs. Reference Voltage Rev. A | Page 7 of 16

AD5551/AD5552 0 0.037 VDD = 5V VDD = 5V –0.025 VTAR E=F 2=5 °2C.5V 0.025 TVAR E=F 2=5 °2C.5V –0.050 B) S SB)–0.075 R (L 0.012 ERROR (L––00..110205 DE ERRO 0 GAIN –0.150 RO-CO–0.012 E –0.175 Z –0.025 –0.200 –0.225 –40 TEMPERA25TURE (°C) 85 01943-012 –0.037 –40 TEMPERA25TURE (°C) 85 01943-015 Figure 12. Gain Error vs. Temperature Figure 15. Zero-Code Offset Error vs. Temperature 132 2.0 VVDRDEF = = 5 2V.5V TA = 25°C 130 TA = 25°C 128 1.5 A) A) REFERENCE VOLTAGE NT (µ 126 NT (µ VDD = 5V E E R R UR 124 UR 1.0 SUPPLY VOLTAGE Y C Y C VREF = 2.5V PL 122 PL P P U U S 120 S 0.5 118 116 –40 TEMPERA25TURE (°C) 85 01943-013 00 1 2 VOLTA3GE (V) 4 5 6 01943-016 Figure 13. Supply Current vs. Temperature Figure 16. Supply Current vs. Reference Voltage or Supply Voltage 200 200 VDD = 5V 180 VREF = 2.5V TA = 25°C 160 A) 150 T (µV) 140 NT (µ N 120 E E R R R UR 100 CU 100 C E LY 80 NC P E P R U 60 E S F E 50 40 R 20 0 1 2 3 4 5 6DI7GIT8AL9 IN1P0U1T1 V1O2L1T3A1G4E1 5(V1)61718192021 01943-014 00 10,000 20,000 C3O0,D00E0 (De4c0i,m00a0l) 50,000 60,000 70,000 01943-017 Figure 14. Supply Current vs. Digital Input Voltage Figure 17. Reference Current vs. Code Rev. A | Page 8 of 16

AD5551/AD5552 VREF = 2.5V 2µs/DIV VREF = 2.5V VDD = 5V VDD = 5V TA = 25°C TA = 25°C CS (5V/DIV) DIN (5V/DIV) 10pF 50pF 100pF 200pF VOUT (50mV/DIV) 2µs/DIV 01943-018 VOUT (0.5V/DIV) 01943-020 Figure 18. Digital Feedthrough Figure 20. Large Signal Settling Time 1.236 5 VREF = 2.5V 1.234 CS 0 TVAD D= =2 55°VC VOUT (1V/DIV) –5 V) 1.232 E ( V) G E ( –10 TA AG1.230 OL T V OL –15 AL V1.228 GIT GVOAUINT (=5 0–m21V6/DIV) VOUT –20 DI 1.226 –25 1.224 –30 0.5µs/DIV 01943-021 –0.5 0 0.5TIME (ns)1.0 1.5 2.0 01943-019 Figure 19. Digital-to-Analog Glitch Impulse Figure 21. Small Signal Settling Time Rev. A | Page 9 of 16

AD5551/AD5552 TERMINOLOGY Digital-to-Analog Glitch Impulse Relative Accuracy Digital-to-analog glitch impulse is the impulse injected into the For the DAC, relative accuracy or integral nonlinearity (INL) is analog output when the input code in the DAC register changes a measure of the maximum deviation, in LSBs, from a straight state. It is normally specified as the area of the glitch in nV-sec line passing through the endpoints of the DAC transfer function. and is measured when the digital input code is changed by A typical INL vs. code plot can be seen in Figure 6. 1 LSB at the major carry transition. A plot of the glitch impulse Differential Nonlinearity is shown in Figure 19. Differential nonlinearity is the difference between the measured Digital Feedthrough change and the ideal 1 LSB change between any two adjacent Digital feedthrough is a measure of the impulse injected into the codes. A specified differential nonlinearity of ±1 LSB maximum analog output of the DAC from the digital inputs of the DAC, ensures monotonicity. A typical DNL vs. code plot can be seen but is measured when the DAC output is not updated. CS is in Figure 9. held high, while the CLK and DIN signals are toggled. It is Gain Error specified in nV-sec and is measured with a full-scale code change Gain error is the difference between the actual and ideal analog on the data bus, that is, from all 0s to all 1s and vice versa. A output range, expressed as a percent of the full-scale range. It typical plot of digital feedthrough is shown in Figure 18. is the deviation in slope of the DAC transfer characteristic Power Supply Rejection Ratio from ideal. This specification indicates how the output of the DAC is Gain Error Temperature Coefficient affected by changes in the power supply voltage. Power-supply This is a measure of the change in gain error with changes in rejection ratio is quoted in terms of % change in output per % temperature. It is expressed in ppm/°C. change in V for full-scale output of the DAC. V is varied DD DD Zero-Code Error by ±10%. Zero code error is a measure of the output error when zero code Reference Feedthrough is loaded to the DAC register. This is a measure of the feedthrough from the V input to the REF Zero-Code Temperature Coefficient DAC output when the DAC is loaded with all 0s. A 100 kHz, This is a measure of the change in zero code error with a change 1 V p-p is applied to V . Reference feedthrough is expressed REF in temperature. It is expressed in mV/°C. in mV p-p. Rev. A | Page 10 of 16

AD5551/AD5552 THEORY OF OPERATION The AD5551/AD5552 are single, 14-bit, serial input, voltage SERIAL INTERFACE output DACs. They operate from a single supply ranging from The AD5551/AD5552 are controlled by a versatile 3-wire serial 2.7 V to 5.5 V and consume typically 125 μA with a supply of interface, which operates at clock rates up to 25 MHz and is 5 V. Data is written to these devices in a 14-bit word format, via compatible with SPI, QSPI, MICROWIRE, and DSP interface a 3-or 4-wire serial interface. To ensure a known power-up standards. The timing diagram can be seen in Figure 3. Input state, these parts were designed with a power-on reset function. data is framed by the chip select input, CS. After a high-to-low In unipolar mode, the output is reset to 0 V, while in bipolar transition on CS, data is shifted synchronously and latched into mode, the AD5552 output is set to −V . Kelvin sense REF the input register on the rising edge of the serial clock, SCLK. connections for the reference and analog ground are included Data is loaded MSB first in 14-bit words. After 14 data bits on the AD5552. have been loaded into the serial input register, a low-to-high DIGITAL-TO-ANALOG SECTION transition on CS transfers the contents of the shift register to The DAC architecture consists of two matched DAC sections. the DAC. Data can only be loaded to the part while CS is low. A simplified circuit diagram is shown in Figure 22. The DAC The AD5552 has an LDAC function that allows the DAC latch architecture of the AD5551/AD5552 is segmented. The four to be updated asynchronously by bringing LDAC low after CS MSBs of the 14-bit data word are decoded to drive 15 switches, goes high. LDAC should be maintained high while data is E1 to E15. Each of these switches connects one of 15 matched written to the shift register. Alternatively, LDAC may be tied resistors to either AGND or V . The remaining 10 bits of the REF permanently low to update the DAC synchronously. With data word drive switches S0 to S9 of a 10-bit voltage mode R-2R LDAC tied permanently low, the rising edge of CS loads ladder network. the data to the DAC. R R VOUT UNIPOLAR OUTPUT OPERATION 2R 2R 2R . . . . . 2R 2R 2R . . . . . 2R These DACs are capable of driving unbuffered loads of 60 kΩ. Unbuffered operation results in low-supply current, typically S0 S1 . . . . . S9 E1 E2 . . . . . E15 300 μA, and a low-offset error. The AD5551 provides a unipolar VREF output swing ranging from 0 V to V . The AD5552 can be con- REF figured to output both unipolar and bipolar voltages. Figure 23 10-BIT R-2R LADDER INTFOO U15R EMQSUBAsL D SEECGOMDEENDTS 01943-022 shows a typical unipolar output voltage circuit. The code table Figure 22. DAC Architecture for this mode of operation is shown in Table 6. 5V 2.5V With this type of DAC configuration, the output impedance 10µF is independent of code, while the input impedance seen by + 0.1µF 0.1µF the reference is heavily code dependent. The output voltage is dependent on the reference voltage as shown in the following SERIAL equation: INTERFACE VDD VREFF* VREFS* CS AD820/ V =VREF ×D DIN AD5551/ VOUT OP196 UONUIPTOPLUATR OUT 2N SCLK AD5552 LDAC* EXTERNAL where: DGND AGND OP AMP DN iiss tthhee rdeescoimlutailo dna otaf twhoer Dd AloCa.d ed to the DAC register. *AD5552 ONLY. 01943-023 Figure 23. Unipolar Output For a reference of 2.5 V, the equation simplifies to the following, Table 6. Unipolar Code Table 2.5×D V = DAC Latch Contents OUT 16,384 MSB LSB Analog Output This gives a VOUT of 1.25 V with midscale loaded, and a VOUT 11 1111 1111 1111 VREF × (16,383/16,384) of 2.5 V with full-scale loaded to the DAC. The LSB size is 10 0000 0000 0000 V × (8192/16,384) = ½ V REF REF VREF/16,384. 00 0000 0000 0001 VREF × (1/16,384) 00 0000 0000 0000 0 V Rev. A | Page 11 of 16

AD5551/AD5552 Assuming a perfect reference, the worst-case output voltage Assuming a perfect reference, the worst-case bipolar output may be calculated from the following equation: voltage may be calculated from the following equation. D ( ) [(V +V )(2+RD)−V (1+RD) V = × V +V +V +INL V = OUT−UNI OS REF OUT−UNI 214 REF GE ZSE OUT−BIP 1+(2+RD)/A where: where: V is the unipolar mode worst-case output. OUT–UNI V is the external op amp input offset voltage. OS D is the decimal code loaded to the DAC. RD is the R and R resistor matching error, unitless. FB IN V is the reference voltage applied to part. REF A is the op amp open-loop gain. V is the gain error in volts. GE OUTPUT AMPLIFIER SELECTION V is the zero-scale error in volts. ZSE INL is the integral nonlinearity in volts. For bipolar mode, use a precision amplifier, supplied from a dual power supply. This provides the ±V output. In a single- BIPOLAR OUTPUT OPERATION REF supply application, selection of a suitable op amp may be more With the aid of an external op amp, the AD5552 may be confi- difficult as the output swing of the amplifier does not usually gured to provide a bipolar voltage output. A typical circuit of include the negative rail, in this case AGND. This can result in such operation is shown in Figure 24. The matched bipolar some degradation of the specified performance unless the offset resistors R and R are connected to an external op amp FB INV application does not use codes near zero. to achieve this bipolar output swing where R = R = 28 kΩ. FB INV The selected op amp needs to have a very low-offset voltage, Table 7 shows the transfer function for this output operating (the DAC LSB is 152 μV with a 2.5 V reference), to eliminate mode. Also provided on the AD5552 are a set of Kelvin the need for output offset trims. Input bias current should also connections to the analog ground inputs. be very low as the bias current multiplied by the DAC output 5V 2.5V impedance (approximately 6K) adds to the zero-code error. 10µF + Rail-to-rail input and output performance is required. For fast 0.1µF 0.1µF settling, the slew rate of the op amp should not impede the RFB +5V settling time of the DAC. Output impedance of the DAC is INTSEERRFIAALCE VDD VREFF VREFS RFB INV constant and code-independent, but to minimize gain errors, CS RINV EXOTPE ARMNAPL the input impedance of the output amplifier should be as high DIN AD5552 VOUT UONUIPTOPLUATR as possible. The amplifier should also have a 3 dB bandwidth of SCLK 1 MHz or greater. The amplifier adds another time constant to –5V LDAC DGND AGNDF AGNDS 01943-024 tAh eh isgyhsteerm 3, dtBhe armefoprlief iienrc breaansdinwgid tthhe rseestutllitns gi nti am fea sotfe rth eef foeucttipvuet . Figure 24. Bipolar Output (AD5552 Only) settling time of the combined DAC and amplifier. FORCE SENSE BUFFER AMPLIFIER SELECTION Table 7. Bipolar Code Table DAC Latch Contents These amplifiers can be single-supply or dual supplies, low MSB LSB Analog Output noise amplifiers. A low-output impedance at high frequencies 11 1111 1111 1111 +V × (8191/8192) is preferred as they need to be able to handle dynamic currents REF 10 0000 0000 0000 +V × (1/8192) of up to ±20 mA. REF 00 0000 0000 0001 0 V 00 0000 0000 0000 −V × (1/8192) REF 00 0000 0000 0000 −V × (8191/8192) = –V REF REF Rev. A | Page 12 of 16

AD5551/AD5552 REFERENCE AND GROUND POWER-ON RESET As the input impedance is code-dependent, the reference pin These parts have a power-on reset function to ensure the output should be driven from a low-impedance source. The AD5551/ is at a known state upon power-up. After power-up, the DAC AD5552 operate with a voltage reference ranging from 2 V to register contains all zeros, until data is loaded from the serial V . Although DAC’s full-scale output voltage is determined by register. However, the serial register is not cleared on power-up, DD the reference, references below 2 V results in reduced accuracy. so its contents are undefined. When loading data initially to the Table 6 and Table 7 outline the analog output voltage for DAC, 14 bits or more should be loaded to prevent erroneous particular digital codes. For optimum performance, Kelvin data appearing on the output. If more than 14 bits are loaded, sense connections are provided on the AD5552. only the last 14 are kept, and if fewer than 14 are loaded, bits remain from the previous word. If the AD5551/AD5552 needs If the application does not require separate force and sense to be interfaced with data shorter than 14 bits, the data should lines, they should be tied together close to the package to be padded with zeros at the LSBs. minimize voltage drops between the package leads and the internal die. ADR291 and ADR293 are suitable references POWER SUPPLY AND REFERENCE BYPASSING for this product. For accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed with a 10 μF tantalum capacitor in parallel with a 0.1 μF ceramic capacitor. Rev. A | Page 13 of 16

AD5551/AD5552 MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5551/AD5552 is via a MICROWIRE TO AD5551/AD5552 INTERFACE serial bus that uses standard protocol compatible with DSP Figure 27 shows an interface between the AD5551/AD5552 and processors and microcontrollers. The communications channel any MICROWIRE-compatible device. Serial data is shifted out requires a 3-wire interface consisting of a clock signal, a data on the falling edge of the serial clock and into the AD5551/ signal and a synchronization signal. The AD5551/AD5552 AD5552 on the rising edge of the serial clock. No glue logic is require a 14-bit data word with data valid on the rising edge of required as the DAC clocks data into the input shift register on SCLK. The DAC update may be done automatically when all the rising edge. the data is clocked in or it may be done under control of LDAC (AD5552 only). MICROWIRE* AD5551/ AD5552* CS CS ADSP-21xx TO AD5551/AD5552 INTERFACE SO DIN Figure 25 shows a serial interface between the AD5551/AD5552 SCLK SCLK athned S tPhOe ARTD S(sPe-r2i1alx px.o Trth) et rAanDsSmPi-t2 a1lxtexr snhaoteu lfdra bme isnegt mtoo odpee.r Tathee i n *ADDITIONAL PINS OMITTED FOR CLARITY. 01943-027 Figure 27. MICROWIRE to AD5551/AD5552 Interface ADSP-21xx is programmed through the SPORT control register 80C51/80L51 TO AD5551/AD5552 INTERFACE and should be configured as follows: internal clock operation, active low framing, 16-bit word length. The first 2 bits are don’t A serial interface between the AD5551/AD5552 and the 80C51/ care as AD5551/AD5552 keeps the last 14 bits. Transmission is 80L51 microcontroller is shown in Figure 28. TxD of the micro- initiated by writing a word to the Tx register after the SPORT controller drives the SCLK of the AD5551/AD5552, while RxD has been enabled. Because of the edges-triggered difference, an drives the serial data line of the DAC. P3.3 is a bit programmable inverter is required at the SCLKs between the DSP and the DAC. pin on the serial port which is used to drive CS. ADSP-21xx* AD5551/ 80C51/ AD5551/ AD5552* 80L51* AD5552* FO LDAC** P3.4 LDAC** TFS CS P3.3 CS DT DIN RxD DIN SCLK SCLK TxD SCLK **A*ADDD5I5T5IO2 NOANLL YP.INS OMITTED FOR CLARITY. 01943-025 **A*ADDD5I5T5IO2 NOANLL YP.INS OMITTED FOR CLARITY. 01943-028 Figure 25. ADSP-21xx to AD5551/AD5552 Interface Figure 28. 80C51/80L51 to AD5551/AD5552 Interface 68HC11 TO AD5551/AD5552 INTERFACE The 80C51/80L51 provides the LSB first, while the AD5551/ AD5552 expect the MSB of the 14-bit word first. Take care to Figure 26 shows a serial interface between the AD5551/AD5552 ensure that the transmit routine takes this into account. Usually and the 68HC11 microcontroller. SCK of the 68HC11 drives the it can be done through software by shifting out and accumu- SCLK of the DAC, while the MOSI output drives the serial data lating the bits in the correct order before inputting to the DAC. line DIN. CS signal is driven from one of the port lines. The Also, 80C51 outputs 2 byte words/16 bits data, thus the first 68HC11 is configured for master mode; MSTR = 1, CPOL = 0, two bits, after rearrangement, should be don’t care as they are and CPHA = 0. Data appearing on the MOSI output is valid on dropped from the 14-bit word of the DAC. the rising edge of SCK. When data is to be transmitted to the DAC, P3.3 is taken low. 68HC11/ AD5551/ 68L11* AD5552* Data on RxD is valid on the falling edge of TxD, so the clock must be inverted as the DAC clocks data into the input shift register PC6 LDAC** PC7 CS on the rising edge of the serial clock. The 80C51/80L51 transmits MOSI DIN its data in 8-bit bytes with only eight falling clock edges occur- SCK SCLK ring in the transmit cycle. As the DAC requires a 14-bit word, **A*ADDD5I5T5IO2 NOANLL YP.INS OMITTED FOR CLARITY. 01943-026 iPn3p.3u t( osirg annayl toon teh oe fD thAeC o, tshoe rP 3p.r3o gshraomulmd abbel eb rboiutsg)h its ltohwe CatS t he Figure 26. 68HC11/68L11 to AD5551/AD5552 Interface beginning of the 16-bit write cycle 2 × 8 bit words and held low until the 16-bit 2 × 8 cycle is completed. After that, P3.3 is brought high again and the new data loads to the DAC. Again, the first two bits, after rearranging, should be don’t care. LDAC on the AD5552 may also be controlled by the 80C51/80L51 serial port output by using another bit programmable pin, P3.4. Rev. A | Page 14 of 16

AD5551/AD5552 APPLICATIONS INFORMATION OPTOCOUPLER INTERFACE DECODING MULTIPLE AD5551/AD5552S The digital inputs of the AD5551/AD5552 are Schmitt- The CS pin of the AD5551/AD5552 can be used to select one of triggered, so they can accept slow transitions on the digital a number of DACs. All devices receive the same serial clock and input lines. This makes these parts ideal for industrial applica- serial data, but only one device receives the CS signal at any one tions where it may be necessary that the DAC is isolated from time. The DAC addressed is determined by the decoder. There the controller via optocouplers. Figure 29 illustrates such an is some digital feedthrough from the digital input lines. Using a interface. burst clock minimizes the effects of digital feedthrough on the analog signal channels. Figure 30 shows a typical circuit. 5V REGULATOR POWER 10µF 0.1µF AD5551/ SCLK AD5552 CS VDD DIN DIN VOUT 10kΩ VDD SCLK VDD SCLK SCLK ENABLE EN AD5551/ AD5552 10kΩVDD AADD55555512/ ADCDORDEESDS DECODER CDSIN VOUT CS CS VOUT SCLK DGND VDD AADD55555512/ CS DIN 10kΩ DIN DIN VOUT GND SCLK 01943-029 AD5551/ Figure 29. AD5551/AD5552 in an Optocoupler Interface AD5552 CS DSCINLK VOUT 01943-030 Figure 30. Addressing Multiple AD5551/AD5552s Rev. A | Page 15 of 16

AD5551/AD5552 OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIOARRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 31. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 14 8 6.20 (0.2441) 3.80 (0.1496) 1 7 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 1.75 (0.0689) 0.25 (0.0098) 45° 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AB C(RINOEFNPETARRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 32. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 INL DNL Temperature Range Package Description Package Option AD5551BRZ ±1 LSB ±0.8 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5551BRZ-REEL7 ±1 LSB ±0.8 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5551BR ±1 LSB ±0.8 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5551BR-REEL7 ±1 LSB ±0.8 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5552BRZ ±1 LSB ±0.8 LSB −40°C to +85°C 14-Lead SOIC_N R-14 1 Z = RoHS Compliant Part. ©2000–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01943-0-5/10(A) Rev. A | Page 16 of 16

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