Dual-Current Output, Parallel Input, 16-Bit Multiplying DAC with 4-Quadrant Resistors Data Sheet AD5547-EP FEATURES FUNCTIONAL BLOCK DIAGRAM Dual channel R1A RCOMA VREFA ROFSA 16-bit resolution: AD5547-EP RFBA 2- or 4-quadrant, 6.8 MHz bandwidth multiplying DAC VDD ±1 LSB DNL REINGPISUTTER REDGAICST AER DAC A IOUTA ±2 LSB INL D0TO D15 DD01T5O RS RS AGNDA Operating supply voltage: 2.7 V to 5.5 V AGNDB Low noise: 12 nV/√Hz Low power: IDD = 10 μA maximum DAC A REINGPISUTTERRS REDGAICS TBERRS DAC B IOUTB 0.5 μs settling time WR DAC B RFBB Built-in RFB facilitates current-to-voltage conversion A0,A1 ADDR POWER ROFSB Built-in 4-quadrant resistors allow 0 V to –10 V, 0 V to +10 V, DECODE ON AD5547-EP RESET 2 moAr ± f1u0ll -Vsc oauletp cuutrsr ent ± 20%, with VREF = 10 V DGND RS MSB LDAC R1B RCOMB VREFB 10108-013 Figure 1. Extended automotive operating temperature range −55°C to +125°C GENERAL DESCRIPTION Selectable zero-scale/midscale power-on presets The AD5547-EP is a dual precision, 16-bit, multiplying, low power, Compact 38-lead TSSOP package current-output, parallel input, digital-to-analog converter (DAC). It ENHANCED PRODUCT FEATURES is designed to operate from a single +5 V supply with ±10 V Supports defense and aerospace applications (AQEC multiplying references for 4-quadrant outputs with a 6.8 MHz standard) bandwidth. Military temperature range (such as −55°C to +125°C). The built-in, 4-quadrant resistors facilitate resistance matching Controlled manufacturing baseline and temperature tracking, which minimize the number of One assembly/test site components needed for multiquadrant applications. In addition, One fabrication site the feedback resistor (R ) simplifies the I-to-V conversion with Enhanced product change notification FB an external buffer. Qualification data available on request APPLICATIONS The AD5547-EP is available in a compact, 38-lead TSSOP package and operates at the extended automotive temperature Automatic test equipment range of −55°C to +125°C. Additional application and technical Instrumentation information can be found in the AD5547 data sheet. Digitally controlled calibration Digital waveform generation VREF U1 –VREF C1 R1A RCOMA VREFA ROFSA RFBA C2 R1 R2 ROFS RFB IOUTA U2 AD5547-EP 16-BIT VOUTA 16-BIT DATA DAC A AGNDA –VREFTO +VREF POWER-ON RESET WRLDACRS MSBA0,A1 WR LDAC 2 (ONE CHANNEL SHOWN ONLY) A0M,SRABS1 10108-002 Figure 2. 16-Bit 4-Quadrant Multiplying DAC with Minimum of External Components (Only One Channel Is Shown) Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.

AD5547-EP Data Sheet TABLE OF CONTENTS Features..............................................................................................1  Electrical Characteristics..............................................................3  Enhanced Product Features............................................................1  Absolute Maximum Ratings............................................................5  Applications.......................................................................................1  ESD Caution...................................................................................5  Functional Block Diagram..............................................................1  Pin Configuration and Function Descriptions..............................6  General Description.........................................................................1  Typical Performance Characteristics..............................................8  Revision History...............................................................................2  Outline Dimensions.......................................................................10  Specifications.....................................................................................3  Ordering Guide..........................................................................10  REVISION HISTORY 9/11—Revision 0: Initial Version Rev. 0 | Page 2 of 12

Data Sheet AD5547-EP SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = 2.7 V to 5.5 V, I = virtual GND, GND = 0 V, V = −10 V to +10 V, T = −55°C to +125°C, unless otherwise noted. DD OUT REF A Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit STATIC PERFORMANCE1 Resolution N 1 LSB = V /216 = 153 μV at V = 10 V 16 Bits REF REF Relative Accuracy INL ±2 LSB Differential Nonlinearity DNL Monotonic ±1 LSB Output Leakage Current I Data = zero scale, T = 25°C 10 nA OUT A Data = zero scale, T = T maximum 20 nA A A Full-Scale Gain Error G Data = full scale ±1 ±5 mV FSE Bipolar Mode Gain Error G Data = full scale ±1 ±5 mV E Bipolar Mode Zero-Scale Error G Data = full scale ±1 ±4 mV ZSE Full-Scale Temperature Coefficient2 TCV 1 ppm/°C FS REFERENCE INPUT V Range V −18 +18 V REF REF REF Input Resistance REF 4 5 6 kΩ R1 and R2 Resistance R1 and R2 4 5 6 kΩ R1-to-R2 Mismatch Δ(R1 to R2) ±0.5 ±1.5 Ω Feedback and Offset Resistance R , R 8 10 12 kΩ FB OFS Input Capacitance2 C 5 pF REF ANALOG OUTPUT Output Current I Data = full scale 2 mA OUT Output Capacitance2 C Code dependent 200 pF OUT LOGIC INPUT AND OUTPUT Logic Input Low Voltage V V = 5 V 0.8 V IL DD V = 3 V 0.4 V DD Logic Input High Voltage V V = 5 V 2.4 V IH DD V = 3 V 2.1 V DD Input Leakage Current I 10 μA IL Input Capacitance2 C 10 pF IL INTERFACE TIMING2, 3 See Figure 3 Data to WR Setup Time t V = 5 V 20 ns DS DD V = 3 V 35 ns DD Data to WR Hold Time t V = 5 V 0 ns DH DD V = 3 V 0 ns DD WR Pulse Width t V = 5 V 20 ns WR DD V = 3 V 35 ns DD LDAC Pulse Width t V = 5 V 20 ns LDAC DD V = 3 V 35 ns DD RS Pulse Width t V = 5 V 20 ns RS DD V = 3 V 35 ns DD WR to LDAC Delay Time t V = 5 V 0 ns LWD DD V = 3 V 0 ns DD SUPPLY CHARACTERISTICS Power Supply Range V 2.7 5.5 V DD RANGE Positive Supply Current I Logic inputs = 0 V 10 μA DD Power Dissipation P Logic inputs = 0 V 0.055 mW DISS Power Supply Sensitivity P ∆V = ±5% 0.003 %/% SS DD Rev. 0 | Page 3 of 12

AD5547-EP Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit AC CHARACTERISTICS4 Output Voltage Settling Time t To ±0.1% of full scale, data cycles from zero scale 0.5 μs S to full scale to zero scale Reference Multiplying Bandwidth BW V = 100 mV rms, data = full scale 6.8 MHz REF DAC Glitch Impulse Q V = 0 V, midscale – 1 to midscale −3.5 nV-s REF Multiplying Feedthrough Error V /V V = 100 mV rms, f = 10 kHz −78 dB OUT REF REF Digital Feedthrough Q WR = 1, LDAC toggles at 1 MHz 7 nV-s D Total Harmonic Distortion THD V = 5 V p-p, data = full scale, f = 1 kHz −104 dB REF Output Noise Density e f = 1 kHz, BW = 1 Hz 12 nV/√Hz N Analog Crosstalk C Signal input at Channel A and measures the −95 dB AT output at Channel B, f = 1 kHz 1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP97 I-to-V converter amplifier. The device RFB terminal is tied to the amplifier output. The +IN pin of the OP97 is grounded, and the IOUT of the DAC is tied to the OP97’s −IN pin. Typical values represent average readings measured at 25°C. 2 Guaranteed by design; not subject to production testing. 3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and are timed from a voltage level of 1.5 V. 4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where the AD8065 was used. Timing Diagram t WR WR DATA t t DH DS t LWD LDAC t LDAC t RS RS 10108-018 Figure 3. AD5547-EP Timing Diagram Rev. 0 | Page 4 of 12

Data Sheet AD5547-EP ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Stresses above those listed under Absolute Maximum Ratings V to GND –0.3 V to +8 V may cause permanent damage to the device. This is a stress DD R , R , R1, R , and VREF to GND –18 V to +18 V rating only; functional operation of the device at these or any FB OFS COM Logic Inputs to GND –0.3 V to +8 V other conditions above those indicated in the operational V(I ) to GND –0.3 V to V + 0.3 V section of this specification is not implied. Exposure to absolute OUT DD Input Current to Any Pin except Supplies ±50 mA maximum rating conditions for extended periods may affect Thermal Resistance (θ )1 device reliability. JA Maximum Junction Temperature (TJ MAX) 150°C Operating Temperature Range −55°C to +125°C ESD CAUTION Storage Temperature Range −65°C to +150°C Lead Temperature Vapor Phase, 60 sec 215°C Infrared, 15 sec 220°C 1 Package power dissipation = (TJ MAX − TA)/θJA. Rev. 0 | Page 5 of 12

AD5547-EP Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D1 1 38 D2 D0 2 37 D3 ROFSA 3 36 D4 RFBA 4 35 D5 R1A 5 34 D6 RCOMA 6 33 D7 VREFA 7 32 D8 IOUTA 8 31 D9 AGNDA 9 AD5547-EP 30 D10 DGND 10 TOP VIEW 29 VDD (Not to Scale) AGNDA 11 28 D11 IOUTB 12 27 D12 VREFB 13 26 D13 RCOMB 14 25 D14 R1B 15 24 D15 RFBB 16 23 RS ROFSB 17 22 MSB WAR0 1189 2210 LAD1AC 10108-003 Figure 4. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1, 2, 24 to D0 to D15 Digital Input Data Bits D0 to D15. Signal level must be ≤ V + 0.3 V. DD 28, 30 to 38 3 R Bipolar Offset Resistor A. Accepts up to ±18 V. In 2-quadrant mode, R ties to R . In 4-quadrant mode, R OFSA OFSA FBA OFSA ties to R and the external reference. 1A 4 R Internal Matching Feedback Resistor A. Connects to the external op amp for I-to-V conversion. FBA 5 R 4-Quandrant Resistor. In 2-quadrant mode, R shorts to the V pin. In 4-quadrant mode, R ties to R . Do 1A 1A REFA 1A OFSA not connect when operating in unipolar mode. 6 R Center Tap Point of the Two 4-Quadrant Resistors, R and R . In 4-quadrant mode, R ties to the inverting COMA 1A 2A COMA node of the reference amplifier. In 2-quadrant mode, R shorts to the associated V pin. Do not connect if COMA REFA operating in unipolar mode. 7 V DAC A Reference Input in 2-Quadrant Mode, R2 Terminal in 4-Quadrant Mode. In 2-quadrant mode, V is the REFA REFA reference input with constant input resistance vs. code. In 4-quadrant mode, V is driven by the external REFA reference amplifier. 8 I DAC A Current Output. Connects to the inverting terminal of external precision I-to-V op amp for voltage output. OUTA 9 AGNDA DAC A Analog Ground. 10 DGND Digital Ground. 11 AGNDB DAC B Analog Ground. 12 I DAC B Current Output. Connects to inverting terminal of external precision I-to-V op amp for voltage output. OUTB 13 V DAC B Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code. If configured REFB with an external op amp for 4-quadrant multiplying, V becomes –V . REFB REF 14 R Center Tap Point of the Two 4-Quadrant Resistors, R and R . In 4-quadrant mode, R ties to the inverting COMB 1B 2B COMB node of the reference amplifier. In 2-quadrant mode, R shorts to the V pin. Do not connect if operating in COMB REFB unipolar mode. 15 R 4-Quandrant Resistor. In 2-quadrant mode, R shorts to the V pin. In 4-quadrant mode, R ties to R . Do not 1B 1B REFB 1B OFSB connect if operating in unipolar mode. 16 R Internal Matching Feedback Resistor B. Connects to external op amp for I-to-V conversion. FBB 17 R Bipolar Offset Resistor B. Accepts up to ±18 V. In 2-quadrant mode, R ties to R . In 4-quadrant mode, R OFSB OFSB FBB OFSB ties to R and an external reference. 1B 18 WR Write Control Digital Input In, Active Low. WR transfers shift register data to the DAC register on the rising edge. Signal level must be ≤V + 0.3 V. DD Rev. 0 | Page 6 of 12

Data Sheet AD5547-EP Pin No. Mnemonic Description 19 A0 Address Pin 0. Signal level must be ≤V + 0.3 V. DD 20 A1 Address Pin 1. Signal level must be ≤V + 0.3 V. DD 21 LDAC Digital Input Load DAC Control. Signal level must be ≤V + 0.3 V. DD 22 MSB Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The signal level must be ≤V + 0.3 V. DD 23 RS Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1. Signal level must be ≤V + 0.3 V. DD 29 VDD Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V. Table 4. Address Decoder Pins A1 A0 Output Update 0 0 DAC A 0 1 None 1 0 DAC A and DAC B 1 1 DAC B Table 5. Control Inputs RS WR LDAC Register Operation 0 X X Reset the output to 0 with MSB = 0; reset the output to midscale with MSB = 1. 1 0 0 Load the input register with data bits. 1 1 1 Load the DAC register with the contents of the input register. 1 0 1 The input and DAC registers are transparent. 1 When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on the falling edge of the pulse and are then loaded into the DAC register on the rising edge of the pulse. 1 1 0 No register operation. Rev. 0 | Page 7 of 12

AD5547-EP Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 5 VDD= 5V 0.8 TA= 25°C 0.6 4 B) S 0.4 L (D D L(LSB) 0.02 RRENT I 3 N U I–0.2 C 2 Y L –0.4 P P U –0.6 S 1 –0.8 –1.00 8192 16,384 24,5C7O6D3E2(,7D6e8cim40a,l9)60 49,152 57,344 65,536 10108-019 00 0.5 1.0 LO1.G5IC IN2.P0UT V2.O5LTA3G.0E VIH3 .(5V) 4.0 4.5 5.0 10108-023 Figure 5. AD5547-EP Integral Nonlinearity Error Figure 8. Supply Current vs. Logic Input Voltage 1.0 3.0 0.8 2.5 0.6 0.4 A) m 2.0 L (LSB) 0.02 URRENT ( 1.5 0x5555 N C D–0.2 Y 0x8000 L –0.4 SUPP 1.0 0xFFFF –0.6 0x0000 0.5 –0.8 –1.00 8192 16,384 24,5C7O6D3E2 (,7D6e8cim40a,l9)60 49,152 57,344 65,536 10108-020 010k 100kCLOCK FRE1QMUENCY (Hz)10M 100M 10108-024 Figure 6. AD5547-EP Differential Nonlinearity Error Figure 9. AD5547-EP Supply Current vs. Clock Frequency 1.5 90 VREF= 2.5V TA= 25°C 80 VDD= 5V ± 10% 1.0 VREF= 10V 70 B) S L 0.5 60 OR ( INL B) R d 50 TY ER 0 DNL SRR (– 40 RI P EA–0.5 30 N LI 20 –1.0 GE 10 –1.52 4 SUPPLY VOLT6AGE VDD (V) 8 10 10108-022 010 100 F1RkEQUENCY 1(0Hkz) 100k 1M 10108-014 Figure 7. Linearity Error vs. Supply Voltage, VDD Figure 10. Power Supply Rejection Ratio (PSRR) vs. Frequency Rev. 0 | Page 8 of 12

Data Sheet AD5547-EP 2 0 LDAC 1 –2 –4 –6 B) d 2 N ( –8 AI G –10 –12 VOUT –14 CH1 5.00V CH2 2.00V M 200ns B4A0 CC0.HH0110 n s 2–.67.02V0V 10108-025 ––118610k 100k FREQU1EMNCY (Hz) 10M 100M 10108-017 Figure 11. Settling Time from Full Scale to Zero Scale Figure 13. AD5547-EP Unipolar Reference Multiplying Bandwidth –3.85 –3.90 –3.95 V)–4.00 (UT VO–4.05 –4.10 –4.15 –4.20–20 –10 0 TIM1E0 (ns) 20 30 40 10108-016 Figure 12. AD5547-EP Midscale Transition and Digital Feedthrough Rev. 0 | Page 9 of 12

AD5547-EP Data Sheet OUTLINE DIMENSIONS 9.80 9.70 9.60 38 20 4.50 4.40 4.30 6.40BSC 1 19 PIN1 1.20 MAX 0.15 0.05 8° COPL0A.1N0ARITY B0.S5C0 00..2177 SPELAANTIENG 00..2009 0° 00..7600 0.45 COMPLIANTTOJEDECSTANDARDSMO-153-BD-1 Figure 14. 38-Lead Thin Shrink Small Outline Package [TSSOP] (RU-38) Dimension s shown in millimeters ORDERING GUIDE Model1 Resolution (Bits) DNL (LSB) INL (LSB) Temperature Range Package Description Package Option AD5547SRU-EP 16 ±1 ±2 −55°C to +125°C 38-Lead TSSOP RU-38 1 Z = RoHS Compliant Part. Rev. 0 | Page 10 of 12

Data Sheet AD5547-EP NOTES Rev. 0 | Page 11 of 12

AD5547-EP Data Sheet NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10108-0-9/11(0) Rev. 0 | Page 12 of 12

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