Dual, Current-Output, Serial-Input, 16-/14-Bit DACs Data Sheet AD5545/AD5555 FEATURES FUNCTIONAL BLOCK DIAGRAM 16-bit resolution AD5545 VREFA VREFB 14-bit resolution AD5555 16 OR 14 ±1 LSB DNL monotonic VDD D0..DX RFBA ±1 LSB INL SDI REINGPISUTTER R REDGAICST AER R DAC A IOUTA 2 mA full-scale current ±20%, with V = 10 V AGNDA REF 0.5 µs settling time RFBB 2Q multiplying reference-input 6.9 MHz BW CCLKS EN REINGPISUTTER R REDGAICST BER R DAC B AIOGUNTDBB Zero or midscale power-up preset DAC A B Zero or midscale dynamic reset ADDR POWER- AD5545/ DECODE ON AD5555 3-wire interface RESET Compact 16-lead TSSOP package DGND RSMSB LDAC 02918-0-001 Figure 1. APPLICATIONS Automatic test equipment Instrumentation Digitally controlled calibration Industrial control PLCs Programmable attenuator PRODUCT OVERVIEW The AD5545/AD5555 are 16-bit/14-bit, current-output, digital- to-analog converters designed to operate from a 4.5 V to 5.5 V supply range. An external reference is needed to establish the full-scale output-current. An internal feedback resistor (R ) enhances FB the resistance and temperature tracking when combined with an external op amp to complete the I-to-V conversion. A serial data interface offers high speed, 3-wire microcontroller compatible inputs using serial data in (SDI), clock (CLK), and chip select (CS). Additional LDAC function allows simultaneous update operation. The internal reset logic allows power-on preset and dynamic reset at either zero or midscale, depending on the state of the MSB pin. The AD5545/AD5555 are packaged in the compact TSSOP-16 package and can be operated from −40°C to +85°C. Rev. I Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5545/AD5555 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Layout and Power Supply Bypassing ....................................... 11 Applications ....................................................................................... 1 Grounding ................................................................................... 11 Product Overview ............................................................................. 1 Applications Information .............................................................. 12 Functional Block Diagram .............................................................. 1 Stability ........................................................................................ 12 Revision History ............................................................................... 2 Bipolar Output ............................................................................ 12 Specifications ..................................................................................... 3 Programmable Current Source ................................................ 13 Electrical Characteristics ............................................................. 3 DAC with Programmable Input Reference Range ................ 14 Timing Diagrams .......................................................................... 4 Reference Selection .................................................................... 15 Absolute Maximum Ratings ............................................................ 5 Amplifier Selection .................................................................... 15 ESD Caution .................................................................................. 5 Evaluation Board for the AD5545 ................................................ 17 Pin Configuration and Function Descriptions ............................. 6 System Demonstration Platform .............................................. 17 Typical Performance Characteristics ............................................. 7 Operating the Evaluation Board .............................................. 17 Theory of Operation ........................................................................ 9 Evaluation Board Schematics ................................................... 18 Digital-to-Analog Converter ...................................................... 9 Evaluation Board Layout ........................................................... 21 Serial Data Interface ................................................................... 10 Outline Dimensions ....................................................................... 23 Power-Up Sequence ................................................................... 11 Ordering Guide .......................................................................... 23 REVISION HISTORY 1/16—Rev. H to Rev. I Added Figure 29 ............................................................................. 20 Deleted Positive Voltage Output Section and Figure 22; Added Evaluation Board Layout Section, Figure 30, and Renumbered Section ...................................................................... 12 Figure 31, ......................................................................................... 21 Changes to Ordering Guide .......................................................... 23 Added Figure 32 ............................................................................. 22 Changes to Ordering Guide .......................................................... 23 4/14—Rev. G to Rev. H Change to Interface Timing Parameter, Table 1 ........................... 3 3/11—Rev. B to Rev. C Change to Equation 4, Bipolar Output Section .......................... 12 4/13—Rev. F to Rev. G Changes to Product Overview Section .......................................... 1 4/10—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 23 Changes to 2Q Multiplying Reference Input ................................. 1 Changes to AC Characteristics and Endnote 3 in Table 1 ........... 4 2/13—Rev. E to Rev. F Changes to Figure 13 and Figure 15 ............................................... 8 Change to VDD Pin Description, Table 3 ..................................... 6 Added Reference Selection Section, Amplifier Selection Section, Changed ADA4899 to ADA4899-1, Table 12 ............................. 16 and Table 10 .................................................................................... 15 Changes to Ordering Guide .......................................................... 23 Added Table 11 and Table 12 ........................................................ 16 Changes to Ordering Guide .......................................................... 17 12/11—Rev. D to Rev. E Added Figure 13; Renumbered Sequentially ................................ 8 9/09—Rev. 0 to Rev. A Changes to Features Section ............................................................ 1 5/11—Rev. C to Rev. D Changes to Static Performance, Relative Accuracy, AD5545C Added Evaluation Board for the AD5545 Section, System Parameter, Table 1 ............................................................................. 3 Demonstration Platform Section, and Operating the Evaluation Moved ESD Caution.......................................................................... 5 Board Section .................................................................................. 17 Changes to Ordering Guide .......................................................... 16 Added Figure 25 and Figure 26; Renumbered Sequentially ..... 17 Added Evaluation Board Schematics Section, Figure 27 .......... 18 7/03—Revision 0: Initial Version Added Figure 28 .............................................................................. 19 Rev. I | Page 2 of 23

Data Sheet AD5545/AD5555 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = 5 V ± 10%, I = virtual GND, GND = 0 V, V = 10 V, T = full operating temperature range, unless otherwise noted. DD OUT REF A Table 1. Parameter Symbol Conditions Min Typ Max Unit STATIC PERFORMANCE1 Resolution N AD5545, 1 LSB = V /216 = 153 µV when V = 10 V 16 Bits REF REF AD5555, 1 LSB = V /214 = 610 µV when V = 10 V 14 Bits REF REF Relative Accuracy INL AD5545B ±2 LSB AD5555C ±1 LSB AD5545C ±1 LSB Differential Nonlinearity DNL Monotonic ±1 LSB Output Leakage Current I Data = 0x0000, T = 25°C 10 nA OUT A Data = 0x0000, T = T Max 20 nA A A Full-Scale Gain Error G Data = full scale ±1 ±4 mV FSE Full-Scale Temperature Coefficient2 TCV 1 ppm/°C FS REFERENCE INPUT V Range V –12 +12 V REF REF Input Resistance R 5 kΩ3 REF Input Capacitance2 C 5 pF REF ANALOG OUTPUT Output Current I Data = full scale 2 mA OUT Output Capacitance2 C Code dependent 200 pF OUT LOGIC INPUTS AND OUTPUT Logic Input Low Voltage V 0.8 V IL Logic Input High Voltage V 2.4 V IH Input Leakage Current I 10 µA IL Input Capacitance2 C 10 pF IL INTERFACE TIMING2, 4 Clock Input Frequency fCLK 50 MHz Clock Width High tCH 10 ns Clock Width Low tCL 10 ns CS to Clock Setup tCSS 0 ns Clock to CS Hold tCSH 10 ns Data Setup tDS 5 ns Data Hold tDH 10 ns LDAC Setup tLDS 5 ns Hold tLDH 10 ns LDAC Width tLDAC 10 ns SUPPLY CHARACTERISTICS Power Supply Range V range 4.5 5.5 V DD Positive Supply Current I Logic inputs = 0 V 10 µA DD Power Dissipation P Logic inputs = 0 V 0.055 mW DISS Power Supply Sensitivity PSS ∆V = ±5% 0.006 %/% DD Rev. I | Page 3 of 23

AD5545/AD5555 Data Sheet Parameter Symbol Conditions Min Typ Max Unit AC CHARACTERISTICS Output Voltage Setting Time t To ±0.1% full scale, data = zero scale to 0.5 µs S full scale to zero scale Reference Multiplying BW BW V = 100 mV rms, data = full scale, C1 = 5.6 pF 6.9 MHz REF DAC Glitch Impulse Q V = 0 V, data = midscale minus 1 to midscale –2 nV-s REF Feedthrough Error V /V Data = zero scale, V = 100 mV rms, –81 dB OUT REF REF f = 1 kHz, same channel Digital Feedthrough Q CS = logic high and fCLK = 1 MHz 7 nV-s Total Harmonic Distortion THD V = 5 V p-p, data = full scale, f = 1 kHz to 10 kHz –104 dB REF Analog Crosstalk C V = 0 V, measure V with V = 5 V p-p –95 dB TA REFB OUTB REFA sine wave, data = full scale, f = 1 kHz to 10 kHz Output Spot Noise Voltage e f = 1 kHz, BW = 1 Hz 12 nV/√Hz N 1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP1177 I-to-V converter amplifier. The AD5545 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25°C. 2 These parameters are guaranteed by design and not subject to production testing. 3 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier and the AD8065 for the THD specification. 4 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. TIMING DIAGRAMS SDI A1 A0 D15 D14 D13 D12 D11 D10 D1 D0 CLK INPUT REG LD tDS tDH tCH tCL CS tCSS tCSH LDAC tLDS tLDH tLDAC 02918-0-003 Figure 2. AD5545 18-Bit Data Word Timing Diagram SDI A1 A0 D13 D12 D11 D10 D09 D08 D1 D0 CLK INPUT REG LD tDS tDH tCH tCL CS tCSS tCSH LDAC tLDS tLDH tLDAC 02918-0-004 Figure 3. AD5555 16-Bit Data Word Timing Diagram Rev. I | Page 4 of 23

Data Sheet AD5545/AD5555 ABSOLUTE MAXIMUM RATINGS Table 2. Stresses at or above those listed under Absolute Maximum Parameter Rating Ratings may cause permanent damage to the product. This is a V to GND –0.3 V to +8 V stress rating only; functional operation of the product at these DD V to GND –18 V to +18 V or any other conditions above those indicated in the operational REF Logic Inputs to GND –0.3 V to +8 V section of this specification is not implied. Operation beyond V(I ) to GND –0.3 V to V + 0.3 V the maximum operating conditions for extended periods may OUT DD Input Current to Any Pin except ±50 mA affect product reliability. Supplies Package Power Dissipation (T max – T )/θ ESD CAUTION J A JA Thermal Resistance θ JA 16-Lead TSSOP 150°C/W Maximum Junction Temperature 150°C (T max) J Operating Temperature Range –40°C to +85°C Storage Temperature Range –65°C to +150°C Lead Temperature RU-16 (Vapor Phase, 60 sec) 215°C RU-16 (Infrared, 15 sec) 220°C Rev. I | Page 5 of 23

AD5545/AD5555 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RFBA 1 16 CLK VREFA 2 15 LDAC IOUTA 3 14 MSB AD5545/ AGNDA 4 13 VDD AD5555 AGNDB 5 TOP VIEW 12 DGND (Not to Scale) IOUTB 6 11 CS VREFB 7 10 RS RFBB 8 9 SDI 02918-0-002 Figure 4. 16-Lead TSSOP Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 R A Establish voltage output for DAC A by connecting this pin to an external amplifier output. FB 2 V A DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can REF be tied to the V pin. DD 3 I A DAC A Current Output. OUT 4 A A DAC A Analog Ground. GND 5 A B DAC B Analog Ground. GND 6 I B DAC B Current Output. OUT 7 V B DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. REF This pin can be tied to the V pin. DD 8 R B Establish voltage output for DAC B by the R B pin connecting to an external amplifier output. FB FB 9 SDI Serial Data Input. Input data loads directly into the shift register. 10 RS Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or midscale. Register Data = 0x0000 when MSB = 0. Register Data = 0x8000 for AD5545 and 0x2000 for AD5555 when MSB = 1. 11 CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the input register when CS/LDAC returns high. This does not affect LDAC operation. 12 DGND Digital Ground Pin. 13 V Positive Power Supply Input. Specified range of operation 5 V ± 10%. DD 14 MSB MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can also be tied permanently to ground or V . DD 15 LDAC Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers. Asynchronous active low input. See Table 7 and Table 8 for operation. 16 CLK Clock Input. Positive edge clocks data into shift register. Rev. I | Page 6 of 23

Data Sheet AD5545/AD5555 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 B) 0.2 B) 0.2 INL(LS–0.02 DNL (LS–0.02 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 0 0248 4096 6144 8192 10240 12288 14336 16384 CODE(Decimal) CODE (Decimal) 02918-0-009 02918-0-012 Figure 5. AD5545 Integral Nonlinearity Error Figure 8. AD5555 Differential Nonlinearity Error 1.0 1.5 VREF=2.5V 0.8 TA=25°C 1.0 0.6 0.4 SB) L 0.5 B) 0.2 OR ( INL S R DNL (L–0.02 RITY ER 0 DNL EA–0.5 –0.4 N LI –0.6 –1.0 GE –0.8 –1.0 –1.5 0 8192 16384 24576 32768 40960 49152 57344 65536 2 4 6 8 10 CODE (Decimal) SUPPLY VOLTAGE VDD (V) 02918-0-010 02918-0-013 Figure 6. AD5545 Differential Nonlinearity Error Figure 9. Linearity Errors vs. VDD 1.0 5 VDD=5V 0.8 TA=25°C 0.6 4 B) S 0.4 L (D D L (LSB) 0.20 RRENT I 3 N U I–0.2 C 2 Y L –0.4 PP U S –0.6 1 –0.8 –1.0 0 0 2048 4096 6144 8192 10240 12288 14336 16384 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CODE (Decimal) LOGIC INPUT VOLTAGE VIH (V) 02918-0-011 02918-0-014 Figure 7. AD5555 Integral Nonlinearity Error Figure 10. Supply Current vs. Logic Input Voltage Rev. I | Page 7 of 23

AD5545/AD5555 Data Sheet 3.0 2 0 2.5 –2 A) CURRENT (m 21..05 0x5555 AIN (dB) ––64 Y 0x8000 G L –8 P P 1.0 U S 0xFFFF –10 0.5 0x0000 –12 0 –14 10k 100k 1M 10M 100M 10k 100k 1M 10M 100M CLOCK FREQUENCY (Hz) FREQUENCY (Hz) 02918-0-117 02918-0-015 Figure 11. Supply Current vs. Clock Frequency Figure 14. Reference Multiplying Bandwidth 90 80 VDD=5V± 10% VREF=10V 70 CS 60 B) d 50 R (- SS 40 P 30 20 VOUT 10 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) 02918-0-016 02918-0-018 Figure 12. Power Supply Rejection Ration vs. Frequency Figure 15. Settling Time –3.70 20 0 –3.75 –20 B) –3.80 d M ( –40 U V)–3.85 CTR –60 (UT PE VO–3.90 S –80 R E W–100 –3.95 O P –120 –4.00 –140 –4.05 –160 –200 –100 0 100 200 300 400 0 5 10 15 20 25 TIME (ns) 02918-0-119 FREQUENCY (Hz) 02918-0-113 Figure 13. AD5545/AD5555 Analog THD Figure 16. Midscale Transition and Digital Feedthrough Rev. I | Page 8 of 23

Data Sheet AD5545/AD5555 THEORY OF OPERATION The AD5545/AD5555 contain a 16-/14-bit, current-output, These DACs are also designed to accommodate ac reference input digital-to-analog converter, a serial-input register, and a DAC signals. The AD5545/AD5555 accommodate input reference register. Both parts require a minimum of a 3-wire serial data voltages in the range of –12 V to +12 V. The reference voltage interface with an additional LDAC for dual channel simultaneous inputs exhibit a constant nominal input-resistance value of update. 5 kΩ, ±30%. The DAC output (IOUT) is code dependent, pro- ducing various output resistances and capacitances. When DIGITAL-TO-ANALOG CONVERTER choosing an external amplifier, the user should take into The DAC architecture uses a current-steering R-2R ladder account the variation in impedance generated by the AD5545/ design. Figure 17 shows the typical equivalent DAC. The DAC AD5555 on the amplifiers inverting input node. The feedback contains a matching feedback resistor for use with an external resistance in parallel with the DAC ladder resistance dominates I-to-V converter amplifier. The RFB pin is connected to the output voltage noise. output of the external amplifier. The I terminal is connected OUT VIN 5V to the inverting input of the external amplifier. These DACs are 2.500V VOUT designed to operate with either negative or positive reference ADR03 voltages. The V power pin is used only by the logic to drive DD GND the DAC switches on and off. Note that a matching switch is used in series with the internal 5 kΩ feedback resistor. If users VDD R R R RFBA attempt to measure the RFB value, power must be applied to VDD VREFA 2R 2R 2R R 5kΩ to achieve continuity. The V input voltage and the digital data +3V REF (D) loaded into the corresponding DAC register, according to S2 S1 IOUTA VCC VOUT Equation 1 and Equation 2, determine the DAC output voltage. AD8628 VOUT =–VREF×D/65,536 (1) AD5545/AD5555 –3VVEE LOAD V =–V ×D/16,384 (2) AGNDA OUT REF DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY: Note that the output full-scale polarity is the opposite of the SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED 02918-0-006 V polarity for dc reference voltages. Figure 18. Recommended System Connections REF VDD R R R VREF RFB 2R 2R 2R R 5kΩ S2 S1 IOUT GND DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY: SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED 02918-0-005 Figure 17. Equivalent R-2R DAC Circuit Rev. I | Page 9 of 23

AD5545/AD5555 Data Sheet SERIAL DATA INTERFACE to the DAC A register. At this time, the output is not updated. To load DAC B data, pull CS low for an 18-bit duration and program The AD5545/AD5555 use a minimum 3-wire (CS, SDI, CLK) DAC B with the proper address and data, then pull CS high to serial data interface for single channel update operation. With Table 7 as an example (AD5545), users can tie LDAC low and latch data to the DAC B register. Finally, pull LDAC low and then high to update both the DAC A and DAC B outputs RS high, and then pull CS low for an 18-bit duration. New serial simultaneously. data is then clocked into the serial-input register in an 18-bit data-word format with the MSB bit loaded first. Table 8 defines Table 6 shows that each DAC A and DAC B can be individually the truth table for the AD5555. Data is placed on the SDI pin loaded with a new data value. In addition, a common new data and clocked into the register on the positive clock edge of CLK. value can be loaded into both DACs simultaneously by setting Bit For the AD5545, only the last 18-bits clocked into the serial A1 = A0 = high. This command enables the parallel combination register are interrogated when the CS pin is strobed high, of both DACs, with IOUTA and IOUTB tied together, to act as one transferring the serial register data to the DAC register and DAC with significant improved noise performance. updating the output. If the applied microcontroller outputs ESD Protection Circuits serial data in different lengths than the AD5545, such as 8-bit All logic input pins contain back-biased ESD protection Zeners bytes, three right justified data bytes can be written to the connected to digital ground (DGND) and V as shown in DD AD5545. The AD5545 ignores the six MSB and recognizes the Figure 19. 18 LSB as valid data. After loading the serial register, the rising edge of CS transfers the serial register data to the DAC register VDD DIGITAL and updates the output; during the CS strobe, the CLK should INPUTS not be toggled. 5kΩ If users want to program each channel separately but update them DGND simultaneously, program LDAC and RS high initially, then pull 02918-0-007 CS low for an 18-bit duration and program DAC A with the Figure 19. Equivalent ESD Protection Circuits proper address and data bits. CS is then pulled high to latch data Table 4. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1 MSB LSB Bit Position B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 Note that only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D15 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5545 shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers. Table 5. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1 MSB LSB Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 Note that only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D13 to Bit D0) to the decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5555 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers. Table 6. Address Decode A1 A0 DAC Decoded 0 0 None 0 1 DAC A 1 0 DAC B 1 1 DAC A and DAC B Rev. I | Page 10 of 23

Data Sheet AD5545/AD5555 Table 7. AD5545 Control Logic Truth Table1, 2 CS CLK LDAC RS MSB Serial Shift Register Function Input Register Function DAC Register H X H H X No effect Latched Latched L L H H X No effect Latched Latched L ↑+ H H X Shift register data advanced one bit Latched Latched L H H H X No effect Latched Latched ↑+ L H H X No effect Selected DAC updated Latched with current SR current H X L H X No effect Latched Transparent H X H H X No effect Latched Latched H X ↑+ H X No effect Latched Latched H X H L 0 No effect Latched data = 0x0000 Latched data = 0x0000 H X H L H No effect Latched data = 0x8000 Latched data = 0x8000 1 SR = shift register, ↑+ = positive logic transition, and X = don’t care. 2 At power-on, both the input register and the DAC register are loaded with all 0s. Table 8. AD5555 Control Logic Truth Table1, 2 CS CLK LDAC RS MSB Serial Shift Register Function Input Register Function DAC Register H X H H X No effect Latched Latched L L H H X No effect Latched Latched L ↑+ H H X Shift register data advanced one bit Latched Latched L H H H X No effect Latched Latched ↑+ L H H X No effect Selected DAC updated Latched with current SR current H X L H X No effect Latched Transparent H X H H X No effect Latched Latched H X ↑+ H X No effect Latched Latched H X H L 0 No effect Latched data = 0x0000 Latched data = 0x0000 H X H L H No effect Latched data = 0x2000 Latched data = 0x2000 1 SR = shift register, ↑+ = positive logic transition, and X = don’t care. 2 At power-on, both the input register and the DAC register are loaded with all 0s. POWER-UP SEQUENCE (see Figure 20). Users should not apply switching regulators for V due to the power supply rejection ratio degradation over It is recommended to power-up V and ground prior to any DD DD frequency. reference voltages. The ideal power-up sequence is A x, DGND, GND V , V x, and digital inputs. A noncompliance power-up AD5545/ DD REF AD5555 sequence can elevate reference current, but the device will resume normal operation once VDD is powered. VDDC2 +C1 VDD LAYOUT AND POWER SUPPLY BYPASSING 10µF 0.1µF AGNDX It is a good practice to employ compact, minimum lead length DGND layout design. The input leads should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. 02918-0-008 Figure 20. Power Supply Bypassing and Grounding Connection Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to GROUNDING the device should be bypassed with 0.01 µF to 0.1 µF disc or The DGND and A x pins of the AD5545/AD5555 refer to the GND chip ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or digital and analog ground references. To minimize the digital electrolytic capacitors should also be applied at VDD to minimize ground bounce, the DGND terminal should be joined remotely any transient disturbance and to filter any low frequency ripple at a single point to the analog ground plane (see Figure 20). Rev. I | Page 11 of 23

AD5545/AD5555 Data Sheet APPLICATIONS INFORMATION STABILITY BIPOLAR OUTPUT VDD The AD5545/AD5555 is inherently a 2-quadrant multiplying U1 DAC. It can easily be set up for unipolar output operation. The C1 VDD RFB full-scale output polarity is the inverse of the reference input VREF VREF IOUT voltage. VO AD8628 In some applications, it may be necessary to generate the full GND 4-quadrant multiplying capability or a bipolar output swing. This AD5545/AD5555 U2 02918-0-020 is easily accomplished by using an additional external amplifier, U4, configured as a summing amplifier (see Figure 22). In this Figure 21. Operational Compensation Capacitor for Gain Peaking circuit, the second amplifier, U4, provides a gain of 2, which Prevention increases the output span magnitude to 5 V. Biasing the external In the I-to-V configuration, the IOUT of the DAC and the amplifier with a 2.5 V offset from the reference voltage results in a inverting node of the op amp must be connected as close as full 4-quadrant multiplying circuit. The transfer equation of this possible, and proper PCB layout techniques must be employed. circuit shows that both negative and positive output voltages are Because every code change corresponds to a step function, gain created because the input data (D) is incremented from code zero peaking may occur if the op amp has limited GBP, and if there (V = −2.5 V) to midscale (V = 0 V) to full scale (V = OUT OUT OUT is excessive parasitic capacitance at the inverting node. +2.5 V). An optional compensation capacitor, C1, can be added for V = (D/32,768 − 1) × V (AD5545) (3) OUT REF stability as shown in Figure 21. C1 should be found empirically, V = (D/8192 − 1) × V (AD5555) (4) OUT REF but 6 pF is generally more than adequate for the compensation. For the AD5545, the external resistance tolerance becomes the dominant error that users should be aware of. R1 R2 10kΩ±0.01% 10kΩ±0.01% C2 U4 +5V +5V 5kΩ±0.01% ADR03 U1 R3 1/2V+ VO C1 AD8620 VDD RFB V– 5V VOUTVIN VREF IOUT 1/2 –5V GND GND AD8620 –2.5 < VO < +2.5 U3 AD5545/AD5555 U2 02918-0-022 Figure 22. Four-Quadrant Multiplying Application Circuit Rev. I | Page 12 of 23

Data Sheet AD5545/AD5555 PROGRAMMABLE CURRENT SOURCE If the resistors are perfectly matched, Z is infinite, which is O desirable, and the resistors behave as an ideal current source. Figure 23 shows a versatile V-to-I conversion circuit using On the other hand, if they are not matched, Z can be either improved Howland Current Pump. In addition to the precision O positive or negative. The latter can cause oscillation. As a result, current conversion it provides, this circuit enables a bidirec- C1 is needed to prevent the oscillation. For critical applications, tional current flow and high voltage compliance. This circuit C1 could be found empirically but typically falls in the range of can be used in a 4 mA to 20 mA current transmitter with up to a few picofarads. a 500 Ω of load. In Figure 23, it shows that if the resistor network is matched, the load current is VDD (R2+R3) U1 I = R1 ×V ×D (5) VDD RFB L R3 REF VREF VREF IOUT R1' R2' 150kΩ 15kΩ GND AD8628 R3, in theory, can be made small to achieve the current needed C1 within the U3 output current driving capability. This circuit is AD5545/AD5555 10pF U2 versatile such that the AD8510 can deliver ±20 mA in both VDD R3' directions, and the voltage compliance approaches 15 V, which 50Ω U3 is mainly limited by the supply voltages of U3. However, users V+ AD8510 must pay attention to the compensation. Without C1, it can be V– R3 shown that the output impedance becomes 50Ω VSS R1′R3(R1+R2) VL Z = (6) O R1(R2′+R3′)–R1′(R2+R3) R1 R2 150kΩ 15kΩ LOAD IL 02918-0-023 Figure 23. Programmable Current Source with Bidirectional Current Control and High Voltage Compliance Capabilities Rev. I | Page 13 of 23

AD5545/AD5555 Data Sheet DAC WITH PROGRAMMABLE INPUT By putting Equations 7 through 10 together, the following REFERENCE RANGE results: Because high voltage references can be costly, users may  D  1 C  cloown svidoletra gues irnegfe ornene coef ttoh efo DrmAC as s, ian gdlieg-ictahla pnonteeln DtiAomC ewteitrh, aan d a VREFABVREF D 128DDC (11) 1 A  C programmable input reference range. This approach optimizes 2N 128D C the programmable range as well as facilitates future system upgrades with just software changes. Figure 24 shows this Table 9 shows a few examples of VREFAB of the 14-bit AD5555. implementation. V AB is in the feedback network, therefore, REF Table 9. V ABvs. D and D of the AD5555 REF B C V ABV 1 RWB––V DA RWB (7) DC DA VREFAB REF REF  RWA  REF_AB 2N RWA 0 X VREF 32 0 1.33 V REF where: 32 8192 1.6 V REF V AB = reference voltage of V A and V B REF REF REF 64 0 2 V REF V = external reference voltage REF 64 8192 4 V REF D = DAC A digital code in decimal A 96 0 4 V REF N = number of bits of DAC 96 8192 –8 V REF R and R are digital potentiometer 128-step programmable WB WA The output of DAC B is, therefore, resistances and are given by D R DC R (8) VOBVREFAB2NB (12) WB AB 128 where D is the DAC B digital code in decimal. B 128D R  C R (9) WA 128 AB The accuracy of VREFAB is affected by the matching of the input and feedback resistors and, therefore, a digital potentiometer is R D WB  C (10) used for U4 because of its inherent resistance matching. The R 128D WA C AD7376 is a 30 V or ±15 V, 128-step digital potentiometer. If where D = digital potentiometer digital code in decimal 15 V or ±7.5 V is adequate for the application, a 256-step C (0 ≤ D ≤ 127). AD5260 digital potentiometer can be used instead. C +5V C1 +15V VVDRDEFRAFBUA1AIOUTA OP4V1+77 A U4 B AGNDA V– +15V AD7376 W C2 U2A –15V 2 U3 2.2p VIN AD5555 3 TEMPTVROIUMT 56 VREF OP4177 VREF_AB GND U2C 4 ADR03 C3 RFBBIOUTB POT VOB VREFB U1B OP4177 AGNDB U2B 02918-0-024 Figure 24. DAC with Programmable Input Reference Range Rev. I | Page 14 of 23

Data Sheet AD5545/AD5555 REFERENCE SELECTION The input bias current of an op amp also generates an offset at the voltage output because of the bias current flowing in the When selecting a reference for use with the AD55xx series feedback resistor, R . of current output DACs, pay attention to the output voltage, FB temperature coefficient specification of the reference. Choosing Common-mode rejection of the op amp is important in voltage- a precision reference with a low output temperature coefficient switching circuits because it produces a code-dependent error minimizes error sources. Table 10 lists some of the references at the voltage output of the circuit. available from Analog Devices, Inc., that are suitable for use Provided that the DAC switches are driven from true wideband with this range of current output DACs. low impedance sources (V and AGND), they settle quickly. IN AMPLIFIER SELECTION Consequently, the slew rate and settling time of a voltage-switching DAC circuit is determined largely by the output op amp. To obtain The primary requirement for the current-steering mode is an minimum settling time in this configuration, minimize capacitance amplifier with low input bias currents and low input offset voltage. at the V node (the voltage output node in this application) of Because of the code-dependent output resistance of the DAC, REF the DAC. This is done by using low input capacitance buffer the input offset voltage of an op amp is multiplied by the variable amplifiers and careful board design. gain of the circuit. A change in this noise gain between two adjacent digital fractions produces a step change in the output Analog Devices offers a wide range of amplifiers for both precision voltage due to the amplifier’s input offset voltage. This output dc and ac applications, as listed in Table 11 and Table 12. voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the DAC to be nonmonotonic. Table 10. Suitable Analog Devices Precision References Maximum Temperature Part No. Output Voltage (V) Initial Tolerance (%) Drift (ppm/°C) I (mA) Output Noise (µV p-p) Package(s) SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-5, SC70-5 ADR02 5.0 0.06 3 1 10 SOIC-8 ADR02 5.0 0.06 9 1 10 TSOT-5, SC70-5 ADR03 2.5 0.1 3 1 6 SOIC-8 ADR03 2.5 0.1 9 1 6 TSOT-5, SC70-5 ADR06 3.0 0.1 3 1 10 SOIC-8 ADR06 3.0 0.1 9 1 10 TSOT-5, SC70-5 ADR420 2.048 0.05 3 0.5 1.75 SOIC-8, MSOP-8 ADR421 2.50 0.04 3 0.5 1.75 SOIC-8, MSOP-8 ADR423 3.00 0.04 3 0.5 2 SOIC-8, MSOP-8 ADR425 5.00 0.04 3 0.5 3.4 SOIC-8, MSOP-8 ADR431 2.500 0.04 3 0.8 3.5 SOIC-8, MSOP-8 ADR435 5.000 0.04 3 0.8 8 SOIC-8, MSOP-8 ADR391 2.5 0.16 9 0.12 5 TSOT-5 ADR395 5.0 0.10 9 0.12 8 TSOT-5 Rev. I | Page 15 of 23

AD5545/AD5555 Data Sheet Table 11. Suitable Analog Devices Precision Op Amps V Maximum I Maximum 0.1 Hz to 10 Hz OS B Part No. Supply Voltage (V) (µV) (nA) Noise (µV p-p) Supply Current (µA) Package(s) OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8, PDIP-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP-8, SOIC-8 AD8675 ±5 to ±18 75 2 0.1 2300 MSOP-8, SOIC-8 AD8671 ±5 to ±15 75 12 0.077 3000 MSOP-8, SOIC-8 ADA4004-1 ±5 to ±15 125 90 0.1 2000 SOIC-8, SOT-23-5 AD8603 1.8 to 5 50 0.001 2.3 40 TSOT-5 AD8607 1.8 to 5 50 0.001 2.3 40 MSOP-8, SOIC-8 AD8605 2.7 to 5 65 0.001 2.3 1000 WLCSP-5, SOT-23-5 AD8615 2.7 to 5 65 0.001 2.4 2000 TSOT-5 AD8616 2.7 to 5 65 0.001 2.4 2000 MSOP-8, SOIC-8 Table 12. Suitable Analog Devices High Speed Op Amps Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/µs) V (Max) (µV) I (Max) (nA) Package(s) OS B AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23-5 AD8066 5 to 24 145 180 1500 0.006 SOIC-8, MSOP-8 AD8021 5 to 24 490 120 1000 10,500 SOIC-8, MSOP-8 AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5 ADA4899-1 5 to 12 600 310 35 100 LFCSP-8, SOIC-8 AD8057 3 to 12 325 1000 5000 500 SOT-23-5, SOIC-8 AD8058 3 to 12 325 850 5000 500 SOIC-8, MSOP-8 AD8061 2.7 to 8 320 650 6000 350 SOT-23-5, SOIC-8 AD8062 2.7 to 8 320 650 6000 350 SOIC-8, MSOP-8 AD9631 ±3 to ±6 320 1300 10,000 7000 SOIC-8, PDIP-8 Rev. I | Page 16 of 23

Data Sheet AD5545/AD5555 EVALUATION BOARD FOR THE AD5545 The EVAL-AD5545SDZ is used in conjunction with an SDP1Z system demonstration platform board available from Analog Devices, which is purchased separately from the evaluation board. The USB-to-SPI communication to the AD5545 is completed using this Blackfin®-based demonstration board. SYSTEM DEMONSTRATION PLATFORM The system demonstration platform (SDP) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. The SDP board is based on the Blackfin ADSP-BF527 processor with USB connectivity to the PC through a USB 2.0 high speed port. For more information about this device, see the system demonstration platform web page. OPERATING THE EVALUATION BOARD The evaluation board requires ±12 V and +5 V supplies. The +12 V V and −12 V V are used to power the output DD SS amplifier, and the +5 V is used to power the DAC (DVDD). 02918-0-027 Figure 26. Evaluation Board Software—AD5545 Dual DAC 02918-0-025 Figure 25. Evaluation Board Software – Device Selection Window Rev. I | Page 17 of 23

AD5545/AD5555 Data Sheet EVALUATION BOARD SCHEMATICS 820-0-81920 Figure 27. EVAL-AD5545SDZ Schematic Part A Rev. I | Page 18 of 23

Data Sheet AD5545/AD5555 920-0-81920 Figure 28. EVAL-AD5545SDZ Schematic Part B Rev. I | Page 19 of 23

AD5545/AD5555 Data Sheet 030-0-81920 Figure 29. EVAL-AD5545SDZ Schematic Part B Rev. I | Page 20 of 23

Data Sheet AD5545/AD5555 EVALUATION BOARD LAYOUT 02918-0-031 Figure 30. Silkscreen 02918-0-032 Figure 31. Component Side Rev. I | Page 21 of 23

AD5545/AD5555 Data Sheet 02918-0-033 Figure 32. Solder Side Rev. I | Page 22 of 23

Data Sheet AD5545/AD5555 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0.S6C5 0.19 SPELAANTIENG 0° 0.45 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 33. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE INL DNL Resolution Temperature Package Package Ordering Model1, 2 LSB LSB (Bits) Range Description Option Qty AD5545BRUZ ±2 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5545BRUZ-REEL7 ±2 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5545CRUZ ±1 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5545CRUZ-REEL7 ±1 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5555CRU ±1 ±1 14 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5555CRUZ ±1 ±1 14 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5555CRUZ-REEL7 ±1 ±1 14 −40°C to +85°C 16-Lead TSSOP RU-16 1000 EV-AD5544/45SDZ Evaluation Board 1 The AD5545/AD5555 contain 3131 transistors. The die size measures 71 mil. × 96 mil., 6816 sq. mil. 2 Z = RoHS Compliant Part. ©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02918-0-1/16(I) Rev. I | Page 23 of 23