2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-Bit DACs Data Sheet AD5541/AD5542 FEATURES FUNCTIONAL BLOCK DIAGRAMS Full 16-bit performance VDD 3 V and 5 V single-supply operation 8 AD5541 Low 0.625 mW power dissipation REF 3 16-BIT DAC 1 VOUT 1 µs settling time 2 AGND Unbuffered voltage output capable of driving 60 kΩ loads directly CS 4 16-BIT DAC LATCH SPI-/QSPI-/MICROWIRE-compatible interface standards DIN 6 CONTROL Power-on reset clears DAC output to 0 V (unipolar mode) LOGIC 5 kV HBM ESD classification SCLK 5 SERIAL INPUT REGISITER L ow glitch: 1.1 nV-sec DG7ND 07557-001 Figure 1. AD5541 APPLICATIONS VDD 14 Digital gain and offset adjustment AD5542 RFB Automatic test equipment RINV 1 RFB Data acquisition systems 13 INV REFF 6 Industrial process control 16-BIT DAC 2 VOUT GENERAL DESCRIPTION REFS 5 3 AGNDF The AD5541/AD5542 are single, 16-bit, serial input, voltage CS 7 16-BIT DAC LATCH output digital-to-analog converters (DACs) that operate from 4 AGNDS LDAC 11 CONTROL a single 2.7 V to 5.5 V supply. The DAC output range extends SCLK 8 LOGIC from 0 V to V . DIN 10 SERIAL INPUT REGISITER Tmhoen DotAoCn iocu, ptprRuoEtvF ridaningge e1x LteSnBd IsN frLo mac 0c uVr atocy V aRtE F1 a6n bdi tiss wguitahraonutte ed DG12ND 07557-002 Figure 2. AD5542 adjustment over the full specified temperature range of −40°C to Table 1. +85°C. Offering unbuffered outputs, the AD5541/AD5542 Part No. Description achieve a 1 µs settling time with low power consumption and low AD5541A/AD5542A Single, 16-bit unbuffered nanoDAC™, offset errors. Providing a low noise performance of 11.8 nV/√Hz ±1 LSB INL, LFCSP and low glitch, the AD5541/AD5542 is suitable for deployment AD5024/AD5044/AD5064 Quad 12-/14-/16-bit nanoDAC, across multiple end systems. ±1 LSB INL, TSSOP The AD5542 can be operated in bipolar mode, which generates AD5062 Single, 16-bit nanoDAC, ±1 LSB INL, SOT-23 a ±V output swing. The AD5542 also includes Kelvin sense REF AD5063 Single, 16-bit nanoDAC, ±1 LSB INL, connections for the reference and analog ground pins to reduce SOT-23 layout sensitivity. PRODUCT HIGHLIGHTS The AD5541/AD5542 utilize a versatile 3-wire interface that is compatible with SPI, QSPI™, MICROWIRE™ and DSP interface 1. Single-Supply Operation. The AD5541 and AD5542 are fully standards. The AD5541/AD5542 are available in 8-lead and specified and guaranteed for a single 2.7 V to 5.5 V supply. 14-lead SOIC packages. 2. Low Power Consumption. These parts consume typically 0.625 mW with a 5 V supply and 0.375 mV at 3 V. 3. 3-Wire Serial Interface. 4. Unbuffered Output Capable of Driving 60 kΩ Loads. This reduces power consumption because there is no internal buffer to drive. 5. Power-On Reset Circuitry. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1999–2012 Analog Devices, Inc. All rights reserved.

AD5541/AD5542 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Bipolar Output Operation ......................................................... 12 Applications ....................................................................................... 1 Output Amplifier Selection ....................................................... 12 General Description ......................................................................... 1 Force Sense Amplifier Selection ............................................... 12 Functional Block Diagrams ............................................................. 1 Reference and Ground ............................................................... 12 Product Highlights ........................................................................... 1 Power-On Reset .......................................................................... 13 Revision History ............................................................................... 2 Power Supply and Reference Bypassing .................................. 13 Specifications ..................................................................................... 3 Microprocessor Interfacing ........................................................... 14 Timing Characteristics ................................................................ 4 AD5541/AD5542 to ADSP-21xx Interface ............................. 14 Absolute Maximum Ratings ............................................................ 5 AD5541/AD5542 to 68HC11/68L11 Interface....................... 14 ESD Caution .................................................................................. 5 AD5541/AD5542 to MICROWIRE Interface ........................ 14 Pin Configurations and Function Descriptions ........................... 6 AD5541/AD5542 to 80C51/80L51 Interface .......................... 14 Typical Performance Characteristics ............................................. 7 Applications Information .............................................................. 15 Terminology .................................................................................... 10 Optocoupler Interface ................................................................ 15 Theory of Operation ...................................................................... 11 Decoding Multiple AD5541/AD5542s .................................... 15 Digital-to-Analog Section ......................................................... 11 Outline Dimensions ....................................................................... 16 Serial Interface ............................................................................ 11 Ordering Guide .......................................................................... 17 Unipolar Output Operation ...................................................... 11 REVISION HISTORY 3/12—Rev. E to Rev. F Changes to Product Highlights ....................................................... 1 Change to Figure 19 ......................................................................... 9 Changes to Table 1 ............................................................................. 3 Changes to Ordering Guide .......................................................... 17 Changes to Table 3 ............................................................................. 5 Changes to Figure 16, Figure 17, and Figure 19 ....................... 8, 9 3/11—Rev. D to Rev. E Changes to Theory of Operations Section .................................. 11 Changed +105°C to +85°C, General Description Section .......... 1 Changes to Microprocessor Interfacing Section ........................ 14 Changes to Outline Dimensions .................................................. 16 2/11—Rev. C to Rev. D Changes to Ordering Guide .......................................................... 17 Changes to Features Section, General Description Section, Product Highlights Section ............................................................. 1 8/08—Rev. A to Rev. B Added Table 1; Renumbered Sequentially .................................... 1 Updated Format .................................................................. Universal Added Output Noise Spectral Density Parameter and Output Changes to Timing Characteristics Section ................................... 4 Noise Parameter, Table 2.................................................................. 3 Changes to Table 3 ............................................................................. 5 Changes to Ordering Guide .......................................................... 17 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 17 4/10—Rev. B to Rev. C Changes to General Description Section ...................................... 1 10/99—Rev. 0 to Rev. A Changes to Features List .................................................................. 1 Rev. F | Page 2 of 20

Data Sheet AD5541/AD5542 SPECIFICATIONS V = 2.7 V to 5.5 V, 2.5 V ≤ V ≤ V , AGND = DGND = 0 V. All specifications T = T to T , unless otherwise noted. DD REF DD A MIN MAX Table 2. Parameter1 Min Typ Max Unit Test Conditions STATIC PERFORMANCE Resolution 16 Bits Relative Accuracy (INL) ±0.5 ±1.0 LSB L, C grades ±0.5 ±2.0 LSB B, J grades ±0.5 ±4.0 LSB A grade Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB Guaranteed monotonic ±1.5 LSB J grade Gain Error +0.5 ±2 LSB T = 25°C A ±3 LSB Gain Error Temperature Coefficient ±0.1 ppm/°C Unipolar Zero Code Error ±0.3 ±0.7 LSB T = 25°C A ±1.5 LSB Unipolar Zero Code Temperature Coefficient ±0.05 ppm/°C AD5542 Bipolar Resistor Matching 1.000 Ω/Ω R /R , typically R = R = 28 kΩ FB INV FB INV ±0.0015 ±0.0076 % Ratio error Bipolar Zero Offset Error ±1 ±5 LSB T = 25°C A ±6 LSB Bipolar Zero Temperature Coefficient ±0.2 ppm/°C Bipolar Zero Code Offset Error ±1 ±5 LSB T = 25°C A ±6 LSB Bipolar Gain Error +1 ±5 LSB T = 25°C A ±6 LSB Bipolar Gain Temperature Coefficient ±0.1 ppm/°C OUTPUT CHARACTERISTICS Output Voltage Range 0 V − 1 LSB V Unipolar operation REF −V V − 1 LSB V AD5542 bipolar operation REF REF Output Voltage Settling Time 1 μs To 1/2 LSB of FS, C = 10 pF L Slew Rate 17 V/μs C = 10 pF, measured from 0% to 63% L Digital-to-Analog Glitch Impulse 1.1 nV-sec 1 LSB change around the major carry Digital Feedthrough 0.2 nV-sec All 1s loaded to DAC, V = 2.5 V REF DAC Output Impedance 6.25 kΩ Tolerance typically 20% Output Noise Spectral Density 11.8 nV/√Hz DAC code = 0x8400, frequency = 1 kHz Output Noise 0.134 µV p-p 0.1 Hz to 10 Hz Power Supply Rejection Ratio ±1.0 LSB ΔV ± 10% DD DAC REFERENCE INPUT Reference Input Range 2.0 V V DD Reference Input Resistance2 9 kΩ Unipolar operation 7.5 kΩ AD5542, bipolar operation LOGIC INPUTS Input Current ±1 μA Input Low Voltage, V 0.8 V INL Input High Voltage, V 2.4 V INH Input Capacitance3 10 pF Hysteresis Voltage3 0.15 V REFERENCE 3 Reference −3 dB Bandwidth 2.2 MHz All 1s loaded Reference Feedthrough 1 mV p-p All 0s loaded, V = 1 V p-p at 100 kHz REF Signal-to-Noise Ratio 92 dB Reference Input Capacitance 26 pF Code 0x0000 26 pF Code 0xFFFF Rev. F | Page 3 of 20

AD5541/AD5542 Data Sheet Parameter1 Min Typ Max Unit Test Conditions POWER REQUIREMENTS Digital inputs at rails V 2.7 5.5 V DD I 125 150 μA DD Power Dissipation 0.625 0.825 mW 1 Temperature ranges are as follows: A, B, C versions: −40°C to +85°C; J, L versions: 0°C to 70°C. 2 Reference input resistance is code-dependent, minimum at 0x8555. 3 Guaranteed by design, not subject to production test. TIMING CHARACTERISTICS V = 2.7 V to 5.5 V ±10%, V = 2.5 V, V = 3 V and 90% of V , V = 0 V and 10% of V , AGND = DGND = 0 V; −40°C < T < DD REF INH DD INL DD A +85°C, unless otherwise noted. Table 3. Parameter1, 2 Limit Unit Description f 25 MHz max SCLK cycle frequency SCLK t 40 ns min SCLK cycle time 1 t 20 ns min SCLK high time 2 t 20 ns min SCLK low time 3 t 10 ns min CS low to SCLK high setup 4 t 15 ns min CS high to SCLK high setup 5 t 30 ns min SCLK high to CS low hold time 6 t 20 ns min SCLK high to CS high hold time 7 t 15 ns min Data setup time 8 t 4 ns min Data hold time (V = 90% of V , V = 10% of V ) 9 INH DD INL DD t 7.5 ns min Data hold time (V = 3V, V = 0 V) 9 INH INL t 30 ns min LDAC pulse width 10 t 30 ns min CS high to LDAC low setup 11 t 30 ns min CS high time between active periods 12 1 Guaranteed by design and characterization. Not production tested 2 All input signals are specified with t = t = 1 ns/V and timed from a voltage level of (V + V )/2. R F INL INH t1 SCLK t6 t2 t3 t5 t4 t7 CS t12 t8 t5 DIN DB15 t11 t10 L*DAADC55*42 ONLY. CAN BE TIED PERMANENTLY LOW IF REQUIRED. 07557-003 Figure 3. Timing Diagram Rev. F | Page 4 of 20

Data Sheet AD5541/AD5542 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings A may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to AGND −0.3 V to +6 V DD section of this specification is not implied. Exposure to absolute Digital Input Voltage to DGND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect V to AGND −0.3 V to V + 0.3 V OUT DD device reliability. AGND, AGNDF, AGNDS to DGND −0.3 V to +0.3 V ESD CAUTION Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range Industrial (A, B, C Versions) −40°C to +85°C Commercial (J, L Versions) 0°C to 70°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature (T max) 150°C J Package Power Dissipation (T max – T )/θ J A JA Thermal Impedance, θ JA SOIC (R-8) 149.5°C/W SOIC (R-14) 104.5°C/W Lead Temperature, Soldering Peak Temperature1 260°C ESD2 5 kV 1 As per JEDEC Standard 20. 2 HBM Classification. Rev. F | Page 5 of 20

AD5541/AD5542 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUT 1 8 VDD AGND 2 AD5541 7 DGND RCESF 43 (NToOt Pto V SIEcWale) 65 DSCINLK 07557-004 Figure 4. AD5541 Pin Configuration Table 5. AD5541 Pin Function Descriptions Pin No. Mnemonic Description 1 V Analog Output Voltage from the DAC. OUT 2 AGND Ground Reference Point for Analog Circuitry. 3 REF Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V . DD 4 CS Logic Input Signal. The chip select signal is used to frame the serial data input. 5 SCLK Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. 6 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK. 7 DGND Digital Ground. Ground reference for digital circuitry. 8 V Analog Supply Voltage, 5 V ± 10%. DD RFB 1 14 VDD VOUT 2 13 INV AGNDF 3 AD5542 12 DGND AGNDS 4 TOP VIEW 11 LDAC (Not to Scale) REFS 5 10 DIN REFF 6 9 NC CS N7C = NO CONNECT8 SCLK 07557-005 Figure 5. AD5542 Pin Configuration Table 6. AD5542 Pin Function Descriptions Pin No. Mnemonic Description 1 RFB Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output. 2 V Analog Output Voltage from the DAC. OUT 3 AGNDF Ground Reference Point for Analog Circuitry (Force). 4 AGNDS Ground Reference Point for Analog Circuitry (Sense). 5 REFS Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V . DD 6 REFF Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V . DD 7 CS Logic Input Signal. The chip select signal is used to frame the serial data input. 8 SCLK Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. 9 NC No Connect. 10 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK. 11 LDAC LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the input register. 12 DGND Digital Ground. Ground reference for digital circuitry. 13 INV Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to external op amps inverting input in bipolar mode. 14 V Analog Supply Voltage, 5 V ± 10%. DD Rev. F | Page 6 of 20

Data Sheet AD5541/AD5542 TYPICAL PERFORMANCE CHARACTERISTICS 0.50 0.50 VDD = 5V VDD = 5V VREF = 2.5V B) VREF = 2.5V TY (LSB) 0.25 RITY (LS 0.25 NEARI 0 LINEA AL NONLI–0.25 TIAL NON 0 R N INTEG–0.50 DIFFERE–0.25 –0.750 8192 16384 24576 C32O7D6E8 40960 49152 57344 65536 07557-006 –0.500 8192 16384 24576 C32O7D6E8 40960 49152 57344 65536 07557-009 Figure 6. Integral Nonlinearity vs. Code Figure 9. Differential Nonlinearity vs. Code 0.25 0.75 VDD = 5V VDD = 5V VREF = 2.5V B) VREF = 2.5V TY (LSB) 0 RITY (LS 0.50 NEARI–0.25 LINEA 0.25 AL NONLI–0.50 TIAL NON 0 R N INTEG–0.75 DIFFERE–0.25 –1.00–60 –40 –20 0 TEM20PERA4T0URE6 (0°C) 80 100 120 140 07557-007 –0.50–60 –40 –20 0 TEM20PERA4T0URE6 (0°C) 80 100 120 140 07557-010 Figure 7. Integral Nonlinearity vs. Temperature Figure 10. Differential Nonlinearity vs. Temperature 0.50 0.75 VREF = 2.5V VDD = 5V TA = 25°C TA = 25°C 0.25 0.50 B) DNL B) DNL S S L L OR ( 0 OR ( 0.25 R R R R E E Y Y T T RI–0.25 RI 0 A A NE NE INL LI LI –0.50 –0.25 INL –0.752 3 SUPP4LY VOLTAG5E (V) 6 707557-008 –0.500 1 RE2FERENCE 3VOLTAGE4 (V) 5 6 07557-011 Figure 8. Linearity Error vs. Supply Voltage Figure 11. Linearity Error vs. Reference Voltage Rev. F | Page 7 of 20

AD5541/AD5542 Data Sheet 0 0.15 VDD = 5V VDD = 5V –0.1 VTAR E=F 2=5 °2C.5V 0.10 TVAR E=F 2=5 °2C.5V –0.2 B) S SB) –0.3 R (L 0.05 ERROR (L ––00..45 DE ERRO 0 GAIN –0.6 RO-CO–0.05 E –0.7 Z –0.10 –0.8 –0.9 –40 TEMPERA25TURE (°C) 85 08898-012 –0.15 –40 TEMPERA25TURE (°C) 85 08898-015 Figure 12. Gain Error vs. Temperature Figure 15. Zero-Code Error vs. Temperature 2.0 132 VDD = 5V TA = 25°C VREF = 2.5V 130 TA = 25°C 1.5 Y CURRENT (µA) 111222468 LY CURRENT (µA) 1.0 RVDEDF E=R 5EVNCE VOLTASVGUREEPFP =L Y2 .V5VOLTAGE L 122 P P P P U SU 120 S 0.5 118 116 –40 TEMPERA25TURE (°C) 85 08898-013 00 1 2 VOLTA3GE (V) 4 5 6 08898-016 Figure 13. Supply Current vs. Temperature Figure 16. Supply Current vs. Reference Voltage or Supply Voltage 200 200 VDD = 5V 180 VREF = 2.5V TA = 25°C 160 A) 150 T (µV) 140 ENT (µ N 120 R E R LY CURR 10800 ENCE CU 100 P R UP 60 FE S E 50 R 40 20 0 1 2 3 4 5 6DI7GIT8AL9 IN1P0U1T1 V1O2L1T3A1G4E1 5(V1)61718192021 08898-014 00 10,000 20,000 C3O0,D00E0 (De4c0i,m00a0l) 50,000 60,000 70,000 08898-017 Figure 14. Supply Current vs. Digital Input Voltage Figure 17. Reference Current vs. Code Rev. F | Page 8 of 20

Data Sheet AD5541/AD5542 VVRDEDF = = 5 2V.5V 2µs/DIV VVRDEDF = = 5 2V.5V 100 TA = 25°C 100 TA = 25°C CS (5V/DIV) DIN (5V/DIV) 10pF 50pF 100pF 200pF VOUT (50mV/DIV) 10 10 2µs/DIV 08898-018 VOUT (0.5V/DIV) 08898-020 Figure 18. Digital Feedthrough Figure 20. Large Signal Settling Time 1.236 5 CS 0 1.234 VREF = 2.5V VDD = 5V –5 TA = 25°C E (V)1.232 –10 19000•••• •••• •••• •••• •••• •••• •••• •••• •••• •••• VOUT (1V/DIV) G A1.230 T OL –15 V 1.228 VOUT –20 VOUT (50mV/DIV) 1.226 GAIN = –216 –25 10 1LSB = 8.2mV 0%•••• •••• •••• •••• •••• •••• •••• •••• •••• •••• 1.224 –30 –0.5 0 0.5TIME (µs)1.0 1.5 2.0 07557-032 0.5µs/DIV 07557-021 Figure 19. Digital-to-Analog Glitch Impulse Figure 21. Small Signal Settling Time Rev. F | Page 9 of 20

AD5541/AD5542 Data Sheet TERMINOLOGY Digital-to-Analog Glitch Impulse Relative Accuracy or Integral Nonlinearity (INL) Digital-to-analog glitch impulse is the impulse injected into the For the DAC, relative accuracy or INL is a measure of the analog output when the input code in the DAC register changes maximum deviation, in LSBs, from a straight line passing state. It is normally specified as the area of the glitch in nV-sec through the endpoints of the DAC transfer function. A typical and is measured when the digital input code is changed by INL vs. code plot can be seen in Figure 6. 1 LSB at the major carry transition. A plot of the digital-to- Differential Nonlinearity (DNL) analog glitch impulse is shown in Figure 19. DNL is the difference between the measured change and the Digital Feedthrough ideal 1 LSB change between any two adjacent codes. A specified Digital feedthrough is a measure of the impulse injected into differential nonlinearity of ±1 LSB maximum ensures mono- the analog output of the DAC from the digital inputs of the tonicity. Figure 9 illustrates a typical DNL vs. code plot. DAC, but it is measured when the DAC output is not updated. Gain Error CS is held high while the CLK and DIN signals are toggled. It Gain error is the difference between the actual and ideal analog is specified in nV-sec and is measured with a full-scale code output range, expressed as a percent of the full-scale range. change on the data bus, that is, from all 0s to all 1s and vice It is the deviation in slope of the DAC transfer characteristic versa. A typical plot of digital feedthrough is shown in from ideal. Figure 18. Gain Error Temperature Coefficient Power Supply Rejection Ratio (PSRR) Gain error temperature coefficient is a measure of the change PSRR indicates how the output of the DAC is affected by changes in gain error with changes in temperature. It is expressed in in the power supply voltage. Power-supply rejection ratio is ppm/°C. quoted in terms of percent change in output per percent change Zero Code Error in V for full-scale output of the DAC. V is varied by ±10%. DD DD Zero code error is a measure of the output error when zero code Reference Feedthrough is loaded to the DAC register. Reference feedthrough is a measure of the feedthrough from the Zero Code Temperature Coefficient V input to the DAC output when the DAC is loaded with all REF This is a measure of the change in zero code error with a change 0s. A 100 kHz, 1 V p-p is applied to V . Reference feedthrough REF in temperature. It is expressed in mV/°C. is expressed in mV p-p. Rev. F | Page 10 of 20

Data Sheet AD5541/AD5542 THEORY OF OPERATION The AD5541/AD5542 are single, 16-bit, serial input, voltage SERIAL INTERFACE output DACs. They operate from a single supply ranging from The AD5541/AD5542 are controlled by a versatile 3- or 4-wire 2.7 V to 5.5 V and consume typically 125 µA with a supply of serial interface that operates at clock rates up to 25 MHz and is 5 V. Data is written to these devices in a 16-bit word format, compatible with SPI, QSPI, MICROWIRE, and DSP interface via a 3- or 4-wire serial interface. To ensure a known power-up standards. The timing diagram is shown in Figure 3. Input data state, these parts are designed with a power-on reset function. is framed by the chip select input, CS. After a high-to-low In unipolar mode, the output is reset to 0 V; in bipolar mode, transition on CS, data is shifted synchronously and latched into the AD5542 output is set to −V . Kelvin sense connections for REF the input register on the rising edge of the serial clock, SCLK. the reference and analog ground are included on the AD5542. Data is loaded MSB first in 16-bit words. After 16 data bits have DIGITAL-TO-ANALOG SECTION been loaded into the serial input register, a low-to-high transition The DAC architecture consists of two matched DAC sections. on CS transfers the contents of the shift register to the DAC. Data A simplified circuit diagram is shown in Figure 22. The DAC can be loaded to the part only while CS is low. architecture of the AD5541/AD5542 is segmented. The four The AD5542 has an LDAC function that allows the DAC latch MSBs of the 16-bit data-word are decoded to drive 15 switches, to be updated asynchronously by bringing LDAC low after CS E1 to E15. Each switch connects one of 15 matched resistors to goes high. LDAC should be maintained high while data is written either AGND or V . The remaining 12 bits of the data-word REF to the shift register. Alternatively, LDAC can be tied perma- drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder nently low to update the DAC synchronously. With LDAC tied network. permanently low, the rising edge of CS loads the data to the DAC. R R VOUT UNIPOLAR OUTPUT OPERATION 2R 2R 2R . . . . . 2R 2R 2R . . . . . 2R These DACs are capable of driving unbuffered loads of 60 kΩ. S0 S1 . . . . . S11 E1 E2 . . . . . E15 Unbuffered operation results in low supply current, typically VREF 300 μA, and a low offset error. The AD5541 provides a unipolar output swing ranging from 0 V to V . The AD5542 can be REF 12-BIT R-2R LADDER INTFOO U15R EMQSUBAsL D SEECGOMDEENDTS 07557-022 cshoonwfigs uar teydp tioc aolu utpnuipt obloatrh o uuntippuotl avro altnadg eb icpiorclauri tv.o Tlthaeg ecso. dFeig tuarbel e2 3 Figure 22. DAC Architecture for this mode of operation is shown in Table 7. With this type of DAC configuration, the output impedance 5V 2.5V 10µF is independent of code, while the input impedance seen by + 0.1µF 0.1µF the reference is heavily code dependent. The output voltage is dependent on the reference voltage, as shown in the following equation: SERIAL INTERFACE VDD REF(REFF*) REFS* CS AD820/ V ×D OP196 VOUT = RE2FN DSCINLK AD5541/AD5542 OUT UONUIPTOPLUATR LDAC* EXTERNAL where: DGND AGND OPAMP D is the decimal data-word loaded to the DAC register. *AD5542 ONLY. 07557-023 N is the resolution of the DAC. Figure 23. Unipolar Output For a reference of 2.5 V, the equation simplifies to the following: Table 7. Unipolar Code Table 2.5×D V = DAC Latch Contents OUT 65,536 MSB LSB Analog Output 1111 1111 1111 1111 V × (65,535/65,536) This gives a V of 1.25 V with midscale loaded and 2.5 V with REF OUT 1000 0000 0000 0000 V × (32,768/65,536) = ½ V full-scale loaded to the DAC. REF REF 0000 0000 0000 0001 V × (1/65,536) The LSB size is V /65,536. REF REF 0000 0000 0000 0000 0 V Rev. F | Page 11 of 20

AD5541/AD5542 Data Sheet Assuming a perfect reference, the unipolar worst-case output Assuming a perfect reference, the worst-case bipolar output voltage can be calculated from the following equation: voltage can be calculated from the following equation: [( )( ) ( )] D ( ) V +V 2+RD −V 1+RD VOUT-UNI = 216 × VREF +VGE +VZSE +INL VOUT-BIP = OUT−UNI 1O+S (2+RD) REF A where: V is unipolar mode worst-case output. where: OUT−UNI D is code loaded to DAC. V is the bipolar mode worst-case output. OUT-BIP V is reference voltage applied to the part. V is the unipolar mode worst-case output. REF OUT−UNI V is gain error in volts. V is the external op amp input offset voltage. GE OS V is zero scale error in volts. RD is the R and R resistor matching error. ZSE FB INV INL is integral nonlinearity in volts. A is the op amp open-loop gain. BIPOLAR OUTPUT OPERATION OUTPUT AMPLIFIER SELECTION With the aid of an external op amp, the AD5542 can be confi- For bipolar mode, a precision amplifier should be used and gured to provide a bipolar voltage output. A typical circuit of supplied from a dual power supply. This provides the ±V REF such operation is shown in Figure 24. The matched bipolar output. In a single-supply application, selection of a suitable op offset resistors, R and R , are connected to an external op amp may be more difficult as the output swing of the amplifier FB INV amp to achieve this bipolar output swing, typically R = R = does not usually include the negative rail, in this case, AGND. FB INV 28 kΩ. Table 8 shows the transfer function for this output This can result in some degradation of the specified performance operating mode. Also provided on the AD5542 are a set of unless the application does not use codes near zero. Kelvin connections to the analog ground inputs. The selected op amp needs to have a very low-offset voltage (the +5V +2.5V DAC LSB is 38 μV with a 2.5 V reference) to eliminate the need 10µF + for output offset trims. Input bias current should also be very 0.1µF 0.1µF low because the bias current, multiplied by the DAC output impedance (approximately 6 kΩ), adds to the zero code error. SERIAL RFB +5V Rail-to-rail input and output performance is required. For fast INTERFACE CSVDD REFF REFS RFB INV settling, the slew rate of the op amp should not impede the DIN RINV OUT UNIPOLAR settling time of the DAC. Output impedance of the DAC is SCLK AD5541/AD5542 OUTPUT constant and code-independent, but to minimize gain errors, LDAC –5V the input impedance of the output amplifier should be as high DGND AGNDF AGNDS EXOTPEARMNPAL 07557-024 a1s M poHszs iobrle g. rTehatee ra.m Tphleif iaemr pshliofiuelrd a adldsos ahnaovteh ae r3 tdimB eb aconndswtaidntth t oo f Figure 24. Bipolar Output (AD5542 Only) the system, hence increasing the settling time of the output. A Table 8. Bipolar Code Table higher 3 dB amplifier bandwidth results in a shorter effective DAC Latch Contents settling time of the combined DAC and amplifier. MSB LSB Analog Output FORCE SENSE AMPLIFIER SELECTION 1111 1111 1111 1111 +V × (32,767/32,768) REF Use single-supply, low-noise amplifiers. A low-output impedance 1000 0000 0000 0001 +V × (1/32,768) REF at high frequencies is preferred because the amplifiers need to 1000 0000 0000 0000 0 V be able to handle dynamic currents of up to ±20 mA. 0111 1111 1111 1111 −V × (1/32,768) REF 0000 0000 0000 0000 −V × (32,768/32,768) = −V REFERENCE AND GROUND REF REF Because the input impedance is code-dependent, the reference pin should be driven from a low impedance source. The AD5541/ AD5542 operate with a voltage reference ranging from 2 V to V . References below 2 V result in reduced accuracy. The full- DD scale output voltage of the DAC is determined by the reference. Table 7 and Table 8 outline the analog output voltage or partic- ular digital codes. For optimum performance, Kelvin sense connections are provided on the AD5542. If the application does not require separate force and sense lines, tie the lines close to the package to minimize voltage drops between the package leads and the internal die. Rev. F | Page 12 of 20

Data Sheet AD5541/AD5542 POWER-ON RESET POWER SUPPLY AND REFERENCE BYPASSING The AD5541/AD5542 have a power-on reset function to ensure For accurate high-resolution performance, it is recommended that the output is at a known state on power-up. On power-up, that the reference and supply pins be bypassed with a 10 μF the DAC register contains all 0s until the data is loaded from tantalum capacitor in parallel with a 0.1 μF ceramic capacitor. the serial register. However, the serial register is not cleared on power-up, so its contents are undefined. When loading data initially to the DAC, 16 bits or more should be loaded to prevent erroneous data appearing on the output. If more than 16 bits are loaded, the last 16 are kept, and if less than 16 bits are loaded, bits remain from the previous word. If the AD5541/AD5542 need to be interfaced with data shorter than 16 bits, the data should be padded with 0s at the LSBs. Rev. F | Page 13 of 20

AD5541/AD5542 Data Sheet MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5541/AD5542 is via a AD5541/AD5542 TO MICROWIRE INTERFACE serial bus that uses standard protocol that is compatible with Figure 27 shows an interface between the AD5541/AD5542 DSP processors and microcontrollers. The communications and any MICROWIRE-compatible device. Serial data is shifted channel requires a 3- or 4-wire interface consisting of a clock out on the falling edge of the serial clock and into the AD5541/ signal, a data signal and a synchronization signal. The AD5542 on the rising edge of the serial clock. No glue logic is AD5541/AD5542 require a 16-bit data-word with data valid on required because the DAC clocks data into the input shift the rising edge of SCLK. The DAC update can be done register on the rising edge. automatically when all the data is clocked in or it can be done under control of the LDAC (AD5542 only). CS CS AD5541/ AD5541/AD5542 TO ADSP-21XX INTERFACE MICROWIRE* SO DIN AD5542* Fanigdu trhe e2 A5 DshSoPw-2s 1ax sxe. rTiahl ei nAteDrSfaPc-e2 1bxextw seheonu tldh eb Ae Dse5t 5to4 1o/pAeDra5t5e 4in2 *ADDITIONAL PINSSC OLKMITTED FOR CLASRCITLYK. 07557-027 Figure 27. AD5541/AD5542 to MICROWIRE Interface the SPORT transmit alternate framing mode. The ADSP-21xx are programmed through the SPORT control register and should be AD5541/AD5542 TO 80C51/80L51 INTERFACE configured as follows: internal clock operation, active low A serial interface between the AD5541/AD5542 and the 80C51/ framing, 16-bit word length. Transmission is initiated by 80L51 microcontroller is shown in Figure 28. TxD of the micro- writing a word to the Tx register after the SPORT has been controller drives the SCLK of the AD5541/AD5542, and RxD enabled. As the data is clocked out on each rising edge of the drives the serial data line of the DAC. P3.3 is a bit programmable serial clock, an inverter is required between the DSP and the pin on the serial port that is used to drive CS. DAC, because the AD5541/AD5542 clock data in on the falling edge of the SCLK. The 80C51/80L51 provide the LSB first, whereas the AD5541/ AD5542 expects the MSB of the 16-bit word first. Care should FO LDAC** be taken to ensure the transmit routine takes this into account. TFS CS AD5541/ ADSP-21xx AD5542* When data is to be transmitted to the DAC, P3.3 is taken low. DT DIN Data on RxD is valid on the falling edge of TxD, so the clock SCLK SCLK must be inverted as the DAC clocks data into the input shift **A*ADDD5I5T4IO2 NOANLL YP.INS OMITTED FOR CLARITY. 07557-025 rtreagnisstmeri to dna tthae i nri 8si-nbgit e bdygtee so wf tihthe osenrliya le icglohct kfa. lTlihneg 8c0loCc5k1 e/8d0gLes5 1 Figure 25. AD5541/AD5542 to ADSP-21xx Interface occurring in the transmit cycle. As the DAC requires a 16-bit AD5541/AD5542 TO 68HC11/68L11 INTERFACE word, P3.3 must be left low after the first eight bits are transferred, Figure 26 shows a serial interface between the AD5541/AD5542 and brought high after the second byte is transferred. LDAC on and the 68HC11/68L11 microcontroller. SCK of the 68HC11/ the AD5542 can also be controlled by the 80C51/ 80L51 serial 68L11 drives the SCLK of the DAC, and the MOSI output drives port output by using another bit programmable pin, P3.4. the serial data line serial DIN. The CS signal is driven from one P3.4 LDAC** of the port lines. The 68HC11/68L11 is configured for master 80C51/ P3.3 CS AD5541/ mode: MSTR = 1, CPOL = 0, and CPHA = 0. Data appearing 80L51* AD5542* RxD DIN on the MOSI output is valid on the rising edge of SCK. TxD SCLK 68HC11/ PPCC67 LCDSAC**AD5541/ **A*ADDD5I5T4IO2 NOANLL YP.INS OMITTED FOR CLARITY. 07557-028 68L11* AD5542* Figure 28. AD5541/AD5542 to 80C51/80L51 Interface MOSI DIN SCK SCLK **A*ADDD5I5T4IO2 NOANLL YP.INS OMITTED FOR CLARITY. 07557-026 Figure 26. AD5541/AD5542 to 68HC11/68L11 Interface Rev. F | Page 14 of 20

Data Sheet AD5541/AD5542 APPLICATIONS INFORMATION OPTOCOUPLER INTERFACE DECODING MULTIPLE AD5541/AD5542s The digital inputs of the AD5541/AD5542 are Schmitt-triggered so The CS pin of the AD5541/AD5542 can be used to select one of that they can accept slow transitions on the digital input lines. a number of DACs. All devices receive the same serial clock and This makes these parts ideal for industrial applications where it serial data, but only one device receives the CS signal at any one may be necessary to isolate the DAC from the controller via time. The DAC addressed is determined by the decoder. There is optocouplers. Figure 29 illustrates such an interface. some digital feedthrough from the digital input lines. Using a burst clock minimizes the effects of digital feedthrough on the 5V analog signal channels. Figure 30 shows a typical circuit. REGULATOR POWER 10µF 0.1µF AD5541/AD5542 SCLK CS VDD DIN DIN VOUT 10kΩ VDD VDD SCLK SCLK SCLK ENABLE EN AD5541/AD5542 VDD AD5541/AD5542 ADCDORDEESDS DECODER CDSIN VOUT 10kΩ SCLK CS CS VOUT DGND AD5541/AD5542 VDD CS DIN VOUT 10kΩ SCLK DIN DIN GND 07557-029 ACSD5541/AD5542 Figure 29. AD5541/AD5542 in an Optocoupler Interface DSCINLK VOUT 07557-030 Figure 30. Addressing Multiple AD5541/AD5542s Rev. F | Page 15 of 20

AD5541/AD5542 Data Sheet OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA (CRINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 31. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 14 8 6.20 (0.2441) 3.80 (0.1496) 1 7 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 45° 1.75 (0.0689) 0.25 (0.0098) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AB C(RINOEFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 32. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Rev. F | Page 16 of 20

Data Sheet AD5541/AD5542 ORDERING GUIDE Model1 INL DNL Temperature Range Package Description Package Option AD5541CR ±1 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541CRZ ±1 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541CRZ-REEL7 ±1 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541LR ±1 LSB ±1 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541LR-REEL7 ±1 LSB ±1 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541LRZ ±1 LSB ±1 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541LRZ-REEL7 ±1 LSB ±1 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541BR ±2 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541BRZ ±2 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541BRZ-REEL ±2 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541JR ±2 LSB ±1.5 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541JR-REEL7 ±2 LSB ±1.5 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541JRZ ±2 LSB ±1.5 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541JRZ-REEL7 ±2 LSB ±1.5 LSB 0°C to 70°C 8-Lead SOIC_N R-8 AD5541AR ±4 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541AR-REEL7 ±4 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541ARZ ±4 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5541ARZ-REEL7 ±4 LSB ±1 LSB −40°C to +85°C 8-Lead SOIC_N R-8 AD5542CR ±1 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542CR-REEL7 ±1 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542CRZ ±1 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542CRZ-REEL7 ±1 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542LR ±1 LSB ±1 LSB 0°C to 70°C 14-Lead SOIC_N R-14 AD5542LRZ ±1 LSB ±1 LSB 0°C to 70°C 14-Lead SOIC_N R-14 AD5542BR ±2 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542BRZ ±2 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542BRZ-REEL7 ±2 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542JR ±2 LSB ±1.5 LSB 0°C to 70°C 14-Lead SOIC_N R-14 AD5542JR-REEL7 ±2 LSB ±1.5 LSB 0°C to 70°C 14-Lead SOIC_N R-14 AD5542JRZ ±2 LSB ±1.5 LSB 0°C to 70°C 14-Lead SOIC_N R-14 AD5542JRZ-REEL7 ±2 LSB ±1.5 LSB 0°C to 70°C 14-Lead SOIC_N R-14 AD5542AR ±4 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542AR-REEL7 ±4 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542ARZ ±4 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 AD5542ARZ-REEL7 ±4 LSB ±1 LSB −40°C to +85°C 14-Lead SOIC_N R-14 EVAL-AD5541/42EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. F | Page 17 of 20

AD5541/AD5542 Data Sheet NOTES Rev. F | Page 18 of 20

Data Sheet AD5541/AD5542 NOTES Rev. F | Page 19 of 20

AD5541/AD5542 Data Sheet NOTES ©1999–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07557-0-3/12(F) Rev. F | Page 20 of 20